High frequency test device, method and wireless radio frequency communication system

Abstract

The present application discloses a high-frequency frequency testing device, method and wireless radio frequency communication system, which relates to the field of wireless radio frequency communication technology, including: an injection-locked frequency divider; a first frequency divider connected to the injection-locked frequency divider, for performing frequency reduction processing on the output signal of the injection-locked frequency divider; a frequency divider calibration module, connected to the first frequency divider and the injection-locked frequency divider respectively, for determining whether the frequency division range of the injection-locked frequency divider at the current moment includes the target frequency range corresponding to the signal to be tested when the injection-locked frequency divider is in the frequency divider calibration mode; if not, adjusting the resonant frequency so that the frequency division range of the injection-locked frequency divider includes the target frequency range; a controller, connected to the injection-locked frequency divider, for controlling the injection-locked frequency divider to enter the high-frequency frequency test mode when the frequency division range of the injection-locked frequency divider includes the target frequency range. The present application can achieve accurate testing of high frequencies at a low cost.

Description

Technical Field

[0001] The present application relates to the field of wireless radio frequency communication technology, and in particular to a high-frequency frequency testing device, method and wireless radio frequency communication system. Background Art

[0002] In the field of wireless RF communications, high-frequency signals in different frequency bands are often used as data transmission carriers to increase channel capacity and reduce interference between different frequency bands. To ensure normal system communication, the communication frequency bands of the transmitter, antenna, and data receiver modules must be consistent. This requires accurate knowledge and calibration of the carrier frequency generated by the transmitter's VCO (voltage-controlled oscillator) within the designed range.

[0003] Currently, when performing high frequency testing, expensive high frequency testing equipment is usually used to perform high frequency testing. Although the high frequency testing equipment has good testing accuracy, the testing cost is relatively high. Summary of the Invention

[0004] The main purpose of this application is to provide a high-frequency frequency testing device, method and wireless radio frequency communication system, aiming to achieve accurate testing of high-frequency frequencies at low cost.

[0005] To achieve the above objectives, the present application proposes a high-frequency frequency testing device, comprising:

[0006] injection-locked frequency divider;

[0007] a first frequency divider connected to the injection-locked frequency divider, and configured to perform frequency reduction processing on an output signal of the injection-locked frequency divider;

[0008] a frequency divider calibration module, connected to the first frequency divider and the injection-locked frequency divider, respectively, and configured to obtain, when the injection-locked frequency divider is in a frequency divider calibration mode, a first target signal output by the first frequency divider after down-conversion processing is performed on the output signal, and determine, based on the first target signal, whether a frequency division range of the injection-locked frequency divider at a current moment includes a target frequency range corresponding to the signal to be measured; if not, adjust the capacitance value of the injection-locked frequency divider to adjust the resonant frequency of the injection-locked frequency divider to obtain a new frequency division range, until the frequency division range of the injection-locked frequency divider includes the target frequency range;

[0009] The controller is connected to the injection-locked frequency divider and is used to control the injection-locked frequency divider to enter a high-frequency test mode when the frequency division range of the injection-locked frequency divider includes the target frequency range.

[0010] In one embodiment, when the capacitance unit in the injection-locked frequency divider is a capacitance bank, the frequency divider calibration module includes a first digital signal processor;

[0011] A first input terminal of the first digital signal processor is connected to an output terminal of the first frequency divider, a second input terminal of the first digital signal processor is connected to the target frequency range, and an output terminal of the first digital signal processor is connected to a digital control signal access terminal of the injection-locked frequency divider;

[0012] The first digital signal processor is used to adjust the digital control signal of the capacitor group to adjust the capacitance value of the injection-locked frequency divider.

[0013] In one embodiment, the high frequency frequency testing device further includes a second digital signal processor;

[0014] The input end of the second digital signal processor is connected to the output end of the first frequency divider, and is used to obtain a second target signal output by the first frequency divider after down-conversion processing of the output signal when the injection-locked frequency divider is in a high-frequency test mode, and test the frequency of the signal to be tested based on the second target signal.

[0015] In one embodiment, when the capacitance unit in the injection-locked frequency divider is a variable capacitor, the frequency divider calibration module includes:

[0016] a first digital signal processor, wherein a first input end of the first digital signal processor is connected to an output end of the first frequency divider, and a second input end of the first digital signal processor is connected to the target frequency range, and is used to obtain the first target signal when the injection-locked frequency divider is in a frequency divider calibration mode, and determine, based on the first target signal, whether the frequency division range of the injection-locked frequency divider at a current moment includes the target frequency range corresponding to the signal to be measured;

[0017] a frequency detector and a filter connected to the output terminal of the first digital signal processor, configured to adjust the bias voltage of the variable capacitor to adjust the capacitance value of the injection-locked frequency divider when the frequency division range of the injection-locked frequency divider at a current moment does not include the target frequency range;

[0018] A switching element is respectively connected to the output end of the frequency detector and the filter and the bias voltage access end of the injection-locked frequency divider, and is used to enter a closed state when the injection-locked frequency divider is in a frequency divider calibration mode, and to enter an open state when the injection-locked frequency divider is in a high-frequency frequency test mode.

[0019] In one embodiment, the high frequency testing device further includes:

[0020] a second frequency divider, connected to the output end of the first frequency divider, and configured to obtain, when the injection-locked frequency divider is in a high-frequency test mode, a second target signal output by the first frequency divider after down-converting the output signal, and down-convert the second target signal to obtain a down-converted second target signal;

[0021] The third digital signal processor is connected to the output end of the second frequency divider, and is used to obtain the second target signal after frequency reduction processing output by the second frequency divider, and test the frequency of the signal to be tested according to the second target signal after frequency reduction processing.

[0022] In one embodiment, a frequency division coefficient of the second frequency divider is greater than or equal to 2.

[0023] In one embodiment, the controller is further connected to the switching element, the frequency detector, and the filter, and is further configured to:

[0024] When the injection-locked frequency divider is in a frequency divider calibration mode, controlling the switch element to enter a closed state, and controlling the frequency detector and the filter to power on;

[0025] When the injection-locked frequency divider is in a high-frequency test mode, the switch element is controlled to enter an off state, and the frequency detector and the filter are controlled to be powered off.

[0026] In one embodiment, the controller is further configured to:

[0027] When the injection-locked frequency divider is in a frequency divider calibration mode, controlling an input terminal of the injection-locked frequency divider to be empty;

[0028] When the injection-locked frequency divider is in a high-frequency test mode, the input end of the injection-locked frequency divider is controlled to access the signal to be tested.

[0029] In addition, to achieve the above-mentioned purpose, the present application also provides a wireless radio frequency communication system, which includes the high-frequency frequency testing device described above.

[0030] In addition, to achieve the above objectives, the present application also provides a high-frequency frequency testing method, the method comprising:

[0031] When the injection-locked frequency divider is in a frequency divider calibration mode, down-converting an output signal of the injection-locked frequency divider to obtain a first target signal;

[0032] determining, based on the first target signal, whether a frequency division range of the injection-locked frequency divider at a current moment includes a target frequency range corresponding to the signal to be measured;

[0033] If not, adjusting the capacitance value of the injection-locked frequency divider to adjust the resonant frequency of the injection-locked frequency divider to obtain a new frequency division range, until the frequency division range of the injection-locked frequency divider includes the target frequency range;

[0034] If so, the injection locked frequency divider is controlled to enter a high frequency test mode.

[0035] In addition, to achieve the above objectives, the present application also provides a computer-readable storage medium, on which a computer program is stored. The computer program is executed by a processor to implement the steps of the high-frequency frequency testing method described above.

[0036] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the high-frequency frequency testing method described above are implemented.

[0037] The present application provides a high-frequency frequency testing device, comprising: an injection-locked frequency divider; a first frequency divider, connected to the injection-locked frequency divider, for performing frequency reduction processing on an output signal of the injection-locked frequency divider; a frequency divider calibration module, connected to the first frequency divider and the injection-locked frequency divider, respectively, for obtaining, when the injection-locked frequency divider is in a frequency divider calibration mode, a first target signal output by the first frequency divider after performing frequency reduction processing on the output signal, and determining, based on the first target signal, whether a frequency division range of the injection-locked frequency divider at a current moment includes a target frequency range corresponding to a signal to be tested; if not, adjusting the capacitance value of the injection-locked frequency divider to obtain a new frequency division range until the frequency division range of the injection-locked frequency divider includes the target frequency range; and a controller, connected to the injection-locked frequency divider, for controlling the injection-locked frequency divider to enter a high-frequency frequency testing mode when the frequency division range of the injection-locked frequency divider includes the target frequency range.

[0038] Therefore, the technical solution provided by this application, by providing a divider calibration module, calibrates the resonant frequency of the injection-locked divider before high-frequency testing, ensuring that the frequency division range of the injection-locked divider includes the target frequency range corresponding to the signal to be tested. As a result, the technical solution provided by this application can achieve accurate high-frequency testing at a low cost, without the need for expensive high-frequency testing equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0040] Figure 1 A schematic diagram of the structure of a wireless radio frequency communication system provided in an embodiment of the present application;

[0041] Figure 2 A schematic structural diagram of an injection-locked frequency divider provided in an embodiment of the present application;

[0042] Figure 3 Another structural diagram of the injection-locked frequency divider provided in an embodiment of the present application;

[0043] Figure 4 A schematic structural diagram of a high-frequency frequency testing device provided in the first embodiment of the present application;

[0044] Figure 5 A schematic structural diagram of a high-frequency frequency testing device provided in the second embodiment of the present application;

[0045] Figure 6 This is a waveform diagram of the injection-locked frequency divider provided in the second embodiment of the present application in the frequency divider calibration mode;

[0046] Figure 7 A schematic structural diagram of the high-frequency frequency testing device provided in the second embodiment of the present application further including a second digital signal processor;

[0047] Figure 8 This is a waveform diagram of the injection-locked frequency divider provided in the second embodiment of the present application in a high-frequency test mode;

[0048] Figure 9 This is a working principle diagram of the high-frequency frequency testing device when the injection-locked frequency divider provided in the second embodiment of the present application is in the frequency divider calibration mode;

[0049] Figure 10 A diagram showing the working principle of a high-frequency test device when the injection-locked frequency divider provided in the second embodiment of the present application is in a high-frequency test mode;

[0050] Figure 11 A schematic structural diagram of a high-frequency frequency testing device provided in the third embodiment of the present application;

[0051] Figure 12 This is a waveform diagram of the injection-locked frequency divider provided in the third embodiment of the present application in the frequency divider calibration mode;

[0052] Figure 13 A schematic structural diagram of the high-frequency frequency testing device provided in the third embodiment of the present application further including a second frequency divider and a third digital signal processor;

[0053] Figure 14 This is a waveform diagram of the injection-locked frequency divider provided in the third embodiment of the present application in a high-frequency test mode;

[0054] Figure 15 This is a working principle diagram of a high-frequency frequency testing device when the injection-locked frequency divider provided in the third embodiment of the present application is in the frequency divider calibration mode;

[0055] Figure 16 A diagram showing the working principle of a high-frequency test device when the injection-locked frequency divider provided in the third embodiment of the present application is in a high-frequency test mode;

[0056] Figure 17 A flow chart of a high-frequency frequency testing method provided in an embodiment of the present application.

[0057] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0058] Description of Figure Numbers:

[0059] 10. Injection-locked frequency divider; 20. First frequency divider; 30. Frequency divider calibration module; 40. Controller; 50. Second digital signal processor; 60. Second frequency divider; 70. Third digital signal processor; 31. First digital signal processor; 32. Frequency detector and filter; VCO, voltage-controlled oscillator; S1, switch element; V TUNE , bias voltage; Vip and Vin, the input of the injection-locked frequency divider; Vop and Von, the output of the injection-locked frequency divider; VBP and VBN, the DC bias signal access terminal of the injection-locked frequency divider; T Cal , calibration sampling time; VDD1~VDD2, power supply voltage; GND1~GND2, ground; C1~C n , capacitance; C var , variable capacitor; En, calibration signal; RST, reset signal; L, inductor. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0061] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0062] In addition, the descriptions of "first", "second", etc. in this application are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0063] In the field of wireless radio frequency communication, in order to increase channel capacity and reduce interference between different frequency bands, high-frequency signals in different frequency bands are often used as data transmission carriers, that is, carriers. Figure 1 The mixed signal in the figure is the coupling of the transmitted data and the carrier. RX (Receiver) is the receiving end, PA (Power Amplifier) ​​is the power amplifier, LNA (Low Noise Amplifier) ​​is the low noise amplifier, VDD1 and VDD2 are the power supply voltages, and GND1 and GND2 are grounds. To ensure normal system communication, the communication frequency bands of the transmitter, antenna, and data receiver modules must be in the same range. This requires accurately knowing and calibrating the carrier frequency generated by the transmitter VCO to within the designed range.

[0064] Currently, the common practice is to build a frequency divider into the TX (Transmitter) to divide the frequency signal generated by the VCO into a low-frequency output. The VCO resonant frequency is then calculated by measuring the frequency of the output low-frequency signal and multiplying it by the division coefficient. The frequency divider only works at the test frequency to reduce system power consumption.

[0065] However, when the VCO's resonant frequency is in the millimeter-wave band (30 GHz to 300 GHz), conventional frequency dividers are insufficient. In this case, the first or first few stages of the frequency divider often require an injection-locked frequency divider (ILFD) to be effective. However, ILFDs can experience frequency drift due to factors such as process variations, and their frequency division range is often unclear. This can cause the actual frequency division range of the frequency divider to differ from the designed range, thus affecting high-frequency test accuracy.

[0066] In order to ensure the test accuracy of high frequency, expensive high frequency test equipment is currently used to complete the test, but the test cost is relatively high.

[0067] The commonly used structure of injection locked frequency divider can be referred to Figure 2 and Figure 3 (Vip and Vin in the figure are the input terminals of the injection-locked divider, VBP and VBN are the DC bias signal access terminals of the injection-locked divider, and Vop and Von are the output terminals of the injection-locked divider). It consists of a VCO and an input circuit (in order to distinguish it from the VCO in TX, the VCO in the injection-locked divider will be referred to as DVCO). In the input circuit, the injection pair PMOS / NMOS is used to convert the signal to be measured into a current signal to couple into the DVCO; two resistors are used to isolate the DC bias signal from the input signal to be measured; and two capacitors are used to couple the injected signal to be measured. The frequency division mechanism of the injection-locked divider is: if the resonant frequency of the DVCO is , then the frequency division range of the injection-locked frequency divider is ;in, Related to the swing of the input signal to be measured, Frequency drift may occur due to factors such as process deviation. Therefore, the frequency division range of the injection-locked frequency divider is often unclear, which will cause the actual frequency division range of the frequency divider to be inconsistent with the designed range.

[0068] Based on this, in order to ensure that the frequency division range of the injection locked frequency divider can be adjusted to the design value during the test, the present application relates to a DVCO resonant frequency A calibrable mechanism that automatically calibrates the resonant frequency of the injection-locked divider using the target frequency range corresponding to the signal under test in divider calibration mode , so that the frequency division range of the injection-locked frequency divider includes the target frequency range, thereby ensuring that the injection-locked frequency divider can accurately divide the signal to be tested during the test.

[0069] It is understood that the resonant frequency of the inductor-capacitor VCO can be expressed as the following formula 1:

[0070] Formula 1;

[0071] in, is the resonant frequency, L is the inductance, and C is the capacitance. As can be seen from Formula 1, the resonant frequency can be adjusted by adjusting the inductance and capacitance. However, since the inductance is usually difficult to adjust, the resonant frequency is usually adjusted by adjusting the capacitance.

[0072] The capacitor unit in the injection-locked frequency divider can be Figure 2 The capacitor bank shown can also be Figure 3 The variable capacitor shown. Therefore, the capacitance value of the injection-locked frequency divider can be adjusted in two ways. Specifically:

[0073] When the capacitor unit in the injection-locked frequency divider is Figure 2 When the capacitor group shown is <n:1>That is, a set of digital control signals for the capacitor group (for example, assuming the capacitor group includes three capacitors, that is, n is 3, then a set of digital control signals can include three digital control signals: 100, 110, and 111). By inputting different digital control signals, the capacitance value of the injection-locked frequency divider can be changed, and the resonant frequency under various digital control signals can be obtained as follows:

[0074]

[0075] in, ~ are the resonant frequencies under different digital control signals, ~ is each capacitor in the capacitor group. It can be seen that the designable frequency division range of the injection locked frequency divider is , it is necessary to ensure during design 、 、…、 The difference between two adjacent values ​​is less than .

[0076] When the capacitor unit in the injection-locked frequency divider is Figure 3 When the variable capacitor is shown, the capacitance calculation formula of the variable capacitor can be expressed as the following formula 2:

[0077] Formula 2;

[0078] in, is the capacitance of the variable capacitor, is the bias voltage, is the capacitance of the variable capacitor at zero bias (i.e. the capacitance of the variable capacitor when the bias voltage is zero), is a parameter related to the characteristics of semiconductor materials. It is determined by the process of variable capacitors. It reflects the inherent electrical characteristics of the material and affects the relationship between the capacitance value and the bias voltage. m is also determined by the process of variable capacitors. It determines the rate at which the capacitance value changes with the bias voltage. Therefore, by changing the bias voltage, the size of the variable capacitor can be adjusted, resulting in the following formulas 3 and 4:

[0079] Formula 3;

[0080] in, is the minimum resonant frequency of the injection-locked frequency divider.

[0081] Formula 4;

[0082] in, is the maximum resonant frequency of the injection-locked frequency divider, is the power supply voltage.

[0083] It can be seen from this that the designable frequency division range of the injection-locked frequency divider is .

[0084] Based on this, the first embodiment of the present application proposes a high frequency frequency testing device, please refer to Figure 4 , the high frequency test device may include:

[0085] Injection locked frequency divider 10;

[0086] The first frequency divider 20 is connected to the injection-locked frequency divider 10 and is used to perform frequency reduction processing on the output signal of the injection-locked frequency divider 10;

[0087] The frequency divider calibration module 30 is connected to the first frequency divider 20 and the injection-locked frequency divider 10, respectively, and is used to obtain a first target signal output by the first frequency divider 20 after down-conversion processing is performed on the output signal when the injection-locked frequency divider 10 is in the frequency divider calibration mode, and determine, based on the first target signal, whether the frequency division range of the injection-locked frequency divider 10 at a current moment includes the target frequency range corresponding to the signal to be measured; if not, adjust the capacitance value of the injection-locked frequency divider 10 to adjust the resonant frequency of the injection-locked frequency divider 10 to obtain a new frequency division range, until the frequency division range of the injection-locked frequency divider 10 includes the target frequency range;

[0088] The controller 40 is connected to the injection-locked frequency divider 10 and is used to control the injection-locked frequency divider 10 to enter a high-frequency test mode when the frequency division range of the injection-locked frequency divider 10 includes the target frequency range.

[0089] It should be noted that the resonant frequency of the injection-locked frequency divider mentioned in this embodiment and the following embodiments actually refers to the resonant frequency of the VCO in the injection-locked frequency divider. When the injection-locked frequency divider 10 is in the frequency divider calibration mode, the first frequency divider 20 downconverts its output signal, and the resulting signal is the first target signal. The signal to be measured is a high-frequency signal of the frequency to be tested. Generally speaking, the user can know the approximate frequency range of the signal to be measured, and this approximate frequency range is the target frequency range corresponding to the signal to be measured.

[0090] Additionally, it should be noted that the output signal of the injection-locked frequency divider 10 is a high-frequency signal, while the frequency divider calibration module 30 can only process signals with lower frequencies. Therefore, the first frequency divider 20 is required to down-convert the output signal of the injection-locked frequency divider 10. The frequency divider calibration module 30 can determine the current resonant frequency of the injection-locked frequency divider 10 by counting the number of pulses of the first target signal within a certain period of time (such as the calibration sampling duration). When adjusting the capacitance value of the injection-locked frequency divider 10, if the current resonant frequency of the injection-locked frequency divider 10 is less than the set target resonant frequency (i.e., the upper and lower limits of the frequency division range of the injection-locked frequency divider 10 are less than the upper and lower limits of the target frequency range), the resonant frequency of the injection-locked frequency divider 10 can be increased by reducing the capacitance value of the injection-locked frequency divider 10 (i.e., the upper and lower limits of the frequency division range of the injection-locked frequency divider 10 are increased). Similarly, if the current resonant frequency of the injection-locked frequency divider 10 is greater than the target resonant frequency, it can also be adjusted to the target resonant frequency by increasing the capacitance value of the injection-locked frequency divider 10.

[0091] In combination with the above content, it can be seen that the technical solution provided by this embodiment is to calibrate the resonant frequency of the injection-locked frequency divider 10 before performing the high-frequency test by setting the divider calibration module 30, so that the frequency division range of the injection-locked frequency divider 10 includes the target frequency range corresponding to the signal to be measured. Therefore, the technical solution provided by this embodiment does not need to use expensive high-frequency test equipment, and can achieve accurate testing of high-frequency frequencies at a low cost. Among them, in actual use, it is only necessary to ensure that the frequency of the signal to be measured is within the frequency division range of the injection-locked frequency divider 10. On this basis, in other embodiments, when the frequency of the signal to be measured is not within the frequency division range currently set by the injection-locked frequency divider 10, the frequency division range of the injection-locked frequency divider 10 can also be adjusted to continue measuring until the frequency of the signal to be measured is measured.

[0092] In addition, in the technical solution provided in this embodiment, the resonant frequency of the injection-locked frequency divider 10 is a settable range value (that is, it can be within the resonant frequency range mentioned above). or Therefore, the technical solution provided by this embodiment can further expand the frequency divisible range of the frequency divider.

[0093] Based on the above first embodiment, a second embodiment of the high frequency test device of the present application is proposed. In the second embodiment, please refer to Figure 5 , in the case where the capacitance unit in the injection-locked frequency divider 10 is a capacitance group, the frequency divider calibration module 30 includes a first digital signal processor 31;

[0094] A first input terminal of the first digital signal processor 31 is connected to the output terminal of the first frequency divider 20, a second input terminal of the first digital signal processor 31 is connected to the target frequency range, and an output terminal of the first digital signal processor 31 is connected to the digital control signal access terminal of the injection locked frequency divider 10;

[0095] The first digital signal processor 31 is used to adjust the digital control signal of the capacitor bank to adjust the capacitance value of the injection-locked frequency divider 10 .

[0096] It should be noted that when the injection-locked frequency divider 10 is in the frequency divider calibration mode, the first digital signal processor 31 obtains the first target signal and determines, based on the first target signal, whether the frequency division range of the injection-locked frequency divider 10 at the current moment includes the target frequency range; if it is determined that the frequency division range of the injection-locked frequency divider 10 at the current moment does not include the target frequency range, when adjusting the capacitance value of the injection-locked frequency divider 10, the capacitance value of the injection-locked frequency divider 10 can be adjusted by adjusting the digital control signal of the capacitor group. For example, assuming that the capacitor group includes three capacitors, the resonant frequency of the injection-locked frequency divider 10 at the current moment is less than the target resonant frequency, and the digital control signal of the capacitor group at the current moment is 111, the digital control signal of the capacitor group can be adjusted from 111 to 110 to reduce the capacitance value of the injection-locked frequency divider 10, thereby increasing the resonant frequency of the injection-locked frequency divider, which means that the upper and lower limits of the frequency division range of the injection-locked frequency divider 10 are increased.

[0097] In one possible implementation, please refer to Figure 5 The third input terminal of the first digital signal processor 31 can be connected to the reference clock to use the reference clock to determine the resonant frequency of the injection-locked frequency divider 10. Specifically, the process of determining the resonant frequency of the injection-locked frequency divider 10 can be expressed as the following formula 5:

[0098] Formula 5;

[0099] in, is the resonant frequency of the injection-locked frequency divider 10, M is the frequency division coefficient of the first frequency divider 20, To calibrate the sampling time, is the number of pulses of the first target signal within the calibration sampling duration.

[0100] In one possible implementation, please refer to Figure 5 The first digital signal processor 31 can also output a calibration completion (Caldone) signal to indicate that the calibration of the resonant frequency is completed. On this basis, taking the calibration with the target resonant frequency corresponding to the test signal (the target resonant frequency refers to the resonant frequency that the injection-locked frequency divider 10 needs to reach in order to test the frequency of the test signal) as an example, the waveform diagram of the injection-locked frequency divider 10 in the divider calibration mode can be referred to. Figure 6 , specifically:

[0101] When the resonant frequency of the injection-locked frequency divider 10 at the current moment is relatively high, that is, the resonant frequency at the current moment is greater than the target resonant frequency, the number of pulses of the first target signal within the calibration sampling period is relatively large (that is, >N pulses in the figure), and the first digital signal processor 31 will not output a calibration completion signal (the calibration completion signal in the corresponding figure always maintains a low level); when the resonant frequency of the injection-locked frequency divider 10 at the current moment is relatively low, that is, the resonant frequency at the current moment is less than the target resonant frequency, the number of pulses of the first target signal within the calibration sampling period is relatively small (that is, <N pulses in the figure), and the first digital signal processor 31 will not output a calibration completion signal (the calibration completion signal in the corresponding figure always maintains a low level); when the resonant frequency of the injection-locked frequency divider 10 at the current moment is consistent with the target resonant frequency, the number of pulses of the first target signal within the calibration sampling period is N, and the first digital signal processor 31 will output a calibration completion signal (the calibration completion signal in the corresponding figure will be converted from a low level to a high level).

[0102] For further information, please refer to Figure 7 , the high frequency test device may further include a second digital signal processor 50;

[0103] The input end of the second digital signal processor 50 is connected to the output end of the first frequency divider 20, and is used to obtain the second target signal output by the first frequency divider 20 after down-conversion processing of the output signal when the injection-locked frequency divider 10 is in the high-frequency test mode, and test the frequency of the signal to be tested based on the second target signal.

[0104] It should be noted that the output signal of the injection-locked frequency divider 10 is a high-frequency signal, while the digital signal processor can only process signals with lower frequencies. Therefore, the first frequency divider 20 is required to downconvert the output signal of the injection-locked frequency divider 10. When the injection-locked frequency divider 10 is in high-frequency test mode, the first frequency divider 20 downconverts its output signal, resulting in the second target signal. The second digital signal processor 50 measures the frequency of the signal to be measured by counting the number of pulses of the second target signal within a certain period of time (e.g., the calibration sampling period).

[0105] In one possible implementation, please refer to Figure 7 The second digital signal processor 50 may also be connected to a reset signal RST to use it to initialize the internal state of the second digital signal processor 50 to ensure the accuracy of the frequency calculation.

[0106] In one possible implementation, please refer to Figure 7 The second digital signal processor 50 can also be connected to a reference clock to use the reference clock to determine the frequency of the signal to be measured. Specifically, the process of determining the frequency of the signal to be measured can be expressed as the following formula 6:

[0107] Formula 6;

[0108] in, is the frequency of the signal to be measured, M is the frequency division coefficient of the first frequency divider 20, is the calibration sampling time when the calibration is completed, is the number of pulses of the second target signal within the calibration sampling time.

[0109] On this basis, the waveform diagram of the injection locked frequency divider 10 in the high frequency test mode can be referred to as Figure 8 , specifically:

[0110] After the input end of the injection-locked frequency divider 10 is connected to the test signal, the test signal is divided by the test signal and down-converted by the first frequency divider 20 to form a second target signal with a lower frequency, which is input to the second digital signal processor 50; thereafter, the second input signal processor can test and obtain the frequency of the test signal by using the above formula 6.

[0111] It is understood that at high frequency the test device is Figure 7 In the structure shown, in order to ensure that when the injection-locked frequency divider 10 is in the frequency divider calibration mode, the calibration of the resonant frequency will not be disturbed by the signal to be measured, and the system will not generate unnecessary power consumption. The controller 40 can control the input terminals Vip and Vin of the injection-locked frequency divider 10 to be empty, and the second digital signal processor 50 does not need to work. Therefore, the working principle of the high-frequency frequency test device can be referred to Figure 9 To ensure that the high-frequency test device can perform frequency testing normally when the injection-locked frequency divider 10 is in high-frequency test mode, and the system does not generate unnecessary power consumption, the controller 40 can control the input terminals Vip and Vin of the injection-locked frequency divider 10 to access the test signal, and the first digital signal processor 31 does not need to work. Therefore, the working principle of the high-frequency test device can be referred to Figure 10 .

[0112] Based on the above first embodiment, a third embodiment of the high frequency test device of the present application is proposed. In the third embodiment, please refer to Figure 11 In the case where the capacitance unit in the injection-locked frequency divider 10 is a variable capacitor, the frequency divider calibration module 30 may include:

[0113] a first digital signal processor 31, wherein a first input end of the first digital signal processor 31 is connected to an output end of the first frequency divider 20, and a second input end of the first digital signal processor 31 is connected to a target frequency range, and is configured to obtain a first target signal when the injection-locked frequency divider 10 is in a frequency divider calibration mode, and determine, based on the first target signal, whether the frequency division range of the injection-locked frequency divider 10 at a current moment includes the target frequency range;

[0114] The frequency detector and filter 32 is connected to the output terminal of the first digital signal processor 31 and is used to adjust the bias voltage V of the variable capacitor when the current frequency division range of the injection locked frequency divider 10 does not include the target frequency range. TUNE , to adjust the capacitance value of the injection-locked frequency divider 10;

[0115] The switching element S1 is respectively connected to the output end of the frequency detector and filter 32 and the bias voltage access end of the injection-locked frequency divider 10, and is used to enter a closed state when the injection-locked frequency divider 10 is in the divider calibration mode, and to enter an open state when the injection-locked frequency divider 10 is in the high-frequency test mode.

[0116] In one possible implementation, please refer to Figure 11 The third input terminal of the first digital signal processor 31 can be connected to the reference clock to determine the resonant frequency of the injection-locked frequency divider 10 using the reference clock.

[0117] In one possible implementation, please refer to Figure 11 The first digital signal processor 31 may also output a calibration completion signal to indicate that the calibration of the resonant frequency is completed.

[0118] In one possible implementation, please refer to Figure 11 The first digital signal processor 31 can also output a calibration signal to the frequency detector and filter 32 to instruct the frequency detector and filter 32 to adjust the bias voltage V TUNE adjustments.

[0119] On this basis, taking the target resonant frequency corresponding to the test signal (the target resonant frequency refers to the resonant frequency that the injection-locked frequency divider 10 needs to reach in order to test the frequency of the test signal) as an example for calibration, the waveform diagram of the injection-locked frequency divider 10 in the divider calibration mode can be referred to. Figure 12 , specifically:

[0120] When the current resonant frequency of the injection-locked frequency divider 10 is too high, that is, the current resonant frequency is greater than the target resonant frequency, the number of pulses of the first target signal within the calibration sampling time is too large (that is, >X pulses in the figure), and the first digital signal processor 31 will not output a calibration completion signal (corresponding to the calibration completion signal in the figure always maintaining a low level), and the first digital signal processor 31 will continue to output a calibration signal to the frequency detector and filter 32 (corresponding to the En signal in the figure always maintaining a high level), and the frequency detector and filter 32 will gradually reduce the bias voltage V of the variable capacitor. TUNE When the current resonant frequency of the injection-locked frequency divider 10 is too low, that is, the current resonant frequency is less than the target resonant frequency, the number of pulses of the first target signal within the calibration sampling time is too small (that is, <X pulses in the figure), and the first digital signal processor 31 will not output a calibration completion signal (corresponding to the calibration completion signal in the figure always maintaining a low level), and the first digital signal processor 31 will continue to output a calibration signal to the frequency detector and filter 32 (corresponding to the En signal in the figure always maintaining a high level), and the frequency detector and filter 32 will gradually increase the bias voltage V of the variable capacitor. TUNE When the current resonant frequency of the injection-locked frequency divider 10 is consistent with the target resonant frequency, the number of pulses of the first target signal within the calibration sampling period is X, and the first digital signal processor 31 outputs a calibration completion signal (the calibration completion signal in the corresponding figure will be converted from a low level to a high level), and the first digital signal processor 31 stops outputting the calibration signal to the frequency detector and the filter 32 (the En signal in the corresponding figure will be converted from a high level to a low level) to maintain the bias voltage V TUNE size.

[0121] Further, in a feasible implementation, please refer to Figure 13 , the high frequency test device may further include:

[0122] a second frequency divider 60 connected to the output end of the first frequency divider 20, and configured to obtain, when the injection-locked frequency divider 10 is in the high-frequency test mode, a second target signal output by the first frequency divider 20 after down-converting the output signal, and down-convert the second target signal to obtain the down-converted second target signal;

[0123] The third digital signal processor 70 is connected to the output end of the second frequency divider 60, and is used to obtain the second target signal after frequency reduction output by the second frequency divider 60, and test the frequency of the signal to be tested according to the second target signal after frequency reduction.

[0124] It is understandable that from a sampling perspective, when the frequencies of the two are consistent, according to the Nyquist sampling theorem, the sampled signal may not be able to accurately restore the original signal characteristics, and aliasing may occur. Therefore, in order to avoid the signal received by the third digital signal processor 70 being consistent with the frequency of the connected reference clock to ensure the test accuracy of high-frequency frequencies, a second frequency divider 60 can be set between the first frequency divider 20 and the third digital signal processor 70 to further down-convert the second target signal to obtain a down-converted second target signal; wherein, the frequency division coefficient of the second frequency divider 60 needs to be greater than or equal to 2.

[0125] It should be noted that the third digital signal processor 70 can measure and obtain the frequency of the signal to be measured by counting the number of pulses of the second target signal after frequency reduction processing within a certain period of time (such as the calibration sampling period).

[0126] In one possible implementation, please refer to Figure 13 The third digital signal processor 70 can also be connected to a reference clock to use the reference clock to determine the frequency of the signal to be measured. Specifically, the process of determining the frequency of the signal to be measured can be expressed as the following formula 7:

[0127] Formula 7;

[0128] in, is the frequency of the signal to be measured, M is the frequency division coefficient of the first frequency divider 20, Y is the frequency division coefficient of the second frequency divider 60, To calibrate the sampling time, is the number of pulses of the second target signal after frequency reduction processing within the calibration sampling time.

[0129] On this basis, the waveform diagram of the injection locked frequency divider 10 in the high frequency test mode can be referred to as Figure 14 , specifically:

[0130] After the input end of the injection-locked frequency divider 10 is connected to the signal to be tested, the signal to be tested is divided by the signal to be tested, and is frequency-reduced by the first frequency divider 20 and the second frequency divider 60, thereby forming a signal with a lower frequency to be input to the third digital signal processor 70. Thereafter, the third digital signal processor 70 can test and obtain the frequency of the signal to be tested by using the above formula 7.

[0131] In a feasible embodiment, the controller 40 can also be connected to the switch element S1 and the frequency detector and filter 32. On this basis, in order to ensure that when the injection-locked frequency divider 10 is in the frequency divider calibration mode, the calibration of the resonant frequency will not be interfered with by the signal to be measured, and the system will not generate unnecessary power consumption; the controller 40 can control the input terminals Vip and Vin of the injection-locked frequency divider 10 to be empty, and control the switch element S1 to enter the closed state, and control the frequency detector and filter 32 to be powered on, and the second frequency divider 60 and the third digital signal processor 70 do not need to work. Therefore, the working principle of the high-frequency frequency test device can be referred to Figure 15 To ensure that the high-frequency test device can perform frequency testing normally when the injection-locked frequency divider 10 is in high-frequency test mode, and the system does not generate unnecessary power consumption, the controller 40 can control the input terminals Vip and Vin of the injection-locked frequency divider 10 to access the signal to be tested, and control the switch element S1 to enter the disconnected state, as well as control the frequency detector and the filter 32 to power off, and the first digital signal processor 31 does not need to work. Therefore, the working principle of the high-frequency test device can be referred to Figure 16 .

[0132] An embodiment of the present application further provides a wireless radio frequency communication system, which may include the high-frequency frequency testing device in the above embodiments. The structure of the high-frequency frequency testing device is specifically as described above and will not be repeated here.

[0133] The wireless RF communication system provided in this embodiment can achieve accurate testing of high frequencies at a low cost. Since the wireless RF communication system of this embodiment includes all technical solutions of all embodiments of the high-frequency frequency testing device described above, and the technical effects achieved are exactly the same, they will not be described in detail here.

[0134] The present application also provides a high frequency frequency testing method, please refer to Figure 17 The high frequency testing method may include steps S10 to S40:

[0135] Step S10, when the injection-locked frequency divider is in a frequency divider calibration mode, down-converting the output signal of the injection-locked frequency divider to obtain a first target signal;

[0136] Step S20, determining whether the frequency division range of the injection-locked frequency divider at the current moment includes the target frequency range corresponding to the signal to be measured based on the first target signal;

[0137] Step S30: If not, adjust the capacitance value of the injection-locked frequency divider to adjust the resonant frequency of the injection-locked frequency divider to obtain a new frequency division range, until the frequency division range of the injection-locked frequency divider includes the target frequency range;

[0138] Step S40: If yes, control the injection locked frequency divider to enter a high frequency test mode.

[0139] In one embodiment, when the capacitor unit in the injection-locked frequency divider is a capacitor bank, step S30 may include:

[0140] The digital control signal of the capacitor bank is adjusted to adjust the capacitance value of the injection-locked frequency divider.

[0141] In one embodiment, after step S40, the high frequency testing method may further include:

[0142] When the injection-locked frequency divider is in a high-frequency test mode, down-converting the output signal of the injection-locked frequency divider to obtain a second target signal;

[0143] The frequency of the signal to be tested is tested according to the second target signal.

[0144] In one embodiment, when the capacitor unit in the injection-locked frequency divider is a variable capacitor, step S30 may include:

[0145] The bias voltage of the variable capacitor is adjusted to adjust the capacitance value of the injection-locked frequency divider.

[0146] In one embodiment, after step S40, the high frequency testing method may further include:

[0147] When the injection-locked frequency divider is in a high-frequency test mode, down-converting the output signal of the injection-locked frequency divider to obtain a second target signal;

[0148] performing frequency reduction processing on the second target signal to obtain a frequency-reduced second target signal;

[0149] The frequency of the signal to be tested is tested according to the second target signal after the frequency reduction processing.

[0150] In one embodiment, the high frequency testing method may further include:

[0151] When the injection-locked frequency divider is in a frequency divider calibration mode, controlling a switch element in the high-frequency frequency test device to enter a closed state, and controlling a frequency detector and a filter in the high-frequency frequency test device to power on;

[0152] When the injection-locked frequency divider is in a high-frequency test mode, the switch element is controlled to enter an off state, and the frequency detector and the filter are controlled to be powered off.

[0153] In one embodiment, the high frequency testing method may further include:

[0154] When the injection locked frequency divider is in the frequency divider calibration mode, controlling the input terminal of the injection locked frequency divider to be empty;

[0155] When the injection-locked frequency divider is in a high-frequency test mode, the input end of the injection-locked frequency divider is controlled to access a signal to be tested.

[0156] The high-frequency frequency testing method provided in this embodiment can achieve accurate high-frequency frequency testing at a low cost. Compared with the prior art, the high-frequency frequency testing method of this embodiment has the same beneficial effects as the high-frequency frequency testing device provided in the above-mentioned embodiment. The other technical features of this high-frequency frequency testing method are the same as those disclosed in the above-mentioned embodiment and are not further described here.

[0157] In addition, an embodiment of the present application further provides a computer-readable storage medium storing a computer program that can be run on a processor, and the computer program is used to execute the high-frequency frequency testing method in the above embodiment.

[0158] The computer-readable storage medium provided in the embodiments of the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0159] The computer-readable storage medium may be included in the high-frequency test device, or may exist independently without being assembled into the high-frequency test device.

[0160] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by a high-frequency frequency testing device, the high-frequency frequency testing device: when the injection-locked frequency divider is in a frequency divider calibration mode, performs frequency reduction processing on the output signal of the injection-locked frequency divider to obtain a first target signal; based on the first target signal, determines whether the frequency division range of the injection-locked frequency divider at the current moment includes the target frequency range corresponding to the signal to be tested; if not, adjusts the capacitance value of the injection-locked frequency divider to adjust the resonant frequency of the injection-locked frequency divider to obtain a new frequency division range until the frequency division range of the injection-locked frequency divider includes the target frequency range; if so, controls the injection-locked frequency divider to enter a high-frequency frequency testing mode.

[0161] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0162] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0163] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0164] The computer-readable storage medium provided in the embodiments of the present application stores computer-readable program instructions for executing the high-frequency frequency testing method described above, enabling accurate high-frequency frequency testing at a low cost. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided in the embodiments of the present application are the same as those of the high-frequency frequency testing method provided in the embodiments described above, and are not further elaborated here.

[0165] In addition, an embodiment of the present application also provides a computer program product, including a computer program, which implements the high-frequency frequency testing method as described above when the computer program is executed by a processor.

[0166] The computer program product provided in the embodiment of the present application can achieve accurate testing of high-frequency frequencies at a low cost. Compared with the prior art, the beneficial effects of the computer program product provided in the embodiment of the present application are the same as the beneficial effects of the high-frequency frequency testing method provided in the above embodiment, and will not be repeated here.

[0167] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made based on the contents of the present application specification and drawings, or direct / indirect application in other related technical fields, are included in the patent protection scope of the present application.

Claims

1. A high frequency frequency testing device, characterized in that, include: injection-locked frequency divider; a first frequency divider connected to the injection-locked frequency divider, and configured to perform frequency reduction processing on an output signal of the injection-locked frequency divider; a frequency divider calibration module, connected to the first frequency divider and the injection-locked frequency divider, respectively, and configured to obtain, when the injection-locked frequency divider is in a frequency divider calibration mode, a first target signal output by the first frequency divider after down-conversion processing is performed on the output signal, and determine, based on the first target signal, whether a frequency division range of the injection-locked frequency divider at a current moment includes a target frequency range corresponding to the signal to be measured; if not, adjust the capacitance value of the injection-locked frequency divider to adjust the resonant frequency of the injection-locked frequency divider to obtain a new frequency division range, until the frequency division range of the injection-locked frequency divider includes the target frequency range; The controller is connected to the injection-locked frequency divider and is used to control the injection-locked frequency divider to enter a high-frequency test mode when the frequency division range of the injection-locked frequency divider includes the target frequency range.

2. The high frequency test device according to claim 1, characterized in that: In the case where the capacitance unit in the injection-locked frequency divider is a capacitance bank, the frequency divider calibration module includes a first digital signal processor; A first input terminal of the first digital signal processor is connected to an output terminal of the first frequency divider, a second input terminal of the first digital signal processor is connected to the target frequency range, and an output terminal of the first digital signal processor is connected to a digital control signal access terminal of the injection-locked frequency divider; The first digital signal processor is used to adjust the digital control signal of the capacitor group to adjust the capacitance value of the injection-locked frequency divider.

3. The high frequency test device according to claim 2, characterized in that: The high frequency testing device further includes a second digital signal processor; The input end of the second digital signal processor is connected to the output end of the first frequency divider, and is used to obtain a second target signal output by the first frequency divider after down-conversion processing of the output signal when the injection-locked frequency divider is in a high-frequency test mode, and test the frequency of the signal to be tested based on the second target signal.

4. The high frequency test device according to claim 1, wherein: In the case where the capacitance unit in the injection-locked frequency divider is a variable capacitor, the frequency divider calibration module includes: a first digital signal processor, wherein a first input end of the first digital signal processor is connected to an output end of the first frequency divider, and a second input end of the first digital signal processor is connected to the target frequency range, and is used to obtain the first target signal when the injection-locked frequency divider is in a frequency divider calibration mode, and determine, based on the first target signal, whether the frequency division range of the injection-locked frequency divider at a current moment includes the target frequency range corresponding to the signal to be measured; a frequency detector and a filter connected to the output terminal of the first digital signal processor, configured to adjust the bias voltage of the variable capacitor to adjust the capacitance value of the injection-locked frequency divider when the frequency division range of the injection-locked frequency divider at a current moment does not include the target frequency range; A switching element is respectively connected to the output end of the frequency detector and the filter and the bias voltage access end of the injection-locked frequency divider, and is used to enter a closed state when the injection-locked frequency divider is in a frequency divider calibration mode, and to enter an open state when the injection-locked frequency divider is in a high-frequency frequency test mode.

5. The high frequency test device according to claim 4, characterized in that: The high frequency testing device also includes: a second frequency divider, connected to the output end of the first frequency divider, and configured to obtain, when the injection-locked frequency divider is in a high-frequency test mode, a second target signal output by the first frequency divider after down-converting the output signal, and down-convert the second target signal to obtain a down-converted second target signal; The third digital signal processor is connected to the output end of the second frequency divider, and is used to obtain the second target signal after frequency reduction processing output by the second frequency divider, and test the frequency of the signal to be tested according to the second target signal after frequency reduction processing.

6. The high frequency test device according to claim 5, characterized in that: The frequency division coefficient of the second frequency divider is greater than or equal to 2.

7. The high frequency test device according to claim 4, characterized in that: The controller is further connected to the switching element, the frequency detector and the filter, and is further configured to: When the injection-locked frequency divider is in a frequency divider calibration mode, controlling the switch element to enter a closed state, and controlling the frequency detector and the filter to power on; When the injection-locked frequency divider is in a high-frequency test mode, the switch element is controlled to enter an off state, and the frequency detector and the filter are controlled to be powered off.

8. The high-frequency frequency testing device according to any one of claims 1 to 7, characterized in that: The controller is also used to: When the injection-locked frequency divider is in a frequency divider calibration mode, controlling an input terminal of the injection-locked frequency divider to be empty; When the injection-locked frequency divider is in a high-frequency test mode, the input end of the injection-locked frequency divider is controlled to access the signal to be tested.

9. A wireless radio frequency communication system, characterized in that: The wireless radio frequency communication system includes the high frequency test device according to any one of claims 1 to 8.

10. A high frequency frequency testing method, characterized in that, The method comprises: When the injection-locked frequency divider is in a frequency divider calibration mode, down-converting an output signal of the injection-locked frequency divider to obtain a first target signal; determining, based on the first target signal, whether a frequency division range of the injection-locked frequency divider at a current moment includes a target frequency range corresponding to the signal to be measured; If not, adjusting the capacitance value of the injection-locked frequency divider to adjust the resonant frequency of the injection-locked frequency divider to obtain a new frequency division range, until the frequency division range of the injection-locked frequency divider includes the target frequency range; If so, the injection locked frequency divider is controlled to enter a high frequency test mode.

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