Process method applied to memory manufacturing
By using the CDE process to trim the floating gate polysilicon layer during the NOR flash memory manufacturing process, the sharp corner protrusion defects at the edge of the floating gate are solved, and the reliability and yield of the flash memory are improved.
Patent Information
- Application Number
- CN202510480724.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2025-08-12
AI Technical Summary
During the NOR flash memory manufacturing process, the floating gate edge is prone to sharp corner protrusion defects, causing electrons to escape, affecting device performance and reliability.
After deposition, etching, and etching of the floating gate polysilicon layer, the floating gate polysilicon layer is trimmed by using the CDE process to remove sharp corner protrusions to form a floating gate of the flash memory.
Effectively remove sharp corner protrusions at the edge of the floating gate, improving the reliability and yield of flash memory products.
Smart Images
Figure CN120475715A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a process method used in memory manufacturing. Background Art
[0002] Non-volatile memory (NVM) is a widely used information storage device that stores 0 / 1 information by storing charge on a floating gate (FG). It also has good resistance to magnetic interference when there is no power maintenance.
[0003] Among NVM memories, NOR (not-or) flash memory is based on Intel's tunnel oxide (ETOX) non-volatile memory structure. It is a voltage-controlled device that uses hot electron injection to write data and tunneling to erase data. Its notable feature is its fast random read speed. As an NVM memory, NOR flash memory offers high device density, low power consumption, and electrical rewritability. It is widely used in electronic storage devices such as smartphones, tablets, digital cameras, and USB flash drives (U disks).
[0004] In the related art, during the NOR flash memory manufacturing process, the floating gate is formed through a sequential process of polysilicon deposition, planarization, dry etching, and shallow trench isolation (STI) wet etching. However, after the STI wet etching, a protruding "pointed corner" defect is easily formed at the edge of the floating gate. When the flash memory device is operating, this protruding corner is prone to cause a tip discharge effect, allowing electrons in the floating gate to escape from the sharp corner, thereby affecting the performance of the flash memory and reducing product reliability and yield. Summary of the Invention
[0005] The present application provides a process method for memory manufacturing, which can solve the problem that the manufacturing method of the flash memory floating gate provided in the related art is prone to forming sharp corner protrusion defects on the floating gate edge. The method includes:
[0006] A wafer is provided, wherein an area on the wafer for forming semiconductor devices includes a first area and a second area, the first area being used to form a flash memory device, and the second area being used to form a logic device. A pad oxide layer is formed on the wafer, and a first STI structure is formed in the wafer in the first area, wherein a top of the first STI structure is higher than a top of the pad oxide layer.
[0007] Depositing a floating gate polysilicon layer in the first region, wherein the floating gate polysilicon layer fills the first trench between the first STI structures;
[0008] Etching the floating gate polysilicon layer so that a top of the floating gate polysilicon layer is lower than a top of the first STI structure;
[0009] Etching the first STI structure so that a top of the first STI structure is lower than a top of the floating gate polysilicon layer;
[0010] The floating gate polysilicon layer is trimmed through the CDE process to remove the sharp protrusions at the edge of the floating gate polysilicon layer. The remaining floating gate polysilicon layer constitutes the floating gate of the flash memory.
[0011] In some embodiments, etching the floating gate polysilicon layer includes:
[0012] The floating gate polysilicon layer is etched by a dry etching process.
[0013] In some embodiments, the dry etching process is performed in an ICP machine.
[0014] In some embodiments, etching the first STI structure includes:
[0015] The first STI structure is etched by a wet etching process.
[0016] In some embodiments, a second STI structure is formed in the wafer in the second region, and a top of the second STI structure is higher than a top of the pad oxide layer;
[0017] A first nitride layer is filled between the second STI structures in the second region, a first oxide layer is formed on the second STI structures in the second region and the first nitride layer, and a second nitride layer is formed on the first oxide layer in the second region.
[0018] The technical solution of this application has at least the following advantages:
[0019] During the manufacturing process of flash memory devices, after the floating gate polysilicon layer is deposited, the floating gate polysilicon layer is etched, and the STI structure is etched, the floating gate polysilicon layer is trimmed through the CDE process to remove the sharp protrusions at the edge of the floating gate polysilicon layer, thereby reducing the subsequent electron escape problem caused by the sharp protrusion defects and improving the reliability and yield of flash memory products. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0021] Figure 1 This is a flow chart of a process method applied to memory manufacturing provided by an exemplary embodiment of the present application;
[0022] Figures 2 to 6 This is a schematic diagram of a floating gate formation process in a process method for memory manufacturing provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0023] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0024] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0025] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0026] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0027] refer to Figure 1 , which shows a flow chart of a process method for memory manufacturing provided by an exemplary embodiment of the present application, such as Figure 1 As shown, the method includes:
[0028] Step S1, providing a wafer, wherein the area on the wafer for forming semiconductor devices includes a first area and a second area, the first area is used to form a flash memory device, the second area is used to form a logic device, a pad oxide layer is formed on the wafer, a first STI structure is formed in the wafer in the first area, and the top of the first STI structure is higher than the top of the pad oxide layer.
[0029] refer to Figure 2 , which shows a cross-sectional schematic diagram after depositing the floating gate polysilicon layer. Figure 2 As shown, the area on the chip 210 for forming semiconductor devices includes a first area 201 and a second area 202. The first area 201 is used to form a flash memory device, and the second area 202 is used to form a logic device. A pad oxide layer 221 is formed on the chip 210. A first STI structure 211 is formed in the chip 210 in the first area 201. The top of the first STI structure 211 is higher than the top of the pad oxide layer 221. A first trench 301 is formed between the first STI structures 211 in the first area 201.
[0030] A second STI structure 212 is formed in the chip 210 of the second region 202. The top of the second STI structure 212 is higher than the top of the pad oxide layer 221. The first nitride layer 241 is filled between the second STI structures 212 of the second region 202. A first oxide layer 222 is formed on the second STI structure 212 and the first nitride layer 241 of the second region 202. A second nitride layer 242 is formed on the first oxide layer 222 of the second region 202.
[0031] The thickness of the first nitride layer 241 is 500 angstroms. The thickness of the first oxide layer 222 is 80 angstroms to 200 angstroms, the thickness of the second nitride layer 242 is 100 angstroms to 300 angstroms, and the thickness of the pad oxide layer 221 is 30 angstroms to 100 angstroms.
[0032] Step S2 : depositing a floating gate polysilicon layer in the first region, wherein the floating gate polysilicon layer fills the first trench between the first STI structures.
[0033] refer to Figure 3 , which shows a cross-sectional schematic diagram after the floating gate polysilicon layer is deposited in the first region. Figure 3 As shown, after the floating gate polysilicon layer 231 is deposited to fill the first trench 301 , a chemical mechanical polishing (CMP) process may be used for planarization until the second nitride layer 242 in the second region 202 is exposed.
[0034] Step S3 , etching the floating gate polysilicon layer so that the top of the floating gate polysilicon layer is lower than the top of the first STI structure.
[0035] refer to Figure 4 , which shows a cross-sectional view of the floating gate polysilicon layer after etching. Figure 4 As shown, the floating gate polysilicon layer 231 can be etched by a dry etching process so that the top of the floating gate polysilicon layer 231 is lower than the top of the first STI structure 211. The dry etching process can be performed in an inductively coupled plasma (ICP) etching machine.
[0036] Step S4: etching the first STI structure so that the top of the first STI structure is lower than the top of the floating gate polysilicon layer.
[0037] refer to Figure 5 , which shows a cross-sectional schematic diagram of the first STI structure after etching. Figure 5 As shown, the first STI structure 211 can be etched by a wet etching process so that the top of the first STI structure 211 is lower than the top of the floating gate polysilicon layer 231. After the etching step, the edge of the floating gate polysilicon layer 231 is formed with a sharp protrusion defect (such as Figure 5 (shown by the dashed line).
[0038] Step S5 , trimming the floating gate polysilicon layer through a CDE process to remove sharp corners and protrusions at the edge of the floating gate polysilicon layer. The remaining floating gate polysilicon layer constitutes the floating gate of the flash memory.
[0039] refer to Figure 6 , which shows a cross-sectional schematic diagram of the floating gate polysilicon layer after trimming by a chemical dry etch (CDE) process. Figure 6 As shown, in this step, the isotropic etching characteristics of the CDE process are utilized to make the etching rate at the sharp-angle protrusions faster than that at other positions, so that the sharp-angle protrusions will not be over-etched at other positions. After this step, the remaining floating gate polysilicon layer 231 constitutes the floating gate of the flash memory, and a second trench 302 is formed between the floating gates.
[0040] To sum up, in the embodiment of the present application, in the manufacturing process of the flash memory device, after the floating gate polysilicon layer is deposited, the floating gate polysilicon layer is etched, and the STI structure is etched in sequence, the floating gate polysilicon layer is trimmed through the CDE process to remove the sharp protrusions at the edge of the floating gate polysilicon layer, thereby reducing the subsequent electron escape problem caused by the sharp protrusion defects and improving the reliability and yield of the flash memory product.
[0041] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. A process method used in memory manufacturing, characterized in that: include: A wafer is provided, wherein an area on the wafer for forming semiconductor devices includes a first area and a second area, the first area being used to form a flash memory device, and the second area being used to form a logic device. A pad oxide layer is formed on the wafer, and a first STI structure is formed in the wafer in the first area, wherein a top of the first STI structure is higher than a top of the pad oxide layer. Depositing a floating gate polysilicon layer in the first region, wherein the floating gate polysilicon layer fills the first trench between the first STI structures; Etching the floating gate polysilicon layer so that a top of the floating gate polysilicon layer is lower than a top of the first STI structure; Etching the first STI structure so that a top of the first STI structure is lower than a top of the floating gate polysilicon layer; The floating gate polysilicon layer is trimmed through the CDE process to remove the sharp protrusions at the edge of the floating gate polysilicon layer. The remaining floating gate polysilicon layer constitutes the floating gate of the flash memory.
2. The method according to claim 1, characterized in that The etching of the floating gate polysilicon layer comprises: The floating gate polysilicon layer is etched by a dry etching process.
3. The method according to claim 2, characterized in that The dry etching process is performed on an ICP machine.
4. The method according to claim 2, characterized in that The etching of the first STI structure includes: The first STI structure is etched by a wet etching process.
5. The method according to any one of claims 1 to 4, characterized in that: A second STI structure is formed in the wafer in the second region, and a top of the second STI structure is higher than a top of the pad oxide layer; A first nitride layer is filled between the second STI structures in the second region, a first oxide layer is formed on the second STI structures in the second region and the first nitride layer, and a second nitride layer is formed on the first oxide layer in the second region.