FPGA (Field Programmable Gate Array) implementation method for high-precision real-time pulse width triggering in high-speed acquisition system
By converting the sampled data into edge feature data in a high-speed acquisition system and using FPGA to judge pulse width width, the problem of insufficient real-time and accuracy in traditional systems is solved, and efficient pulse width triggering and signal storage is achieved.
Patent Information
- Application Number
- CN202510555081.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2025-08-15
AI Technical Summary
Traditional digital processing systems cannot achieve high-precision real-time pulse width triggering in high-speed acquisition systems, especially in the detection and storage of high-frequency signals, resulting in signal loss.
By converting the sampled data with a large bit width into the edge feature data with a small bit width, the pulse width triggering judgment is used to achieve high-precision pulse width triggering, and the parallel sampling data is uploaded to the FPGA for processing, and real-time detection and storage are performed according to the pulse width conditions set by the upper computer.
It realizes high-precision real-time pulse width triggering in high-speed acquisition systems, ensuring the real-time and accuracy of triggering, simplifying the logical process, and saving FPGA resources.
Smart Images
Figure CN120491883A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of high-speed acquisition systems, and more specifically, relates to an FPGA implementation method for high-precision real-time pulse width triggering in a high-speed acquisition system. Background Art
[0002] With the increasing complexity of electrical signals and the rapid development of 5G and 6G technologies, the requirements for observing high-speed electrical signals and acquisition systems are becoming increasingly stringent. Acquisition systems are also becoming increasingly complex. As one of the most important components of acquisition systems, the trigger function is also playing an increasingly complex and important role. Using the trigger function enables stable waveform display and the capture of waveforms with certain characteristics.
[0003] The most basic edge trigger can capture simple waveforms. However, with the advancement of electronic information technology, today's measured signals have more than just a single characteristic. Relying solely on edge triggering to detect level changes in the measured signal cannot meet the requirements of some test scenarios. Therefore, edge triggering cannot capture complex signals. To address this, acquisition systems have added many advanced triggering functions. Pulse width triggering is a frequently used trigger type among acquisition system advanced triggers. Pulse width triggering refers to a triggering method in which the acquisition system captures positive or negative pulses of a specified width.
[0004] In the communications and radar fields, signal frequencies can reach as high as several GHz, and pulse widths can be as low as hundreds of picoseconds. Therefore, the acquisition system's sampling rate must be as high as tens of GHz. However, the storage space and processing speed of the acquisition system are far from sufficient for uninterrupted data acquisition. Consequently, a significant amount of time is required to store and process data. Furthermore, during this processing, the acquisition system cannot acquire new signals, resulting in the loss of signals that meet specific pulse width requirements. High-precision, real-time pulse width triggering, one of the most important functions in an acquisition system, can address this problem by detecting the pulse width of the signal and storing the signals that meet the pulse width requirement.
[0005] However, due to system clock limitations, traditional digital processing cannot achieve real-time detection of the pulse width of the sampled signal for high-speed, large-scale parallel sampling data, or the pulse width detection accuracy is insufficient. Therefore, achieving high-precision real-time pulse width triggering that can detect whether all sampled data meets the specified pulse width triggering requirement in real time is a major challenge. Summary of the Invention
[0006] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide an FPGA implementation method for high-precision real-time pulse width triggering in a high-speed acquisition system. The method converts large-bit-width sampled data into small-bit-width data carrying signal edge characteristics, and then uses the edge characteristic data to determine whether the signal meets the set pulse width characteristics, thereby achieving high-precision pulse width triggering and ensuring the real-time nature of the triggering.
[0007] To achieve the above-mentioned object of the invention, the present invention provides an FPGA implementation method for high-precision real-time pulse width triggering in a high-speed acquisition system, characterized by comprising the following steps:
[0008] (1) Initialization of high-speed acquisition system;
[0009] (2) The host computer sends the high and low comparison levels V_set_H, V_set_L and pulse width trigger conditions to the FPGA;
[0010] Among them, the pulse width trigger conditions include:
[0011] Pulse width points N_set = t_set*f s , f s is the sampling rate of the high-speed acquisition system, and t_set is the set pulse width time;
[0012] Judgment condition: greater than the pulse width point number or less than the pulse width point number;
[0013] Pulse width polarity: positive pulse width or negative pulse width;
[0014] (3) The high-speed acquisition system performs N-channel parallel sampling on the input signal, obtains N-channel parallel sampling data at multiple sampling moments, and then uploads it to the FPGA;
[0015] (4) FPGA generates a shaping signal LS based on the high and low comparison levels V_set_H and V_set_L issued;
[0016] (5) FPGA generates rising edge signal RISE and falling edge signal FALL according to the shaped signal LS;
[0017] (6) FPGA generates an initial matrix ORI with N rows and L columns according to the pulse width point number N_set issued. The elements of the first N_set columns of the initial matrix ORI are all 1, and the elements of the other columns are all 0. The column number variable L satisfies:
[0018]
[0019] Among them, the symbol Indicates rounding up;
[0020] (7) FPGA determines the polarity of the pulse width sent. If the pulse width sent by the host computer is positive, it goes to step (8); if the pulse width sent by the host computer is negative, it goes to step (11);
[0021] (8) Operate the rising edge signal RISE and the initial matrix ORI to generate the transition matrix TRA;
[0022] In the rising edge signal RISE, if a row is 0, then the corresponding row in the transition matrix TRA is set to all 0s; if the nth row in the rising edge signal RISE is 1, then the elements in ORI are shifted right by n-1 bits in sequence and used as the elements after the nth bit in the corresponding row in the transition matrix TRA, and the elements before 1 to n-1 bits are set to 0; where 1≤n≤N;
[0023] (9) Perform an “OR” operation on each column element in the transition matrix TRA to obtain a range level signal array_R;
[0024] (10) FPGA performs pulse width triggering;
[0025] Align the falling edge signal FALL with the range level signal array_R starting from the first element. When the judgment condition received by the FPGA is less than the pulse width point number, find the position where the element in the falling edge signal FALL is 1 and the corresponding element in the range level signal array_R is also 1. The pulse width corresponding to this position is the pulse width less than the pulse width point number N_set. At this time, the FPGA controls the high-speed acquisition system to capture the signal corresponding to this position, store it, and display it;
[0026] When the judgment condition received by the FPGA is greater than the pulse width points, the position where the element in the falling edge signal FALL is 1 and the element in the corresponding range level signal array_R is 0 is found. The pulse width corresponding to this position is the pulse width greater than the pulse width points N_set. At this time, the FPGA controls the high-speed acquisition system to capture the signal corresponding to this position, store it, and display it;
[0027] (11) Similarly, using the falling edge signal FALL and the initial matrix ORI, FPGA performs pulse width triggering according to steps (8) to (10).
[0028] The object of the invention of the present invention is achieved like this:
[0029] The present invention provides an FPGA implementation method for high-precision real-time pulse width triggering in a high-speed acquisition system. The high-speed acquisition system samples input signals in parallel, obtains multi-channel parallel sampling data at multiple sampling moments, and then uploads the data to the FPGA. The FPGA converts the sampled data into integer signals and edge-level signals according to the pulse width triggering conditions issued by the host computer, and ultimately completes real-time high-precision pulse width triggering, generates a trigger signal, completes real-time detection and storage of specific pulse width signals, and finally displays the signal that meets the set pulse width triggering conditions on the host computer. This method can achieve real-time pulse width triggering, ensures the real-time nature of the triggering, and greatly improves the accuracy of the pulse width triggering. Compared with traditional pulse width counting methods, it is simpler and more efficient, greatly simplifies the logic of the pulse width triggering, and saves FPGA resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 This is a flow chart of an FPGA implementation method for high-precision real-time pulse width triggering in a high-speed acquisition system of the present invention;
[0031] Figure 2 It is a schematic diagram of the shaping signal LS, the rising edge signal RISE and the falling edge signal FALL;
[0032] Figure 3 It is a schematic diagram of the initial matrix ORI;
[0033] Figure 4 is a schematic diagram of the generated transition matrix TRA;
[0034] Figure 5 It is a schematic diagram of generating a range level signal array_R;
[0035] Figure 6 This is a schematic diagram of FPGA performing positive pulse width triggering;
[0036] Figure 7 It is a schematic diagram of 8-way LS, RISE, and FALL at two sampling moments;
[0037] Figure 8 This is a schematic diagram of the initial matrix ORI with 4 rows and 8 columns;
[0038] Figure 9 It is a schematic diagram of the transition matrix TRA with 4 rows and 8 columns;
[0039] Figure 10 This is a schematic diagram of the range level signal array_R with 1 row and 8 columns
[0040] Figure 11 This is a schematic diagram of positive pulse width triggering. DETAILED DESCRIPTION
[0041] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, such descriptions will be omitted here.
[0042] Example
[0043] In this embodiment, if Figure 1 As shown, the present invention provides an FPGA implementation method for high-precision real-time pulse width triggering in a high-speed acquisition system, comprising the following steps:
[0044] (1) Initialization of high-speed acquisition system;
[0045] (2) The host computer sends the high and low comparison levels V_set_H, V_set_L and pulse width trigger conditions to the FPGA;
[0046] Among them, the pulse width trigger conditions include:
[0047] Pulse width points N_set = t_set*f s , f s is the sampling rate of the high-speed acquisition system, and t_set is the set pulse width time;
[0048] Judgment condition: greater than the pulse width point number or less than the pulse width point number;
[0049] Pulse width polarity: positive pulse width or negative pulse width;
[0050] (3) The high-speed acquisition system performs N-channel parallel sampling on the input signal, obtains N-channel parallel sampling data at multiple sampling moments, and then uploads it to the FPGA;
[0051] In this embodiment, it is assumed that the high-speed acquisition system includes N sampling channels and collects parallel sampling data at T sampling moments in total. Then, the parallel sampling data is represented by a matrix whose size is N×T.
[0052] (4) FPGA generates a shaping signal LS based on the high and low comparison levels V_set_H and V_set_L issued;
[0053] Traverse the value of each sampling point in the sampled data. If the value of a sampling point is greater than V_set_H, set the element value of the corresponding position in the shaped signal LS to 1; if the value of a sampling point is less than V_set_L, set the element value of the corresponding position in the shaped signal LS to 0; if the value of a sampling point is between V_set_L and V_set_H, take the previous element value of the corresponding position in the shaped signal LS; after traversing each sampling point in the sampled data, obtain a shaped signal LS with the same length as the sampled data and element values of 0 or 1.
[0054] In this embodiment, if Figure 2 As shown, taking the sine signal as an example, the value of the first sampling point is less than V_set_L, so the first element in the shaped signal LS is 0; the values of the second and third sampling points are between V_set_L and V_set_H, then the first element 0 in the shaped signal LS is taken as the value of the second and third elements; the value of the fourth sampling point is greater than V_set_H, then the fourth element in the shaped signal LS is 1; and so on, finally obtaining a matrix of the same size as the parallel sampling data, which is also N×T;
[0055] (5) FPGA generates rising edge signal RISE and falling edge signal FALL according to the shaped signal LS;
[0056] Traverse each element in the shaped signal LS, record the position that changes from 0 to 1 as a rising edge, set the element value at the corresponding position to 1, otherwise it is set to 0, and obtain the rising edge signal RISE;
[0057] Traverse each element in the shaped signal LS, record the position that changes from 1 to 0 as a falling edge, set the element value at the corresponding position to 1, otherwise it is set to 0, and obtain the falling edge signal FALL.
[0058] In this embodiment, if Figure 2 As shown in the figure, if the third to fourth elements in the shaped signal LS change from 0 to 1, the fourth element position in the rising edge signal RISE is recorded as the rising edge position, and the element value at the corresponding position is set to 1, otherwise it is set to 0; similarly, the position where the element value in the shaped signal LS changes from 1 to 0 is recorded as the falling edge position, and the element value at the corresponding position in the falling edge signal FALL is set to 1, otherwise it is set to 0;
[0059] The rising edge signal RISE, the falling edge signal FALL and the shaping signal LS have the same magnitude;
[0060] (6) FPGA generates an initial matrix ORI with N rows and L + N columns according to the pulse width point number N_set issued, where Figure 3 As shown, the elements of the first N_set columns of the initial matrix ORI are all 1, and the elements of the other columns are all 0. The column number variable L satisfies:
[0061]
[0062] Among them, the symbol Indicates rounding up;
[0063] (7) FPGA determines the polarity of the pulse width sent. If the pulse width sent by the host computer is positive, it goes to step (8); if the pulse width sent by the host computer is negative, it goes to step (9);
[0064] (8) FPGA performs positive pulse width triggering;
[0065] (8.1) Operate the rising edge signal RISE and the initial matrix ORI to generate the transition matrix TRA;
[0066] In the rising edge signal RISE, if a row is 0, then the corresponding row in the transition matrix TRA is set to all 0s; if the nth row in the rising edge signal RISE is 1, then the elements in ORI are shifted right by n-1 bits in sequence and used as the elements after the nth bit in the corresponding row in the transition matrix TRA, and the elements before 1 to n-1 bits are set to 0; where 1≤n≤N;
[0067] In this embodiment, taking the first sampling moment as an example, Figure 4 RISE only shows the N elements at the first sampling moment (the first column), where row 0 is 0, so row 0 in TRA is 0, and row 1 in RISE is 1. So shifting row 1 in ORI right by one position gives row 1 in TRA. So the first row in TRA starts with a 0, followed by N_set 1s, and then all 0s.
[0068] (8.2) Perform an OR operation on each column element in the transition matrix TRA to obtain a range level signal array_R. In this embodiment, Figure 5 As shown, the 0th column in TRA is all 0, so the 0th column in array_R is 0, and the 1st column in TRA has an element of 1, so the 1st column in array_R is 1;
[0069] (8.3) FPGA performs pulse width triggering;
[0070] Align the falling edge signal FALL with the range level signal array_R starting from the first element. When the judgment condition received by the FPGA is less than the pulse width point number, find the position where the element in the falling edge signal FALL is 1 and the corresponding element in the range level signal array_R is also 1. The pulse width corresponding to this position is the pulse width less than the pulse width point number N_set. At this time, the FPGA controls the high-speed acquisition system to capture the signal corresponding to this position, store it, and display it;
[0071] When the judgment condition received by the FPGA is greater than the pulse width points, the position where the element in the falling edge signal FALL is 1 and the element in the corresponding range level signal array_R is 0 is found. The pulse width corresponding to this position is the pulse width greater than the pulse width points N_set. At this time, the FPGA controls the high-speed acquisition system to capture the signal corresponding to this position, store it, and display it;
[0072] In this embodiment, if Figure 6 As shown, the length of array_R is greater than FALL, so we need to fill in the elements of FALL's subsequent sampling moments, such as Figure 6 As shown, the data in a bracket in FALL represents the data at a sampling moment;
[0073] When the judgment condition received by FPGA is less than the pulse width point, assuming that the falling edge signal FALL is Figure 6 In FALL_1, when there is 1 element in FALL_1 and the corresponding position in array_R is also 1, the pulse width corresponding to this position is smaller than the pulse width point number N_set. At this time, the FPGA controls the high-speed acquisition system to capture the signal corresponding to this position, store it, and display it.
[0074] When the judgment condition received by FPGA is greater than the pulse width point number, assuming that the falling edge signal FALL is Figure 6 In FALL_2, when 1 element appears in FALL_2 and the corresponding position in array_R is 0, the pulse width corresponding to FALL_2 is greater than the pulse width of N_set. If the judgment condition sent by the host computer is "greater than", the corresponding pulse width can be triggered, and the system captures the signal corresponding to the position where the 1 element appears in FALL_2, stores it, and finally displays it;
[0075] (9) Similarly, use the falling edge signal FALL and the initial matrix ORI to perform negative pulse width triggering on FPGA according to steps (8.1) to (8.3).
[0076] Example
[0077] The input data is parallel N = 4 channels, the pulse width points sent by the host system is N_set = 3, the judgment condition is "greater than the pulse width points", the pulse width polarity is "positive pulse width", assuming that the shaping signal LS, rising edge signal RISE and falling edge signal FALL have been obtained through hysteresis comparison. Figure 7 As shown, it contains a total of 8 LS, RISE, and FALL channels at T = 2 sampling moments. According to the above steps, the generated initial matrix ORI is a matrix with N = 4 rows and L + N = 8 columns, where like Figure 8 As shown, the initial transition matrix TRA is Figure 9 As shown, the range level signal array_R is obtained according to the initial transition matrix, such as Figure 10 As shown, the range level signal array_R and the falling edge signal FALL are judged together, such as Figure 11 As shown in the figure: FALL has two 1s, representing the end points of the pulse widths of length 1 and length 4 in the signal respectively. The first 1 appears in the part with 1 in array_R, which means that this is a pulse width less than the set length N_set=3. Since the set judgment condition is "greater than", the pulse width cannot be triggered. The second 1 appears in the part with 0 in array_R, which means that the pulse width is greater than 3 and can be triggered.
[0078] Although the above describes the illustrative specific embodiments of the present invention to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concepts of the present invention are protected.
Claims
1. A method for implementing high-precision real-time pulse width triggering on FPGA in a high-speed acquisition system, characterized in that: The following steps are involved: (1) Initialization of high-speed acquisition system; (2) The host computer sends the high and low comparison levels V_set_H, V_set_L and pulse width trigger conditions to the FPGA; Among them, the pulse width trigger conditions include: Pulse width points N_set = t_set*f s , f s is the sampling rate of the high-speed acquisition system, and t_set is the set pulse width time; Judgment condition: greater than the pulse width point number or less than the pulse width point number; Pulse width polarity: positive pulse width or negative pulse width; (3) The high-speed acquisition system performs N-channel parallel sampling on the input signal, obtains N-channel parallel sampling data at multiple sampling moments, and then uploads it to the FPGA; (4) FPGA generates a shaping signal LS based on the high and low comparison levels V_set_H and V_set_L issued; (5) FPGA generates rising edge signal RISE and falling edge signal FALL according to the shaped signal LS; (6) FPGA generates an initial matrix ORI with N rows and L columns according to the pulse width point number N_set issued. The elements of the first N_set columns of the initial matrix ORI are all 1, and the elements of the other columns are all 0. The column number variable L satisfies: Among them, the symbol Indicates rounding up; (7) FPGA determines the polarity of the pulse width sent. If the pulse width sent by the host computer is positive, it goes to step (8); if the pulse width sent by the host computer is negative, it goes to step (11); (8) Operate the rising edge signal RISE and the initial matrix ORI to generate the transition matrix TRA; In the rising edge signal RISE, if a row is 0, then the corresponding row in the transition matrix TRA is set to all 0s; if the nth row in the rising edge signal RISE is 1, then the elements in ORI are shifted right by n-1 bits in sequence and used as the elements after the nth bit in the corresponding row in the transition matrix TRA, and the elements before 1 to n-1 bits are set to 0; where 1≤n≤N; (9) Perform an OR operation on each column element in the transition matrix TRA to obtain a range level signal array_R; (10) FPGA performs pulse width triggering; Align the falling edge signal FALL with the range level signal array_R starting from the first element. When the judgment condition received by the FPGA is less than the pulse width point number, find the position where the element in the falling edge signal FALL is 1 and the corresponding element in the range level signal array_R is also 1. The pulse width corresponding to this position is the pulse width less than the pulse width point number N_set. At this time, the FPGA controls the high-speed acquisition system to capture the signal corresponding to this position, store it, and display it; When the judgment condition received by the FPGA is greater than the pulse width number, the position where the element in the falling edge signal FALL is 1 and the element in the corresponding range level signal array_R is also 0 is found. The pulse width corresponding to this position is the pulse width greater than the pulse width number N_set. At this time, the FPGA controls the high-speed acquisition system to capture the signal corresponding to this position, store it, and display it; (11) Similarly, using the falling edge signal FALL and the initial matrix ORI, FPGA performs pulse width triggering according to steps (8) to (10).
2. The FPGA implementation method for high-precision real-time pulse width triggering in a high-speed acquisition system according to claim 1, characterized in that: The method for generating the shaping signal LS is: Traverse the value of each sampling point in the sampled data. If the value of a sampling point is greater than V_set_H, set the element value of the corresponding position in the shaped signal LS to 1; if the value of a sampling point is less than V_set_L, set the element value of the corresponding position in the shaped signal LS to 0; if the value of a sampling point is between V_set_L and V_set_H, take the previous element value of the corresponding position in the shaped signal LS; after traversing each sampling point in the sampled data, obtain a shaped signal LS with the same length as the sampled data and element values of 0 or 1.
3. The FPGA implementation method for high-precision real-time pulse width triggering in a high-speed acquisition system according to claim 1, characterized in that: The method for generating the rising edge signal RISE and the falling edge signal FALL is: Traverse each element in the shaped signal LS, record the position that changes from 0 to 1 as a rising edge, set the element value at the corresponding position to 1, otherwise it is set to 0, and obtain the rising edge signal RISE; Traverse each element in the shaped signal LS, record the position that changes from 1 to 0 as a falling edge, set the element value at the corresponding position to 1, otherwise it is set to 0, and obtain the falling edge signal FALL.