Storage instruction processing method, electronic device and storage medium

Abstract

The present invention provides a data storage instruction processing method, electronic device, and storage medium, and relates to the field of computer technology. The method includes sending the block address of a target cache block corresponding to a target cache line into a data storage instruction prefetch queue, wherein all target data storage instructions cached in the target cache line do not fill the target cache line, and the data storage instruction address of the target data storage instruction includes the block address of the target cache block; performing a data cache data storage address hit check on the target data storage instruction in the data storage instruction prefetch queue, and in the event that the data storage address fails, initiating a prefetch request and executing access to a lower-layer storage system based on the block address of the target cache block, obtaining data of the target cache block and backfilling it into the data cache, and writing the data storage instruction data included in the target data storage instruction for which the prefetch request was initiated and prefetched successfully into the target cache block in the data cache. The present invention can improve the prefetch accuracy and prefetch timeliness of data storage instructions.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method for processing a storage instruction, an electronic device, and a storage medium. Background Art

[0002] Memory walls are a significant issue limiting computer processor performance. Data prefetching, a key approach to mitigating forced failures, requires a trade-off between prefetch coverage, prediction accuracy, and timing control. Incorrect prefetching can negatively impact system performance. Therefore, a key approach to improving processor memory system access performance is to reduce the miss rate of data cache accesses through data prefetching.

[0003] Instructions in the processor that access the storage system, including load instructions and store instructions, both access the data cache. Both load and store instructions can potentially cause a data cache miss. When a load instruction misses the data in the data cache, the data must be retrieved from the underlying storage system as quickly as possible before it can be written back to complete the load operation. The program's subsequent instructions will also require the result of the load instruction. However, store instructions, unlike load instructions, can be directly written back and committed even if a data cache miss occurs. After the commit, the store operation can be completed.

[0004] When write-merging is performed on storage instructions in the storage buffer, and multiple storage instructions are write-merged to fill up a cache line in the storage buffer (it can be understood that a cache line in the storage buffer corresponds to a cache block (Cache Block) in the data cache, and multiple storage instructions can fill up a cache line in the storage buffer after write-merging, which means that the storage instruction data included in the multiple storage instructions can fill up an entire cache block), because the data of the entire cache block written by consecutive storage instructions is existing, even if the storage address hit check of the data cache does not hit, there is no need to read the data of the corresponding cache block in the lower storage system into the data cache.

[0005] However, if a store instruction cannot fill a cache line in the data buffer, the cache block's data must be fetched from the underlying storage system into the data cache. During this data fetching process, the store instruction must wait, and this process also consumes valuable cache ports and bandwidth. When the data buffer is highly occupied, the store instruction data cannot be written from the data buffer to the data cache in a timely manner while waiting for data from the underlying storage system. This can cause the data buffer to be full, impacting the execution of subsequent instructions. Summary of the Invention

[0006] In view of the problems existing in the prior art, the present invention provides a method for processing a storage instruction, an electronic device and a storage medium.

[0007] In a first aspect, the present invention provides a method for processing a store instruction, comprising:

[0008] Cache the store instruction to be processed into the store buffer, and when it is determined that a preset condition is met, send the block address of the target cache block corresponding to the target cache line in the store buffer to the store instruction prefetch queue; all the target store instructions cached in the target cache line do not fill the target cache line, and the store instruction address of the target store instruction includes the block address of the target cache block; the store instruction includes the store instruction address and store instruction data;

[0009] Performing a data cache address hit check on the block address of the target cache block in the data instruction prefetch queue, and in the case where the data address fails, initiating a prefetch request and sending the block address of the target cache block to a memory access failure queue;

[0010] Performing data prefetching, the data prefetching comprising accessing a lower-layer storage system based on a block address of the target cache block, obtaining data of the target cache block, and backfilling the data into the data cache;

[0011] The store instruction data included in the target store instruction for which a prefetch request is initiated and prefetched successfully is written into the target cache block in the data cache.

[0012] In some embodiments, determining that a preset condition is satisfied includes:

[0013] Determining whether the proportion of occupied space in the data buffer reaches a first preset threshold; or

[0014] It is determined that the number of cache blocks corresponding to the pending store instructions cached in the store buffer reaches a second preset threshold.

[0015] In some embodiments, determining that a preset condition is satisfied includes:

[0016] The duration during which no new store instruction is written and merged after the store instruction is cached into the store buffer is used as the first duration, and it is determined that the first duration reaches a third preset threshold.

[0017] In some embodiments, determining that a preset condition is satisfied further comprises:

[0018] The duration of accessing the lower-layer storage system based on the block address of the target cache block, obtaining the data of the target cache block and backfilling the data into the data cache is used as the second duration;

[0019] The duration from when the target store instruction enters the store buffer to when the store instruction data is written into the target cache block in the data cache is used as a third duration;

[0020] Determine that the third duration is not less than the sum of the third preset threshold and the second duration.

[0021] In some embodiments, the first preset threshold, the second preset threshold, and the third preset threshold are pre-set.

[0022] In some embodiments, the first preset threshold, the second preset threshold and the third preset threshold are implemented by setting the control and status registers of the control processor through operating system software, or are pre-set through hardware.

[0023] In some embodiments, the method further comprises:

[0024] Using the duration for which other store instructions cached in other cache lines are cached in the store buffer as a fourth duration, and after determining that the fourth duration reaches a fourth preset threshold, directly performing a store address hit check of the data cache, and determining that the block address of the cache block included in the store instruction address of the other store instruction has not been sent to the store instruction prefetch queue; or

[0025] Determine whether the proportion of occupied space in the data buffer reaches a fifth preset threshold.

[0026] In some embodiments, the fourth preset threshold and the fifth preset threshold are implemented by setting the control and status registers of the control processor through operating system software, or are pre-set through hardware.

[0027] In some embodiments, the priority of performing a data cache store address hit check on the block address of the target cache block in the store instruction prefetch queue is lower than the priority of directly performing a data cache load address and store address hit check on the block address of the cache block included in the load instruction and the other store instructions; and / or

[0028] In the memory access failure queue, the priority of data prefetching based on the block address of the target cache block in the store instruction prefetch queue is lower than the priority of directly acquiring data based on the block address of the cache block included in the fetch instruction and the other store instructions.

[0029] In some embodiments, the method further comprises:

[0030] The prefetch flag of the target store instruction is set to indicate that the prefetch request has been initiated for the target store instruction.

[0031] In a second aspect, the present invention provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for processing storage instructions as described in the first aspect above is implemented.

[0032] In a third aspect, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the storage instruction processing method as described in the first aspect above.

[0033] In a fourth aspect, the present invention further provides a computer program product, comprising a computer program, which, when executed by a processor, implements the method for processing a store instruction as described in the first aspect above.

[0034] The storage instruction processing method, electronic device and storage medium provided by the present invention send the block address of the target cache block corresponding to the target cache line in the storage buffer into the storage instruction prefetch queue; all target storage instructions cached by the target cache line do not fill the target cache line, and the storage instruction address of the target storage instruction includes the block address of the target cache block; perform a storage address hit check of the data cache on the target storage instruction in the storage instruction prefetch queue, and when the storage address fails, initiate a prefetch request and execute access to the lower storage system based on the block address of the target cache block, obtain the data of the target cache block and backfill it to the data cache; write the storage instruction data included in the target storage instruction for which the prefetch request is initiated and prefetched successfully into the target cache block in the data cache. Based on the present invention, the prefetch accuracy and prefetch timeliness of storage instructions can be improved, unnecessary prefetching can be avoided, and the overall performance of the processor can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 It is a structural diagram of the storage instruction processing system provided by the present invention.

[0037] Figure 2It is a flow chart of the method for processing a store instruction provided by the present invention.

[0038] Figure 3 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0040] The access speed of computer processor memory systems has far outstripped the speed of processor computation, leading to the increasingly severe "memory wall" problem, which severely restricts further improvements in processor performance. Cache, a storage mechanism designed to leverage the principle of program access locality, aims to bridge the gap between processor computation speed and memory access speed. However, cache cannot reduce the latency of the processor's first memory access, also known as a computational miss.

[0041] Prefetching is a key technology for improving processor memory access performance. A key approach to improving processor memory system access performance is to reduce the cache miss rate. Data prefetching is a method for reducing computational misses by pre-fetching cache blocks that the processor may need. Data prefetching is essentially a mechanism for guessing the address a program will use to access the memory system, requiring analysis of program behavior. Its core approach is to exploit the spatial and temporal locality inherent in program execution, and its performance improvement is highly correlated with the characteristics of the executed program. If the prefetched data block (i.e., cache block) is not returned by the time the required data block is used, prefetching is delayed, reducing the performance benefits of prefetching. Prefetching consumes processor memory bandwidth and generates additional power consumption. Furthermore, if unneeded cache blocks are retrieved or prefetching is performed at the wrong time, it can cause cache contamination. Prefetching requires careful implementation; flawed prefetching will not only fail to improve overall processor performance, but can actually degrade it. Therefore, in addition to ensuring timeliness, prefetching also needs to strike a balance between prefetch coverage and prefetch accuracy.

[0042] Figure 1 This is a schematic diagram of the structure of the storage instruction processing system provided by the present invention. Figure 1 As shown, it includes the store instruction address pipeline and the store instruction data pipeline:

[0043] The store instruction emits the store instruction base address (Base) and offset (Offset) from the store instruction address reservation station (Store Address RS, i.e. Store Address Reservation) and sends them to the virtual address calculation (Address Generator).

[0044] The store instruction transmits the store instruction data (Data) from the store instruction data reservation station (Store Data RS, i.e. Store Data Reservation) and stores it into the store queue (Store Queue).

[0045] The virtual address calculation is responsible for adding the base address (Base) and the offset (Offset) to obtain the virtual address (Vaddr) of the store instruction and sending it to the data translation lookaside buffer (DTLB).

[0046] The Data Translation Lookaside Buffer (DTLB) is responsible for converting the virtual address (Vaddr) of the store instruction into the physical address (Paddr) of the store instruction and storing it in the store queue.

[0047] After the store instruction in the store queue is submitted, it is written to the store buffer.

[0048] The store buffer merges the store write requests (Store) of the store instructions for the same cache block (CacheBlock) in units of cache lines, and writes the merged multiple Store write requests into the data cache (Data Cache) together.

[0049] Specifically, each store instruction includes a store instruction address and store instruction data, and the execution of the store instruction is to store the store instruction data in the store instruction address. After multiple store instructions are submitted to the store buffer, corresponding processing will be taken based on whether the store instruction addresses included in the multiple store instructions include the block address of the same cache block. It can be understood that the store instruction address includes the block address of the cache block, and if the block address of the cache block included in the store instruction addresses included in the multiple store instructions is the same, it means that these multiple store instructions all point to the same cache block, that is, the store instruction data included in each of them are to be stored in the same cache block. For multiple store instructions including the block address of the same cache block, after entering the store buffer, these store instructions will be cached in the same cache line. Store instructions including block addresses of different cache blocks will be cached in different cache lines. The store instructions that include the block address of the same cache block (i.e., the store instruction addresses included in these store instructions correspond to the same cache block) are cached in the same cache line. This means that the store write requests (Store) for the store instructions for the same cache block are merged in cache line units, and the merged multiple Store write requests are subsequently written into the data cache (Data Cache). Furthermore, if the multiple store instructions are able to fill a cache line in the store buffer after being merged, it means that the store instruction data included in the multiple store instructions can fill an entire cache block. If the multiple store instructions are unable to fill a cache line in the store buffer after being merged, it means that the store instruction data included in the multiple store instructions cannot fill an entire cache block.

[0050] The store pipeline (Store Pipe) is responsible for writing store instruction data from the store buffer to the data cache. The store pipeline consists of four beats (a beat is one processor clock cycle): the first beat reads the meta and tag; the second beat reads the data; the third beat obtains the result of the data read and combines it with the data to be written; and the fourth beat updates the meta, tag, and data based on the result of the operation. If a data cache access misses, the instruction enters the miss queue, accesses the underlying storage system, obtains the required cache block data, and backfills the data cache. The store instruction returns to the store buffer, awaiting data backfill before being resent (Replay).

[0051] like Figure 1As shown, in the store instruction processing system provided by the present invention, a store instruction prefetch queue (Store Prefetch Queue) is added to receive the prefetched store instruction address included in the target store instruction sent by the store buffer and perform a data cache hit check, i.e., a store address hit check. When the check result is that the store address is invalid, data is prefetched for the block address of the cache block included in the store instruction with the invalid address based on the store access invalidation queue to ensure that the subsequent store address hit check can hit and the data writing can be performed smoothly.

[0052] Figure 2 The flowchart of the method for processing a storage instruction provided by the present invention is as follows: Figure 2 As shown, the method includes:

[0053] Step 200: Cache a store instruction to be processed into a store buffer. If it is determined that a preset condition is met, send the block address of a target cache block corresponding to a target cache line in the store buffer to a store instruction prefetch queue; all target store instructions cached in the target cache line do not fill the target cache line, and the store instruction address of the target store instruction includes the block address of the target cache block; the store instruction includes a store instruction address and store instruction data;

[0054] Specifically, after a store instruction is submitted to the store queue, it is cached in the store buffer. Each pending store instruction in the store buffer is processed in units of cache lines, and all pending store instructions for the same cache block are merged into a single cache line.

[0055] It is understandable that if a cache line is filled with multiple pending storage instructions for the same cache block, it can be said that the storage instruction data included in the multiple pending storage instructions can fill the same cache block. Thereafter, in the process of performing the storage address hit check of the data cache, if the check is a hit, the storage instruction data included in the multiple pending storage instructions can be directly written into the cache block already cached in the data cache to complete the data writing. Even if the storage address hit check of the data cache does not hit, since the data is written to the same entire cache block and the written data can fill the entire cache block, it is not necessary to execute the data prefetch process at this time, that is, it is not necessary to read the data of the corresponding cache block in the lower storage system into the data cache, and the data of the cache block can be directly written into the data cache.

[0056] It can also be understood that if one or more pending storage instructions for the same cache block cannot fill up a cache line, it means that the storage instruction data included in the multiple pending storage instructions cannot fill up the same cache block. Therefore, the data part of the cache block in the lower-level storage system that has not been written by the storage instruction needs to be pre-fetched first, that is, the data of the same cache block stored in the lower-level storage system is first backfilled into the data cache, and then the storage instruction data included in the multiple pending storage instructions is written to the same cache block, and then the subsequent write process is executed.

[0057] For ease of description, in this embodiment, the cache line that has not been filled with one or more pending store instructions is referred to as a target cache line, the same cache block is referred to as a target cache block, and the multiple pending store instructions cached in the target cache line are referred to as target store instructions. And each pending store instruction includes a store instruction address and store instruction data. Therefore, it can be seen that all target store instructions cached in the target cache line do not fill the target cache line, and the store instruction address of the target store instruction includes the block address of the target cache block, that is, the store instruction address included in the target store instruction points to the target cache block, and the store instruction data included in the target store instruction is the data to be written into the target cache block.

[0058] Step 201: Perform a data cache address hit check on the block address of the target cache block in the data instruction prefetch queue, and if the data address fails, initiate a prefetch request and send the block address of the target cache block to the memory access failure queue;

[0059] In the present invention, a data cache address hit check is performed on the block address of the target cache block sent to the store instruction prefetch queue. If the check result is a hit, for example, data prefetch has been performed on the cache block pointed to by the store instruction address of the target store instruction before, and the data of the cache block is already stored in the data cache, then the store instruction data included in the target store instruction can be written into the cache block.

[0060] If the result of the check is a miss, that is, the address is invalid, it means that the cache block pointed to by the storage instruction address of the target storage instruction is not stored in the data cache, and since the target storage instruction has not fully written the target cache line at this time, in order to complete the correct writing of the data, it is necessary to execute a data prefetch process for the cache block pointed to by the block address of the target cache block included in the target storage instruction. Specifically, it can be to initiate a prefetch request for the target storage instruction, and send the block address of the target cache block to the memory access invalidation queue for data prefetching.

[0061] Step 202: perform data prefetching, wherein the data prefetching includes accessing a lower-layer storage system based on the block address of the target cache block, obtaining data of the target cache block, and backfilling the data into the data cache;

[0062] The data prefetch process may include: first, determining a prefetch address based on the block address of the target cache block included in the target storage instruction sent to the memory access invalidation queue, that is, the block address of the target cache block is the prefetch address; then accessing the lower-level storage system based on the prefetch address, obtaining the data of the target cache block corresponding to the block address of the target cache block from the lower-level storage system, and backfilling it into the data cache.

[0063] Step 203: write the store instruction data included in the target store instruction for which a prefetch request is initiated and prefetched successfully into the target cache block in the data cache.

[0064] It can be understood that if the data of the target cache block is successfully obtained by accessing the lower-level storage system based on the prefetch address and is backfilled into the data cache, it means that the data prefetch is successful. Subsequently, the target storage instruction that has initiated a prefetch request and successfully prefetched is checked for the storage address hit of the data cache. The check result will be a hit. After the hit, the storage instruction data included in the target storage instruction can be written into the cache block corresponding to the block address of the target cache block in the data cache.

[0065] The present invention sends the block address of the target cache block corresponding to the target cache line into the data storage instruction prefetch queue only when it is determined that the preset conditions are met. That is, the target data storage instruction will not be written to the data cache immediately, but will wait for a period of time, that is, after judging that the preset conditions are met, for example, after waiting for a period of time for write collection, it will write to the data cache. The present invention uses this waiting time to prefetch data. Moreover, the prefetched address is the address to which the data storage instruction is determined to write to the data cache, so it is a precise prefetch, which will not cause waste of prefetching, and ensure the accuracy and timeliness of prefetching. Based on the data storage instruction processing method provided by the present invention, the prefetch accuracy and prefetch timeliness of the data storage instruction can be improved, unnecessary prefetching can be avoided, and the overall performance of the processor can be improved.

[0066] In some embodiments, determining that a preset condition is satisfied may include:

[0067] Determine whether the proportion of occupied space in the data storage buffer reaches a first preset threshold. For example, if the occupied space in the data storage buffer accounts for 60% of the total space, it can be determined that the preset condition is met, and the block address of the target cache block can be sent to the data storage instruction prefetch queue. The first preset threshold (i.e., the proportion of occupied space) can be set based on actual conditions. The first preset threshold can be achieved by setting the control and status register (Control and Status Register, CSR) of the control processor through the operating system software, or it can be pre-set by hardware, and the control and status register can be adjusted dynamically by software or hardware according to the behavior of the program.

[0068] In some embodiments, determining that a preset condition is satisfied may further include:

[0069] Determine whether the number of cache blocks corresponding to the pending store instructions cached in the store buffer reaches a second preset threshold. For example, if the number of cache blocks corresponding to the pending store instructions cached in the store buffer has reached 10, it can be determined that the preset condition is met, and the block address of the target cache block can be sent to the store instruction prefetch queue. The second preset threshold (i.e., the number of store instructions) can be set based on actual conditions. The second preset threshold can be achieved by setting the control and status register (CSR) of the control processor through the operating system software, or can be pre-set by hardware, and the control and status register can be adjusted dynamically by software or hardware according to the behavior of the program.

[0070] In some embodiments, determining that a preset condition is satisfied may further include:

[0071] The duration of time after the store instruction cache enters the store buffer and no new store instruction is written and merged is used as the first duration, and it is determined that the first duration reaches the third preset threshold. After the store buffer is occupied to a certain threshold, the present invention gives priority to controlling the prefetching of cache blocks corresponding to store buffer entries that have not recently been merged with store instructions. The prefetching of the corresponding clock cycle threshold, i.e., the third preset threshold, is initiated after a certain number of clock cycles (i.e., the first duration) of no new store instruction enters the store buffer for write merging. This can be achieved by setting the control and status register (CSR) of the processor through the operating system software, or by presetting it through hardware. The control and status register can be adjusted dynamically by software or hardware according to the behavior of the program.

[0072] It can be understood that, for multiple storage instructions that can be merged, the timing starting point of the first time period is the moment when the last storage instruction among the multiple storage instructions enters the storage buffer, and within the first time period, no new storage instruction enters the storage buffer to be write-merged with the multiple storage instructions mentioned above.

[0073] The target cache block address included in the target store instruction in the store buffer is sent to the store instruction prefetch queue (Store Prefetch Queue) after waiting for a third preset threshold of clock cycles. When the data cache port is idle, an address query is initiated for the data cache to check for a store address hit in the data cache. If the store address misses, a prefetch request is sent to the miss queue (Store Miss Queue), which accesses the underlying storage system to obtain the required cache block data and backfill the data cache (DCache).

[0074] Furthermore, based on the target store instruction in the store buffer being sent to the store instruction prefetch queue after waiting for a third preset threshold of clock cycles, determining whether the preset condition is met further includes:

[0075] The duration of accessing the lower-layer storage system based on the block address of the target cache block, obtaining the data of the target cache block and backfilling the data into the data cache is used as the second duration;

[0076] The duration from when the target store instruction enters the store buffer to when the store instruction data is written into the target cache block in the data cache is used as a third duration;

[0077] Determine that the third duration is not less than the sum of the third preset threshold and the second duration.

[0078] Specifically, the clock threshold for each item in the store buffer to wait for a certain number of clock cycles (i.e., the third time period) without any new instructions entering the write-merge before being written into the data cache can also be achieved by setting the control and status register (CSR) of the processor through the operating system software, or can be pre-set through hardware, and the control and status register can be adjusted dynamically according to the behavior of the program, software, or hardware.

[0079] In the present invention, the clock cycle for writing to the data cache (i.e., the third duration) is no less than the prefetch clock cycle threshold (i.e., the third preset threshold) plus the duration for the memory access invalidation queue to retrieve a cache block from the lower-level storage system (i.e., the second duration). It is understood that the second duration can be predetermined for a specific computer processor system, and the present invention requires that the third duration be equal to or greater than the sum of the third preset threshold plus the second duration. The third preset threshold represents the duration from the time a target store instruction enters the store buffer until the block address of the target cache block included in the target store instruction is sent to the store instruction prefetch queue due to the lack of new store instructions for write-merging. If the clock cycle for writing to the data cache for the target store instruction (i.e., the third duration) is no less than the sum of the third preset threshold plus the second duration, this can minimize the problem of delayed prefetching caused by initiating a write to the data cache before prefetched data has returned. At the same time, it can avoid the situation where the storage buffer is very occupied. The storage instructions cannot be written from the storage buffer to the cache in time because they are waiting to get data from the lower storage system, which will cause the storage buffer to be full and affect the execution of subsequent instructions.

[0080] In some embodiments, not all block addresses of cache blocks included in store instructions will be sent to the store instruction prefetch queue. For example, multiple store instructions that have filled the entire cache line can directly perform a store address hit check of the data cache. In some other cases, such as when the store instruction prefetch queue is full and the store buffer is also full, some store instructions need to be processed in a timely manner even if they have not filled the entire cache line. For example, a store address hit check of the data cache can be directly performed on them, and when the address fails, the block address of the target cache block included in it can be sent to the memory access failure queue for data acquisition process.

[0081] Based on the above, the method may further include:

[0082] The duration for which other storage instructions cached in other cache lines are cached in the storage buffer is used as a fourth duration. After determining that the fourth duration reaches a fourth preset threshold, a storage address hit check of the data cache is directly performed, and the block address of the cache block included in the storage instruction address of the other storage instructions is not sent to the storage instruction prefetch queue. The other storage instructions can be understood as multiple storage instructions that have filled the entire cache line, or can be understood as storage instructions that do not fill the entire cache line and directly perform a storage address hit check of the data cache.

[0083] In some embodiments, for example, when the occupied space in the data buffer accounts for 60% of the total space, the block address of the target cache block is sent to the data buffer instruction prefetch queue. However, if the data buffer reaches 80% or more due to a blockage in the data buffer instruction prefetch queue or other reasons, to ensure efficient processor execution, the block addresses of the cache blocks that should have been sent to the data buffer instruction prefetch queue may no longer be sent to the data buffer instruction prefetch queue, but instead may be directly checked for data cache address hits. In this embodiment, certain preconditions may be set for data buffer instructions processed according to the above process. For example, the duration these data buffer instructions are cached in the data buffer may be accumulated, which may be counted as a fourth duration. When the accumulated fourth duration reaches a fourth preset threshold, it indicates that a large number of data buffer instructions are cached in the data buffer. The block addresses of the cache blocks included in these data buffer instructions may not be sent to the data buffer instruction prefetch queue, but may instead be directly checked for data cache address hits. The precondition may also be determining whether the proportion of occupied space in the data buffer reaches a fifth preset threshold. It can be understood that the fifth preset threshold is greater than the first preset threshold. For example, the first preset threshold is 60%, and the fifth preset threshold is 80%.

[0084] Among them, the fourth preset threshold value and the fifth preset threshold value can be achieved by setting the control and status register (CSR) of the control processor through the operating system software, or can be pre-set by hardware, and the control and status register can be adjusted dynamically by software or hardware according to the behavior of the program.

[0085] It can be understood that, for multiple storage instructions that can be merged, the timing starting point of the fourth time period is the moment when the last storage instruction among the multiple storage instructions enters the storage buffer. During the fourth time period, no new storage instruction enters the storage buffer to be write-merged with the multiple storage instructions mentioned above.

[0086] Further, the priority of performing a data cache store address hit check on the block address of the target cache block in the store instruction prefetch queue is lower than the priority of directly performing a data cache load instruction and a store address hit check on the block address of the cache block included in the load instruction and the other store instructions; and / or

[0087] In the memory access failure queue, the priority of data prefetching based on the block address of the target cache block in the store instruction prefetch queue is lower than the priority of directly acquiring data based on the block address of the cache block included in the fetch instruction and the other store instructions.

[0088] Specifically, the priority of the store instruction prefetch queue (Store Prefetch Queue) for hitting the data cache is set to be lower than the priority of the access to the data cache by the fetch instruction and the other store instructions mentioned above; and the priority of the prefetch request in the memory miss queue (Miss Queue) for accessing the lower-level storage system is also set to be lower than the access request to the lower-level storage system by the fetch instruction and the other store instruction misses mentioned above. This avoids the impact on the processor's normal memory access requests caused by the prefetch request occupying the processor's cache port and memory access bandwidth.

[0089] In the store instruction processing method provided by the present invention, the prefetch flag of the target store instruction can be set to identify that the prefetch request has been initiated for the target store instruction to distinguish it from other store instructions.

[0090] When the processor executes a store instruction, by setting a prefetch flag to mark whether the instruction has initiated a prefetch request, the instruction status can be accurately distinguished. For example, only the flag bit is marked for the target store instruction (such as setting it to 1), and its prefetch request has been triggered to avoid confusion with other store instructions that have not been prefetched. It can also avoid waste of resources. If it is detected that the flag bit is set, the subsequent process skips repeated prefetching to prevent redundant requests from occupying memory bandwidth and increasing the risk of cache pollution (such as squeezing out useful cache lines). It also supports complex execution flow management. When out-of-order execution or abnormal re-execution occurs, the flag bit provides the hardware with a basis for rapid status judgment (such as whether the prefetch is completed), simplifying pipeline scheduling decisions. The present invention accurately tracks the prefetch status of the target instruction through the flag bit, optimizes resource utilization and improves execution efficiency.

[0091] The storage instruction processing method provided in the present invention can improve the pre-fetching accuracy and pre-fetching timeliness of storage instructions, avoid unnecessary pre-fetching, and reduce the impact of storage instruction pre-fetching on the cache port and memory access bandwidth used for normal memory access operations of the processor, thereby improving the overall performance of the processor.

[0092] Figure 3 An example of a physical structure diagram of an electronic device is shown below. Figure 3 As shown, the electronic device may include: a processor 310, a communications interface 320, a memory 330, and a communication bus 340, wherein the processor 310, the communications interface 320, and the memory 330 communicate with each other via the communication bus 340. The processor 310 may call the logic instructions in the memory 330 to execute the method for processing a data storage instruction described in any of the above embodiments, for example, including:

[0093] Cache the store instruction to be processed into the store buffer, and when it is determined that a preset condition is met, send the block address of the target cache block corresponding to the target cache line in the store buffer to the store instruction prefetch queue; all the target store instructions cached in the target cache line do not fill the target cache line, and the store instruction address of the target store instruction includes the block address of the target cache block; the store instruction includes the store instruction address and store instruction data;

[0094] Performing a data cache address hit check on the block address of the target cache block in the data instruction prefetch queue, and in the case where the data address fails, initiating a prefetch request and sending the block address of the target cache block to a memory access failure queue;

[0095] Performing data prefetching, the data prefetching comprising accessing a lower-layer storage system based on a block address of the target cache block, obtaining data of the target cache block, and backfilling the data into the data cache;

[0096] The store instruction data included in the target store instruction for which a prefetch request is initiated and prefetched successfully is written into the target cache block in the data cache.

[0097] Furthermore, the logic instructions in the aforementioned memory 330 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0098] On the other hand, the present invention further provides a computer program product, comprising a computer program. The computer program may be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the method for processing a store instruction described in any of the above embodiments, for example, including:

[0099] Cache the store instruction to be processed into the store buffer, and when it is determined that a preset condition is met, send the block address of the target cache block corresponding to the target cache line in the store buffer to the store instruction prefetch queue; all the target store instructions cached in the target cache line do not fill the target cache line, and the store instruction address of the target store instruction includes the block address of the target cache block; the store instruction includes the store instruction address and store instruction data;

[0100] Performing a data cache address hit check on the block address of the target cache block in the data instruction prefetch queue, and in the case where the data address fails, initiating a prefetch request and sending the block address of the target cache block to a memory access failure queue;

[0101] Performing data prefetching, the data prefetching comprising accessing a lower-layer storage system based on a block address of the target cache block, obtaining data of the target cache block, and backfilling the data into the data cache;

[0102] The store instruction data included in the target store instruction for which a prefetch request is initiated and prefetched successfully is written into the target cache block in the data cache.

[0103] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for processing a store instruction described in any one of the above embodiments is implemented, for example, including:

[0104] Cache the store instruction to be processed into the store buffer, and when it is determined that a preset condition is met, send the block address of the target cache block corresponding to the target cache line in the store buffer to the store instruction prefetch queue; all the target store instructions cached in the target cache line do not fill the target cache line, and the store instruction address of the target store instruction includes the block address of the target cache block; the store instruction includes the store instruction address and store instruction data;

[0105] Performing a data cache address hit check on the block address of the target cache block in the data instruction prefetch queue, and in the case where the data address fails, initiating a prefetch request and sending the block address of the target cache block to a memory access failure queue;

[0106] Performing data prefetching, the data prefetching comprising accessing a lower-layer storage system based on a block address of the target cache block, obtaining data of the target cache block, and backfilling the data into the data cache;

[0107] The store instruction data included in the target store instruction for which a prefetch request is initiated and prefetched successfully is written into the target cache block in the data cache.

[0108] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0109] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for processing a store instruction, characterized in that: include: Cache the store instruction to be processed into the store buffer, and when it is determined that a preset condition is met, send the block address of the target cache block corresponding to the target cache line in the store buffer to the store instruction prefetch queue; all the target store instructions cached in the target cache line do not fill the target cache line, and the store instruction address of the target store instruction includes the block address of the target cache block; the store instruction includes the store instruction address and store instruction data; Performing a data cache address hit check on the block address of the target cache block in the data instruction prefetch queue, and in the case where the data address fails, initiating a prefetch request and sending the block address of the target cache block to a memory access failure queue; Performing data prefetching, the data prefetching comprising accessing a lower-layer storage system based on a block address of the target cache block, obtaining data of the target cache block, and backfilling the data into the data cache; Writing the store instruction data included in the target store instruction for which a prefetch request is initiated and prefetched successfully into the target cache block in the data cache; Determining that the preset condition is met includes: Determining whether a ratio of occupied space in the data storage buffer reaches a first preset threshold; or Determining whether the number of cache blocks corresponding to the pending store instructions cached in the store buffer reaches a second preset threshold; or The duration during which no new store instruction is written and merged after the store instruction is cached into the store buffer is used as the first duration, and it is determined that the first duration reaches a third preset threshold.

2. The method for processing a store instruction according to claim 1, wherein: The determining that the preset condition is satisfied further includes: The duration of accessing the lower-layer storage system based on the block address of the target cache block, obtaining the data of the target cache block and backfilling the data into the data cache is used as the second duration; The duration from when the target store instruction enters the store buffer to when the store instruction data is written into the target cache block in the data cache is used as a third duration; Determine that the third duration is not less than the sum of the third preset threshold and the second duration.

3. The method for processing a store instruction according to claim 1, wherein: The first preset threshold and the second preset threshold are preset.

4. The method for processing a store instruction according to claim 3, wherein: The first preset threshold and the second preset threshold are realized by setting the control and status registers of the control processor through the operating system software, or are pre-set through hardware.

5. The method for processing a store instruction according to claim 1 or 2, wherein: The third preset threshold is preset.

6. The method for processing a store instruction according to claim 5, wherein: The third preset threshold is realized by setting the control and status registers of the control processor through the operating system software, or is pre-set through hardware.

7. The method for processing a store instruction according to claim 1, wherein: The method further comprises: Using the duration for which other store instructions cached in other cache lines are cached in the store buffer as a fourth duration, and after determining that the fourth duration reaches a fourth preset threshold, directly performing a store address hit check of the data cache, and determining that the block address of the cache block included in the store instruction address of the other store instruction has not been sent to the store instruction prefetch queue; or Determine whether the proportion of occupied space in the data buffer reaches a fifth preset threshold.

8. The method for processing a store instruction according to claim 7, wherein: The fourth preset threshold and the fifth preset threshold are realized by setting the control and status registers of the control processor through the operating system software, or are pre-set through hardware.

9. The method for processing a store instruction according to claim 7, wherein: The priority of performing a data cache store address hit check on the block address of the target cache block in the store instruction prefetch queue is lower than the priority of directly performing a data cache load address hit and store address hit check on the block addresses of the cache blocks included in the load instruction and the other store instructions; and / or In the memory access failure queue, the priority of data prefetching based on the block address of the target cache block in the store instruction prefetch queue is lower than the priority of directly acquiring data based on the block address of the cache block included in the fetch instruction and the other store instructions.

10. The method for processing a store instruction according to claim 1, wherein: The method further comprises: The prefetch flag of the target store instruction is set to indicate that the prefetch request has been initiated for the target store instruction.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the store instruction processing method according to any one of claims 1 to 10 is implemented.

12. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the storage instruction processing method according to any one of claims 1 to 10 is implemented.

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