Cascade anti-interference circuit suitable for electrocardiogram monitoring equipment

Abstract

The embodiment of the invention provides a cascade anti-interference circuit suitable for electrocardiogram monitoring equipment. The cascade anti-interference circuit comprises a sliding mean filtering module, a notch filtering module, a lifting wavelet decomposition module, a threshold calculation module, a threshold processing module and a lifting wavelet reconstruction module. While a small circuit scale is ensured, hierarchical noise reduction processing is carried out on ECG signals collected by wearable electrocardiogram monitoring equipment, and ECG signal output with a high signal-to-noise ratio is achieved. The method comprises the following steps: firstly, carrying out sliding mean filtering on an ECG signal collected by wearable ECG monitoring equipment, and filtering baseline drift noise caused by activities such as human respiratory movement and the like; a notch filtering module is used for inhibiting power frequency interference caused by wired and wireless connection of an electromagnetic environment around the equipment; and finally, wavelet noise reduction is realized by using a method for improving wavelet decomposition and reconstruction and threshold noise reduction, and myoelectricity interference caused by autonomous or unconscious movement of the wearer is inhibited, so that an ECG signal with a high signal-to-noise ratio is output and is used for physiological parameter extraction and electrocardio diagnosis.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of digital integrated circuits, and in particular to a cascade anti-interference circuit suitable for electrocardiogram monitoring equipment. Background Art

[0002] Cardiovascular disease (CVD) has become a leading global public health threat. Multiple social pressures and disrupted lifestyles have led to a continued rise in CVD incidence, with a significant trend of younger patients. Globally, approximately 18 million people die from CVD each year, accounting for 31% of all deaths worldwide. my country has a significant CVD patient base, with epidemiological surveys indicating over 330 million people are affected. Traditional electrocardiograms (ECGs) can serve as the gold standard for clinical diagnosis, but their large size and intermittent nature restrict their use to specialized medical settings such as hospitals, making them inadequate for early warning and long-term health management of cardiovascular disease patients. Wearable ECG monitoring devices, by collecting real-time physiological data, offer solutions for the long-term health management of CVD patients and hold significant clinical value. However, ECG signals, as typically weak physiological signals, are susceptible to various noise artifacts during acquisition, requiring prior noise reduction processing to meet clinical diagnostic needs. Summary of the Invention

[0003] An embodiment of the present invention provides a cascade anti-interference circuit suitable for an electrocardiogram (ECG) monitoring device, so as to solve the problem of noise doping in ECG signals collected by existing wearable ECG monitoring devices.

[0004] An embodiment of the present invention provides a cascade anti-interference circuit suitable for electrocardiogram monitoring equipment, comprising: A sliding mean filter module is used to receive an electrocardiogram (ECG) signal and extract a low-frequency component of the ECG signal to obtain an ECG signal with a suppressed baseline drift; a notch filter module, configured to receive the ECG signal processed by the sliding mean filter module, and determine the center frequency point and quality factor based on the power frequency interference frequency characteristic information, thereby eliminating the power frequency interference in the ECG signal; a lifting wavelet decomposition module, configured to receive the ECG signal processed by the notch filter module and decompose the ECG signal into a first-layer detail coefficient group, a second-layer detail coefficient group, a third-layer detail coefficient group and a first-layer approximation coefficient group through three-layer lifting wavelet decomposition; a threshold calculation module, configured to receive the second layer detail coefficient group and the third layer detail coefficient group, and perform median extraction and multiplication and division operations to obtain thresholds of corresponding levels; a threshold processing module, configured to perform forced denoising on the first-layer detail coefficient group, and perform threshold denoising on the second-layer detail coefficient group and the third-layer detail coefficient group based on thresholds of corresponding levels; The lifting wavelet reconstruction module is used to receive the first layer detail coefficient group, the second layer detail coefficient group, the third layer detail coefficient group and the first layer approximation coefficient group processed by the threshold processing module, and perform lifting wavelet reconstruction layer by layer to output the ECG reconstructed signal after noise reduction.

[0005] Preferably, the sliding mean filter module includes a shift register group, three two-input summers, a delay register and a shifter; the window length of the shift register group is 32, which is used for data shift storage, and two groups of two-input summers are used to sum 32 data, of which 31 data can be taken.

[0006] Preferably, the notch filter module is a second-order infinite impulse response (IIR) filter.

[0007] Preferably, the lifting wavelet decomposition module includes a first-layer lifting wavelet decomposition unit, a second-layer lifting wavelet decomposition unit, and a third-layer lifting wavelet decomposition unit; The approximate coefficient group obtained after the input signal passes through the first layer lifting wavelet decomposition unit is used as the input signal of the second layer lifting wavelet decomposition unit, and the approximate coefficient group of the second layer lifting wavelet decomposition unit is used as the input signal of the third layer lifting wavelet decomposition unit.

[0008] Preferably, the first-layer lifting wavelet decomposition unit, the second-layer lifting wavelet decomposition unit, and the third-layer lifting wavelet decomposition unit all include a clock frequency division subunit, a sequence parity splitting subunit, and a prediction updating subunit; The clock frequency division sub-unit realizes the generation and distribution of clocks for various parts of the system by dividing the master clock at different levels; The sequence parity splitting subunit realizes the splitting of the main sequence for prediction update operation by identifying clock pulses of different frequencies; The prediction and update subunit realizes the approximation of the approximate coefficient group and the detail coefficient group through multiple prediction operations and update operations; After single-layer lifting wavelet decomposition, the original sequence is decomposed into a detail coefficient group containing the detail part and an approximate coefficient group containing the remaining part.

[0009] Preferably, the threshold calculation module includes a first absolute value extraction unit, a bitonic network sorting median extraction unit and a threshold multiplication operation unit; The first absolute value extraction unit performs absolute value conversion on the input 16-bit signed number format signal, performs bitonic network sorting on the obtained absolute value sequence, extracts the median value according to the sorting order for threshold calculation, uses the extracted median value to perform threshold multiplication calculation, and obtains the upper and lower thresholds for threshold processing as a result of the threshold multiplication calculation, which are further output to the threshold processing module; The bitwise network sorting median extraction unit includes a discriminator, a bitwise invertor, a two-input adder, a two-to-one selector, and a register. It determines the positive or negative of the data by judging the high bit of the input signal, directly outputs the positive number with a sign bit of 0, and performs a bitwise inversion and then adds 1 to the negative number with a sign bit of 1. Finally, it selects and outputs the absolute value sequence of the input sequence. The threshold multiplication operation unit includes two multipliers, two registers, four shifters, and two two-input summers; the two paths respectively calculate the upper and lower thresholds of the second-layer detail coefficient group and the third-layer detail coefficient group.

[0010] Preferably, the threshold processing unit includes a second absolute value extraction unit, a threshold determination unit, a nonlinear operation unit and an output selection unit; The second absolute value extraction unit is used to extract the absolute value of the input signal; The threshold determination unit is configured to generate a selection signal sel based on the relative size of the absolute value and the upper and lower thresholds, and generate three different selection signals for the three situations where the absolute value is less than the lower threshold, the absolute value is greater than the upper threshold, and the absolute value is between the upper and lower thresholds; when the absolute value is greater than the upper threshold, the input signal is directly output; when the absolute value is less than the lower threshold, the output is set to zero; and when the absolute value is between the upper and lower thresholds, a nonlinear operation is used for output; The nonlinear operation unit includes a division operator unit, a square operator unit and a sign bit splicing operator unit.

[0011] Preferably, the lifting wavelet reconstruction module includes a cascaded first lifting wavelet reconstruction unit, a second lifting wavelet reconstruction unit, and a third lifting wavelet reconstruction unit; The input signal of the first lifting wavelet reconstruction unit is the third-layer detail coefficient group and the third-layer approximate coefficient group after threshold processing. The reconstructed new second-layer approximate coefficient group is connected to the second-layer lifting wavelet reconstruction unit as an input signal, and the new first-layer approximate coefficient group reconstructed from the second-layer detail coefficient group after threshold processing is connected to the third-layer lifting wavelet reconstruction unit as an input signal, and reconstructs the denoised ECG reconstruction signal with the first-layer detail coefficient group after forced denoising.

[0012] Preferably, the first lifting wavelet reconstruction unit, the second lifting wavelet reconstruction unit, and the third lifting wavelet reconstruction unit all include a clock frequency division subunit, an anti-prediction and anti-update subunit, and a parity sequence merging subunit; The clock division subunit is used for generating and distributing the global clock. The anti-prediction and anti-update subunit is used for performing multiple anti-prediction and anti-update operations on the input approximate coefficient group and detail coefficient group to make them approach the parity sequence of the reconstructed sequence. The parity sequence merging subunit merges them to obtain the ECG reconstructed signal.

[0013] An embodiment of the present invention provides a cascaded anti-interference circuit suitable for electrocardiogram (ECG) monitoring equipment, comprising a sliding mean filter module, a notch filter module, a lifting wavelet decomposition module, a threshold calculation module, a threshold processing module, and a lifting wavelet reconstruction module. While ensuring a small circuit scale, the circuit performs hierarchical noise reduction processing on the ECG signal collected by the wearable ECG monitoring equipment to achieve an ECG signal output with a high signal-to-noise ratio. For the ECG signal collected by the wearable ECG monitoring equipment, the circuit of the present invention first performs a sliding mean filter to filter out baseline drift noise caused by human breathing and other activities; secondly, a notch filter module is used to suppress power frequency interference caused by the electromagnetic environment around the equipment through wired and wireless connections; finally, lifting wavelet decomposition and reconstruction and threshold noise reduction methods are used to achieve wavelet noise reduction, suppress myoelectric interference caused by the wearer's voluntary or unconscious movements, and output an ECG signal with a high signal-to-noise ratio for physiological parameter extraction and ECG diagnosis. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 It is a schematic diagram of the overall structure provided by an embodiment of the present invention; Figure 2 Schematic diagram of a sliding mean filter module provided by an embodiment of the present invention; Figure 3 Schematic diagram of a notch filter module provided by an embodiment of the present invention; Figure 4 1 is a general schematic diagram of a wavelet denoising module provided by an embodiment of the present invention; Figure 5 Schematic diagram of a lifting wavelet decomposition module provided by an embodiment of the present invention; Figure 6 Schematic diagram of a single-layer lifting wavelet decomposition module provided by an embodiment of the present invention; Figure 7 is a schematic diagram of a threshold calculation module provided by an embodiment of the present invention; Figure 8 2 is a schematic diagram of an absolute value extraction unit provided by an embodiment of the present invention; Figure 9 Schematic diagram of a timing alignment unit provided by an embodiment of the present invention; Figure 10 2 is a schematic diagram of a threshold multiplication operation module provided by an embodiment of the present invention; Figure 11 is a schematic diagram of a threshold processing module provided by an embodiment of the present invention; Figure 12 Schematic diagram of a lifting wavelet reconstruction module provided by an embodiment of the present invention; Figure 13 Schematic diagram of a single-layer lifting wavelet reconstruction unit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0017] In the embodiments of the present application, the term "and / or" is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0018] The terms "first" and "second" in the embodiments of the present application are only used for descriptive purposes and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present application, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a system, product or device comprising a series of components or units is not limited to the listed components or units, but may optionally also include components or units that are not listed, or may optionally also include other components or units that are inherent to these products or devices. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0019] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0020] Wearable ECG monitoring devices offer significant clinical value by collecting real-time physiological data, providing solutions for the long-term health management of CVD patients. However, ECG signals, as typically weak physiological signals, are susceptible to various noise interferences during the acquisition process, requiring pre-processing for noise reduction to meet the needs of clinical disease diagnosis.

[0021] Therefore, the embodiment of the present invention provides a cascade anti-interference circuit suitable for electrocardiogram monitoring equipment, such as Figure 1 As shown in , including: A sliding mean filter module is used to receive an electrocardiogram (ECG) signal and extract a low-frequency component of the ECG signal to obtain an ECG signal with a suppressed baseline drift; Among them, the sliding mean filter module is connected to the electrocardiogram sensor, and the input end of the electrocardiogram sensor module is the human body electrical signal. By capturing the human body electrical signal, the ECG signal is collected, and the signal is converted from digital to analog and transmitted to the cascade anti-interference circuit for noise suppression; the input end of the sliding mean filter module is the ECG signal collected and digitized by the electrocardiogram sensor. Since the original ECG signal is easily interfered by low-frequency baseline drift noise during acquisition, the sliding mean filter module is used to extract the low-frequency component to obtain the baseline drift signal.

[0022] a notch filter module, configured to receive the ECG signal processed by the sliding mean filter module, and determine the center frequency point and quality factor based on the power frequency interference frequency characteristic information, thereby eliminating the power frequency interference in the ECG signal; Specifically, the input end of the notch filter module is the ECG signal after passing through the sliding mean filter module and performing difference processing. At this time, the baseline drift of the ECG signal is fully suppressed. The notch filter module is used to filter out the power frequency interference coupled into the circuit by the electromagnetic environment, thereby further improving the signal-to-noise ratio of the ECG signal.

[0023] The lifting wavelet decomposition module is used to receive the ECG signal processed by the notch filter module, and decompose the ECG signal into a first-layer detail coefficient group, a second-layer detail coefficient group, a third-layer detail coefficient group and a first-layer approximate coefficient group through three-layer lifting wavelet decomposition; the input end of the lifting wavelet decomposition module is the ECG signal after notch filtering, and the ECG signal is decomposed into three groups of detail coefficients and one group of approximate coefficients through three-layer lifting wavelet decomposition for subsequent extraction and suppression of electromyographic interference.

[0024] a threshold calculation module, configured to receive the second-layer detail coefficient group and the third-layer detail coefficient group, and perform median extraction and multiplication and division operations to obtain thresholds of corresponding levels; specifically, the threshold calculation module extracts the median after performing bitonic sorting on the second-layer detail coefficient group and the third-layer detail coefficient group, and performs threshold calculation based on the median to obtain the second-layer threshold Th2 and the third-layer threshold Th3 and output them; The threshold calculation module includes a bitonic sorting unit and a threshold calculation unit. The bitonic sorting unit uses a sorting algorithm to sort the sequence by size and extract the median. The threshold calculation unit solves the threshold according to the median and threshold calculation formula. The threshold value obtaining unit is designed to include two multipliers and one register. The upper and lower threshold values are obtained by using the multiplier and then stored and outputted by using the register.

[0025] For each detail coefficient group, the threshold calculation module will output two different thresholds. The upper and lower thresholds can facilitate the threshold processing module to perform nonlinear dual threshold processing.

[0026] A threshold processing module is used to perform forced noise reduction processing on the first-layer detail coefficient group, and to perform threshold noise reduction processing on the second-layer detail coefficient group and the third-layer detail coefficient group based on the threshold of the corresponding level; the threshold processing module includes 2 comparators, 2 selectors, 1 absolute value finder, 1 squarer, 1 divider and 4 registers for storing outputs. According to the relationship between the input value and the upper and lower thresholds, three operations of zeroing, improved function calculation and direct output are performed respectively to meet the needs of threshold processing.

[0027] The lifting wavelet reconstruction module is used to receive the first layer detail coefficient group, the second layer detail coefficient group, the third layer detail coefficient group and the first layer approximation coefficient group processed by the threshold processing module, and perform lifting wavelet reconstruction layer by layer to output the ECG reconstructed signal after noise reduction.

[0028] Specifically, each layer of the lifting wavelet reconstruction module includes three deprediction operations, two deupdate operations, and one denormalization operation, including 10 multipliers, 9 delay registers, and 5 adders. The multipliers are used to access the deprediction and deupdate values, the delay registers are used for feedback operations, and the adders are used for iteration of the internal deprediction and deupdate values. Each layer of reconstruction of the lifting wavelet reconstruction module includes multiple inverse prediction and inverse update operations and inverse normalization operations. After each operation, the output is stored in a register. The pipeline structure is used to avoid overly long combinational logic and improve circuit performance.

[0029] Based on the above embodiments, as a preferred implementation, Figure 2 As shown in , the sliding mean filter module includes a shift register group, three two-input summers, a delay register, and a shifter. The shift register group is 32 in length and 16 in data width, requiring 32×16 registers to store ECG data at different positions and delays. Two sets of two-input summers are used to sum 32 data points, of which 31 data points can be used, optimizing circuit area and power consumption. The summed data is shifted to achieve mean calculation. The sliding mean filter circuit has a window width of 32 and includes 32 delay registers and a right shifter. The circuit is used to extract baseline drift and suppress it by subtracting it from the original signal.

[0030] The sliding mean filtering module also includes a mean updater and a difference finder. The mean updater is used to update the window sum corresponding to different points. The repeated data of the mean calculation of two adjacent data points can be reused to optimize the circuit area and power consumption. The difference finder is used to difference the noisy signal and the baseline drift signal to suppress the baseline drift noise. The input end of the shift register group is connected to the output end of the electrocardiograph sensor, the input end of the mean updater is connected to the output end of the shift register group, and the input end of the difference finder is connected to the output end of the mean updater.

[0031] Based on the above embodiment, as a preferred implementation, the notch filter module is a second-order infinite impulse response IIR filter, such as Figure 3As shown in , a direct I-type structure is used for circuit implementation. The circuit includes four delay registers, five multipliers, and four adders. The circuit is used to filter out power frequency interference coupled into the circuit by the external electromagnetic environment, thereby improving the ECG signal-to-noise ratio. The notch filter module has a center frequency of 50Hz, a quality factor of 50, and a 3dB stopband width of 1Hz. The notch filter module can achieve targeted noise suppression at the center frequency point, with minimal impact on the effective signal components near the center frequency point, achieving good power frequency interference suppression. The input of the notch filter module is connected to the output of the sliding mean filter module.

[0032] In this embodiment, the lifting wavelet decomposition module, the threshold calculation module, the threshold processing module and the lifting wavelet reconstruction module constitute a wavelet denoising system. Figure 4 As shown in , the process includes three-layer lifting wavelet decomposition, forced denoising, threshold processing and three-layer wavelet reconstruction; the detail coefficient group obtained by the first-layer lifting wavelet decomposition is subjected to forced denoising, the detail coefficient groups of the second and third-layer lifting wavelet decompositions are subjected to threshold processing, and the third-layer approximate coefficient group and the processed three-layer detail coefficient group are subjected to three-layer lifting wavelet reconstruction to obtain the signal after wavelet denoising.

[0033] Based on the above embodiment, as a preferred implementation, the lifting wavelet decomposition module includes a first-layer lifting wavelet decomposition unit, a second-layer lifting wavelet decomposition unit, and a third-layer lifting wavelet decomposition unit; The approximate coefficient group obtained after the input signal passes through the first layer lifting wavelet decomposition unit is used as the input signal of the second layer lifting wavelet decomposition unit, and the approximate coefficient group of the second layer lifting wavelet decomposition unit is used as the input signal of the third layer lifting wavelet decomposition unit.

[0034] The lifting wavelet decomposition module is composed of three layers of decomposition circuits, each layer of decomposition circuits includes a clock division unit, a sequence parity splitting unit and a prediction update operation unit. The clock division unit is responsible for dividing the input clock signal by different multiples to provide a suitable working clock for the sequence parity splitting unit and the prediction update operation unit. The sequence parity splitting unit divides the input signal into an even sequence group and an odd sequence group according to the clock pulse. The prediction update operation unit performs multiple prediction and update operations on the parity sequence group, so that the parity sequence group continuously approaches the detail coefficient and the approximate coefficient, and finally completes the lifting wavelet decomposition. The input end of the lifting wavelet decomposition module is connected to the output end of the notch filter module. The three layers of lifting wavelet decomposition are cascaded. The approximate coefficient group of each layer of lifting wavelet decomposition serves as the input signal of the next layer of lifting wavelet decomposition.

[0035] Specifically, the lifting wavelet decomposition module adopts a three-layer lifting wavelet decomposition structure and uses the sym4 wavelet basis function for wavelet decomposition; Each layer of the lifting wavelet decomposition circuit includes three prediction operations, two update operations, and one normalization operation, including 10 multipliers, 9 delay registers, and 5 adders. The multipliers are used to access the prediction update value, the delay registers are used for feedback operations, and the adders are used for internal prediction update value iteration. Each layer of decomposition of the lifting wavelet decomposition circuit includes multiple prediction update operations and normalization operations. After each operation, the output is stored in a register. The pipeline structure is used to avoid overly long combinational logic and improve circuit performance.

[0036] Based on the above embodiments, as a preferred implementation, Figure 6 As shown in , the first-layer lifting wavelet decomposition unit, the second-layer lifting wavelet decomposition unit, and the third-layer lifting wavelet decomposition unit all include a clock frequency division subunit, a sequence parity splitting subunit, and a prediction update subunit; The clock division subunit realizes the generation and distribution of clocks for various parts of the system by dividing the main clock at different levels; it divides the input clock signal by different multiples to provide a suitable working clock for the sequence parity splitting subunit and the prediction update operation subunit.

[0037] The sequence parity splitting subunit realizes the splitting of the main sequence for prediction update operation by identifying clock pulses of different frequencies; the input signal is divided into an even sequence group and an odd sequence group according to the clock pulses.

[0038] The prediction and update subunit realizes the approximation of the approximate coefficient group and the detail coefficient group through multiple prediction operations and update operations; multiple prediction and update operations are performed on the parity sequence group, so that the parity sequence group continuously approaches the detail coefficient and the approximate coefficient, and finally completes the lifting wavelet decomposition.

[0039] The input end of the lifting wavelet decomposition module is connected to the output end of the notch filter module. After the single-layer lifting wavelet decomposition, the original sequence is decomposed into a detail coefficient group containing the detail part and an approximate coefficient group containing the remaining part.

[0040] Based on the above embodiments, as a preferred implementation, Figure 7 As shown in , the threshold calculation module includes a first absolute value extraction unit, a bitonic network sorting median extraction unit and a threshold multiplication operation unit; The first absolute value extraction unit is responsible for converting the input signed number signal into an absolute value for median extraction. The bitonic network sorting median extraction unit performs bitonic network sorting on the signal absolute value and extracts the median for threshold multiplication calculation based on the sorting result. The threshold multiplication operation unit is responsible for further multiplying the extracted median to obtain specific upper and lower thresholds. The timing alignment unit is used to beat and delay the original ECG signal to perform timing alignment with the threshold value after sorting extraction and multiplication to prevent timing misalignment in the threshold processing module. The input end of the threshold calculation module is connected to the output end of the lifting wavelet decomposition module, and the input signal is the second and third layer detail coefficients of the lifting wavelet decomposition module.

[0041] The structure of the first absolute value extraction unit is as follows Figure 8 As shown, it includes a discriminator, a bitwise inverter, a two-input adder, a two-to-one selector and a register. The positive and negative data are determined by judging the high bit of the input signal. For positive numbers with a sign bit of 0, they are directly output. For negative numbers with a sign bit of 1, they are bitwise inverted and then added with 1. Finally, the absolute value sequence of the input sequence can be obtained by selection and output.

[0042] The structure of the timing alignment unit is as follows Figure 9 As shown, the device consists of two dual-port RAMs, a 6-bit counter, a value discriminator, a binary selector, an inverter, and an enable register. Since the median extraction module has a delay of 64 clock cycles, to ensure that the threshold calculation result is aligned with the timing of the corresponding processed data segment, two dual-port RAMs are used to perform a ping-pong operation to repeatedly store and read data, achieving a 64-clock delay. At the same time, one of the two dual-port RAMs is in the write state and the other is in the read state to ensure uninterrupted data transmission. The counter, value discriminator, and inverter jointly generate the dual-port RAM's read and write control signals. The binary selector is responsible for gating the output terminals of the two RAMs.

[0043] The bitwise network sorting median extraction unit includes a discriminator, a bitwise invertor, a two-input adder, a two-to-one selector, and a register. It determines the positive or negative of the data by judging the high bit of the input signal, directly outputs the positive number with a sign bit of 0, and performs a bitwise inversion and then adds 1 to the negative number with a sign bit of 1. Finally, it selects and outputs the absolute value sequence of the input sequence. The threshold multiplication unit, such as Figure 10As shown, it includes two multipliers, two registers, four shifters, and two two-input summers; the two paths respectively calculate the upper and lower thresholds of the second-level detail coefficient group and the third-level detail coefficient group, among which the multiplication coefficients c1 and c2 can be implemented by the shift-and-add method to optimize the circuit area and power consumption. For each path, the upper and lower thresholds are in a 1.5-fold relationship.

[0044] Based on the above embodiments, as a preferred implementation, Figure 11 As shown in , the threshold processing module includes a second absolute value extraction unit, a threshold determination unit, a nonlinear operation unit and an output selection unit; The second absolute value extraction unit is used to extract the absolute value of the input signal; The threshold determination unit is configured to generate a selection signal sel based on the relative size of the absolute value and the upper and lower thresholds, and generate three different selection signals for the three situations where the absolute value is less than the lower threshold, the absolute value is greater than the upper threshold, and the absolute value is between the upper and lower thresholds; when the absolute value is greater than the upper threshold, the input signal is directly output; when the absolute value is less than the lower threshold, the output is set to zero; and when the absolute value is between the upper and lower thresholds, a nonlinear operation is used for output; The nonlinear operation unit includes a division operator unit, a square operator unit and a sign bit splicing operator unit.

[0045] Based on the above embodiments, as a preferred implementation, Figure 12 As shown in , the lifting wavelet reconstruction module includes a cascaded first lifting wavelet reconstruction unit, a second lifting wavelet reconstruction unit, and a third lifting wavelet reconstruction unit; The input signal of the first lifting wavelet reconstruction unit is the third-layer detail coefficient group and the third-layer approximate coefficient group after threshold processing. The reconstructed new second-layer approximate coefficient group is connected to the second-layer lifting wavelet reconstruction unit as an input signal, and the new first-layer approximate coefficient group reconstructed from the second-layer detail coefficient group after threshold processing is connected to the third-layer lifting wavelet reconstruction unit as an input signal, and reconstructs the denoised ECG reconstruction signal with the first-layer detail coefficient group after forced denoising.

[0046] Based on the above embodiments, as a preferred implementation, Figure 13 As shown in , the first lifting wavelet reconstruction unit, the second lifting wavelet reconstruction unit, and the third lifting wavelet reconstruction unit all include a clock frequency division subunit, an anti-prediction and anti-update subunit, and a parity sequence merging subunit; The clock division subunit is used for generating and distributing the global clock. The anti-prediction and anti-update subunit is used for performing multiple anti-prediction and anti-update operations on the input approximate coefficient group and detail coefficient group to make them approach the parity sequence of the reconstructed sequence. The parity sequence merging subunit merges them to obtain the ECG reconstructed signal.

[0047] The various embodiments of the present invention can be combined arbitrarily to achieve different technical effects.

[0048] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in this application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive).

[0049] Those skilled in the art will appreciate that all or part of the process steps in the above-described method embodiments can be implemented by a computer program instructing the relevant hardware. The program can be stored in a computer-readable storage medium, and when executed, the program can include the process steps in the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A cascade anti-interference circuit suitable for electrocardiogram monitoring equipment, characterized in that: include: A sliding mean filter module is used to receive an electrocardiogram (ECG) signal and extract a low-frequency component of the ECG signal to obtain an ECG signal with a suppressed baseline drift; a notch filter module, configured to receive the ECG signal processed by the sliding mean filter module, and determine the center frequency point and quality factor based on the power frequency interference frequency characteristic information, thereby eliminating the power frequency interference in the ECG signal; a lifting wavelet decomposition module, configured to receive the ECG signal processed by the notch filter module and decompose the ECG signal into a first-layer detail coefficient group, a second-layer detail coefficient group, a third-layer detail coefficient group and a first-layer approximation coefficient group through three-layer lifting wavelet decomposition; a threshold calculation module, configured to receive the second layer detail coefficient group and the third layer detail coefficient group, and perform median extraction and multiplication and division operations to obtain thresholds of corresponding levels; a threshold processing module, configured to perform forced denoising on the first-layer detail coefficient group, and perform threshold denoising on the second-layer detail coefficient group and the third-layer detail coefficient group based on thresholds of corresponding levels; The lifting wavelet reconstruction module is used to receive the first layer detail coefficient group, the second layer detail coefficient group, the third layer detail coefficient group and the first layer approximation coefficient group processed by the threshold processing module, and perform lifting wavelet reconstruction layer by layer to output the ECG reconstructed signal after noise reduction.

2. The cascade anti-interference circuit suitable for electrocardiogram monitoring equipment according to claim 1, characterized in that: The sliding mean filter module includes a shift register group, three two-input summers, a delay register and a shifter; the window length of the shift register group is 32, which is used for data shift storage, and two groups of two-input summers are used to sum 32 data, of which 31 data can be used.

3. The cascade anti-interference circuit suitable for electrocardiogram monitoring equipment according to claim 1, characterized in that: The notch filter module is a second-order infinite impulse response (IIR) filter.

4. The cascade anti-interference circuit for electrocardiogram monitoring equipment according to claim 1, characterized in that: The lifting wavelet decomposition module includes a first-layer lifting wavelet decomposition unit, a second-layer lifting wavelet decomposition unit, and a third-layer lifting wavelet decomposition unit; The approximate coefficient group obtained after the input signal passes through the first layer lifting wavelet decomposition unit is used as the input signal of the second layer lifting wavelet decomposition unit, and the approximate coefficient group of the second layer lifting wavelet decomposition unit is used as the input signal of the third layer lifting wavelet decomposition unit.

5. The cascade anti-interference circuit suitable for electrocardiogram monitoring equipment according to claim 4, characterized in that: The first-layer lifting wavelet decomposition unit, the second-layer lifting wavelet decomposition unit, and the third-layer lifting wavelet decomposition unit all include a clock frequency division subunit, a sequence parity splitting subunit, and a prediction updating subunit; The clock frequency division sub-unit realizes the generation and distribution of clocks for various parts of the system by dividing the master clock at different levels; The sequence parity splitting subunit realizes the splitting of the main sequence for prediction update operation by identifying clock pulses of different frequencies; The prediction and update subunit realizes the approximation of the approximate coefficient group and the detail coefficient group through multiple prediction operations and update operations; After single-layer lifting wavelet decomposition, the original sequence is decomposed into a detail coefficient group containing the detail part and an approximate coefficient group containing the remaining part.

6. The cascade anti-interference circuit suitable for electrocardiogram monitoring equipment according to claim 1, characterized in that: The threshold calculation module includes a first absolute value extraction unit, a bitonic network sorting median extraction unit and a threshold multiplication operation unit; The first absolute value extraction unit performs absolute value conversion on the input 16-bit signed number format signal, performs bitonic network sorting on the obtained absolute value sequence, extracts the median value according to the sorting order for threshold calculation, uses the extracted median value to perform threshold multiplication calculation, and obtains the upper and lower thresholds for threshold processing as a result of the threshold multiplication calculation, which are further output to the threshold processing module; The bitwise network sorting median extraction unit includes a discriminator, a bitwise invertor, a two-input adder, a two-to-one selector, and a register. It determines the positive or negative of the data by judging the high bit of the input signal, directly outputs the positive number with a sign bit of 0, and performs a bitwise inversion and then adds 1 to the negative number with a sign bit of 1. Finally, it selects and outputs the absolute value sequence of the input sequence. The threshold multiplication operation unit includes two multipliers, two registers, four shifters, and two two-input summers; the two paths respectively calculate the upper and lower thresholds of the second-layer detail coefficient group and the third-layer detail coefficient group.

7. The cascade anti-interference circuit suitable for electrocardiogram monitoring equipment according to claim 4, characterized in that: The threshold processing unit includes a second absolute value extraction unit, a threshold determination unit, a nonlinear operation unit and an output selection unit; The second absolute value extraction unit is used to extract the absolute value of the input signal; The threshold determination unit is configured to generate a selection signal sel based on the relative size of the absolute value and the upper and lower thresholds, and generate three different selection signals for the three situations where the absolute value is less than the lower threshold, the absolute value is greater than the upper threshold, and the absolute value is between the upper and lower thresholds; when the absolute value is greater than the upper threshold, the input signal is directly output; when the absolute value is less than the lower threshold, the output is set to zero; and when the absolute value is between the upper and lower thresholds, a nonlinear operation is used for output; The nonlinear operation unit includes a division operator unit, a square operator unit and a sign bit splicing operator unit.

8. The cascade anti-interference circuit suitable for electrocardiogram monitoring equipment according to claim 5, characterized in that: The lifting wavelet reconstruction module includes a cascaded first lifting wavelet reconstruction unit, a second lifting wavelet reconstruction unit, and a third lifting wavelet reconstruction unit; The input signal of the first lifting wavelet reconstruction unit is the third-layer detail coefficient group and the third-layer approximate coefficient group after threshold processing. The reconstructed new second-layer approximate coefficient group is connected to the second-layer lifting wavelet reconstruction unit as an input signal, and the new first-layer approximate coefficient group reconstructed from the second-layer detail coefficient group after threshold processing is connected to the third-layer lifting wavelet reconstruction unit as an input signal, and reconstructs the denoised ECG reconstruction signal with the first-layer detail coefficient group after forced denoising.

9. The cascade anti-interference circuit suitable for electrocardiogram monitoring equipment according to claim 8, characterized in that: The first lifting wavelet reconstruction unit, the second lifting wavelet reconstruction unit, and the third lifting wavelet reconstruction unit all include a clock frequency division subunit, an anti-prediction and anti-update subunit, and a parity sequence merging subunit; The clock division subunit is used for generating and distributing the global clock. The anti-prediction and anti-update subunit is used for performing multiple anti-prediction and anti-update operations on the input approximate coefficient group and detail coefficient group to make them approach the parity sequence of the reconstructed sequence. The parity sequence merging subunit merges them to obtain the ECG reconstructed signal.

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