Apparatus and method for in-situ read refresh of non-volatile memory devices

Abstract

A memory device includes a memory block with an array of memory cells arranged in a plurality of word lines. The memory cells are programmed to one bit per memory cell, where each memory cell is in an erased data state or a programmed data state. The memory device also includes circuitry configured to determine that the memory cell has experienced significant read disturbs. Without erasing the memory cell, the circuit is further configured to directly program the memory cell in the programmed data state to a higher threshold voltage, the memory cell is programmed to increase a threshold voltage margin between the memory cell in the erased data state and the memory cell in the programmed data state.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to and the benefit of U.S. Provisional Application No. 63 / 552,778, filed on February 13, 2024, entitled “APPARATUS AND METHODS FOR IN-PLACE READ REFRESH FOR NONVOLATILE MEMORY DEVICES,” the entire contents of which are incorporated herein by reference. Background Art 1. Technical Field

[0003] The present disclosure relates generally to nonvolatile memory, and more particularly to improved memory devices optimized to operate at very high read performance and with very low power consumption.

[0004] 2. Related Technologies

[0005] Semiconductor memory is widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memory can be either non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery).

[0006] A non-volatile memory device includes one or more memory chips with multiple memory cell arrays. The memory array may have associated decoders and circuitry for performing read, write, and erase operations. The memory cells within the array may be arranged in rows and columns. Each row is addressable via a word line, and each column is addressable via a bit line. Data can be loaded into the columns of the array using a series of data buses. Each column can hold a predefined data unit, such as a word containing two bytes of information.

[0007] In some applications, semiconductor memory is used to store very large amounts of data that are repeatedly accessed (e.g., read) very quickly. For example, in some machine learning applications, large language models comprising terabytes (or more) of data must be stored in memory and retrieved at very high data rates. Therefore, such applications require very high bandwidth and low power.

[0008] Currently, high-bandwidth volatile memory devices (e.g., DRAM memory devices, also known as "high-bandwidth memory" or "HBM") are used for such applications. While non-volatile memory (e.g., NAND) is significantly less expensive than DRAM, the bandwidth and power consumption of conventional NAND memory devices are too low to provide a viable alternative to HBM devices. Therefore, there is a need for high-bandwidth, low-power non-volatile memory. Summary of the Invention

[0009] One aspect of the present disclosure relates to a method for operating a memory device. The method includes the steps of preparing a memory device comprising a memory block having an array of memory cells arranged in a plurality of word lines. The memory cells are programmed with one bit per memory cell, wherein each memory cell is in an erased data state or a programmed data state. The method then proceeds with the step of determining that the memory cells have experienced significant read disturb. Without erasing the memory cells, the method then proceeds with the step of directly programming the memory cells in the programmed data state to a higher threshold voltage to increase the threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.

[0010] According to another aspect of the present disclosure, the method further includes the steps of: counting the number of read cycles to establish a read cycle count; and comparing the read cycle count to a predetermined threshold. The step of determining that the memory cell has experienced significant read disturb occurs in response to the read cycle count exceeding the predetermined threshold.

[0011] According to yet another aspect of the disclosure, determining that a memory cell has experienced significant read disturb occurs in response to determining that a count of memory cells within a voltage range below a voltage range associated with a programmed data state is greater than a predetermined threshold.

[0012] According to still another aspect of the present disclosure, the method further includes setting a reference voltage SLCR for use during a read operation from a first level to a higher second level after programming the memory cells in the programmed data state to a higher threshold voltage.

[0013] According to another aspect of the present disclosure, the step of programming memory cells in a programmed data state to a higher threshold voltage includes applying a programming voltage to a selected word line; setting a plurality of bit lines electrically coupled to the memory cells of the selected word line and in the programmed data state at a very low voltage; and setting a plurality of bit lines electrically coupled to the memory cells of the selected word line and in the erased data state at an inhibit voltage.

[0014] According to yet further aspects of the present disclosure, the step of directly programming memory cells in a programmed data state to a higher threshold voltage includes a single programming pulse and no verify operation, or includes multiple programming pulses and verify operations.

[0015] Another aspect of the present disclosure relates to a memory device. A memory device includes a memory block having an array of memory cells arranged in a plurality of word lines. The memory cells are programmed with one bit per memory cell, wherein each memory cell is in an erased data state or a programmed data state. The memory device also includes circuitry configured to determine whether a memory cell has experienced significant read disturb. Without erasing the memory cell, the circuitry is further configured to directly program the memory cell in the programmed data state to a higher threshold voltage to increase the threshold voltage margin between the memory cell in the erased data state and the memory cell in the programmed data state.

[0016] According to another aspect of the present disclosure, the circuit is configured to count the number of read cycles to establish a read cycle count and compare the read cycle count to a predetermined threshold. The circuit determines that the memory cell has experienced significant read disturb in response to the read cycle count exceeding the predetermined threshold.

[0017] According to yet another aspect of the present disclosure, the circuit is further configured to set a reference voltage SLCR for use during a read operation from a first level to a second, higher level after programming memory cells in a programmed data state to a higher threshold voltage.

[0018] According to yet another aspect of the present disclosure, when programming memory cells in a programmed data state to a higher threshold voltage, a circuit applies a programming voltage to a selected word line; sets a plurality of bit lines electrically coupled to the memory cells of the selected word line and in the programmed data state at a very low voltage; and sets a plurality of bit lines electrically coupled to the memory cells of the selected word line and in the erased data state at an inhibit voltage.

[0019] According to further aspects of the present disclosure, the circuit is configured to count a number of memory cells having a threshold voltage within a voltage range lower than a voltage range associated with a programmed data state; compare the count of memory cells having a threshold voltage within a voltage range lower than the voltage range associated with the programmed data state to a predetermined threshold; and determine that a memory cell has experienced significant read disturb responsive to the count of memory cells being greater than the predetermined threshold.

[0020] According to yet another aspect of the present disclosure, when programming memory cells in a programmed data state directly to a higher threshold voltage, the circuit applies a single programming pulse to a selected word line without performing a subsequent verification operation, or applies multiple programming pulses to the selected word line and performs a subsequent verification operation.

[0021] Yet another aspect of the present disclosure relates to a computing system comprising a processor unit and a plurality of high bandwidth flash memory (HBF) packages in electrical communication with the processor unit. At least one of the HBF packages comprises a memory block having an array of memory cells arranged in a plurality of word lines. The memory cells are programmed to one bit per memory cell, wherein each memory cell is in an erased data state or a programmed data state. The at least one HBF package in the HBF package further comprises a circuit configured to determine that a memory cell has experienced significant read interference. Without erasing the memory cell, the circuit is further configured to directly program the memory cell in the programmed data state to a higher threshold voltage to increase a threshold voltage margin between the memory cell in the erased data state and the memory cell in the programmed data state.

[0022] According to another aspect of the present disclosure, the circuit is configured to count the number of read cycles to establish a read cycle count and compare the read cycle count to a predetermined threshold. The circuit determines that the memory cell has experienced significant read disturb in response to the read cycle count exceeding the predetermined threshold.

[0023] According to yet another aspect of the present disclosure, the circuit is further configured to set a reference voltage SLCR for use during a read operation from a first level to a second, higher level after programming memory cells in a programmed data state to a higher threshold voltage.

[0024] According to yet another aspect of the present disclosure, when programming memory cells in a programmed data state to a higher threshold voltage, a circuit applies a programming voltage to a selected word line; sets a plurality of bit lines electrically coupled to the memory cells of the selected word line and in the programmed data state at a very low voltage; and sets a plurality of bit lines electrically coupled to the memory cells of the selected word line and in the erased data state at an inhibit voltage.

[0025] According to another aspect of the present disclosure, the circuit is configured to count the number of memory cells having a threshold voltage within a voltage range lower than a voltage range associated with a programmed data state, compare the count of memory cells having a threshold voltage within a voltage range lower than the voltage range associated with the programmed data state to a predetermined threshold, and determine that the memory cell has experienced significant read disturb in response to the count of memory cells being greater than the predetermined threshold.

[0026] According to yet another aspect of the present disclosure, the plurality of HBF packages are capable of electrically communicating with the processor unit at a rate greater than 3 TB / s.

[0027] According to still further aspects of the present disclosure, the HBF package receives a supply voltage of no greater than 1.2V.

[0028] According to another aspect of the present disclosure, when programming memory cells in a programmed data state directly to a higher threshold voltage, the circuit applies a single programming pulse to a selected word line without performing a subsequent verification operation, or applies multiple programming pulses to the selected word line and performs a subsequent verification operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and other features and advantages of the subject disclosure will become more readily understood when considered in conjunction with the following description of the presently preferred embodiments, the appended claims, and the accompanying drawings, in which:

[0030] Figure 1 is a block diagram illustrating one embodiment of a storage system;

[0031] Figure 2A is a block diagram of one embodiment of a memory die;

[0032] Figure 2B is a block diagram of one embodiment of an integrated memory component;

[0033] Figure 3A and Figure 3B shows different embodiments of integrated memory components;

[0034] Figure 4A is a perspective view of a portion of one embodiment of a monolithic three-dimensional memory structure;

[0035] Figure 4B is a block diagram of one embodiment of a memory structure having four planes;

[0036] Figure 4C shows a top view of a portion of one embodiment of a block of memory cells;

[0037] Figure 4Da cross-sectional view showing a portion of one embodiment of a block of memory cells;

[0038] Figure 4E a cross-sectional view showing a portion of one embodiment of a block of memory cells;

[0039] Figure 4F is a cross-sectional view of one embodiment of a vertical column of memory cells;

[0040] Figure 4G A schematic diagram of multiple NAND strings in multiple regions of the same block;

[0041] Figure 5A is a block diagram of one embodiment of a memory structure having four planes;

[0042] Figure 5B is a block diagram of one embodiment of a memory structure having thirty-two planes;

[0043] Figure 5C is a block diagram of another embodiment of a memory structure having thirty-two planes;

[0044] Figure 5D is a block diagram of another embodiment of a memory structure having thirty-two planes;

[0045] Figures 6A to 6C An example NAND string is shown during inhibit, programming, and sensing, respectively;

[0046] Figure 7A shows an example threshold voltage distribution for a page of NAND memory cells;

[0047] Figure 7B shows another example threshold voltage distribution for a page of NAND memory cells;

[0048] Figure 8A shows the threshold voltage distribution of a page of memory cells initially after programming;

[0049] Figure 8B shows the threshold voltage distribution of a page of memory cells after experiencing significant read disturb;

[0050] Figure 9A shows the threshold voltage distribution of a page of memory cells initially after programming;

[0051] Figure 9B Shown with Figure 9A Threshold voltage distribution of the same page of memory cells but after significant read disturb;

[0052] Figure 9C Shown with Figure 9A and Figure 9B Threshold voltage distribution of the same page of memory cells but after a data refresh operation;

[0053] Figure 9D Shown with Figures 9A to 9C a threshold voltage distribution for the same page of memory cells but after a second data refresh operation;

[0054] Figure 10 To illustrate a schematic diagram of an example computing system including a single processing unit and multiple high-bandwidth flash memory (HBF) units; and

[0055] Figure 11 is a flow chart illustrating steps for refreshing data in a memory block according to an example embodiment. DETAILED DESCRIPTION

[0056] Techniques for increasing bandwidth and improving power efficiency of NAND memory to provide a viable alternative to HBM devices are described. More specifically, as further detailed below, a high-bandwidth flash memory (HBF) package is provided that is specifically configured to operate with both very high bandwidth (specifically, very high read performance) and very low power consumption. Thus, the HBF package is optimized for use in large language model operations. Additionally, as further detailed below, the HBF package is configured to automatically refresh data based on the data stored therein to prevent read disturbances without requiring relocation or even erasure of the data.

[0057] Figure 1 A block diagram of one embodiment of a storage system 100 for implementing the techniques described herein. In one embodiment, storage system 100 is a solid-state drive ("SSD"). Storage system 100 may also be a memory card, a USB drive, or any other type of storage system. In other words, the techniques of the present invention are not limited to any one type of memory system.

[0058] Storage system 100 is connected to a host 102, which can be a computer; a server; an electronic device (e.g., a smartphone, tablet, or other mobile device); an appliance; or another device that uses memory and has data processing capabilities. In some embodiments, host 102 is separate from storage system 100 but connected to it. In other embodiments, storage system 100 is embedded within host 102.

[0059] Figure 1The components of the memory system 100 shown in FIG. 1 are electronic circuits. The memory system 100 includes a memory controller 104 connected to a non-volatile memory 106 and a local high-speed volatile memory 108 (e.g., DRAM). The memory controller 104 uses the local high-speed volatile memory 108 to perform certain functions. For example, the local high-speed volatile memory 108 stores a logical address to physical address translation table ("L2P table").

[0060] Memory controller 104 includes a host interface 110 that is connected to and communicates with host 102. In one embodiment, host interface 110 implements NVM Express (NVMe) via PCI Express (PCIe). Other interfaces such as SCSI, SATA, etc. may also be used. Host interface 110 is also connected to a network on chip (NOC) 112.

[0061] A NOC is a communication subsystem on an integrated circuit (IC). It can span synchronous and asynchronous clock domains or utilize unclocked asynchronous logic. NOC technology applies network theory and methods to on-chip communications, offering significant improvements over conventional bus and crossbar interconnects. Compared to other designs, NOCs improve the scalability of system-on-chip (SoCs) and the power efficiency of complex SoCs.

[0062] The NOC's wires and links are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to increase, the NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, the NOC 112 can be replaced by a bus.

[0063] Connected to and in communication with the NOC 112 are a processor 114, an ECC engine 116, a memory interface 118, and a DRAM controller 120. The DRAM controller 120 is used to operate and communicate with local high-speed volatile memory 108 (e.g., DRAM). In other embodiments, the local high-speed volatile memory 108 may be SRAM or another type of volatile memory.

[0064] In operation, processor 114 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 114 is programmed by firmware. In other embodiments, processor 114 is a custom and dedicated hardware circuit without any software. Processor 114 also implements a conversion module, either as a software / firmware process or as a dedicated hardware circuit.

[0065] In many systems, non-volatile memory is addressed internally to the memory system using physical addresses associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the memory system is free to store data as desired across locations on one or more memory dies. To implement such a system, the memory controller 104 (e.g., a translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies.

[0066] One example implementation is to maintain a table (i.e., the L2P table referenced above) that identifies the current translation between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and a corresponding physical address. Although the logical-to-physical address table (or L2P table) includes the word "table," they need not be tables in the literal sense. Rather, the logical-to-physical address table (or L2P table) may be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 108 cannot hold all of the L2P tables. In such cases, the entire set of L2P tables is stored in the non-volatile memory 106, and a subset of the L2P tables is cached (the L2P cache) in the local high-speed volatile memory 108.

[0067] ECC engine 116 performs error correction services. For example, ECC engine 116 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, ECC engine 116 is an electronic circuit programmed by software. For example, ECC engine 116 can be a programmable processor. In other embodiments, ECC engine 116 is a custom, dedicated hardware circuit without any software. In another embodiment, the functions of ECC engine 116 are implemented by processor 114.

[0068] The memory interface 118 communicates with the non-volatile memory 106. In one embodiment, the memory interface provides a switched-mode interface. However, other interfaces may also be used. In some example implementations, the memory interface 118 (or another portion of the controller 104) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory dies.

[0069] In one embodiment, non-volatile memory 106 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of a memory die 200 including non-volatile memory 106. Each of the one or more memory dies of non-volatile memory 106 may be implemented as Figure 2A The memory tube core 200 of FIG. Figure 2AThe components shown in FIG are electronic circuits.

[0070] Memory die 200 includes a memory array 202, which may include nonvolatile memory cells, as described in further detail below. Memory array 202 includes multiple word line layers organized into rows and multiple bit line layers organized into columns. However, other orientations may also be implemented.

[0071] Memory die 200 also includes row control circuitry 204, whose outputs 206 are connected to corresponding word lines of memory array 202. In operation, row control circuitry 204 receives a set of M row address signals and one or more various control signals from system control logic circuitry 208, and may include circuitry such as a row decoder 210, array terminal drivers 212, and block select circuitry 214 for both read and write (program) operations.

[0072] Row control circuitry 204 may also include read and write circuitry. Memory die 200 also includes column control circuitry 216, which includes sense amplifiers 218 having inputs / outputs 220 connected to corresponding bit lines of memory array 202. Although only a single block is shown for memory array 202, memory die 200 may include multiple arrays that can be accessed individually.

[0073] Column control circuitry 216 receives a set of N column address signals and one or more various control signals from system control logic 208. Column control circuitry 216 may also include such circuitry as a column decoder 222, array terminal receiver or driver circuitry 224, block select circuitry 226, read and write circuitry, and I / O multiplexers.

[0074] System control logic 208 receives data from memory controller 104 ( Figure 1 ) receives data and commands and provides output data and status to the host 102. In some embodiments, the system control logic 208 (which includes one or more electronic circuits) includes a state machine 228 that provides die-level control of memory operations. In one embodiment, the state machine 228 is programmable by software. In other embodiments, the state machine 228 does not use software and is implemented entirely in hardware (e.g., electronic circuits). In another embodiment, the state machine 228 is replaced by a microcontroller or microprocessor that is on or off the memory chip.

[0075] The system control logic 208 may also include a power control module 230 that controls the power and voltage supplied to the rows and columns of the memory structure 202 during memory operations and may include charge pump and regulator circuits for generating regulated voltages. The system control logic 208 also includes a storage device 232 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating the memory array 202.

[0076] In operation, commands and data are transmitted between the memory controller 104 and the memory die 200 via the memory controller interface 234 (also referred to as the "communication interface"). The memory controller interface 234 is an electrical interface for communicating with the memory controller 104. Examples of the memory controller interface 234 include a switch mode interface and an open NAND flash interface (ONFI). In other embodiments, other I / O interfaces may also be used.

[0077] In one embodiment, system control logic 208 also includes column replacement control circuitry 236, as described in more detail below.

[0078] In some embodiments, all elements of memory die 200, including system control logic 208, may be formed as part of a single die. In other embodiments, some or all of system control logic 208 may be formed on different dies.

[0079] In one embodiment, memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory levels are formed over a single substrate, such as a wafer. Memory structure 202 may include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active regions disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include a charge trapping layer and are arranged in multiple vertical NAND strings.

[0080] In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0081] The exact type of memory array architecture or memory cells included in the memory structure 202 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required to implement the new claimed embodiments presented herein. For example, suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like. One example of a ReRAM cross-point memory includes reversible resistance switching elements arranged in a cross-point array accessed by X lines and Y lines (e.g., word lines and bit lines).

[0082] In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallization cell. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element can have a wide range of programming thresholds over the entire temperature range.

[0083] Another example is magnetoresistive random access memory (MRAM) that stores data via magnetic storage elements. These elements are formed by two ferromagnetic layers, each of which can maintain magnetization, and the ferromagnetic layers are separated by a thin insulating layer. One of the two ferromagnetic layers is a permanent magnet set to a specific polarity, and the magnetization of the other ferromagnetic layer can be changed to match the magnetization of the external field to store the memory. A memory array can be constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current passes through the write lines, an induced magnetic field is generated. Memory embodiments based on MRAM will be discussed in more detail below.

[0084] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply changing the coordination state of the germanium atoms with a laser pulse (or a light pulse from another source). Therefore, the programming dose is a laser pulse. The memory cell can be inhibited by preventing the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. Note that the use of "pulse" in this document does not require a square pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage light or another wave. These memory elements within each selectable memory cell or bit can include additional series elements as selectors, such as a bidirectional threshold switch or a metal insulator substrate.

[0085] The technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by persons of ordinary skill in the art.

[0086] Figure 2A The components of the memory structure 202 can be grouped into two parts: (1) the memory structure 202 and (2) the peripheral circuitry, which includes Figure 2A 202 for specific uses. However, this reduces the area of the memory die available for peripheral circuitry. This can place quite severe limitations on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuitry within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic component 208, the reduction in available area can limit the available functionality that can be implemented on the chip. Therefore, in the design of the memory die of the memory system 100, a substantial trade-off may need to be made between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuitry.

[0087] Another area where memory structure 202 and peripheral circuitry often conflict is in the processing involved in forming these areas, as these areas often involve different process technologies and the trade-offs when implementing different technologies on a single die. For example, when memory structure 202 is NAND flash memory, this is an NMOS structure, while the peripheral circuitry is typically CMOS-based.

[0088] Elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic 208 typically employ PMOS devices. The processing operations used to manufacture CMOS dies will differ in many respects from processing operations optimized for NMOS flash, NAND memory, or other memory cell technologies.

[0089] In order to improve these defects, the following embodiments can Figure 2A The elements of the memory structure 202 are separated into a separately formed die, which is then bonded to another die. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die), and some or all of the peripheral circuit elements (including one or more control circuits) can be formed on a separate die (referred to as the control die). The memory die can be formed only of memory elements, such as an array of memory cells of a flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory type. Some or all of the circuits in the peripheral circuits (even including elements such as decoders and sense amplifiers) can then be moved to a separate control die. This allows each die in the memory die to be optimized individually according to its technology.

[0090] For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS components, which have now been moved to a control die that can be optimized for CMOS processing. This provides more space for peripheral components, which can now incorporate additional capabilities that might not be easily incorporated if they were confined to the edge of the same die that houses the memory cell array.

[0091] The two dies can then be bonded together in a bonded multi-die memory circuit, where the array on one die is connected to the peripheral components on the other die. For example, while the following description focuses on a bonded memory circuit with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0092] Figure 2B Show Figure 2A An alternative arrangement to the arrangement of may be implemented using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B 1. A functional block diagram of one embodiment of an integrated memory component 240 is shown. One or more integrated memory components 240 can be used to implement the non-volatile memory 106 of the memory system 100.

[0093] Integrated memory assembly 240 includes two types of semiconductor dies (or, more simply, "dies"). Memory die 242 includes memory structure 202 with non-volatile memory cells. Control die 244 includes control circuits 208, 216, and 204 (as described above). In some embodiments, control die 244 is configured to connect to memory structure 202 in memory die 242. In some embodiments, memory die 242 and control die 244 are bonded together.

[0094] Figure 2B An example of peripheral circuitry is shown, including control circuitry formed in a peripheral circuit or control die 244 coupled to memory structure 202 formed in a memory die 242. Common components are shown in FIG. Figure 2A System control logic 208, row control circuitry 204, and column control circuitry 216 are located in control die 244. In some embodiments, all or a portion of column control circuitry 216 and all or a portion of row control circuitry 204 are located on memory die 242. In some embodiments, some circuitry in system control logic 208 is located on memory die 242.

[0095] The system control logic 208, the row control circuitry 204, and the column control circuitry 216 may be formed using conventional processes (e.g., CMOS processes) such that adding elements and functionality more commonly found on the memory controller 104, such as an ECC controller, may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 104 may also be used to manufacture the system control logic 208, the row control circuitry 204, and the column control circuitry 216).

[0096] Thus, while removing such circuitry from a die, such as memory die 242, may reduce the number of steps required to manufacture such a die, adding such circuitry to a die, such as control die 244, may not require many additional process steps. Because some or all of control circuitry 204, 208, 216 is implemented using CMOS technology, control die 244 may also be referred to as a CMOS die.

[0097] Figure 2B Column control circuitry 216 including sense amplifiers 218 is shown on control die 244, coupled to memory structure 202 on memory die 242 via electrical paths 220. Electrical paths 220 can provide electrical connections between column decoders 222, driver circuits 224, block selectors 226, and the bit lines of memory structure 202. In one embodiment, column control circuitry 216 also includes column replacement control circuitry 236, as described in more detail below.

[0098] The electrical paths may extend from column control circuitry 216 in control die 244 through pads on control die 244 that are bonded to corresponding pads on memory die 242 that are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding one of electrical paths 220 that includes a pair of bond pads connected to column control circuitry 216.

[0099] Similarly, row control circuitry 204 (including row decoder 210, array driver 212, and block selector 214) is coupled to memory structure 202 via electrical paths 206. Each of electrical paths 206 may correspond to a word line containing data, a dummy word line, or a select gate line. Additional electrical paths may also be provided between control die 244 and memory die 242.

[0100] For purposes of this document, the phrases "a control circuit," "control circuitry," or "one or more control circuits" may include any one or any combination of memory controller 104, state machine 228, all or a portion of system control logic 208, all or a portion of row control circuitry 204, all or a portion of column control circuitry 216, a microcontroller, a microprocessor, and / or other similarly functional circuitry.

[0101] The control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, one or more controllers programmed by firmware to perform the functions described herein are an example of a control circuit. The control circuitry may include a processor, FGA, ASIC, integrated circuit, or other types of circuitry.

[0102] In some embodiments, there is more than one control die 244 and more than one memory die 242 in the integrated memory component 240. In some embodiments, the integrated memory component 240 includes a stack of multiple control dies 244 and multiple memory dies 242.

[0103] Figure 3A A side view of one embodiment of an integrated memory assembly 300 (e.g., a stack including a control die 304 and a memory structure die 306) stacked on a substrate 302 is shown. In this embodiment, the integrated memory assembly 300 has three control dies 304 and three memory dies 306. In some embodiments, there are more than three memory dies 306 and more than three control dies 304.

[0104] Each control die 304 is attached (e.g., bonded) to at least one memory die 306. Some of the bonding pads 308 / 310 are shown, although more bonding pads may be present. The space between the two die 306, 304 bonded together is filled with a solid layer 312, which may be formed of an epoxy or other resin or polymer. The solid layer 312 protects the electrical connection between the die 306, 304 and further secures the die together. Various materials may be used as the solid layer 312, but in some embodiments, the material may be a Hysol epoxy resin from Henkel Corporation (which has offices in California, USA).

[0105] The integrated memory components 300 may be stacked, for example, in a stepped offset fashion, such that the bonding pads at each level are uncovered and accessible from above. Wire bonds 314 connected to the bonding pads connect the control die 304 to the substrate 302. Multiple such wire bonds may be formed across the entire width of each control die 304 (i.e., formed to the width of the substrate 302). Figure 3A page).

[0106] Memory die through silicon vias (TSVs) 316 may be used to route signals through each memory die 306. Control die TSVs 318 may be used to route signals through each control die 304. TSVs 316, 318 may be formed before, during, or after the formation of the integrated circuits in the semiconductor dies 306, 304. The TSVs may be formed by etching holes through the wafer. These holes may then be lined with a barrier to prevent metal diffusion. The barrier layer, in turn, may be lined with a seed layer, and the seed layer may be plated with an electrical conductor, such as copper, although other suitable materials such as aluminum, tin, nickel, gold may be used. Solder balls 320 may optionally be attached to contact pads 322 on the lower surface of the substrate 302. Solder balls 320 may be used to electrically and mechanically couple the integrated memory assembly 300 to a host device such as a printed circuit board. Solder balls 320 may be omitted in the event that the integrated memory assembly 300 is to be used as an LGA package. Solder balls 320 may form part of the interface between the integrated memory assembly 300 and the memory controller 104 ( Figure 1 ).

[0107] Figure 3B A side view of another embodiment of an integrated memory component 300 stacked on a substrate 302 is shown. Figure 3BThe integrated memory component 300 has three control dies 304 and three memory dies 306. In some embodiments, there are far more than three memory dies 306 and far more than three control dies 304. In this example, each control die 304 is bonded to at least one memory die 306. Optionally, a control die 304 can be bonded to two or more memory dies 306.

[0108] Some of the bonding pads 308, 310 are shown, but there may be many more bonding pads than shown. The space between the two dies 306, 304 bonded together is filled with a solid layer 312, which may be formed of epoxy or other resins or polymers. Figure 3A Compared to the example in Figure 3B The integrated memory component 300 in FIG. 3 has no staircase offset. Memory die TSVs 316 may be used to route signals through each memory die 306. Control die TSVs 318 may be used to route signals through each control die 304.

[0109] As briefly discussed above, the control die 304 and the memory die 306 can be bonded together. Bond pads on each control die 304 and each memory die 306 can be used to bond the two dies together. In some embodiments, the bond pads are bonded directly to each other without solder or other additional materials in a so-called Cu-Cu bonding process.

[0110] In the Cu-Cu bonding process, the bond pads are controlled to be highly flat and formed in a highly controlled environment that is substantially free of ambient particles that might otherwise settle on the bond pads and prevent a tight bond. Under these properly controlled conditions, the bond pads align and press against each other to form a mutual bond based on surface tension.

[0111] As briefly discussed above, the control die 304 and the memory die 306 can be bonded together. The bonding pads on each control die 304 and each memory die 306 can be used to bond the two dies together. In some embodiments, in a so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additional materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment that is substantially free of environmental particles that might otherwise deposit on the bonding pads and prevent a tight bond. Under these properly controlled conditions, the bonding pads align and press against each other to form a mutual bond based on surface tension. This bond can be formed at room temperature, although heat can also be applied. In an embodiment using Cu-Cu bonding, the bonding pads can be approximately 5 square microns and spaced apart at a spacing of 5 μm to 5 μm. Although the process is referred to herein as Cu-Cu bonding, the term can also apply to cases where the bonding pads are formed from materials other than copper. When the bonding pad area is small, it may be difficult to bond the semiconductor dies together. By providing a film layer on the surface of the semiconductor die including the bonding pads, the size of the bonding pads and the spacing between the bonding pads can be further reduced. The film layer is arranged around the bonding pads. When the dies are put together, the bonding pads can be bonded to each other, and the film layers on the individual dies can be bonded to each other. This bonding technology can be referred to as hybrid bonding. In an embodiment using hybrid bonding, the bonding pads can be about 5 square microns and are spaced apart from each other at a spacing of 1 μm to 5 μm. Bonding technology can be used to provide bonding pads with smaller (or larger) sizes and spacings.

[0112] Some embodiments may include a film on the surface of the control die 304 and the memory die 306. If such a film is not initially provided, the space between the die can be underfilled with epoxy or other resins or polymers. The underfill material can be applied as a liquid and then hardened into a solid layer. This underfill step protects the electrical connection between the control die 304 and the memory die 306 and further secures the die together. Various materials can be used as underfill materials, such as Hysol epoxy resin from Henkel Corporation (which has offices in California, USA).

[0113] Figure 4A is a perspective view of a portion of one example embodiment of a monolithic three-dimensional memory array / structure included in a memory structure 202 that includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4AA portion of a memory block 400 is shown. The illustrated structure includes a set of bit lines BL located above a stack 402 of alternating dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D, and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements.

[0114] As will be explained below, in one embodiment, the alternating dielectric and conductive layers are divided into, for example, four or five (or a different number of) regions by isolation regions IR. FIG4 shows an isolation region IR separating two regions. A common source line layer SL is located below the alternating dielectric and word line layers. A memory hole is formed in the stack of alternating dielectric and conductive layers. For example, the memory hole is labeled MH. Note that in Figure 4A In FIG, the dielectric layer is shown in perspective so that the reader can see the memory holes positioned in the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping material to form vertical columns of memory cells.

[0115] Non-volatile memory cells are arranged in the memory wells, and each memory cell can store one or more data bits, for example, up to five data bits per memory cell.More details of a three-dimensional monolithic memory array including the memory structure 202 are provided below.

[0116] Figure 4B To illustrate an example organization of memory structure 202, the memory structure is divided into four planes 404, 406, 408, and 410. Each plane is then divided into M blocks. In one example, each plane has approximately 2,000 blocks ("Block 0" through "Block M-1," where M is 2,000). However, a different number of blocks and planes may be used.

[0117] In one embodiment, a block of memory cells is the unit of erase. That is, all memory cells of a block are erased together. In other embodiments, a block can be divided into sub-blocks, where each block includes multiple word lines, and the sub-blocks can be the unit of erase. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuits.

[0118] In some embodiments, a block represents a group of connected memory cells because the memory cells of the block share a common set of word lines. For example, the word lines of a block are all connected to all vertical NAND strings of the corresponding block. Although Figure 4B Four planes are shown, with each plane containing multiple blocks, but more or less than four planes may be implemented in memory structure 202. In some implementations, the memory structure includes eight planes.

[0119] Each block is typically divided into one or more pages, where each page is a unit of programming / writing and a unit of reading. Other programming units may also be used. In one embodiment, the data of one or more pages is typically stored in a row of memory cells. For example, the data of one or more pages may be stored in memory cells connected to a common word line. In one embodiment, a page includes the data stored in all memory cells connected to the common word line within the block.

[0120] Figures 4C to 4G An example three-dimensional ("3D") NAND structure is shown, corresponding to Figure 4A structure and can be used to implement Figure 2A and Figure 2B Memory structure 202. Figure 4C is a block diagram showing a top view of a portion 412 of block 2 of surface 404. Figure 4C It can be seen that Figure 4C The blocks shown in FIG extend in the direction 414. In one embodiment, the memory array has many such layers, wherein Figure 4C Only the top layer is shown.

[0121] Figure 4C A plurality of circles representing memory wells (also referred to as vertical columns) are shown. Each of the memory wells / vertical columns includes a plurality of select transistors (also referred to as select gates or selection gates) and a plurality of memory cells. In one embodiment, each memory well / vertical column implements a NAND string. For example, Figure 4C A subset of the memory holes / vertical columns / NAND strings 416, 418, 420, 422, 424, 426, 428, 430, and 432 are labeled.

[0122] Figure 4C Also shown is a set of bit lines 434 , including bit lines 436 , 438 , 440 , 442 , . . . , 444 . Figure 4C Twenty-four bit lines are shown because only a portion of the block is shown. It is contemplated that more than twenty-four bit lines are connected to the memory wells / vertical columns of the block. Each circle representing a memory well / vertical column has an "x" to indicate that it is connected to one of the bit lines. For example, bit line 436 is connected to memory wells / vertical columns 418, 420, 422, 426, and 432. Bit lines 436, 438, 440, and 442 are also in electrical communication with all other blocks in a given plane.

[0123] Figure 4CThe block shown in FIG includes a set of isolation regions 446, 448, 450 and 452 formed of SiO2. However, other dielectric materials may also be used. Isolation regions 446, 448, 450 and 452 are used to divide the top layer of the block into five regions. For example, Figure 4C The top layer shown in FIG is divided into regions 454 , 456 , 458 , 460 , and 462 .

[0124] In one embodiment, the isolation regions only divide the layers used to implement the select gates so that NAND strings in different regions can be independently selected. In one exemplary implementation, a bit line is connected to one memory well / vertical column / NAND string in each of regions 454, 456, 458, 460, and 462. In this implementation, each block has twenty-four rows of active columns, and each bit line is connected to five rows in each block.

[0125] In one embodiment, all five memory wells / vertical columns / NAND strings connected to a common bit line are connected to the same word line group; therefore, the system uses the drain-side select lines to select one (or another subset) of the five for the memory operation (program, verify, read, and / or erase) to be performed.

[0126] Figure 4C Also shown is line interconnect LI, which is a metal connection from above the memory array to the source line SL. Line interconnect LI is located adjacent to regions 454 and 462.

[0127] although Figure 4C Each region 454, 456, 458, 460, and 462 in the block is shown to have four rows of memory holes / vertical columns, and with five regions there are twenty-four rows of memory holes / vertical columns, but these exact numbers are example implementations. Other embodiments may include more or fewer regions per block; more or fewer rows of memory holes / vertical columns per region; and more or fewer rows of vertical columns per block.

[0128] Figure 4C Also shown are staggered memory holes / vertical columns. In other embodiments, different staggering patterns can be used. In some embodiments, the memory holes / vertical columns are not staggered.

[0129] Figure 4D A portion of one embodiment of a three-dimensional memory structure 202 is shown, showing the Figure 4C The cross-sectional view cuts through the memory holes / vertical columns (NAND strings) 428 and 430 of the region 462 (see Figure 4C ).

[0130] Figure 4DThe structure includes two drain-side selection layers SGD0 and SGD1; two source-side selection layers SGS0 and SGS1; two drain-side GIDL generation transistor layers SGDT0 and SGDT1; two source-side GIDL generation transistor layers SGSB0 and SGSB1; two drain-side dummy word line layers DD0 and DD1; two source-side dummy word line layers DS0 and DS1; dummy word line layers DU and DL separated by a joint; one hundred and sixty-two word line layers WL0 to WL161 for connecting to data memory cells; and a dielectric layer DL. Other embodiments may implement more or less than the above-described embodiment. Figure 4D In one embodiment, SGD0 and SGD1 are connected together, and SGS0 and SGS1 are connected together. In other embodiments, more or fewer SGDs (more or fewer than three) are connected together, and more or fewer SGS devices (more or fewer than two) are connected together.

[0131] In one embodiment, erasing a memory cell is performed using gate induced drain leakage (GIDL), which includes generating charge carriers at a GIDL generation transistor such that the carriers are injected into a charge trapping layer of a NAND string to change (lower) the corresponding threshold voltage Vt of the memory cell. Figure 4D In some embodiments, there are two GIDL generation transistors at each end of the NAND string; however, in other embodiments, there are more or less than two GIDL generation transistors.

[0132] An embodiment that uses GIDL on both sides of a NAND string may have GIDL generation transistors on both sides. An embodiment that uses GIDL only on the drain side of a NAND string may have GIDL generation transistors only on the drain side. An embodiment that uses GIDL only on the source side of a NAND string may have GIDL generation transistors only on the source side.

[0133] The GIDL generation transistor has an abrupt PN junction to generate charge carriers for the GIDL, and during fabrication, phosphorus diffusion is performed in the polysilicon channel of the GIDL generation transistor. In some cases, the GIDL generation transistor with the shallowest phosphorus diffusion is the GIDL generation transistor that generates charge carriers during erase. However, in some embodiments, charge carriers may be generated by multiple GIDL generation transistors on a particular side of the NAND string.

[0134] Memory holes / vertical columns 428, 430 are shown protruding through the drain side select layer, source side select layer, dummy word line layer, GIDL generation transistor layer, and word line layer. In one embodiment, each memory hole / vertical column includes a vertical NAND string. Beneath the memory holes / vertical columns and the layers listed below is a substrate 464, an insulating film 466 thereon, and a source line SL. The NAND string of the memory hole / vertical column 428 has a source terminal at the bottom of the stack and a drain terminal at the top of the stack. Figure 4C Consistent, Figure 4D Vertical memory wells / columns 428 are shown connected to bit lines 442 via connectors 468 .

[0135] For ease of reference, the drain side selection layer, the source side selection layer, the dummy word line layer, the GIDL generation transistor layer, and the data word line layer are collectively referred to as a conductive layer.

[0136] In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layer, such as doped polysilicon, metals (such as tungsten), metal silicides such as nickel silicide, tungsten silicide, aluminum silicide, or combinations thereof.

[0137] In some embodiments, different conductive layers may be formed of different materials. Between the conductive layers is a dielectric layer DL. In one embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0138] The nonvolatile memory cells are formed along memory holes / vertical columns that extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WL0 to W161 are connected to the memory cells (also referred to as data memory cells). A dummy word line layer is connected to a plurality of dummy memory cells that do not store data. In some embodiments, the data memory cells and the dummy memory cells may have the same structure. Drain-side select layers SGD0 and SGD1 are used to electrically connect and disconnect the NAND string to and from the bit lines. Source-side select layers SGS0 and SGS1 are used to electrically connect and disconnect the NAND string to and from the source line SL.

[0139] Figure 4DA memory array implemented as a two-layer architecture is shown, wherein the levels are separated by a joint region. In one embodiment, etching so many word line layers intermixed with dielectric layers is expensive and / or challenging. To alleviate this burden, a first stack of word line layers (e.g., WL0 to WL80) is laid down with alternating dielectric layers, followed by the joint region, and then a second stack of word line layers (e.g., WL81 to WL161) is laid down with alternating dielectric layers. Thus, the joint region is positioned between the first stack of word line layers and the second stack of word line layers. In one embodiment, the joint region is made of the same material as the word line layers. In other embodiments, there may be no joint region or there may be multiple joint regions.

[0140] Figure 4E A portion of one embodiment of a three-dimensional memory structure 202 is shown, showing the Figure 4C The cross-sectional view cuts through the memory holes / vertical columns (NAND strings) 416 and 470 of the region 454 (see Figure 4C ). Figure 4E Shown with Figure 4D Same alternating conductive and dielectric layers.

[0141] Figure 4E Also shown is an isolation region 446 that occupies a portion of the space that would otherwise be used for memory holes / vertical columns / NAND strings, including a portion of the space that would otherwise be used for memory holes / vertical columns 470. More specifically, a portion of the vertical columns 470 (e.g., half the diameter) has been removed in layers SGDT0, SGDT1, SGD0, and SGD1 to accommodate isolation region 446. Thus, while most of vertical columns 470 are cylindrical (having a circular cross-section), portions of vertical columns 470 in layers SGDT0, SGDT1, SGD0, and SGD1 have a semicircular cross-section. In one embodiment, after forming the stack of alternating conductive and dielectric layers, the stack is etched to create space for the isolation region, and the space is subsequently filled with SiO2. This structure allows for individual control of SGDT0, SGDT1, SGD0, and SGD1 (in layers 454, 456, 458, 460, and 462). Figure 4C shown in ).

[0142] Figure 4F Show Figure 4D4. A cross-sectional view of an area 472 including a portion of the memory holes / vertical columns 428 is shown. In one embodiment, the memory holes / vertical columns are circular. However, in other embodiments, other shapes may be used. In one embodiment, the memory holes / vertical columns 428 include an inner core layer 474 made of a dielectric such as SiO2. Surrounding the inner core 474 is a polysilicon channel 476 (materials other than polysilicon may alternatively be used). The channel 476 extends between the bit line and the source line and is connected to the bit line and the source line. Surrounding the channel 476 is a tunnel dielectric 478 layer, which may have an ONO structure. Surrounding the tunnel dielectric 478 layer is a charge trapping layer 480, which may be formed of, for example, silicon nitride. It should be understood that the technology described herein is not limited to any particular material or structure.

[0143] Figure 4F The dielectric layer DL is shown, along with wordline layers WL160, WL159, WL158, WL157, and WL156. Each of these wordline layers includes a wordline region 482 surrounded by an aluminum oxide layer 484, which is surrounded by a blocking oxide layer 486. In other embodiments, the blocking oxide layer 486 may be a vertical layer parallel to and adjacent to the charge trapping layer 480. The physical interaction of the wordline layers with the vertical columns forms the memory cells of the NAND string. Thus, in one embodiment, a memory cell includes a channel 476, a tunneling dielectric 478, a charge trapping layer 480, a blocking oxide layer 486, an aluminum oxide layer 484, and a wordline region 482. For example, wordline layer WL160 and a portion of memory hole / vertical column 428 constitute memory cell MC1. Wordline layer WL159 and a portion of memory hole / vertical column 428 constitute memory cell MC2. Word line layer WL158 and a portion of memory hole / vertical column 428 constitute memory cell MC3. Word line layer WL157 and a portion of memory hole / vertical column 428 constitute memory cell MC4. Word line layer WL156 and a portion of memory hole / vertical column 428 constitute memory cell MC5. In other architectures, the memory cells may have different structures; however, the memory cells will still be storage cells.

[0144] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 480 associated with the memory cell (e.g., in the memory cell). In response to an appropriate voltage on the word line region 482, these electrons are attracted from the channel 476 into the charge trapping layer 480 through the tunneling dielectric 478. The threshold voltage (Vth) of the memory cell increases in proportion to the amount of charge stored.

[0145] In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer 480. During an erase operation, electrons return to the channel 476 or holes are injected into the charge trapping layer 480 to recombine with the electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer 480 via a physical mechanism such as GIDL, as described above.

[0146] Figure 4G for Figures 4B to 4F A schematic diagram of a portion of a three-dimensional memory array is shown in FIG. Figure 4G Physical data word lines WL0 to WL161 are shown extending across the entire block. Figure 4G The structure corresponds to Figure 4B 4. Portion 412 of block 2 includes bit line 436. In one embodiment, within a block, each bit line is connected to five NAND strings, one NAND string in each of regions 454, 456, 458, 460, 462 (in Figure 4C shown in ).

[0147] In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer 480. During an erase operation, electrons return to the channel 476 or holes are injected into the charge trapping layer 480 to recombine with the electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer 480 via a physical mechanism such as GIDL, as described above.

[0148] Figure 4G for Figures 4B to 4F A schematic diagram of a portion of a three-dimensional memory array is shown in FIG. Figure 4G Physical data word lines WL0 to WL161 are shown extending across the entire block. Figure 4G The structure corresponds to Figure 4B 4. Portion 412 of block 2 includes bit line 436. In one embodiment, within a block, each bit line is connected to five NAND strings, one NAND string in each of regions 454, 456, 458, 460, 462 (in Figure 4C shown in ).

[0149] Similarly, drain side select line / layer SGD1 is separated by isolation regions 446, 448, 450 and 452 (in Figure 4C ) to form SGD1-s0, SGD1-s1, SGD1-s2, SGD1-s3 and SGD1-s4 so as to be individually connected to and independently control regions 454, 456, 458, 460, 462 (in Figure 4Cs2, SGDT0-s3, and SGDT0-s4 for separate connections to and independent control of regions 454, 456, 458, 460, and 462. Further, drain-side GIDL generation transistor control line / layer SGDT1 is separated by isolation regions 446, 448, 450, and 452 to form SGDT1-s0, SGDT1-s1, SGDT1-s2, SGDT1-s3, and SGDT1-s4 for separate connections to and independent control of regions 454, 456, 458, 460, and 462.

[0150] Figure 4G Only the NAND strings connected to bit line 436 are shown. However, a complete schematic diagram of the block would show each bit line and the five vertical NAND strings (in separate areas) connected to each bit line.

[0151] although Figures 4B to 4G An exemplary memory for

[0045] is a three-dimensional memory structure comprising vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein.

[0152] The present disclosure relates to a technology for increasing the bandwidth of non-volatile memory devices for the purpose of producing high-bandwidth flash (HBF) memory devices that can be used as an alternative to HBM, particularly for machine learning inference operations. The HBF memory devices of the present disclosure are configured to operate according to a storage scheme of 1 bit per memory cell (sometimes referred to as "single-level cell" or "SLC" memory). The SLC storage scheme was chosen (as opposed to other storage schemes that allow multiple bits to be stored in each memory cell) because it is the fastest solution for reducing read latency (and increasing bandwidth).

[0153] Figure 10An example embodiment of a computing system 1000 constructed according to aspects of the present disclosure is shown. The computing system 1000 includes a single graphics processor unit (GPU) 1002 (or similar processor unit) and eight HBF packages 1004, all of which are in electrical communication with the single GPU 1002. Such a computing system 1000 may be particularly useful for storing data related to large language models because once the model data has been stored in the HBF package 1004, the model data will not be updated or changed very frequently. Therefore, for machine learning inference applications, the HBF package 1004 can be viewed as a write-once, read-many memory. In some embodiments, the computing system 1000 may include more or less than eight HBF packages 1004. For example, in another embodiment, the computing system includes five HBF packages in electrical communication with a single GPU.

[0154] In an exemplary embodiment, each of the HBF packages 1004 includes eight memory dies, where each memory die includes thirty-two facets that can be operated independently and simultaneously. In some embodiments, the number of dies in each HBF package and the number of facets per die can vary relative to these figures.

[0155] As described in further detail below, one aspect of the present disclosure relates to a method of operating a computing system 1000 that includes transferring data between a single GBU 1002 and a HBF package 1004 at a rate greater than 2.7 TB / s and preferably greater than 3 TB / s.

[0156] As described above, in some machine learning applications, large language models comprising terabytes (or more) of data must be stored in memory and retrieved at very high data rates. Such applications requiring very high bandwidth and low power typically store data in HBM DRAM. For example, in existing machine learning system applications, a processor (e.g., a CPU, GPU, or other processor) is coupled to six (6) HBM DRAM devices and has a system bandwidth of 3TB / s. However, DRAM is very expensive and each DRAM device has a limited capacity. Therefore, the cost of the number of HBM chips required to store the entire large language model is very high.

[0157] Non-volatile memory (e.g., NAND) is significantly cheaper than DRAM, but the bandwidth of conventional NAND memory devices is much lower than that of HBM DRAM. For example, an HBM DRAM die has a bandwidth of approximately 75 GB / s. In comparison, a conventional NAND memory die has a bandwidth of approximately 4.4 GB / s.

[0158] Achieving a bandwidth greater than 2.7 TB / s (preferably at least 3 TB / s) using conventional NAND memory devices would require a considerable number of memory packages. For example, with 16 memory dies per memory package, each memory package has a bandwidth of 16 x 4.4 GB / s = 70.4 GB / s. To provide a bandwidth of 3 TB / s, forty-four (44) memory packages would be required, which is impractical.

[0159] Additionally, conventional NAND memory devices have too high a power consumption to provide a viable alternative to HBM devices. For example, in conventional NAND technology, the memory array itself has a power efficiency of approximately 4.5 pJ / bit (e.g., greater than 4.1 pJ / bit). However, in an exemplary embodiment, the HBF package 1004 has a power efficiency of no greater than approximately 1 pJ / bit (i.e., less than 1.1 pJ / bit).

[0160] The present disclosure generally relates to techniques for increasing the bandwidth and reducing the power consumption of non-volatile memory, such as flash memory. In particular, the aforementioned HBF package utilizes the techniques to provide the HBF package with sufficient bandwidth and acceptable power efficiency for use in large language model processing.

[0161] In an embodiment, the bandwidth of HBF memory is increased by: (1) increasing the number of memory planes per memory die; (2) increasing the number of input / output (I / O) channels per memory die to accommodate the increased bandwidth of the memory die; and (3) reducing the physical page size to reduce read latency. These are described below.

[0162] As mentioned above, memory structures such as Figure 2A The memory structure 202 may include multiple planes, and each plane may operate in parallel. For example, Figure 5A A diagram showing a memory structure including four planes: P00, P01, P02, and P03.

[0163] In one embodiment, each of the surfaces P00, P01, P02, and P03 is divided into two sub-surfaces. For example, surface P00 includes a first sub-surface P000 and a second sub-surface P001, second sub-surface P01 includes a first sub-surface P010 and a second sub-surface P011, third sub-surface P02 includes a first sub-surface P020 and a second sub-surface P021, and fourth sub-surface P03 includes a first sub-surface P030 and a second sub-surface P031.

[0164] In one embodiment, each of planes P00, P01, P02, and P03 includes a logical page and a physical page size. Figure 5AIn the embodiment of the present invention, the physical page size is 8kB / page, and each logical page contains two physical pages (ie, each logical page is 16kB).

[0165] In one embodiment, the memory die comprising faces P00, P01, P02, and P03 has a capacity of 32 GB. In one embodiment, sixteen (16) memory dies are included in the memory package, and the memory package has a capacity of 16×32 GB=512 GB. Other capacities per memory die and other numbers of memory dies per memory package may be used.

[0166] In one embodiment, a memory die including planes P00, P01, P02, and P03 has a read latency ("tR") of approximately 15 μs. The bandwidth of each die can be determined based on the read latency and the logical page size as follows:

[0167]

[0168] In one embodiment, the memory die including planes P00, P01, P02, and P03 has 8-bit I / O and an I / O speed of 4.8 G-transfers / s. Since the I / O speed (4.8 G-transfers / s) is faster than the memory die data rate (4.4 GB / s), the I / O speed is not a factor limiting the data rate of the memory die.

[0169] In one embodiment, the number of faces per memory die is increased to increase memory die bandwidth. For example, Figure 5B A diagram illustrating a memory structure including thirty-two (32) planes: four planes in the x-direction (e.g., planes P00, P01, P02, and P03) and eight planes in the y-direction (e.g., planes P03, P13, P23, P33, P43, P53, P63, and P73).

[0170] In one embodiment, surfaces P00, P01, P02, ..., P72, and P73 are divided into two sub-surfaces. For example, surface P00 includes a first sub-surface P000 and a second sub-surface P001, second sub-surface P01 includes a first sub-surface P010 and a second sub-surface P011, ..., and the thirty-second sub-surface P73 includes a first sub-surface P730 and a second sub-surface P731.

[0171] In one embodiment, planes P00, P01, P02, ..., P72, and P73 include logical and physical page sizes. Figure 5B In the embodiment of the present invention, the physical page size is 8kB / page, and each logical page contains two physical pages (ie, each logical page is 16kB).

[0172] You can use the following methods to Figure 5A Structure export Figure 5B The structure of: keep the same number of faces in the x direction (4 faces in the x direction); split the face in half in the y direction and repeat four copies (a total of 8 faces in the y direction), for a total of 4×8=32 faces per memory die. This is Figure 5A Eight (8) times the number of faces of the embodiment. Therefore, the total capacity per die is 0.5 x 8 x 32 GB = 128 GB, and the bandwidth per die is 8 x 4.4 GB / s = 35.2 GB / s.

[0173] In one embodiment, in a memory package (e.g., Figure 10 Each HBF package 1004 shown in FIG includes sixteen (16) memory dies, so the memory package has a capacity of 16×128GB=2TB. Each memory package has a bandwidth of 16×35.2GB / s=563.2GB / s. In order to provide a bandwidth greater than 2.7TB / s (preferably, about 3TB / s), five (5) memory packages will be required. Figure 10 Eight HBF packages 1004 are shown in the exemplary embodiment of FIG.

[0174] To provide this bandwidth, the number of I / O channels per die must be increased. As mentioned above, an 8-bit I / O has a speed of 4.8 G-transfers / s. If the number of I / Os is increased by a factor of eight to 64 I / Os, the I / O speed increases to 8×4.8 G-transfers / =38.4 G-transfers / s, which is faster than the memory die data rate (35.2 GB / s).

[0175] In another embodiment, the memory die bandwidth can be increased by reducing the physical page size to reduce the read latency tR. For example, Figure 5C A diagram illustrating a memory structure comprising thirty-two (32) planes: eight (8) planes in the x-direction (e.g., planes P00, P01, ..., P07) and four (4) planes in the y-direction (e.g., planes P07, P17, P27, and P37).

[0176] In one embodiment, surfaces P00, P01, P02, ..., P36, and P37 are divided into two sub-surfaces. For example, surface P00 includes a first sub-surface P000 and a second sub-surface P001, second sub-surface P01 includes a first sub-surface P010 and a second sub-surface P011, ..., and the thirty-second sub-surface P37 includes a first sub-surface P370 and a second sub-surface P371.

[0177] In one embodiment, planes P00, P01, P02, ..., P36, and P37 include logical and physical page sizes. Figure 5C In the embodiment of the present invention, the physical page size is 4kB / page, and each logical page contains two physical pages (ie, 8kB per logical page).

[0178] Figure 5C The structure of Figure 5B The structure of derives from: Split each 8kB face in the x direction into two (2) 4kB faces (eight faces in the x direction), and reduce the number of faces in the y direction by half (four faces in the y direction), for a total of thirty-two (32) faces. This is the same as Figure 5B The total capacity of each die is 64GB.

[0179] By cutting each word line in half (from 8kB to 4kB), the read latency tR is reduced. In one embodiment, Figure 5C The read latency tR of the implementation is 4μs (compared to Figure 5B The read latency tR of the implementation is 15 μs. The bandwidth of each die can be determined based on the read latency and the logical page size as follows:

[0180]

[0181] In one embodiment, in a memory package (e.g., Figure 10 The HBF package 1004 shown in FIG. 1 includes sixteen (16) memory dies, so the memory package has a capacity of 16×64GB=1TB. Each memory package has a bandwidth of 16×66GB / s=1.1TB / s. To provide a bandwidth of approximately 3TB / s, three (3) memory packages would be required, which is practical.

[0182] To provide this bandwidth, the number of I / Os per die is also increased. As mentioned above, an 8-bit I / O has a speed of 4.8 G-transfers / s. If the number of I / Os is increased sixteen (16) times to one hundred and twenty-eight (128) I / Os, the I / O speed increases to 16 x 4.8 G-transfers / s = 77 G-transfers / s, which is faster than the memory die data rate (66 GB / s). In other words, by significantly increasing the number of I / Os, the I / Os do not limit the bandwidth.

[0183] The memory die bandwidth can be further increased by further reducing the physical page size to reduce the read latency tR. For example, Figure 5D A diagram illustrating a memory structure comprising thirty-two (32) planes: eight (8) planes in the x-direction (e.g., planes P00, P01, ..., P07) and four (4) planes in the y-direction (e.g., planes P07, P17, P27, and P37).

[0184] In one embodiment, surfaces P00, P01, P02, ..., P36, and P37 are divided into two sub-surfaces. For example, surface P00 includes a first sub-surface P000 and a second sub-surface P001, second sub-surface P01 includes a first sub-surface P010 and a second sub-surface P011, ..., and the thirty-second sub-surface P37 includes a first sub-surface P370 and a second sub-surface P371.

[0185] In one embodiment, planes P00, P01, P02, ..., P36, and P37 include logical and physical page sizes. Figure 5D In the embodiment of the present invention, the physical page size is 2kB / page, and each logical page contains two physical pages (ie, each logical page is 4kB).

[0186] Figure 5D The structure of Figure 5C The structure of derives: Split each 4kB face in the x direction into two 2kB faces (8 faces in the x direction), and keep half the same number of faces in the y direction (4 faces in the y direction), for a total of 32 faces. This is the same as Figure 5C The total capacity of each die is 32GB.

[0187] By cutting each word line in half (from 4kB to 2kB), the read latency tR is reduced. In one embodiment, Figure 5D The read latency tR of the example is 1.7μs (compared to Figure 5B The read latency tR of the implementation is 15μs, and Figure 5C The read latency of the implementation is 4μs). The per-die bandwidth can be determined based on the read latency and the logical page size as follows:

[0188]

[0189] In one embodiment, eight (8) memory dies are included in a memory package, so the memory package has a capacity of 8×32GB=256GB. Each memory package has a bandwidth of 8×77GB / s=616GB / s. To provide a bandwidth of approximately 3TB / s, at least five (5) memory packages are provided.

[0190] To provide this bandwidth, the number of I / Os per die must be increased. As mentioned above, an 8-bit I / O has a speed of 4.8 G-transfers / s. If the number of I / Os is increased sixteen (16) times to one hundred and twenty-eight (128) I / Os, the I / O speed increases to 16 x 4.8 G-transfers / s = 77 G-transfers / s, which is roughly the same as the memory die data rate (77 GB / s).

[0191] The first technique for improving the power efficiency of the HBF package 1004 (as Figure 10 shown) is to reduce the supply voltage. The power consumed by the NAND array is approximately equal to VCC × ICC, where VCC is the supply voltage and ICC is the supply current. For current NAND memories, a supply voltage of VCC = 2.5V is typically used. One technique for reducing power consumption (and thus improving power efficiency) is to reduce the supply voltage VCC, such as VCC = 1.2V.

[0192] With the reduced supply voltage VCC, the memory device still must perform various functions, such as programming, inhibition, and sensing. Figures 6A to 6C An example NAND string during these three different memory operations is shown. In particular, Figures 6A to 6C example NAND strings during inhibition, programming, and sensing are shown, respectively.

[0193] For inhibition, as Figure 6A shown, 1.2V VCC is provided to the inhibition bit line. This voltage needs to be high enough to cut off the unselected SGD transistors to provide channel boosting for the inhibition operation. That is, (VSGD – VDD) < Vt.

[0194] For programming, as Figure 8B shown, the bit line voltage VBL = 0V is transferred to the channel. This requires the bias VSGD on the SGD cell to be greater than the threshold voltage of the SGD cell, VSGD > Vt. In one embodiment, the threshold voltage of the SGD cell is approximately 1.5V.

[0195] Therefore, for inhibition, (VSGD – VDD) < Vt is required, and for programming, VSGD > Vt is required. From these two requirements, the following can be derived:

[0196] VSGD > Vt upper tail

[0197] VSGD < VDDSA + Vt lower tail

[0198] In an embodiment, Vt lower tail is approximately 1.5V and Vt upper tail is approximately 1.9V, and VDDSA is approximately 1.1V. Therefore, according to the above two conditions:

[0199] 1.9V < VSGD < 2.6V

[0200] For sensing, as Figure 6CAs shown, the bit line voltage VBL needs to provide sufficient drain-source voltage for the NAND string. In conventional NAND devices, the source line voltage VCELSRC is set to 1V. In such a scenario, the bit line voltage needs to provide VBLC (about 0.2V) + VCELSRC + a little transistor threshold voltage + some temperature compensation (TCO) voltage, which results in about 1.5V, which cannot be derived from VCC if VCC = 1.2V. Therefore, in the scheme referred to as the "positive sensing" scheme in this article, the source line voltage VCELSRC is set to 0V instead. Since the source line voltage VCELSRC is set to a lower voltage, the bit line voltage needs to provide VBLC (about 0.2V) + 0V + a little transistor threshold voltage + some temperature compensation (TCO) voltage, which results in about 0.5V, which can be provided with a lower VCC = 1.2V. Therefore, the VCC 1.2V external power source can provide the correct voltage for the HBF package 1004.

[0201] The second technique to improve the power efficiency of the HBF package 1004 is to reduce all internal voltages within the NAND device. In one example embodiment, the V read, VDDSA, and VBL voltages are set as follows:

[0202] Conventional NAND HBF V Read (V) 4.7 2.4 VDDSA(V) 2.2 1.1 VBL(V) 0.3 0.15 Isensing(nA) 20 10

[0203] Figure 7A Example threshold voltage distributions for NAND memory cells are shown. In particular, the example threshold voltage distributions include an erased state (eg, a "1") distribution and a programmed state (eg, a "0") distribution for conventional NAND memory cells.

[0204] In the illustrated example, both threshold distributions are wide (e.g., such as can be achieved using a one program, zero verify "1P0V" program approach), and there is a wide separation between the two threshold distributions. In the example shown, a read verify level SLCR of 0V is used, and the unselected word lines are biased at a voltage of Vread = 4.7V.

[0205] Figure 7B HBF package 1004 (eg Figure 10 1 ). In particular, the exemplary threshold voltage distribution includes an erased state (e.g., “1”) distribution and a programmed state (e.g., “0”) distribution. Since programming operations are not frequently performed in HBF package 1004, the threshold voltage distribution can be made very narrow during programming, much narrower than Figure 7A The threshold voltage distribution of a conventional NAND memory device is shown in .

[0206] In addition, the gap between the two distributions can be brought very close together. By reducing the gap and the threshold voltage distribution width, the unselected word line voltage of Vread can be reduced from a conventional voltage (e.g., 4.7V). In one exemplary embodiment, Vread is set to 2.4V to further reduce power consumption.

[0207] Additionally, in one exemplary embodiment of the HBF package 1004, the read verification level SLCR may be lowered from 0V (eg, at Figure 7A In one embodiment, the read verify level SLCR is set at the upper tail of the erase distribution. For example, the read verify level SLCR = -1V or some other level. By setting the read verify level SLCR at the upper tail of the erase distribution, the amount of overload between the erase state distribution and the read verify level SLCR is reduced, which in turn reduces power consumption during sensing.

[0208] As described above, large language model processing is read intensive for the HBF package 1004. Therefore, the HBF package 1004 will experience a large amount of read disturb. When reading a selected memory cell, a pass voltage VREAD is applied to the unselected word lines of the memory block, and a reference voltage SLCR is applied to the selected word line containing the selected memory cell (see Figure 6C ). A sensing operation is then performed to determine whether the threshold voltage Vt of the selected memory cell is above or below the reference voltage VCG. This process can unintentionally induce a weak programming effect in some memory cells of the memory block. Over time, if this process is repeated frequently without any intervening erase or program cycles, the accumulated charge in the memory cell can change its threshold voltage Vt, potentially causing bit errors.

[0209] For example, Figure 8A An example threshold voltage Vt distribution of multiple memory cells (e.g., a page) in an example memory block immediately after programming is shown. After a large number of reads (e.g., 100,000 reads) in a memory block, the erase distribution will be widened by repeated unintentional weak programming. Therefore, as Figure 8B As shown, the upper tail of the erased data state "1" has encroached on the lower tail of the programmed data state "0." Therefore, due to read disturb, the margin (the voltage difference between the upper tail of the erased data state and the lower tail of the programmed data state) has been significantly reduced.

[0210] Conventionally, after experiencing severe read disturbance in one block, the data is relocated to a new block (called "relocation"), and the host can then continue reading from the new block. Although this results in a well-defined threshold voltage (Vt) distribution in the relocated block, it requires consuming program-erase cycles to program the data into the new block B, which compromises endurance. In addition, the block management function becomes more complex because the logical-to-physical block table must track the relocated data.

[0211] In one embodiment, read disturb can be detected by monitoring the error rate detected and corrected by the ECC engine. Corrective action is then triggered in response to the error rate exceeding a predetermined threshold error rate. In another embodiment, the number of read cycles in the memory block since the data was programmed is counted. After the count reaches a predetermined threshold (e.g., one hundred thousand read cycles), corrective action is then triggered. In yet another embodiment, when the data is initially programmed, a read is performed at two voltages between the upper tail of the erased data state and the lower tail of the programmed data state (e.g., see Figure 9A ). The number of memory cells having a threshold voltage Vt between the two voltages is counted. If the number of memory cells within the voltage range is below a predetermined threshold, then the memory cells have not experienced significant read disturb. On the other hand, if the number of memory cells within the voltage range is above a predetermined threshold, then it is determined that the memory cells have experienced significant read disturb.

[0212] One aspect of the present disclosure relates to a method for refreshing data "in place" after a large amount of read disturb has occurred, thereby increasing the erased data state ( Figure 8A and Figure 8B "1" in the program) and the programmed data state ( Figure 8A and Figure 8B In an embodiment, the in-place refresh technique may be implemented by any one or any combination of the memory controller 104, the state machine 228, all or a portion of the system control logic 208, all or a portion of the row control circuitry 204, all or a portion of the column control circuitry 216, a microcontroller, a microprocessor, and / or any other similar functional circuitry.

[0213] Figure 9A shows the threshold voltage Vt distribution of a page of memory cells in a memory block shortly after programming, and Figure 9B 1 shows the threshold voltage Vt distribution for the same page of memory cells after a large amount of read disturb has occurred. According to the in-place refresh technique, in response to detecting that a memory cell has experienced a certain amount of read disturb (e.g., by detecting read disturb or by a read cycle count exceeding a predetermined threshold), the memory cell in the programmed data state ( Figure 9A and Figure 9B The memory cell with a "1" in the SLCR is programmed to a higher threshold voltage Vt level, and the control gate voltage VCG employed during the sensing operation is lowered from the SLCR (e.g., Figure 9A and Figure 9B ) is increased to SLCR_2 located between the upper tail of the erased data state ("1") and the programmed data state ("0"). In other words, the programmed data state has been advanced to increase the threshold voltage Vt margin.

[0214] Programming of memory cells in a programmed data state ("0") occurs on a word-by-word basis from one side of the memory block toward the opposite side of the memory block. Programming can include one or more program loops, each of which includes a programming pulse (hereinafter referred to as a VPGM pulse) and (optionally) a verify pulse. In some embodiments, programming during an in-place refresh operation includes one program loop with a single VPGM pulse and zero verify pulses (1P0V). In some other embodiments, an in-place refresh operation can include multiple program loops, each with a VPGM pulse and a verify operation (nPnV). In some embodiments, the programming voltage VPGM is increased by a fixed step size dVpgm between program loops.

[0215] Figure 6B The voltages applied to an example NAND string containing a memory cell being refreshed (specifically, any of the memory cells in a programmed data state) during a VPGM pulse are shown. As shown, a programming voltage is applied to the selected word line WLn containing the memory cell to be refreshed, and a very low voltage (VBL=0V) is applied to the bit line coupled to the NAND string. The large gate-to-channel differential causes some electrons to navigate into the charge trapping material of the selected memory cell, thereby increasing its threshold voltage Vt. Turning now to Figure 6C For memory cells that are not desired to be programmed (specifically, and for memory cells in an erased data state), a relatively high inhibit voltage (VBL=1.2V) is applied to the bit line coupled to the corresponding NAND string, so that a relatively low gate-to-channel voltage exists and programming of the selected memory cells is inhibited.

[0216] Now turn Figure 9DIf the memory block experiences further read disturbance, the memory cells in the programmed data state ("0") can be further programmed to further increase their threshold voltage Vt, thereby increasing the threshold voltage Vt margin between the erased data state ("1") and the programmed data state ("0"). The control gate voltage employed during reading is then adjusted to SLCR_3, which is between the upper tail of the erased data state ("1") and the lower tail of the programmed data state ("1"). This process can be repeated multiple times within the acceptable threshold voltage Vt window.

[0217] Now turn Figure 11 , a flowchart 1100 is provided showing the steps of refreshing data in place according to an exemplary embodiment of the present disclosure. These steps may be performed by the following components: a controller; a processor or processing device or any other circuit that executes instructions stored in a memory; and / or other circuits described herein that are explicitly configured / programmed to perform the following steps.

[0218] At step 1102, a first sub-block (eg, Figure 9A and Figure 9B The memory cells of the lower sub-block SB0 are shown to have experienced significant read disturb. This may include detecting read disturb or determining that the read cycle count since data was programmed into the first sub-block exceeds a predetermined threshold.

[0219] At step 1104, without erasing the memory cells of the selected word line, at least one VPGM pulse is applied to the selected word line to further program the memory cells in the programmed data state to a higher threshold voltage Vt and thereby increase the threshold voltage Vt margin between the erased data state and the programmed data state.

[0220] At step 1106 , a reference voltage SLCR for use during a read operation is increased from a first level to a second, higher level.

[0221] The process can then proceed sequentially through all word lines in the memory block until all memory cells have been refreshed.

[0222] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0223] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected such that they are capable of communicating electronic signals between them.

[0224] For the purposes of this document, the term "based on" may be understood to mean "based, at least in part, on."

[0225] For the purposes of this document, the use of numerical terms such as a "first," "second," and "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0226] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0227] The above detailed description has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and with various modifications as suited to the specific use contemplated. The scope of the invention is intended to be defined by the claims appended hereto.

Claims

1. A method of operating a memory device, the method comprising the steps of: preparing a memory device including a memory block having an array of memory cells arranged in a plurality of word lines, the memory cells being programmed with one bit per memory cell, wherein each memory cell is in an erased data state or a programmed data state; determining that the memory cell has experienced significant read disturb; as well as The memory cells in the programmed data state are directly programmed to a higher threshold voltage without erasing the memory cells to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.

2. The method according to claim 1, further comprising the steps of: counting the number of read cycles to establish a read cycle count; as well as comparing the read count cycle with a predetermined threshold; as well as Wherein said step of determining that said memory cell has experienced significant read disturb occurs in response to said read cycle count exceeding said predetermined threshold.

3. The method of claim 1 , wherein the step of determining that the memory cells have experienced significant read disturb occurs in response to determining that a count of memory cells within a voltage range below a voltage range associated with the programmed data state is greater than a predetermined threshold.

4. The method according to claim 1, further comprising the steps of: After the step of programming the memory cells in the programmed data state to a higher threshold voltage, a reference voltage SLCR used during a read operation is set from a first level to a second, higher level.

5. The method of claim 1 , wherein programming the memory cells in the programmed data state to a higher threshold voltage comprises: applying a programming voltage to the selected word line; providing a plurality of bit lines electrically coupled to the memory cells of the selected word line and in the programmed data state at a very low voltage; as well as A plurality of bit lines are provided that are electrically coupled to the memory cells of the selected word line and are in the erased data state at an inhibit voltage.

6. The method of claim 1 wherein the step of programming the memory cells in the programmed data state directly to a higher threshold voltage comprises a single programming pulse and no verify operation, or comprises multiple programming pulses and verify operations.

7. A memory device, comprising: a memory block with an array of memory cells arranged in a plurality of word lines, the memory cells being programmed with one bit per memory cell, wherein each memory cell is in an erased data state or a programmed data state; and A circuit, the circuit being configured to: determining that the memory cell has experienced significant read disturb; as well as The memory cells in the programmed data state are directly programmed to a higher threshold voltage without erasing the memory cells to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.

8. The memory device of claim 7, wherein the circuit is configured to count a number of read cycles to establish a read cycle count; and comparing the read count cycle to a predetermined threshold; and Wherein the circuit determines that the memory cell has experienced significant read disturb in response to the read cycle count exceeding the predetermined threshold.

9. The memory device of claim 7, wherein the circuit is further configured to set a reference voltage SLCR used during a read operation from a first level to a second, higher level after programming the memory cells in the programmed data state to the higher threshold voltage.

10. The memory device of claim 7, wherein when programming the memory cell in the programmed data state to a higher threshold voltage, the circuit: applying a programming voltage to the selected word line; providing a plurality of bit lines electrically coupled to the memory cells of the selected word line and in the programmed data states at very low voltages; as well as A plurality of bit lines are provided that are electrically coupled to the memory cells of the selected word line and are in the erased data state at an inhibit voltage.

11. The memory device of claim 7 , wherein the circuit is configured to count a number of memory cells having a threshold voltage within a voltage range lower than a voltage range associated with the programmed data state, comparing the count of memory cells having threshold voltages within the voltage range below the voltage range associated with the programmed data states to a predetermined threshold, and A memory cell is determined to have experienced significant read disturb in response to the count of the memory cell being greater than the predetermined threshold.

12. The memory device of claim 7 , wherein when programming the memory cells in the programmed data state directly to a higher threshold voltage, the circuit applies a single programming pulse to the selected word line without performing a subsequent verification operation, or applies multiple programming pulses to the selected word line and performs a subsequent verification operation.

13. A computing system, comprising: Processor unit; a plurality of high-bandwidth flash memory (HBF) packages in electrical communication with the processor unit; At least one of the HBF packages includes a memory block with an array of memory cells arranged in a plurality of word lines, the memory cells being programmed with one bit per memory cell, wherein each memory cell is in an erased data state or a programmed data state; and The at least one of the HBF packages further comprises a circuit configured to: determining that the memory cell has experienced significant read disturb; as well as The memory cells in the programmed data state are directly programmed to a higher threshold voltage without erasing the memory cells to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.

14. The computing system of claim 13, wherein the circuit is configured to count the number of read cycles to establish a read cycle count; and comparing the read count cycle to a predetermined threshold; and Wherein the circuit determines that the memory cell has experienced significant read disturb in response to the read cycle count exceeding the predetermined threshold.

15. The computing system of claim 13, wherein the circuit is further configured to set a reference voltage SLCR used during a read operation from a first level to a second, higher level after programming the memory cells in the programmed data state to the higher threshold voltage.

16. The computing system of claim 13 , wherein when programming the memory cell in the programmed data state to a higher threshold voltage, the circuit: applying a programming voltage to the selected word line; providing a plurality of bit lines electrically coupled to the memory cells of the selected word line and in the programmed data states at very low voltages; as well as A plurality of bit lines are provided that are electrically coupled to the memory cells of the selected word line and are in the erased data state at an inhibit voltage.

17. The computing system of claim 13 , wherein the circuit is configured to count a number of memory cells having a threshold voltage within a voltage range lower than a voltage range associated with the programmed data state, comparing the count of memory cells having threshold voltages within the voltage range below the voltage range associated with the programmed data states to a predetermined threshold, and A memory cell is determined to have experienced significant read disturb in response to the count of the memory cell being greater than the predetermined threshold.

18. The computing system of claim 13, wherein the plurality of HBF packages are capable of electrically communicating with the processor unit at a rate greater than 3 TB / s.

19. The computing system of claim 13, wherein the HBF package receives a supply voltage no greater than 1.2V.

20. The computing system of claim 13 , wherein when programming the memory cells in the programmed data state directly to a higher threshold voltage, the circuit applies a single programming pulse to the selected word line without performing a subsequent verification operation, or applies multiple programming pulses to the selected word line and performs a verification operation.

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