High-reverse-voltage-resistant high-end ideal diode

Abstract

The invention discloses a high reverse voltage resistant high-end ideal diode, which relates to the technical field of power diodes, comprises a circuit, and is characterized in that the circuit comprises a PMOS main tube V1, a comparator circuit, a protection circuit and a power supply VCC, and the protection circuit is used for protecting the comparator circuit; the comparator circuit comprises two transistors which are independent or have the same parameters and are packaged together, a diode pair transistor and a resistor, a drain electrode of the PMOS main tube V1 is connected to a power supply VCC, and a source electrode of the PMOS main tube V1 is connected to an output end power supply Vout; the comparator circuit compares the size of the power supply VCC and the size of the output end power supply Vout and outputs a comparison signal to the grid electrode of the PMOS main tube V1 to control the conduction and cut-off of the PMOS main tube V1. The high-reverse-voltage-resistant high-end ideal diode has the advantages that the high-reverse-voltage-resistant high-end ideal diode is provided with a resistor voltage division circuit and a voltage stabilizing diode fixed voltage division circuit, and is capable of preventing backflow and resistant to high reverse voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of power diodes, and in particular to a high-end ideal diode capable of withstanding high reverse voltage. Background Art

[0002] Due to its unidirectional conduction characteristics, the diode has a relatively high reverse voltage resistance and a very small reverse current, and has an excellent backflow prevention function. The Schottky diode has a small voltage drop, a relatively low reverse voltage resistance, a large reverse current, and a weaker backflow prevention function. The MOS tube used as an ideal diode has a relatively small main voltage drop and a low impedance characteristic, but the reverse voltage resistance of the MOS tube gate and source is relatively low. The ideal diode implementation schemes that are most similar to the present invention are as follows, but they all have certain shortcomings.

[0003] PNP pair + PMOS tube technical solution: Figure 1 As shown, the PNP pair uses two PNP tubes from the same manufacturer and the same batch to ensure that the parameters of the two PNP tubes are basically equal, or preferably the PNP pair is packaged together, the parameters of the two PNP tubes are almost equal, thus ensuring proper switching and anti-backflow functions. Since the BE junction of the BJT tube is essentially a PN junction, equivalent to a diode, the BE junction of the BJT tube can be replaced by a diode. Figure 1 The PNP pair of tubes V2 and V3 form a comparator circuit. The bases of the V2 and V3 tubes are connected together, which is equivalent to the cathodes of the two diodes being connected together (it belongs to a common cathode circuit. According to the conduction principle of two diodes, the diode with a higher anode voltage will be turned on first, and the other diode with a lower anode voltage will be cut off or weakly turned on). Therefore, of the PNP pair of tubes V2 and V3, whichever PNP tube has a higher emitter voltage, its emitter junction (corresponding to the EB junction) will be turned on first, and the emitter junction of the other PNP tube with a lower emitter junction voltage will be cut off.

[0004] The PNP pair + PMOS tube solution better realizes the ideal diode function and controls the conduction and cutoff of the PMOS tube V1: when the input power supply VCC is not less than the output power supply Vout, the PMOS tube V1 is turned on; otherwise, the PMOS tube V1 is cut off, preventing the current of the output power supply Vout from flowing back to the input power supply VCC, protecting the input power circuit, which is equivalent to a high-end ideal diode. The disadvantage is that the bias resistance of the PNP tube is in the kiloohm level, and the static operating current loss is at least in the milliampere level, which means the current loss is relatively large.

[0005] For NPN tubes: the base (P region) is very thin and has a very low doping concentration, which is conducive to the conduction of carriers; the emitter (N region) has a small area and a high doping concentration, which is conducive to the emission of carriers; the collector (N region) has a large area and a very low doping concentration, which is conducive to the collection of carriers. The typical doping concentrations of the emitter, base, and collector regions of NPN tubes are 10 19 / cm 3 , 10 17 / cm 3 , 10 15 / cm 3 The same is true for PNP diodes. Generally speaking, the higher the doping concentration of the PN junction, the greater the charge density, and the lower the reverse breakdown voltage. Zener diodes are made based on this principle and are generally used for reverse bias voltage. As long as the reverse current is controlled within a certain range, the Zener diode will not be damaged by overheating. During normal use, a current-limiting resistor is required in series to prevent damage.

[0006] When the collector C is open, the voltage VEBO between the base and emitter of the PNP tube when the PN junction is reversely broken down is generally a few volts for small-power BJT tubes (the voltage VCBO between the collector and the base when the PN junction is reversely broken down and the voltage VCEO between the collector and the emitter when the PN junction is reversely broken down, both reverse breakdown voltages are usually tens of volts). For common PNP tubes, VCBO = -40V, VCEO = -25V, and VEBO = -5V. The normal working conditions of BJT tubes require: satisfying |VCE| < |VCEO|, |VEB| < |VEBO|.

[0007] For MOS tubes, the gate-source voltage difference is relatively small, and the maximum value is usually V GS(MAX) = ±8V or ±12V (the drain-source voltage difference can reach tens of volts, and the common MOS tube V DS(MAX) = ±30V or ±60V), once the gate-source voltage difference V GS Exceed V GS(MAX) , the gate source may be broken down and the MOS tube may be damaged.

[0008] Figure 1 (PNP pair + PMOS tube technical solution) When working in the forward direction, the PMOS tube V1 and the PNP tube V2 are turned on, and the PNP tube V3 is turned off: VCC outputs current normally, and the output voltage difference is relatively small. It can generally be considered that Vout ≈ VCC (actually Vout < VCC); VA = VCC - V F (V F =0.7V is the forward conduction voltage drop of the diode), the base and emitter voltage difference of V3 tube is V3 BE =VA-Vout=VCC-V F -Vout≈-V F=-0.6V, generally speaking, the VEBO of the PNP tube is -5V, so V3 BE <-VEBO=5V, the base and emitter of V3 will not be broken down. The maximum voltage difference between the gate and source of PMOS V1 is usually V GS(MAX) = ±8V, ±12V, ±20V, since V3 is cut off, the voltage VB≈0V, V1 GS =VB-Vout≈0V-Vout≈-Vout, if V1 GS ≈-Vout≈-VCC<-V GS(MAX) =-8V, the gate and source of V1 tube may be broken down, so the gate and source of V1 tube need to be protected.

[0009] When VCC>Vout, in normal operation, V2 EB =V F =0.7V, PNP tube V2 is turned on (corresponding to the drain-source channel on-resistance V2R CE VA = VCC - V F , conduction voltage drop V2 EC =V2 EB =V F =0.7V; at the beginning, the body diode of V1 tube is turned on, Vout = VCC-V F , V3 EB =Vout-VA=VCC-V F -(VCC-V F )=0V, PNP tube V3 is cut off (cut-off impedance V3R CE Theoretically, it is infinite, V3R CE V2R CE The collector voltage of V3 (gate of V1) is VB = V3. C =V1 G ≈0V, the drain-source channel of V1 tube is turned on, and the conduction voltage drop of V1 tube is V1 DS =I1 DS ×V1R DS(ON) , Vout=VCC-V1 DS =VCC-I1 DS ×V1R DS(ON) , V3 EB =VCC-I1 DS ×V1R DS(ON) -(VCC-V F )=V F -I1 DS ×V1R DS(ON) <V F , PNP tube V3 is cut off (cut-off impedance V3R CERelatively large, V3R CE V2R CE The on-state current is much smaller than that of the V2 tube), VB is pulled down to the negative pole of the power supply by the resistor R2, and the collector voltage of the PNP tube V3 VB=V3 C ≈0V, V3 EC =Vout≈VCC, so the V3 tube generally will not break down.

[0010] When an external reverse power supply is connected, that is, Vout>VCC, V3 tube is turned on, V1 tube and V2 tube are turned off: VCC cannot output current normally, and Vout generally cannot reversely flow current to VCC. Since V3 tube is turned on, VA=Vout-V F , the base and emitter voltage difference of V2 tube is V2 BE =VA-VCC=Vout-V F -VCC, if V2 BE =Vout-VCC-V F >-VEBO=5V, the base and emitter of V2 tube may break down, so the base and emitter of V2 tube need to be protected. Since V3 tube is turned on, VB≈Vout, V1 GS =VB-Vout≈Vout-Vout≈0V<V GS(MAX) , the gate and source of V1 tube will not be broken down. If the reverse voltage Vout is relatively large, PNP tube V2 is cut off and PNP tube V3 is turned on, and the voltage VA = Vout-V F , once VA-VCC>|VBEO|, Vout-V F -VCC>|VBEO|=5V(V F =0.7V is the diode conduction threshold voltage), that is, Vout-VCC>V F +5V=5.7V, which means that the reverse voltage Vout is 5.7V higher than the operating voltage VCC, and the PNP tube V2 may be damaged.

[0011] The above technical solution analysis shows that: when forward conduction occurs, the PMOS tube V1 needs to be protected, and when an external reverse power supply (Vout>VCC) is connected, the PNP tube V2 needs to be protected; if VCC is greater than V GS(MAX) , that is, excessive VCC will damage the PMOS transistor V1; the reverse voltage (Vout) cannot exceed a certain voltage (such as 5V) compared to the operating voltage VCC. Therefore, the reverse voltage (Vout) should not be too large. Excessive Vout will damage the PNP transistor V2, which will limit the application scenario. Therefore, it is possible to try to take advantage of the relatively large reverse breakdown voltage of the diode (tens of volts) and the characteristics of the Zener diode. Therefore, it is necessary to combine the characteristics of the diode to design a high-end ideal diode with high reverse voltage resistance to expand the application range. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to overcome the deficiencies in the prior art and provide a high-end ideal diode that can withstand high reverse voltage.

[0013] To solve the above technical problems, the present invention provides a technical solution: a high-end ideal diode with high reverse voltage resistance, comprising a circuit, wherein the circuit includes a PMOS main body V1, a comparator circuit, a protection circuit and a power supply VCC, wherein the protection circuit is used to protect the comparator circuit;

[0014] The comparator circuit includes two independent or identically parametered transistors, a diode pair, and a resistor packaged together. The drain of the PMOS main tube V1 is connected to the power supply VCC, and the source is connected to the output power supply Vout.

[0015] The comparator circuit compares the power supply VCC with the output power supply Vout and outputs a comparison signal to the gate of the PMOS tube V1 to control the on and off of the PMOS tube V1.

[0016] Preferably, the comparator circuit includes PNP auxiliary tubes V2 and V3, and resistors R1 and R2;

[0017] The emitter of the PNP auxiliary tube V2 is connected to the power supply VCC, the collector is grounded through the resistor R1, the base is connected to the collector, and the base is connected to the base of the PNP auxiliary tube V3;

[0018] The emitter of the PNP auxiliary tube V3 is connected to the output power supply Vout, the collector is grounded via the resistor R2, and the collector is also connected to the gate of the PMOS main tube V1.

[0019] Preferably, the protection circuit includes a diode pair D1 and D2 connected to the bases of the PNP auxiliary tubes V2 and V3 respectively, wherein the cathodes of the diode pair D1 and D2 are connected to each other, and the anodes are connected to the bases of the PNP auxiliary tubes V2 and V3 respectively.

[0020] Preferably, the protection circuit includes a pair of voltage-stabilizing diodes D1 and D2, and resistors R4 and R5;

[0021] The cathodes of the voltage-stabilizing diodes D1 and D2 are connected, and the anodes are connected to the bases of the PNP auxiliary tubes V2 and V3 respectively. The resistor R4 is connected between the power supply VCC and the emitter of the PNP auxiliary tube V2. The resistor R5 is connected between the output power supply Vout and the emitter of the PNP auxiliary tube V3.

[0022] Preferably, the protection circuit further comprises an overvoltage protector for protecting the PMOS main circuit V1 , wherein the overvoltage protector is connected between the source and the gate of the PMOS main circuit V1 .

[0023] Preferably, the overvoltage protector is any one of a resistor R3 (voltage-dividing resistor R2) or a voltage-stabilizing diode.

[0024] The advantages of the present invention over the prior art are: the circuit has the functions of preventing backflow and withstanding high reverse voltage, and can protect the previous stage circuit; the use of high-end load switches and comparators makes the circuit simple, low-cost and highly practical. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is the schematic diagram of the high-end ideal diode implemented by the existing technology PNP tube comparator;

[0026] Figure 2 A high-end ideal diode (1) with high reverse voltage resistance, based on a diode pair + a PNP pair.

[0027] Figure 3 It is a high-end ideal diode (II) with high reverse voltage resistance based on a Zener diode pair + a PNP pair.

[0028] Figure 4 It is a high-end ideal diode (III) with high reverse voltage resistance, which is composed of a diode pair + a Zener diode + a PNP pair.

[0029] Figure 5 for Figure 2 Forward bias simulation;

[0030] Figure 6 for Figure 2 Reverse bias simulation;

[0031] Figure 7 for Figure 3 Forward bias simulation;

[0032] Figure 8 for Figure 3 Reverse bias simulation;

[0033] Figure 9 for Figure 4 Forward bias simulation;

[0034] Figure 10 for Figure 4 Reverse bias simulation. DETAILED DESCRIPTION

[0035] The present invention will be described in further detail below with reference to the accompanying drawings.

[0036] A high-end ideal diode with high reverse voltage resistance includes a PMOS main transistor V1, a comparator circuit, a protection circuit, etc. The comparator circuit (also known as a differential amplifier circuit) is composed of two independent PNP auxiliary transistors or a PNP pair of transistors V2 and V3 with the same parameters and packaged together, a diode, a resistor, etc.

[0037] The comparator is used to compare the magnitudes of the input power supply VCC and the output power supply Vout. The comparison signal output by the comparator is connected to the gate of the PMOS tube V1 to control the on and off of the PMOS tube V1.

[0038] The diode pair D1 and D2 have a relatively high reverse breakdown voltage and unidirectional conduction characteristics, which can improve the high reverse voltage resistance of the ideal diode; the design is based on the characteristics of the diode's relatively large reverse breakdown voltage (tens of volts) and the voltage regulator tube.

[0039] When the input power supply VCC is not less than the output power supply Vout, the comparator outputs a comparison signal of a low level, that is, the gate VB of the PMOS tube V1 is a low level, that is, VB≈0V, and the PMOS tube V1 is turned on; when the input power supply VCC is less than the output power supply Vout, the comparator outputs a comparison signal of a high level, VB≈Vout, that is, the gate VB of the PMOS tube V1 is a high level, and the PMOS tube V1 is turned off.

[0040] Implementation Method 1

[0041] A high-side ideal diode with high reverse voltage resistance. Figure 1 Improve the circuit by adding diodes D1, D2 and resistor R3, such as Figure 2 As shown, it includes a PMOS supervisor V1, a comparator circuit, a protection circuit, etc.

[0042] Preferably, the comparator circuit is composed of two independent PNP auxiliary tubes or a pair of PNP tubes V2 and V3 with the same parameters and packaged together, resistors R1 and R2, etc.

[0043] Preferably, the comparator is used to compare the magnitudes of the input power supply VCC and the output power supply Vout, and the comparison signal output by the comparator is connected to the gate of the PMOS supervisor V1 to control the on and off of the PMOS supervisor V1.

[0044] Preferably, the overvoltage protection circuit comprises a diode pair D1 and D2, and a resistor R3. The diode pair D1 and D2 have high reverse breakdown voltage and unidirectional conduction characteristics, improving the ideal diode's ability to withstand high reverse voltages. Resistors R3 and R2 form a voltage divider network to protect the gate-source voltage difference of the PMOS transistor V1 from overvoltage. Generally, the reverse voltage withstand value of the diode D1 is required to be higher than the maximum value of Vout, and the reverse voltage withstand value of the diode D2 is required to be higher than the maximum value of VCC.

[0045] Preferably, when the input power supply VCC is not less than the output power supply Vout, the V2 tube and the D1 tube are turned on, the V3 tube and the D2 tube are turned off, and the comparator outputs the comparison signal VB. Since R2 and R3 form a voltage divider circuit, VB is at a low level, VB≈Vout×R2 / (R2+R3), that is, the gate VB of the PMOS main V1 is at a low level, satisfying V1 GS =VB

[0046] -Vout=-Vout×R3 / (R2+R3)<V TP , PMOS is in charge of V1 conduction, that is -Vout×R3 / (R2+R3)<

[0047] V TP =V TP(MAX) =-2.5V; and protect V1 tube from overvoltage -Vout×R3 / (R2+R3)>-|V GS(MAX) If VCC = 12V, R1 = R2 = 100kΩ, then 28.409kΩ < R3 < 242.424kΩ. Diode D2 provides reverse protection, preventing breakdown of the base and emitter of PNP transistor V3.

[0048] Preferably, when the input power supply VCC is less than the output power supply Vout, the V2 tube and the D1 tube are cut off, the V3 tube is saturated and turned on, and the D2 tube is turned on, and the comparator outputs the comparison signal VB as a high level, VB = Vout-V3 EC(sat) ≈Vout(V3 EC(sat) is the saturation conduction voltage drop of V3 tube, V3 EC(sat) <0.3V), that is, the gate VB of the PMOS V1 is high, V1 GS ≈-V3 EC(sat) >V TP >-|V GS(MAX) |, the PMOS tube V1 is cut off to protect the gate and source voltage difference of the PMOS tube V1 from exceeding the voltage; the diode D1 reversely protects the base and emitter of the PNP tube V2 from being broken down.

[0049] Implementation Method 2

[0050] A high-end ideal diode with high reverse voltage resistance, in embodiment 1 Figure 2 Improvements are made on the basis of the circuit, using a voltage-stabilizing diode pair to replace the diode pair D1 and D2, and adding resistors R4 and R5 in series between the power supply VCC and the emitter of the V2 tube, and the power supply Vout and the emitter of the V3 tube, as shown in the figure. Figure 3 As shown, it includes a PMOS supervisor V1, a comparator circuit, a protection circuit, etc.

[0051] Preferably, compared with the first embodiment, the above embodiment uses a pair of Zener diodes, which are generally used for reverse bias voltage. Generally, the reverse voltage withstand value of the Zener diode D1 is required to be higher than the maximum value of Vout, and the reverse voltage withstand value of the Zener diode D2 is required to be higher than the maximum value of VCC.

[0052] Preferably, when the input power supply VCC is not less than the output power supply Vout, the V2 tube and the D1 tube are turned on, the V3 tube and the D2 tube are turned off, and the comparator outputs the comparison signal VB. Since R2 and R3 form a voltage divider circuit, VB is at a low level, VB≈Vout×R2 / (R2+R3), that is, the gate VB of the PMOS main V1 is at a low level, satisfying V1 GS =VB-Vout=-Vout×R3 / (R2+R3)<V TP , PMOS is in charge of V1 conduction, that is -Vout×R3 / (R2+R3)<V TP =V TP(MAX) =-2.5V; and protect V1 tube from overvoltage -Vout×R3 / (R2+R3)>-|V GS(MAX) If VCC = 12V, R1 = R2 = 100kΩ, then 28.409kΩ < R3 < 242.424kΩ. Diode D2 provides reverse protection, preventing breakdown of the base and emitter of PNP transistor V3.

[0053] Preferably, when the input power supply VCC is less than the output power supply Vout, the V2 tube and the D1 tube are turned off, the V3 tube and the D2 tube are turned on, and the comparator outputs the comparison signal VB as a high level, VB = Vout - V3 EC(sat) ≈Vout(V3 EC(sat) is the saturation conduction voltage drop of V3 tube, V3 EC(sat) <0.3V), that is, the gate VB of the PMOS V1 is high, V1 GS ≈0V, the PMOS tube V1 is cut off, protecting the gate and source voltage difference of the PMOS tube V1 from exceeding the voltage; the voltage regulator diode D1 reversely protects the base and emitter of the PNP tube V2 from being broken down.

[0054] Implementation Method 3

[0055] A high-end ideal diode with high reverse voltage resistance, in embodiment 1 Figure 2The circuit is improved by replacing the resistor R3 with the voltage stabilizing diode D3, and the rest remain unchanged, such as Figure 4 As shown, it includes a PMOS supervisor V1, a comparator circuit, a protection circuit, etc.

[0056] Preferably, compared with the first embodiment, due to the use of diodes D1 and D2, it is generally required that the reverse voltage withstand value of diode D1 is higher than the maximum value of Vout, the reverse voltage withstand value of diode D2 is higher than the maximum value of VCC, and the voltage stabilizing value of voltage stabilizing diode D3 is V Z <|V GS(MAX) |.

[0057] Preferably, when the input power supply VCC is not less than the output power supply Vout, VCC>V Z >|V TP(MAX) |, V2 and D1 are turned on, V3 and D2 are turned off, and the comparator outputs the comparison signal VB at a low level, VB≈VCC-V Z , that is, the gate VB of the PMOS V1 is low, V1 GS =VB-Vout=-V Z <V TP(MAX) , the PMOS tube V1 is turned on; the diode D2 reversely protects the base and emitter of the PNP tube V3 from breakdown; the resistor R2 and the voltage-stabilizing diode D3 form a fixed voltage divider circuit, and the maximum value of the gate-source voltage difference of V1 is |V GS(MAX) |Greater than the breakdown voltage V Z , protecting the gate and source voltage difference of PMOS V1 from overvoltage. The breakdown voltage of Zener diode D3 is V Z , satisfying V Z <|V GS(MAX) |, such as |V GS(MAX) |=8V, you can use V Z =7.5V Zener diode.

[0058] Preferably, when the input power supply VCC is less than the output power supply Vout, the V2 tube and the D1 tube are turned off, the V3 tube and the D2 tube are turned on, and the comparator outputs the comparison signal VB as a high level, VB = Vout - V3 EC(sat) ≈Vout(V3 EC(sat) is the saturation conduction voltage drop of V3 tube, V3 EC(sat) <0.3V), that is, the gate VB of the PMOS V1 is high, V1 GS ≈0V, the PMOS transistor V1 is cut off; the diode D1 reversely protects the base and emitter of the PNP transistor V2 from breakdown.

[0059] according to Figures 2 to 4The circuit schematic was simulated using National Instruments' Multisim (version V14.0). The PMOS tube was NVTFS5124PLTAG from ON Semiconductor, with a minimum on-threshold voltage of V TP(MIN) =-1.5V, maximum V TP(MAX) =-2.5V, typical value V not given TP , the on-state current can reach -6A, the on-state resistance R DS(ON) =0.26Ω(V GS =-10V), R DS(ON) =0.38Ω(V GS =-4.5V); the diode is a Motorola device, model 1N3492 (with a reverse voltage of 100V); the load resistor RL = 10Ω, R3 = 180kΩ, and the specific simulation test is as follows.

[0060] Implementation Method 1 Simulation

[0061] DC power supply forward bias simulation test (when the input power supply VCC is not less than the output power supply Vout): VCC = VCC1 = 12V (switch J1 is closed, switch J2 is open): V2 tube is turned on, V3 tube is cut off, and the comparator output comparison signal VB is low level (relative to VCC). The theoretical value VB = 12.0V × 100k / (180k + 100k) = 4.28V, which is not much different from the simulation test value VB = 4.20V (test point PR6). The simulation test is as follows: Figure 5 As shown, the PMOS V1 is turned on, and the gate-source voltage difference between the PMOS V1 is V1 GS =VB-Vout=4.20V-11.7V=-7.5V>-|V GS(MAX) |=-8V, the gate-source voltage difference of the PMOS transistor V1 meets the requirement, and the PMOS transistor V1 is not damaged; the diode D2 can withstand a large reverse voltage and protect the base and emitter of the PNP transistor V3 from damage. When forward conducting, the output power supply Vout of the PMOS transistor V1 is 11.7V (test point PR2), and the conduction voltage drop of the PMOS transistor V1 is 12V-11.7V=0.3V, which is lower than the conduction voltage drop of the diode V F , the positive output current of the power supply is 1.17A (test points PR1 and PR3), corresponding to the drain-source channel on-resistance R DS(ON) =0.3V / 1.17A=0.256Ω, which is not much different from the datasheet data.

[0062] DC power supply reverse bias simulation test (input power supply VCC is less than output power supply Vout): After switch J1 is closed, switch J2 is also closed. Assuming the maximum reverse voltage Vout = 30V > VCC = 12V: V3 tube is turned on and V2 tube is turned off. The output comparison signal VB of the comparator is Vout-V3. EC(sat) ≈29.8V, which is not much different from the simulation test value VB=29.9V (test point PR6). Figure 6 As shown, the gate VB of the PMOS V1 is high, and the PMOS V1 is cut off to prevent the Vout current from flowing back to VCC, thus protecting the VCC power supply front-stage circuit; the gate-source voltage difference V1 of the PMOS V1 is GS =29.9V-30V=-0.1V>-|V GS(MAX) | = -8V. The gate-source voltage difference of the PMOS transistor V1 meets the requirement, and the PMOS transistor V1 is not damaged. Diode D1 can withstand a large reverse voltage (greater than VCC2), protecting the base and emitter of the PNP transistor V2. The reverse current flowing through the PMOS transistor is -355nA (test point PR1, which is negligible), indicating no reverse current. The output current of power supply VCC1 is -355nA (test point PR5, which is negligible).

[0063] Implementation Method 2 Simulation

[0064] DC power supply forward bias simulation test (when the input power supply VCC is not less than the output power supply Vout), R1 = R2 = 100kΩ, R3 = 180kΩ, R4 = R5 = 1kΩ: VCC = VCC1 = 12V (switch J1 is closed, switch J2 is open): V2 tube is turned on, V3 tube is cut off, and the comparator outputs the comparison signal VB as a low level (relative to VCC). The theoretical value VB = 12.0V × 100k / (180k + 100k) = 4.28V, which is not much different from the simulation test value VB = 4.36V (test point PR6). The simulation test is as follows: Figure 7 As shown, the PMOS V1 is turned on, and the gate-source voltage difference between the PMOS V1 is V1 GS =VB-Vout=4.31V-11.7V=-7.39V>-|V GS(MAX) |=-8V, the gate-source voltage difference of the PMOS transistor V1 meets the requirement, and the PMOS transistor V1 is not damaged; the diode D2 can withstand a large reverse voltage and protect the base and emitter of the PNP transistor V3 from damage. When forward conducting, the output power supply Vout of the PMOS transistor V1 is 11.7V (test point PR2), and the conduction voltage drop of the PMOS transistor V1 is 12V-11.7V=0.3V, which is lower than the conduction voltage drop of the diode V F, the positive output current of the power supply is 1.17A (test points PR1 and PR3), corresponding to the drain-source channel on-resistance R DS(ON) =0.3V / 1.17A=0.256Ω, which is not much different from the datasheet data.

[0065] DC power supply reverse bias simulation test (input power supply VCC is less than output power supply Vout): After switch J1 is closed, switch J2 is also closed. Assuming the maximum reverse voltage Vout = 30V > VCC = 12V: V3 tube is turned on and V2 tube is turned off. The output comparison signal VB of the comparator is Vout-V3. EC(sat) ≈29.8V, which is not much different from the simulation test value VB=29.4V (test point PR6). Figure 8 As shown, the gate VB of the PMOS V1 is high, and the PMOS V1 is cut off to prevent the Vout current from flowing back to VCC, thus protecting the VCC power supply front-stage circuit; the gate-source voltage difference V1 of the PMOS V1 is GS =29.4V-30V=-0.6V>-|V GS(MAX) | = -8V. The gate-source voltage difference of the PMOS transistor V1 meets the requirement, and the PMOS transistor V1 is not damaged. Zener diode D1 and resistor R4 operate in the reverse voltage range. As long as the reverse voltage of Zener diode D1 (greater than VCC2) is greater than VCC2, they can protect the base and emitter of the PNP transistor V2 from damage. The reverse current of the PMOS transistor is -355nA (test point PR1, which is negligible), and it can be assumed that there is no backflow current. The output current of power supply VCC1 is -355nA (test point PR5, which is negligible).

[0066] Implementation Method 3 Simulation

[0067] DC power supply forward bias simulation test (when the input power supply VCC is not less than the output power supply Vout): VCC = VCC1 = 12V (switch J1 is closed, switch J2 is open): V2 tube is turned on, V3 tube is cut off, and the comparator outputs the comparison signal VB as a low level (relative to VCC). The theoretical value VB = Vout-Vz = 12V-7.5V = 4.5V, which is not much different from the simulation test value VB = 4.31V (test point PR6). The simulation test is as follows: Figure 9 As shown, the gate level of the PMOS V1 is 4.31V, the PMOS V1 is turned on, and the gate-source voltage difference of the PMOS V1 is V1. GS =4.31V-12V=-7.69V>-|V GS(MAX)|=-8V, the gate-source voltage difference of the PMOS transistor V1 meets the requirement, and the PMOS transistor V1 is not damaged; the diode D2 can withstand a large reverse voltage and protect the base and emitter of the PNP transistor V3 from damage. When forward conducting, the output power supply Vout of the PMOS transistor V1 is 11.7V (test point PR2), and the conduction voltage drop of the PMOS transistor V1 is 12V-11.7V=0.3V, which is lower than the conduction voltage drop of the diode V F , the positive output current of the power supply is 1.17A (test points PR1 and PR3), corresponding to the on-resistance R DS =0.3V / 1.17A=0.256Ω, which is not much different from the datasheet data.

[0068] DC power supply reverse bias simulation test (input power supply VCC is less than output power supply Vout): After switch J1 is closed, switch J2 is also closed. Assuming the maximum reverse voltage Vout = 30V > VCC = 12V: V3 tube is turned on and V2 tube is turned off. The output comparison signal VB of the comparator is Vout-V3. EC(sat) ≈29.8V, which is not much different from the simulation test value VB=29.9V (test point PR6). Figure 10 As shown, the gate VB of the PMOS V1 is high, and the PMOS V1 is cut off to prevent the Vout current from flowing back to VCC, thus protecting the VCC power supply front-stage circuit; the gate-source voltage difference V1 of the PMOS V1 is GS =29.9V-30V=-0.1V>-|V GS(MAX) | = -8V. The gate-source voltage difference of the PMOS transistor V1 meets the requirement, and the PMOS transistor V1 is not damaged. Diode D1 can withstand a large reverse voltage (greater than VCC2), protecting the base and emitter of the PNP transistor V2. The reverse current flowing through the PMOS transistor is -355nA (test point PR1, which is negligible), indicating no reverse current. The output current of power supply VCC1 is -355nA (test point PR5, which is negligible).

[0069] The beneficial effects of the present invention are: Figure 1 The circuit is improved on the basis of the back-end controlled high-end ideal diode composed of (PNP pair tube + PMOS main tube technical solution), and three high-end ideal diodes with high reverse voltage resistance are designed by using resistor voltage divider and Zener diode fixed voltage divider circuit. The value range of the circuit voltage divider resistor is theoretically derived and the three circuits are simulated by software. The simulation results show that the three circuits have the functions of preventing backflow and withstanding high reverse voltage, which can protect the previous stage circuit; using high-end load switch and comparator, the circuit is very simple and has a very low cost advantage.

[0070] The above describes in detail the preferred embodiments of the present invention. It should be understood that those skilled in the art can make numerous modifications and variations based on the concepts of the present invention without inventive effort. Therefore, any technical solutions that can be derived by those skilled in the art through logical analysis, reasoning, or limited experimentation based on the concepts of the present invention and the prior art should be within the scope of protection defined by the claims.

Claims

1. A high-end ideal diode capable of withstanding high reverse voltage, characterized in that: The circuit includes a PMOS main body V1, a comparator circuit, a protection circuit and a power supply VCC, and the protection circuit is used to protect the comparator circuit; The comparator circuit includes two independent or identically parametered transistors, a diode pair, and a resistor packaged together. The drain of the PMOS main tube V1 is connected to the power supply VCC, and the source is connected to the output power supply Vout. The comparator circuit compares the power supply VCC with the output power supply Vout and outputs a comparison signal to the gate of the PMOS tube V1 to control the on and off of the PMOS tube V1.

2. The high-end ideal diode with high reverse voltage resistance according to claim 1, wherein: The comparator circuit includes PNP auxiliary tubes V2 and V3, and resistors R1 and R2; The emitter of the PNP auxiliary tube V2 is connected to the power supply VCC, the collector is grounded through the resistor R1, the base is connected to the collector, and the base is connected to the base of the PNP auxiliary tube V3; The emitter of the PNP auxiliary tube V3 is connected to the output power supply Vout, the collector is grounded via the resistor R2, and the collector is also connected to the gate of the PMOS main tube V1.

3. The high-side ideal diode with high reverse voltage resistance according to claim 2, wherein: The protection circuit includes a diode pair D1 and D2 connected to the bases of the PNP auxiliary tubes V2 and V3 respectively. The cathodes of the diode pair D1 and D2 are connected to each other, and the anodes are connected to the bases of the PNP auxiliary tubes V2 and V3 respectively.

4. The high-end ideal diode with high reverse voltage resistance according to claim 2, wherein: The protection circuit includes a pair of voltage-stabilizing diodes D1 and D2, and resistors R4 and R5; The cathodes of the voltage-stabilizing diodes D1 and D2 are connected, and the anodes are connected to the bases of the PNP auxiliary tubes V2 and V3 respectively. The resistor R4 is connected between the power supply VCC and the emitter of the PNP auxiliary tube V2. The resistor R5 is connected between the output power supply Vout and the emitter of the PNP auxiliary tube V3.

5. A high-end ideal diode with high reverse voltage resistance according to claim 3 or 4, characterized in that: The protection circuit further includes an overvoltage protector for protecting the PMOS main body V1 , wherein the overvoltage protector is connected between a source and a gate of the PMOS main body V1 .

6. The high-side ideal diode with high reverse voltage resistance according to claim 5, wherein: The overvoltage protector is either a resistor R3 or a voltage stabilizing diode.

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