Method and application of preparing two-dimensional semiconductor single crystal metal contacts by atomic-level layer-by-layer evaporation

Abstract

This invention discloses a method and application for preparing single-crystal metal contacts for two-dimensional semiconductors by atomic-level layer-by-layer evaporation. This method, which relates to the field of contact engineering for two-dimensional semiconductor transistors, successfully produces single-crystal metals on atomically smooth two-dimensional semiconductors through van der Waals (vdW) epitaxy, compared to traditional continuous evaporation. This method is used to improve the gold-semiconductor contacts of transistors and enhance overall transistor performance. This method utilizes an industrially compatible step-by-step evaporation process to in-situ deposit single-crystal metals such as bismuth (Bi), silver (Ag), and indium (In) onto a single layer of two-dimensional semiconductor (such as MoS2 or WSe2). Utilizing a low dose of approximately 0.5 nm per step and ultra-stable deposition conditions, this method minimizes the physical damage caused by "high-energy" deposition, inhibits disordered grain growth, and enables free atomic migration and uniform nucleation, followed by layer-by-layer van der Waals epitaxy into single crystals.

Description

Technical Field

[0001] The present invention belongs to the field of two-dimensional semiconductor transistor contact engineering, and specifically relates to a method and application of preparing two-dimensional semiconductor single crystal metal contacts by atomic-level layer-by-layer evaporation. Background Art

[0002] Two-dimensional semiconductors, due to their atomic-scale thickness and lack of dangling bonds on their surfaces, are considered ideal candidate materials for breaking through the physical limitations of traditional silicon-based devices and realizing high-performance electronic devices in the "post-Moore era." However, their actual performance is limited by the non-ideal contact problem at the metal-semiconductor interface. Traditional physical vapor deposition techniques (such as thermal evaporation and magnetron sputtering) deposit polycrystalline metals through high-energy processes, which lead to thermal stress, lattice damage, and chemical disorder at the interface, causing severe Fermi level pinning and high contact resistance, limiting device performance. Although methods such as molecular beam epitaxy and chemical vapor deposition are available for growing single-crystalline metals, high temperatures or lattice matching limit their application in two-dimensional materials. There is an urgent need for an industrially compatible metal deposition technology that can precisely control the crystal structure and interface cleanliness.

[0003] This paper proposes an innovative atomic-scale layer-by-layer evaporation technique. Through step-by-step deposition (0.5 nm per step) and an ultra-stable growth temperature and pressure environment, single-crystalline metals (single-crystalline Bi, single-crystalline Ag, and single-crystalline In) are grown in situ on the surface of a monolayer two-dimensional semiconductor (such as MoS2 or WSe2). This method circumvents traditional high-energy physics damage and utilizes the van der Waals epitaxy mechanism to achieve uniform nucleation and layer-by-layer assembly of metal atoms, forming a grain-boundary-free, defect-free, atomically flat van der Waals metal-semiconductor interface. Experimental results show that the single-crystalline contact significantly suppresses the Fermi level pinning effect and significantly reduces the contact resistance to near the quantum limit, enabling high-performance monolayer MoS2 transistors. Furthermore, the thermal stability of the single-crystalline metal is significantly improved, and the temperature limit of devices with single-crystalline Bi contacts far exceeds their melting point, providing a breakthrough solution for the industrial application of two-dimensional electronic devices. Summary of the Invention

[0004] The present invention proposes a method and application for preparing two-dimensional semiconductor single crystal metal contacts by atomic-level layer-by-layer evaporation. Through discrete evaporation-relaxation cycles, the physical damage of traditional high-energy processes is avoided, and the van der Waals epitaxial mechanism is used to achieve uniform nucleation and layer-by-layer assembly of metal atoms. Long-range ordered single crystal metals are successfully grown in situ on the surface of a single-layer two-dimensional semiconductor (such as MoS2, WSe2), forming an ideal van der Waals contact interface.

[0005] The technical solution of the present invention is as follows:

[0006] A method for preparing two-dimensional semiconductor single crystal metal contacts by atomic-level layer-by-layer evaporation includes the following steps:

[0007] 1) Preparation of 2D material substrates

[0008] Large-area monolayer MoS2 is synthesized on SiO2 / Si substrates via chemical vapor deposition, or single-layer or multi-layer 2D materials are obtained from bulk materials through mechanical exfoliation. Chemical vapor deposition achieves uniform 2D material growth in an inert gas atmosphere by precisely controlling the precursor distribution and reaction temperature gradient. Mechanical exfoliation utilizes a viscous medium (PDMS) to separate the bulk material layer by layer, ultimately yielding high-quality single-layer or multi-layer 2D materials on the target substrate.

[0009] 2) Preparation of single crystal metals by atomic-level layer-by-layer evaporation process

[0010] The 2D material substrate is placed in a high-vacuum thermal evaporation chamber, where metal is deposited layer by layer using an intermittent "evaporation-relaxation" cycle. Each stage deposits only a 0.5nm layer of metal (approximately one atomic layer), followed by a 5-minute pause to allow the chamber temperature and pressure to return to near-initial stable states. This prevents the thermal effects and thermal stress accumulation caused by continuous evaporation, which can lead to disordered grain growth and undesirable interfaces that damage the 2D material. This process, through an ultra-low deposition rate and a stable evaporation environment, promotes the free migration of metal atoms and, following the van der Waals epitaxial mechanism, forms a long-range ordered single crystal structure on the 2D material surface, ultimately achieving an atomically flat and defect-free metal-semiconductor interface.

[0011] Beneficial effects:

[0012] 1) Atomic-level layer-by-layer evaporation technology is used to prepare single-crystal metals to achieve ideal van der Waals metal-semiconductor junctions

[0013] The atomic-level layer-by-layer evaporation process proposed in this invention can achieve low-energy injection damage and high-crystalline quality single-crystal metal van der Waals epitaxial growth on the surface of a single-layer two-dimensional semiconductor. By discretizing the metal deposition process, controlling each step to approximately 0.5nm, and setting a relaxation time after each deposition, thermal stress is effectively released, disordered grain growth is suppressed, and metal atoms are allowed to spontaneously migrate and uniformly nucleate on the surface of the two-dimensional material, forming a single crystal structure layer by layer. The resulting metal-semiconductor interface is an ideal van der Waals interface with atomically flat and long-range order, no chemical bond coupling, and no interface defects. It significantly suppresses the Fermi level pinning effect, reduces the Schottky barrier, and is expected to achieve an ideal ohmic contact.

[0014] 2) Atomic-level layer-by-layer evaporation technology is universal

[0015] The atomic-level layer-by-layer evaporation process described in this invention is applicable to a variety of metals (such as Bi, Ag, and In) and a variety of two-dimensional semiconductor materials (such as MoS2 and WSe2). It does not rely on lattice matching or covalent bonding, thus overcoming the substrate limitations of traditional epitaxial growth. The process achieves single-crystal structures and clean interfaces across a wide range of material systems, demonstrating broad versatility and scalability.

[0016] 3) Comply with the Schottky-Mott rule

[0017] The single-crystal metals produced by the atomic-level layer-by-layer evaporation process described in this invention possess a stable and standardized work function. Transistors in contact with MoS2 exhibit a clear linear correlation between the Schottky barrier and the work function (pinning factor S = 0.97), approaching the Schottky-Mott limit. By selecting single-crystal metals with different work functions, precise control of the device's n-type or p-type transmission characteristics can be achieved.

[0018] 4) Ultra-high performance MoS2 transistors based on single-crystal Bi contacts

[0019] MoS2 transistor devices using single-crystal Bi contacts achieve ultra-low contact resistance, high mobility, high on-off ratio, and high on-state current, demonstrating excellent electrical performance. Furthermore, the device exhibits excellent thermal stability, meeting the thermal budget requirements of advanced back-end interconnect processes. This provides key support for the large-scale integration and industrial application of two-dimensional electronic devices, marking a substantial step forward in the engineering of two-dimensional semiconductor contacts. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 : Polycrystalline Bi / MoS2 interface prepared by traditional continuous evaporation process.

[0021] Figure 2 : Single crystal Bi / MoS2 interface prepared by atomic-level layer-by-layer evaporation process.

[0022] Figure 3 : Size and orientation of single crystal Bi.

[0023] Figure 4 : Universal applicability of atomic-level layer-by-layer evaporation process in metals and two-dimensional semiconductors.

[0024] Figure 5 : Comparative statistics of work functions of single crystal metals and polycrystalline metals.

[0025] Figure 6 : Statistics of Schottky barriers in contacts between MoS2 and various single crystal metals.

[0026] Figure 7 : Transfer characteristic curves of single-crystal Bi-MoS2 transistors.

[0027] Figure 8 : Extraction of contact resistance of single crystal Bi-MoS2 transistors.

[0028] Figure 9 : Temperature dependence of mobility of single-crystal Bi-MoS2 transistors.

[0029] Figure 10: Schottky barrier heights of single-crystal Bi and polycrystalline Cr contact devices.

[0030] Figure 11 : Ultrashort channel Bi-MoS2 transistor.

[0031] Figure 12 : Thermal stability test of Bi / MoS2 transistor. DETAILED DESCRIPTION

[0032] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. However, the following embodiments are intended only to explain the present invention, and the scope of protection of the present invention should include the entire contents of the claims. Moreover, through the description of the following embodiments, those skilled in the art can fully implement the entire contents of the claims of the present invention.

[0033] Example

[0034] This embodiment provides a vapor deposition process for preparing high-quality single-crystal metal. The specific preparation steps are as follows (taking semi-metal Bi as an example):

[0035] 1. Preparation of single crystal metals using atomic-level layer-by-layer evaporation technology

[0036] The specific steps are as follows:

[0037] 1) Synthesis of large-area monolayer MoS2 by chemical vapor deposition and mechanical exfoliation to prepare single-layer and multilayer two-dimensional materials

[0038] A Si / SiO2 substrate (285nm SiO2) was placed in a horizontal hot mantel. A quartz boat containing 150mg of S powder was placed at the front of the tube, and a quartz boat containing 50mg of MoO3 powder and 5mg of NaCl was placed at the center of the heating chamber, heated to 680°C. The substrate was placed at the center of another downstream heating chamber, heated to 850°C. Argon was introduced into the quartz tube as a carrier gas at a flow rate of 300sccm. Using this method, large-area MoS2 monolayers were well grown on the pre-placed substrate.

[0039] The mechanical stripping method is to place a block of two-dimensional material on tape, repeatedly stick and peel the block material, and then stick the tape on a flat PDMS film (corresponding to the material area on the tape). After removing the tape, stick the target substrate (silicon wafer) on the PDMS film covered with two-dimensional material. After a period of time, remove it and look for single-layer or multi-layer two-dimensional materials on the silicon wafer under an optical microscope.

[0040] 2) Atomic-level layer-by-layer evaporation device and process parameters

[0041] The preparation of single crystal metal is done by using thermal evaporation equipment, adopting an intermittent step-by-step evaporation process. Specifically, only 0.5nm of metal is evaporated in each step, and then the evaporation is paused for 5 minutes to minimize the pressure and temperature in the cavity, ensuring that the metal is deposited in a constant temperature and pressure environment (such as Figure 1 and Figure 2 (As shown, a comparison between traditional continuous evaporation and atomic-level layer-by-layer evaporation processes). This low-dose, ultra-stable deposition minimizes physical damage caused by deposition and allows the evaporated metal to form a single crystal structure according to the van der Waals epitaxial mode, forming an ideal metal-semiconductor interface. Taking Bi as an example, for our device, after evaporating 0.5nm of Bi, the temperature and pressure in the chamber increased from 17°C to 19.3°C, and the pressure increased from 0.85×10 -5 Pa rises to 9.1×10 -5 After pausing for 5 minutes, these two parameters gradually recovered to the stable values ​​close to the initial values ​​of 18°C ​​and 0.85×10 -5 Pa, repeat the above steps until the target metal thickness is reached.

[0042] 2. Characterization of Single Crystal Metals

[0043] In order to clarify the crystalline quality of the prepared metal film and its contact interface with the single-layer MoS2, the present invention uses a variety of high-resolution structural characterization techniques such as scanning transmission electron microscopy, electron backscatter diffraction and selected area electron diffraction to systematically analyze the Bi metal film deposited by the atomic-level layer-by-layer evaporation process. The scanning transmission electron microscope image clearly shows that Bi atoms grow a long-range ordered single crystal structure on the surface of the single-layer MoS2 and are in close contact with MoS2, forming a sharp and clean metal-semiconductor interface, confirming that the single-crystalline Bi / MoS2 interface is an ideal van der Waals contact interface (such as Figure 2 As shown). The selected area electron diffraction pattern confirms that the single crystal Bi grows along the

[0001] direction, follows the thermodynamic principle, and preferentially grows along the lowest energy surface. The large-scale atomic structure images in the horizontal and vertical directions together show that the metal Bi achieves uniform and isotropic epitaxial growth on the MoS2 substrate, forming a complete and continuous single crystal structure. In addition, the electron backscattered diffraction pattern of the metal grown on a large area monolayer MoS2 shows that the average crystal domain size exceeds 30μm, the crystal domain orientation is highly consistent, is not limited by area, and can be extended to infinity (such as Figure 3 These results clearly demonstrate that the atomic-level layer-by-layer evaporation process can achieve atomically flat and high-quality single-crystalline metals on the surface of two-dimensional materials, and is a key technical means to achieve high-quality metal-semiconductor contact interfaces.

[0044] 3. Verification of the universality of atomic-level layer-by-layer evaporation technology

[0045] The atomic-level layer-by-layer evaporation process has good universality and scalability and can be applied to a variety of metal and two-dimensional semiconductor materials (such as Figure 4 As shown, the process is universal. Large-scale scanning transmission electron microscopy images in the horizontal and vertical directions confirm that single-crystalline Ag and single-crystalline In can also be successfully prepared on single-layer MoS2, forming an ideal van der Waals metal-semiconductor interface. However, some metal oxidation was observed at the In / MoS2 interface. This is due to the intercalation oxidation of water and oxygen in the van der Waals gap of In-MoS2 during the sample preparation process, further indicating that the single-crystalline In / MoS2 interface is dominated by van der Waals interactions rather than strong covalent bonds. In addition, the atomic-level layer-by-layer evaporation process is compatible with various two-dimensional materials and is not restricted by lattice matching; for example, single-crystalline Bi can also be grown on single-layer WSe2, and the preferred growth direction is also along the

[0001] direction, confirming that the (0001) plane is the lowest energy plane of single-crystalline Bi.

[0046] 4. Standard work function accurately controls Schottky barrier height

[0047] The single crystal metal prepared by the atomic-level layer-by-layer evaporation process in the present invention has a highly consistent crystal orientation, thereby showing standardized work function characteristics (such as Figure 5 As shown in Figure 2, the work function of single crystal and polycrystalline metals is compared. For example, single crystal Bi grows along the

[0001] plane, and its corresponding work function is 3.98 eV, which is very consistent with the conduction band of monolayer MoS2. Since Bi is a semi-metal, its state density near the Fermi level is extremely low, which can effectively weaken the metal-induced gap state, thereby suppressing the Fermi level pinning effect (e.g., Figure 6 Schottky barrier statistics are shown in Figure 2. Further research has shown that when single-crystal metals with different work functions (such as In, Ag, Au, and Pd) are used in contact with MoS2, the Schottky barrier height of the device exhibits a highly linear correlation with the metal work function, with the resulting pinning factor (S) reaching as high as 0.97, approaching the Schottky-Mott limit. This result demonstrates that single-crystal metal contacts grown using an atomic-level layer-by-layer evaporation process can precisely control the Schottky barrier, providing a solid foundation for building low-power, high-performance devices.

[0048] 5. Fabrication and electrical performance characterization of ultra-low contact resistance field-effect transistors

[0049] 1) Preparation of single crystal Bi-MoS2 field effect transistor:

[0050] In this invention, the fabrication process of a single-crystal Bi-MoS2 field-effect transistor involves patterning the two-dimensional semiconductor MoS2 and constructing high-quality single-crystal metal source and drain electrodes. First, a large-area monolayer MoS2 thin film is synthesized on a SiO2 / Si substrate using chemical vapor deposition. Reactive ion etching (RIE) then patterns the thin film into a rectangular active area with fixed geometric dimensions. Polymethyl methacrylate (PMMA) is then spin-coated uniformly on the substrate surface (spin coating parameters: 500 rpm for 5 seconds; 4000 rpm for 40 seconds). The photoresist layer is then baked on a 150°C hotplate for 5 minutes to cure the photoresist. Electron beam lithography (EBL) is used to precisely define the source and drain electrode patterns at both ends of the rectangular MoS2 active area. The metal electrodes are deposited using atomic-level layer-by-layer evaporation, sequentially depositing a 20nm thick Bi layer and a 20nm thick Au protective layer to achieve single-crystal metal source and drain electrodes with a long-range ordered structure. Finally, the photoresist is removed by immersion in acetone followed by rinsing with isopropyl alcohol, achieving pattern lift-off and completing the device fabrication. This process can effectively ensure the formation of an atomically clean and flat van der Waals contact interface between metal and two-dimensional semiconductor, and is a key step in achieving high-performance, low-contact resistance single-crystal metal contact devices.

[0051] 2) Transfer characteristic curve test

[0052] MoS2 transistors with single-crystal Bi contacts exhibit excellent n-type field-effect device properties (e.g. Figure 7 As shown). At source-drain bias V DS = 1V, the on / off ratio is as high as 2.9 × 10 10 , significantly outperforming single-layer MoS2 devices using polycrystalline Bi or polycrystalline Cr contacts, by approximately 2 and 3 orders of magnitude, respectively. Furthermore, the device exhibits highly linear output characteristics at room temperature, with an on-state current of 56μA / μm, 56 times that of devices with Cr contacts and 4.67 times that of devices with polycrystalline Bi contacts. These results demonstrate that an ideal ohmic contact with low potential barriers and efficient carrier injection is formed between single-crystalline Bi and MoS2, providing key support for the realization of high-performance, low-power two-dimensional semiconductor devices.

[0053] 3) Extracting contact resistance using the transmission line method

[0054] In order to accurately evaluate the contact quality of the device, the present invention uses the transmission line method to extract and analyze the contact resistance (such as Figure 8(As shown). In the high-dielectric-constant SiNx dielectric, the contact resistance is as low as 35Ω·μm, approaching its theoretical limit (28Ω·μm). This performance is at the forefront of currently reported two-dimensional semiconductor contact technologies, significantly outperforming various advanced contact strategies including polycrystalline Bi, semi-metallic Sb contacts, phase change engineering, electrode metal transfer, and low-melting-point metal evaporation. This demonstrates the unique advantage of the single-crystal metal contact of this invention in achieving low-resistance and high-efficiency electron injection.

[0055] 4) Temperature dependence of mobility

[0056] Single-crystal Bi / MoS2 transistors exhibit excellent electron mobility (88 cm 2 ·V -1 ·s -1 ), the mobility is further increased to 253cm at low temperature (77K) 2 ·V -1 ·s -1 (like Figure 9 Temperature dependence analysis shows that in the high temperature region the mobility follows μ∝T -1.5 The scattering behavior of the single-crystal Bi and MoS2 indicates that the mobility is mainly dominated by optical phonon scattering. In the low-temperature region, the mobility approaches the saturation value, indicating that the device is close to the scattering limit. These results fully demonstrate that a high-quality van der Waals contact interface is formed between the single-crystal Bi and MoS2, effectively suppressing interface defects and impurity scattering, thereby achieving efficient electron injection and excellent carrier transport performance.

[0057] 5) Comparative test of Schottky barrier height

[0058] Schottky barrier height (Φ B ) is extracted by fitting the Arrhenius curve under varying temperatures (e.g. Figure 10 As shown). The results show that the single crystal Bi contact device exhibits zero Schottky barrier characteristics, indicating that an ideal ohmic contact is formed between single crystal Bi and monolayer MoS2. This is mainly attributed to two aspects: (1) Single crystal Bi has semi-metallic properties, and the density of states at the Fermi level is close to zero. Combined with its standard work function value (3.98eV), it is very well matched with the conduction band of monolayer MoS2, resulting in saturation of the metal-induced gap state; (2) Single crystal Bi realizes an atomically neat, ordered and clean van der Waals contact interface on the surface of a two-dimensional semiconductor through an atomic-level layer-by-layer evaporation process. The interface defect state density is extremely low, which effectively suppresses the Fermi level pinning effect. In contrast, polycrystalline Cr contact exhibits a higher Schottky barrier due to its mismatched metal work function value, non-ideal interface, numerous gap states and stronger Fermi level pinning. This comparison further verifies the unique advantages and industrial value of the single crystal metal electrode used in the present invention in constructing a low barrier and ideal contact interface.

[0059] 6) Ultra-short channel device performance test

[0060] In order to verify the current driving capability of the device at the extreme scale, the present invention prepared a transistor with a channel length of 50nm (such as Figure 11 (As shown). Under drain bias conditions of 2.5V and 1.5V, the maximum on-state currents were measured to be 1.93mA / μm and 1.36mA / μm, respectively, successfully realizing a quasi-ballistic transport device. These results demonstrate that even at sub-100nm scales, single-crystal Bi electrodes fabricated using an atomic-level layer-by-layer evaporation process can maintain extremely low contact resistance and excellent carrier injection efficiency, providing strong support for the realization of high-performance, ultra-short-channel two-dimensional semiconductor devices.

[0061] 7) Thermal stability comparison test

[0062] The results of thermal stability test showed that ( Figure 12 As shown in Figure 3 ), devices using single-crystal Bi contacts exhibit excellent thermal stability in high-temperature environments, with a maximum operating temperature of up to 690K, significantly higher than Bi's intrinsic melting point (544.5K). Devices using polycrystalline Bi contacts have a temperature limit of only 480K. This exceptional thermal stability is attributed to the highly ordered and dense atomic arrangement in the single-crystal structure, which effectively suppresses the metal's diffusion behavior and interface degradation at high temperatures. The single-crystal metal contact solution proposed in this invention not only fully meets the thermal budget requirements of advanced integrated circuit back-end interconnect processes, but also lays a key technical foundation for the stable operation and large-scale integration of two-dimensional material devices in high-temperature applications.

[0063] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the broadest scope consistent with the principles and novel features of the present application.

Claims

1. A method for preparing two-dimensional semiconductor single crystal metal contacts by atomic-level layer-by-layer evaporation, characterized in that: The following steps are involved: (1) Preparation of two-dimensional semiconductor substrates: obtaining single-layer or multi-layer two-dimensional semiconductor materials on Si / SiO2 substrates by chemical vapor deposition or mechanical exfoliation; (2) placing the substrate in a high vacuum thermal evaporation chamber; (3) Depositing the target metal using a step-by-step evaporation process with a deposition thickness of 0.5 nm per step. After each step, a 5-minute pause was performed to restore the chamber temperature and pressure to their initial stable state. (4) Repeat step (3) until the metal layer reaches the target thickness, forming a long-range ordered single crystal metal film and forming an atomically flat van der Waals contact interface with the two-dimensional semiconductor.

2. The method according to claim 1, characterized in that The two-dimensional semiconductor is MoS2 or WSe2, and the single crystal metal is Bi, Ag or In.

3. The method according to claim 1, characterized in that The deposition rate of the step-by-step evaporation process is 0.1 nm / s, and the initial vacuum degree of the chamber is ≈8.5×10 -5 Pa, temperature fluctuation range ≤±2℃.

4. The method according to claim 1, wherein The work function of the single crystal metal film is consistent with that of its bulk single crystal and matches the energy band of the two-dimensional semiconductor, thereby achieving a linear correlation between the Schottky barrier height and the metal work function.

5. The method according to claim 1, wherein The van der Waals contact interface has the following characteristics: Contact resistance ≤35Ω·μm, close to the quantum limit; Thermal stability ≥690K, higher than the melting point of single crystal metal.

6. The method according to claim 1, characterized in that The crystal domain size of the single crystal metal film is greater than or equal to 30 μm, and the crystal orientation grows along the [0001] direction.

7. The method according to claim 1, characterized in that The method is suitable for regulating the n-type or p-type electrical properties of MoS2 by selecting a single crystal metal with matching work function.

8. Use of the method according to claim 1 in preparing a two-dimensional semiconductor transistor with single crystal metal contacts, characterized in that: include: Single-layer MoS2 active region; Single crystal metal source and drain electrodes deposited by atomic-level layer-by-layer evaporation process; The transistor has a switching ratio of ≥2.9×10 10 , on-state current ≥56 μA / μm, electron mobility ≥88cm 2 ·V -1 ·s -1 .

9. The use according to claim 8, characterized in that Its ultra-short channel device has an on-state current of ≥1.93mA / μm at a drain bias of 2.5 V, exhibiting quasi-ballistic transmission characteristics.

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