Source-drain parasitic resistance processing method, parasitic resistance structure and test structure

Abstract

The invention relates to the technical field of semiconductors, in particular to a source-drain parasitic resistance processing method, a parasitic resistance structure and a test structure, and the method comprises the steps: determining the first total resistance of any one field effect transistor in a preset number of field effect transistors under different overdrive voltages; performing linear fitting on the different overdrive voltages and the first total resistance under the different overdrive voltages to obtain a first test resistance; determining a second total resistance when the preset number of field effect transistors are connected in series; performing linear fitting on the number of the preset number of field effect transistors connected in series and the second total resistance to obtain a second test resistance; and performing source-drain parasitic resistance analysis processing on the first test resistor and the second test resistor to obtain source-drain parasitic resistance. According to the invention, the extraction convenience and feasibility of the source-drain parasitic resistance can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of field effect transistors, and in particular to a source-drain parasitic resistance processing method, a parasitic resistance structure, and a test structure. Background Art

[0002] The reduction in size of field-effect transistors is conducive to meeting the high integration requirements of integrated circuit chips, but the reduction in transistor size has brought great difficulties to its design, processing, testing, etc. Therefore, its processing process needs to be optimized. Generally, parasitic resistance includes gate parasitic resistance and source-drain parasitic resistance. When the metal gate (HKMG) is introduced, due to the good conductivity of the metal, the source-drain parasitic resistance usually has a greater impact on device performance. By effectively monitoring the source-drain parasitic resistance (Repi), we can accurately understand the improvement of process conditions, thereby providing direction for further process adjustments.

[0003] Related technologies typically measure different source-drain parasitic resistances by setting multiple gate period lengths (Contact Poly Pitch, CPP) and gate length combinations. However, the method of combining multiple CPP and gate lengths requires that the difference between CPP and gate length be constant to ensure the accuracy of source-drain parasitic resistance extraction. However, in actual testing, it is difficult to find an effective combination with a fixed CPP and gate length, which seriously affects the ability to extract source-drain parasitic resistance. Summary of the Invention

[0004] The present application provides a source-drain parasitic resistance processing method, a parasitic resistance structure and a test structure to at least solve the problem in the related art that CPP and gate length cannot be arbitrarily determined, thereby seriously affecting the ability to extract the source-drain parasitic resistance.

[0005] In order to solve the above technical problems, the technical solutions of this application are as follows:

[0006] According to a first aspect of an embodiment of the present application, a method for processing source-drain parasitic resistance is provided, the method comprising:

[0007] Providing a preset number of field effect transistors;

[0008] Determining a first total resistance of any one of the preset number of field effect transistors under different overdrive voltages;

[0009] Performing linear fitting on the different over-driving voltages and the first total resistances under the different over-driving voltages to obtain a first test resistance; the first test resistance is determined as a parasitic resistance excluding a channel resistance distributed in the channel;

[0010] determining a second total resistance when the preset number of field effect transistors are connected in series;

[0011] Performing linear fitting on the number of the preset number of field effect transistors connected in series and the second total resistance to obtain a second test resistance; the second test resistance is determined as a parasitic resistance other than the channel resistance and the source-drain parasitic resistance;

[0012] A source-drain parasitic resistance analysis process is performed on the first test resistor and the second test resistor to obtain the source-drain parasitic resistance of the field effect transistor.

[0013] According to a second aspect of an embodiment of the present application, a source-drain parasitic resistance structure of a field effect transistor is provided. The field effect transistor includes a gate region, a source-drain region, and a lead-out layer. The lead-out layer is in contact with the source-drain region, and one lead-out layer is arranged between two adjacent gate regions. The source-drain parasitic resistance structure is applied to a source-drain parasitic resistance processing method of a field effect transistor. The source-drain parasitic resistance includes a back-end winding resistance distributed in a metal interconnect line, a middle lead resistance distributed in the lead-out layer, a contact resistance distributed between the source-drain region and the lead-out layer, a source-drain parasitic resistance distributed in the source-drain region and between the source-drain region and the channel, and a channel resistance distributed in the channel.

[0014] According to a third aspect of the present application, a test structure is provided for testing source-drain parasitic resistance of a field-effect transistor, the test structure comprising a preset number of field-effect transistors connected in series; the field-effect transistor comprising a gate region, a source-drain region, and a lead-out layer, the lead-out layer being in contact with the source-drain region, one lead-out layer being disposed between two adjacent gate regions, the length between two adjacent gate regions being one and only one, and the length of the gate region being one and only one;

[0015] Any one of the preset number of field effect transistors connected in series is used for testing to obtain the first test resistor, and the preset number of field effect transistors connected in series are used for testing to obtain the second test resistor.

[0016] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:

[0017] The source-drain parasitic resistance processing method, parasitic resistance structure and test structure provided in the embodiments of the present application are obtained by combining two methods of extracting resistance, namely, extracting different components separately through a segmented resistance extraction method, and then combining them to disassemble the parasitic resistance of smaller components. The first extraction method is: determining the first total resistance of any one of the preset number of field effect transistors under different over-drive voltages; performing linear fitting on the different over-drive voltages and the first total resistance under the different over-drive voltages to obtain a first test resistance, which is determined by the parasitic resistance other than the channel resistance distributed in the channel. The second extraction method is: determining the second total resistance corresponding to each of the preset number of field effect transistors when the preset number of field effect transistors are connected in series; performing linear fitting on the number of the preset number of field effect transistors in series and the second total resistance to obtain a second test resistance, which is determined by the parasitic resistance other than the channel resistance and the source-drain parasitic resistance. Finally, the first test resistor and the second test resistor are combined with each other to disassemble the parasitic resistance of smaller components to analyze and process the source-drain parasitic resistance to obtain the source-drain parasitic resistance of the field-effect transistor. As a result, a segmented resistance extraction method can be used to extract the source-drain parasitic resistance through one CPP and gate length combination, without setting multiple CPP and gate length combinations, thereby improving the convenience and feasibility of extracting the source-drain parasitic resistance and reducing the cost of extracting the source-drain parasitic resistance.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application, and do not constitute an improper limitation on the present application.

[0020] Figure 1 A schematic diagram of the structure of an existing method for extracting the source-drain parasitic resistance of a fin field effect transistor is shown.

[0021] Figure 2 A schematic diagram of a conventional linear fitting method for extracting source-drain parasitic resistance is shown.

[0022] Figure 3 FIG. 1 is a schematic structural diagram of a fin field-effect transistor according to an exemplary embodiment.

[0023] Figure 4 FIG. 1 is a parasitic resistance structure of a FinFET according to an exemplary embodiment.

[0024] Figure 5A schematic diagram of a structure in which a predetermined number of fin field effect transistors are connected in series according to an exemplary embodiment is shown. Figure 1 .

[0025] Figure 6 A schematic diagram of a structure in which a predetermined number of fin field effect transistors are connected in series according to an exemplary embodiment is shown. Figure 2 .

[0026] Figure 7 A schematic diagram of a structure in which a predetermined number of fin field effect transistors are connected in series according to an exemplary embodiment is shown. Figure 3 .

[0027] Figure 8 This is a flow chart of a method for processing source-drain parasitic resistance according to an exemplary embodiment. Figure 1 .

[0028] Figure 9 This is a flow chart of a method for processing source-drain parasitic resistance according to an exemplary embodiment. Figure 2 .

[0029] Figure 10 Shown is a schematic diagram of the connection between the source region, drain region and gate region.

[0030] Figure 11 is a schematic diagram showing a first test resistance obtained by fitting according to an exemplary embodiment.

[0031] Figure 12 The figure is a schematic diagram showing a flow chart of calculating the second total resistance according to an exemplary embodiment.

[0032] Figure 13 The figure is a schematic diagram showing a flow chart of testing a second test resistor according to an exemplary embodiment.

[0033] Figure 14 is a schematic diagram showing a method of obtaining a second test resistance by fitting according to an exemplary embodiment.

[0034] Figure 15 The figure is a schematic diagram showing a flow chart of determining channel resistance according to an exemplary embodiment.

[0035] The following is a supplementary explanation of the reference numerals:

[0036] 1-Fin, 2-Gate region, 3-Lead layer, 4-Source region, 5-Drain region, 51-First drain region, 52-Second drain region, 53-Third drain region, 54-Fourth drain region, 55-Fifth drain region, 6-Back-end winding resistance, 7-Middle lead resistance, 8-Contact resistance, 9-Source-drain parasitic resistance itself, 10-Source-drain extension resistance, 11-Channel resistance. DETAILED DESCRIPTION

[0037] The following provides many different embodiments or examples for implementing the different features of the provided subject matter. The specific examples of the components and configurations described below are disclosed in a simplified manner. Of course, these components and configurations are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present application may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0038] Additionally, spatially relative terms, such as "below," "beneath," "lower," "on," "upper," "front," "back," "above," and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

[0039] It should be noted that the field effect transistors in the embodiments of the present application may include, but are not limited to, fin field effect transistors (FinFETs), planar metal-oxide semiconductor field effect transistors (MOSFETs), etc. Among them, the fin field effect transistor (FinFET) is a complementary metal semiconductor transistor. The main difference between its structure and that of a planar metal-oxide semiconductor field effect transistor (MOSFET) is that its channel is composed of a fin raised on an insulating substrate, with the source and drain electrodes distributed at both ends of the fin, and the gate closely attached to the sidewalls and top of the fin.

[0040] The problems existing in the existing source-drain parasitic resistance extraction method will now be described in detail with reference to the accompanying drawings.

[0041] Figure 1 FIG. 1 shows a schematic diagram of a structure of an existing method for extracting the source-drain parasitic resistance of a fin field effect transistor. Figure 1 As described above, the existing technology needs to provide two combinations of CPP (i.e., CPP1 and CPP2) and gate length (i.e., L1 and L2). These two CPP and gate length combinations need to satisfy CPP1-L1=CPP2-L2 to ensure that the source-drain parasitic resistance (Repi) + source-drain stretching resistance (Rsp) remains unchanged, thereby testing the total on-state resistance under different numbers of FinFET source-drain series connections.

[0042] Linear fits are performed using the total resistance as the ordinate and the length of the series FinFET as the abscissa. The slopes are: channel resistance (Rch) + source-drain parasitic resistance (Repi) + source-drain stretching resistance (Rsp), and the intercepts are: contact resistance (Rcon) + mid-segment resistance (Rmol) + back-end resistance (Rbeol).

[0043] Figure 2 The conventional linear fitting diagram for extracting source-drain parasitic resistance is shown in FIG. Figure 2 As shown, there is a slope Slope1 = = Rch1 + Repi + source-drain stretching resistance (Rsp); slope Slope2 = Rch2 + Repi + Rsp. Combining these two equations and considering that Rch varies linearly with channel length in the linear region, we can get Repi + Rsp and Rch.

[0044] However, in advanced processes, both CPP and gate length are constrained by design rules, requiring them to take fixed values. This makes it difficult to find a suitable combination with a fixed CPP-L difference, making the aforementioned design difficult to implement. This makes extracting source-drain parasitic resistance more difficult and expensive, significantly impacting the extraction capability.

[0045] Based on this, the embodiments of the present application provide a source-drain parasitic resistance processing method, a parasitic resistance structure and a test structure to solve the above-mentioned problems existing in the prior art.

[0046] First, extraction of source-drain parasitic resistance of a fin field-effect transistor is taken as an example for explanation.

[0047] Figure 3 is a schematic structural diagram of a fin field effect transistor according to an exemplary embodiment. Figure 4 FIG is a source-drain parasitic resistance structure of a fin field effect transistor according to an exemplary embodiment. Figure 3 The fin field effect transistor includes a fin 1, a gate region 2 distributed on the fin, a source-drain region, and a lead layer 3. The lead layer 3 is in contact with the source-drain region. The source-drain region includes a source region 4 and a drain region 5. One lead layer 3 is provided between two adjacent gate regions. The source-drain parasitic resistance structure may include:

[0048] The back-end winding resistance distributed in the metal interconnect line, the middle lead resistance distributed in the lead layer 3, the contact resistance distributed between the source and drain region and the lead layer 3, the source and drain parasitic resistance distributed in the source and drain region and between the source and drain region and the channel, and the channel resistance distributed in the channel.

[0049] Specifically, if Figure 3As shown, the embodiment of the present application can pre-divide the parasitic resistance of the FinFET to be tested into different components, including:

[0050] Back-end winding resistance (Rbeol)6: refers to the resistance of the back-end metal wire segment distributed within the metal interconnect line.

[0051] Middle lead resistance (Rmol) 7: refers to the resistance distributed in the lead layer 3.

[0052] Contact resistance (Rcon) 8: refers to the contact resistance distributed between the source and drain regions and the lead-out layer 3 .

[0053] Source-drain parasitic resistance (Repi) 9: refers to the resistance distributed in the source and drain regions.

[0054] Source-drain stretching resistance (Rsp)10: refers to the resistance distributed between the source-drain region and the channel.

[0055] Channel resistance (Rch) 11: refers to the resistance distributed across the channel, where the channel is a thin semiconductor layer between the source and drain regions.

[0056] It should be noted that since Repi and Rsp are difficult to distinguish during testing, the source-drain parasitic resistance finally extracted in the embodiment of the present application refers to the source-drain parasitic resistance itself and the source-drain stretching resistance, that is, the source-drain parasitic resistance finally extracted is Repi+Rsp.

[0057] The present application implements the method of pre-dividing the FinFET parasitic resistance to be tested into different components (Rbeol, Rmol, Rcon, Repi, Rsp, Rch). The divided resistance includes the resistance distributed at the rear end of the metal interconnection line, the resistance in the lead-out layer in contact with the source and drain regions, and the resistance inside the source and drain regions, inside the channel, and between the source and drain regions and the channel. In this way, during the resistance extraction process, different resistance components can be extracted separately and then combined with each other to disassemble the parasitic resistance of smaller components, which is conducive to improving the extraction convenience and feasibility of the source and drain parasitic resistance and reducing the extraction cost of the source and drain parasitic resistance.

[0058] The present application also provides a source-drain parasitic resistance test structure for a FinFET, which is used to test the source-drain parasitic resistance of a FinFET. The test structure includes a preset number of FinFETs connected in series. The FinFET includes a fin 1, a gate region 2 distributed on the fin 1, a source-drain region, and a lead layer 3. The lead layer 3 is in contact with the source-drain region. One lead layer 3 is provided between two adjacent gate regions 2. The length between two adjacent gate regions 2 has one and only one type, and the length of the gate region 2 has one and only one type. The first test resistance is determined by the parasitic resistance excluding the channel resistance 11 distributed in the channel. The second test resistance is determined by the parasitic resistance excluding the channel resistance 11 and the source-drain parasitic resistance. Any one of the preset number of FinFETs connected in series is used to test and obtain the first test resistance, and the preset number of FinFETs connected in series are used to test and obtain the second test resistance.

[0059] Figure 5 A schematic diagram of a structure in which a predetermined number of fin field effect transistors are connected in series according to an exemplary embodiment is shown. Figure 1 . Figure 6 A schematic diagram of a structure in which a predetermined number of fin field effect transistors are connected in series according to an exemplary embodiment is shown. Figure 2 Please refer to Figure 5 and Figure 6 , the test structure includes a preset number of fin field effect transistors connected in series, and the fin field effect transistor includes a fin 1, a gate region 2 distributed on the fin, a source and drain region and a lead layer 3, and a lead layer 3 is provided between two adjacent gate regions. The embodiment of the present application does not specifically limit the number of fins. In one embodiment, it includes a preset number of root fins, the fins are strip-shaped, and the lead layer 3 is distributed on the outer fins. In another embodiment, it includes a preset number of root fins, the fins are strip-shaped, and the lead layer 3 is distributed on the middle fin. In the third embodiment, it includes a preset number of root fins, the fins are strip-shaped, and the lead layer 3 spans the middle of the preset number of root fins. There is only one length between two adjacent gate regions 2, and there is only one length of the gate region 2, that is, the length between the two gate regions 2 is fixed and unique, and the length of the gate region 2 is also fixed and unique. That is, the test structure can extract the test resistor through one CPP and gate length combination, without setting multiple CPP and gate length combinations, thereby improving the extraction accuracy, extraction efficiency, extraction convenience and extraction feasibility of the test resistor and reducing the extraction cost of the test resistor.

[0060] Please continue to see Figure 3 and Figure 4 , Figure 3 and Figure 4It can be any one of the preset number of fin field effect transistors connected in series, and the first test resistance can be extracted through any one of the fin field effect transistors. For any one of the fin field effect transistors, it may include a fin 1, a gate region 2 distributed on the fin, a source and drain region, and a lead-out layer 3. The first test resistance can be extracted through any one of the fin field effect transistors, thereby improving the extraction accuracy, extraction efficiency, extraction convenience, and extraction feasibility of the first test resistance, and reducing the extraction cost of the first test resistance. It should be noted that, in some embodiments, extracting the first test resistance through any one of the fin field effect transistors can also be understood as: selecting several fin field effect transistors from a preset number of fin field effect transistors connected in series, extracting the first test resistance through each fin field effect transistor respectively, and finally calculating the average of the first test resistances extracted by several fin field effect transistors to obtain the final first test resistance.

[0061] Since the first test resistance is determined as the parasitic resistance excluding the channel resistance 11 distributed in the channel, and the parasitic resistance of the FinFET to be tested is divided into different components (Rbeol, Rmol, Rcon, Repi, Rsp, Rch), the "parasitic resistance excluding the channel resistance distributed in the channel" may include Rbeol, Rmol, Rcon, Repi, and Rsp. Assuming that the first test resistance is defined as Rext, in one embodiment, Rext = Rbeol + Rmol + Rcon + Repi + Rsp.

[0062] Since the first test resistance is determined as the parasitic resistance other than the channel resistance 11 and the source-drain parasitic resistance, and the FinFET parasitic resistance to be tested is divided into different components (Rbeol, Rmol, Rcon, Repi, Rsp, Rch), and the source-drain parasitic resistance includes Repi + Rsp, then the "parasitic resistance other than the channel resistance and the source-drain parasitic resistance" can include Rbeol, Rmol, and Rcon. Assuming that the second test resistance is defined as Rres, in one embodiment, Rres = Rbeol + Rmol + Rcon.

[0063] The test structure of the embodiment of the present application includes a test structure of a preset number of Fin field-effect transistors connected in series. The first test resistor is tested by any one of the Fin field-effect transistors in the test structure, and the second test resistor is tested by the preset number of Fin field-effect transistors connected in series, thereby realizing a combination of two resistance extraction methods, namely, extracting different components separately through a segmented resistance extraction method, and then combining the first test resistor and the second test resistor with each other to disassemble the parasitic resistance of smaller components. Thus, through the segmented resistance extraction method, the source-drain parasitic resistance can be extracted through one CPP and gate length combination, without setting multiple CPP and gate length combinations, thereby improving the convenience and feasibility of extracting the source-drain parasitic resistance and reducing the cost of extracting the source-drain parasitic resistance.

[0064] Please continue to see Figure 5 and Figure 6 The preset number of fin field effect transistors connected in series include one source region 4 and a preset number of drain regions 5. For example, the preset number of fin field effect transistors connected in series include one source region 4 and three drain regions 5.

[0065] It should be noted that, structurally, the preset number of fin field effect transistors connected in series include a source region 4 and a preset number of drain regions 5, for example. Figure 5 and Figure 6 As shown, the preset number of drain regions includes a first drain region 51, a second drain region 52 and a third drain region 53. However, during the test, only one source region 4 and one drain region 5 are tested at the same time. The one drain region 4 is used to connect with different drain regions 5 during the test to test the current between the one source region 4 and the different drain regions 5. That is, during the test, if it is necessary to test the current between the source region 4 and a certain drain region 5, the source region 4 is connected to the drain region 5, and the other drain regions are not connected. Figure 6 As shown in the figure, if the current between the source region 4 and the first drain region 51 needs to be tested, the source region 4 and the first drain region 51 can be connected, and the second drain region 52 and the third drain region 53 are not connected. If the current between the source region 4 and the second drain region 52 needs to be tested, the source region 4 and the second drain region 52 can be connected, and the other drain regions are not connected. If the current between the source region 4 and the third drain region 53 needs to be tested, the source region 4 and the third drain region 53 can be connected, and the other drain regions are not connected. After obtaining the current between the source region and different drain regions, the resistance corresponding to each of the first drain region 51, the second drain region 52, and the third drain region 53 can be calculated. Then, a linear fit is performed based on the calculated resistance and the number of preset fin field effect transistors connected in series to obtain the second test resistance.

[0066] The embodiment of the present application sets a source region and a preset number of drain regions in series, and enables one drain region to be connected to different drain regions respectively during testing to test the current between the one source region and the different drain regions, thereby achieving accurate testing of the current in different drain regions, thereby further improving the extraction accuracy, extraction convenience and extraction feasibility of the source-drain parasitic resistance.

[0067] It should be noted that the embodiments of the present application do not limit the number of the preset number of FinFETs connected in series. In one embodiment, since linear fitting is required during the source-drain parasitic resistance test, in order to verify the fitting effect of the linear fit, improve the accuracy of the linear fit and the feasibility of the fitting results, and thereby improve the convenience and feasibility of extracting the source-drain parasitic resistance, the number of the preset number of FinFETs connected in series can be at least three.

[0068] It should be noted that, when the preset number of FinFETs connected in series is greater than three, at least three FinFETs may be selected to extract the second test resistance. Figure 7 A schematic diagram of a structure in which a predetermined number of fin field effect transistors are connected in series according to an exemplary embodiment is shown. Figure 3 .like Figure 7 As shown, when the number of FinFETs connected in series is greater than three, the preset number of drain regions includes a first drain region 51, a second drain region 52, a third drain region 53, a fourth drain region 54, and a fifth drain region 55. At least three of the drain regions can be selected to extract the second test resistance. For example, the first drain region 51, the third drain region 53, and the fifth drain region 55 are selected, the source region 4 is connected to the first drain region 51 to measure the current between the source region 4 and the first drain region 51, the source region 4 is connected to the third drain region 53 to measure the current between the source region 4 and the third drain region 53, and the source region 4 is connected to the fifth drain region 55 to measure the current between the source region 4 and the fifth drain region 55. The resistance corresponding to each of the first drain region 51, the third drain region 53, and the fifth drain region 55 is calculated. Then, a linear fit is performed based on the calculated resistance and the number of the preset number of FinFETs connected in series to obtain the second test resistance.

[0069] above Figures 3 to 7All of them are explained using fin field effect transistors as examples. The above-mentioned source-drain parasitic resistance structure and test structure can also be applied to MOSFET, that is, the embodiment of the present application also provides a source-drain parasitic resistance structure of MOSFET, MOSFET includes a gate region, a source-drain region and a lead layer, the lead layer is in contact with the source-drain region, and a lead layer is provided between two adjacent gate regions, the source-drain parasitic resistance structure is applied to the source-drain parasitic resistance processing method of MOSFET, the source-drain parasitic resistance includes the back-end winding resistance distributed in the metal interconnection line, the middle lead resistance distributed in the lead layer, the contact resistance distributed between the source-drain region and the lead layer, the source-drain parasitic resistance distributed in the source-drain region and between the source-drain region and the channel, and the channel resistance distributed in the channel. For the specific process of source-drain parasitic resistance decomposition, please refer to the above. Figures 3 to 7 , and no specific limitation is given to this.

[0070] Accordingly, an embodiment of the present application also provides a test structure for the source-drain parasitic resistance of a MOSFET, wherein the test structure is used to test the source-drain parasitic resistance of a MOSFET, and the test structure includes a preset number of field effect transistors connected in series; the field effect transistor includes a gate region, a source-drain region and a lead-out layer, the lead-out layer is in contact with the source-drain region, and one lead-out layer is provided between two adjacent gate regions, and the length between two adjacent gate regions has one and only one type, and the length of the gate region has one and only one type; any one of the preset number of field effect transistors connected in series is used to test and obtain the first test resistance, and the preset number of field effect transistors connected in series are used to test and obtain the second test resistance. For the specific test structure, please refer to the above Figures 3 to 7 , and no specific limitation is given to this.

[0071] The present application also provides a method for processing source-drain parasitic resistance. Figure 8 This is a flow chart of a method for processing source-drain parasitic resistance according to an exemplary embodiment. Figure 1 ,like Figure 8 As shown, the source-drain parasitic resistance processing method combines two resistance extraction methods, that is, extracting different components separately through segmented resistance extraction, and then combining them to disassemble the parasitic resistance of smaller components. Specifically, the source-drain parasitic resistance processing method may include:

[0072] S11. Provide a preset number of field effect transistors.

[0073] The field effect transistor may include but is not limited to: FinFET, MOSFET, etc. The embodiment of the present application does not limit the number of field effect transistors to be tested.

[0074] Optionally, after determining a preset number of field effect transistors to be tested, the parasitic resistance of the field effect transistor can be divided into different components (Rbeol, Rmol, Rcon, Repi, Rsp, Rch) according to the resistance decomposition method in the above-mentioned source-drain parasitic resistance structure embodiment.

[0075] S13. Determine a first total resistance of any one field effect transistor among the preset number of field effect transistors under different overdrive voltages.

[0076] S15. Performing linear fitting on the different overdrive voltages and the first total resistances at the different overdrive voltages to obtain a first test resistance; the first test resistance is determined as a parasitic resistance excluding a channel resistance distributed in the channel;

[0077] Optionally, the first extraction method in the segmented extraction method can be for a single field effect transistor, and any one field effect transistor from a preset number of field effect transistors can be taken to test the current under different overdrive voltages, and the first total resistance under different overdrive voltages can be calculated. The first test resistance can be obtained by linearly fitting the different overdrive voltages and the first total resistance under the different overdrive voltages. It should be noted that, in some embodiments, extracting the first test resistance for a single field effect transistor can also be understood as: selecting a number of fin field effect transistors from a preset number of fin field effect transistors connected in series, extracting the first test resistance through each fin field effect transistor respectively, and finally calculating the average of the first test resistances extracted from the several fin field effect transistors to obtain the final first test resistance.

[0078] In one embodiment, as described above, the first test resistor (Rext) may be the sum of all resistors except the channel resistor 11 .

[0079] S17. Determine a second total resistance when the preset number of field effect transistors are connected in series.

[0080] S19. Perform linear fitting on the number of the preset number of field effect transistors connected in series and the second total resistance to obtain a second test resistance; the second test resistance is determined as the parasitic resistance excluding the channel resistance and the source-drain parasitic resistance.

[0081] Optionally, the second extraction method in the segmented extraction method can be for the preset number of field effect transistors connected in series. For the preset number of field effect transistors connected in series, the current when different numbers of FinFETs are connected in series can be tested, the second total resistance can be calculated, and the number of the preset number of field effect transistors connected in series and the second total resistance can be linearly fitted to calculate the second test resistance.

[0082] In one embodiment, as described above, the second test resistor (Rres) may be the sum of all parasitic resistances except the source-drain resistance and the channel resistance.

[0083] S111 . Perform source-drain parasitic resistance analysis on the first test resistor and the second test resistor to obtain the source-drain parasitic resistance of the field effect transistor.

[0084] Optionally, after obtaining the first test resistor and the second test resistor through the above-mentioned segmented extraction method, the calculation formulas of the first test resistor and the second test resistor can be combined and decomposed into smaller component parasitic resistances to perform source-drain parasitic resistance analysis and obtain the source-drain parasitic resistance (Repi+Rsp) of the field effect transistor.

[0085] The source-drain parasitic resistance processing method, parasitic resistance structure and test structure provided in the embodiments of the present application are obtained by combining two methods of extracting resistance, namely, extracting different components separately through a segmented resistance extraction method, and then combining them to disassemble the parasitic resistance of smaller components. The first extraction method is: determining the first total resistance of any one of the preset number of field effect transistors under different over-drive voltages; performing linear fitting on the different over-drive voltages and the first total resistance under the different over-drive voltages to obtain a first test resistance, which is determined by the parasitic resistance other than the channel resistance distributed in the channel. The second extraction method is: determining the second total resistance corresponding to each of the preset number of field effect transistors when the preset number of field effect transistors are connected in series; performing linear fitting on the number of the preset number of field effect transistors in series and the second total resistance to obtain a second test resistance, which is determined by the parasitic resistance other than the channel resistance and the source-drain parasitic resistance. Finally, the first test resistor and the second test resistor are combined with each other to disassemble the parasitic resistance of smaller components to analyze and process the source-drain parasitic resistance to obtain the source-drain parasitic resistance of the field-effect transistor. As a result, a segmented resistance extraction method can be used to extract the source-drain parasitic resistance through one CPP and gate length combination, without setting multiple CPP and gate length combinations, thereby improving the convenience and feasibility of extracting the source-drain parasitic resistance and reducing the cost of extracting the source-drain parasitic resistance.

[0086] It should be noted that the above step S13 can be implemented in various ways, which are not specifically limited.

[0087] Figure 9 This is a flow chart of a method for processing source-drain parasitic resistance according to an exemplary embodiment. Figure 2 ,like Figure 9As shown, in one embodiment, in the above step S13, the above determining the first total resistance of any one of the preset number of field effect transistors under different overdrive voltages may include:

[0088] S131. Determine the drain current of any one of the field effect transistors under different overdrive voltages in the linear region.

[0089] S133. Based on the different over-driving voltages and the drain currents under the different over-driving voltages, generate a first total resistance under the different over-driving voltages.

[0090] In this embodiment, the drain current of any field effect transistor under different overdrive voltages in the linear region can be measured. The ratio of the drain current under different overdrive voltages and the drain current under different overdrive voltages is calculated to obtain the first total resistance under different overdrive voltages. The linear region refers to: when the field effect transistor is turned on, if the voltage between the drain and the source (VDS) is small, the drain current and VDS are approximately linearly related, and this working range is the linear region.

[0091] Since there is an approximately linear relationship between the drain current in the linear region and VDS, different first total resistances are generated through different driving voltages in the linear region and the drain currents under the different over-driving voltages, so that the inverse of the first total resistance is also linearly related to the driving voltage, thereby improving the accuracy of subsequent linear fitting of different over-driving voltages and the first total resistance under the different over-driving voltages, thereby improving the test accuracy of the first test resistance and the convenience and feasibility of extracting the source-drain parasitic resistance, and reducing the extraction cost of the source-drain parasitic resistance.

[0092] It should be noted that in order to improve the test accuracy of the first total resistance, abnormal drain currents in the drain currents under different over-drive voltages can also be filtered out, and the unfiltered over-drive voltage and the corresponding drain current can be calculated to generate the first total resistance.

[0093] In an optional embodiment, before step S131, the method may further include an operation of determining different over-driving voltages. The operation of determining different over-driving voltages may include:

[0094] The threshold voltage and gate-source voltage of any one of the field effect transistors are determined.

[0095] The different over-driving voltages are generated according to the gate-source voltage and the threshold voltage of any one of the field effect transistors.

[0096] In this embodiment, the overdrive voltage can be defined as over drive, which can refer to the gate-source voltage minus the threshold voltage, wherein the gate-source voltage refers to the voltage between the gate region and the source region, and the threshold voltage refers to the critical voltage of the field effect transistor. The threshold voltage can be obtained in a variety of ways, and there is no specific limitation on this. For example, the voltage at which the field effect transistor starts to conduct under a given voltage can be measured to obtain the threshold voltage.

[0097] Optionally, the gate-source voltage can be defined as V GS , define the threshold voltage as V T , then over drive = V GS -V T Overdrive is a variable that changes with the gate-source voltage. Therefore, by changing the gate-source voltage, different overdrive voltages can be obtained, thereby improving the generation accuracy of the overdrive voltage and thus improving the test accuracy of the first test resistor.

[0098] It should be noted that the embodiments of the present application do not limit the number of overdrive voltages. Since linear fitting is required during the first test resistor test, in order to verify the fitting effect of the linear fit, improve the accuracy of the linear fit and the feasibility of the fitting results, and thereby improve the convenience and feasibility of extracting the first test resistor, the number of overdrive voltages can be at least three.

[0099] Hereinafter, the above steps for generating the first total resistance under different overdriving voltages will be described by taking the field effect transistor as FinFET and the number of overdriving voltages as three as an example;

[0100] Measure the threshold voltage and three different gate-source voltages, calculate the difference between the three gate-source voltages and the threshold voltage to obtain three overdrive voltages; take a single FinFET, and measure the drain currents Idlin1, idlin2, and idlin3 under the three overdrive voltages (Vod1, Vod2, and Vod3) in the linear region. From Vd / Idlin=R, calculate the three first total resistances R1, R2, and R3, where Vod1 / Idlin1=R1, Vod2 / Idlin2=R2, and Vod3 / Idlin3=R3. The connection diagram of the source region, drain region, and gate region is shown in the figure below. Figure 10 As shown, Figure 10 V in G Represents V GS , V OD It represents over drive, V S It represents the source region voltage, V D It represents the voltage in the drain region.

[0101] It should be noted that extracting the first test resistance for a single field-effect transistor can also be understood as: selecting a plurality of field-effect transistors from a preset number of field-effect transistors connected in series, extracting the first test resistance through each field-effect transistor, and finally calculating the average of the first test resistances extracted from the plurality of field-effect transistors to obtain the final first test resistance. Accordingly, the calculation method for the first total resistance can also include: determining the first total resistance of each of the plurality of field-effect transistors at different overdrive voltages, performing arithmetic averaging or weighted averaging on the first total resistances of each of the plurality of field-effect transistors at different overdrive voltages to obtain the first total resistance. Furthermore, the drain current of each of the plurality of field-effect transistors at different overdrive voltages in the linear region can be determined, performing arithmetic averaging or weighted averaging on the drain current of each of the plurality of field-effect transistors at different overdrive voltages in the linear region to obtain the average drain current at different overdrive voltages, and generating the first total resistance at the different overdrive voltages based on the different overdrive voltages and the average drain current at the different overdrive voltages.

[0102] It should be noted that the above step S15 can be implemented in various ways, which are not specifically limited.

[0103] In one embodiment, continue as Figure 9 As shown, in the above step S15, performing linear fitting on the different over-driving voltages and the first total resistance under the different over-driving voltages to obtain the first test resistance may include:

[0104] S151. Use the reciprocals of the different over-driving voltages as the first coordinate on the first coordinate axis, and use the first total resistance under the different over-driving voltages as the second coordinate on the second coordinate axis.

[0105] S153. Perform linear fitting on the first coordinate and the second coordinate to obtain a first fitting straight line.

[0106] S155. Generate the first test resistor based on the intersection of the first fitting straight line and the second coordinate axis, wherein the first test resistor is generated based on the rear winding resistance, the middle lead resistance, the contact resistance, and the source-drain parasitic resistance.

[0107] In this embodiment, since the drain current in the linear region is approximately linearly related to VDS, different first total resistances are generated by different driving voltages in the linear region and the drain currents under the different overdrive voltages, so that the reciprocal of the first total resistance is also linearly related to the driving voltage. Therefore, in order to improve the accuracy of linear fitting of different overdrive voltages and the first total resistance under the different overdrive voltages, thereby improving the test accuracy of the first test resistance and the convenience and feasibility of extracting the source-drain parasitic resistance, in the above step S151, the reciprocal of the different overdrive voltages can be used as the first coordinate on the first coordinate axis, and the first total resistance under the different overdrive voltages can be used as the second coordinate on the second coordinate axis. Optionally, the first coordinate axis and the second coordinate axis are different coordinate axes, and both can be any one of the horizontal axis and the vertical axis. In one embodiment, the first coordinate axis is the horizontal axis and the second coordinate axis is the vertical axis. In another embodiment, the first coordinate axis is the vertical axis and the second coordinate axis is the horizontal axis.

[0108] Optionally, in the above step S153, the first coordinate and the second coordinate can be linearly fitted based on the least squares method, the pyplot fitting function, the neural network fitting function and other fitting methods to obtain the first fitting straight line, which is not specifically limited.

[0109] The following describes the process of performing linear fitting on the first coordinate and the second coordinate to obtain a first fitting line, taking the least squares method as an example: The basic idea of the least squares method is:

[0110]

[0111] in, is a set of linearly independent functions selected in advance, a k is the coefficient to be determined ((k=1,2,…,m,m<n)), and the fitting criterion is to make y i (i=1,2,…,n) and f(x i ) i The sum of squares is minimized.

[0112] Let (x, y) be a pair of observations, and x = [x1, x2, ..., x n ] T ∈R n , y = R satisfies the following theoretical function:

[0113] y = f(x, ω);

[0114] Among them, ω=[ω1,ω2,…,ω n ] T is an undetermined parameter. The above formula can be used to find the optimal estimate of the parameter ω of the function f(x, ω).

[0115] For the first coordinate and the second coordinate in the embodiment of the present application, the first coordinate and the second coordinate can be used as a pair of observations to obtain a first fitting straight line.

[0116] Optionally, in step S155, the intersection of the first fitting straight line and the second coordinate axis can be obtained. In one embodiment, the coordinates corresponding to the intersection can be directly used as the first test resistance. In another embodiment, in order to further improve the test accuracy of the first test resistance, a reference value for the first test resistance can be pre-set. If the difference between the first test resistance and the reference value is large, refitting is performed until the difference between the first test resistance and the reference value is less than a preset difference threshold. It should be noted that when the first coordinate axis is the horizontal axis and the second coordinate axis is the vertical axis, the first test resistance is the intersection of the first fitting straight line and the vertical axis. When the first coordinate axis is the vertical axis and the second coordinate axis is the horizontal axis, the first test resistance is the intersection of the first fitting straight line and the horizontal axis.

[0117] It should be noted that the first test resistance is determined by the rear winding resistance 6, the middle lead resistance 7, the contact resistance 8 and the source-drain parasitic resistance. In one embodiment, Rext=Rbeol+Rmol+Rcon+Repi+Rsp.

[0118] Since the linear region channel resistance 11 is affected by the gate-source voltage (V GS ), while other parasitic resistances except the channel resistance 11 are not affected by the gate-source voltage. Therefore, under different over-driving voltage conditions, linear fitting is performed on the first total resistance and the inverse of different over-driving voltages. The sum of all other parasitic resistances except the channel resistance 11 can be accurately determined through the intersection of the first fitting straight line and the second coordinate axis, thereby improving the testing convenience and testing feasibility of the first test resistor and reducing the testing cost of the first test resistor.

[0119] In the following, the above step S15 is described by taking the first coordinate axis as the horizontal axis, the second coordinate axis as the vertical axis, and three different overdriving voltages as an example:

[0120] Figure 11 is a schematic diagram showing a first test resistance obtained by fitting according to an exemplary embodiment. Figure 11 The horizontal axis is the inverse of the different overdrive voltages, and the vertical axis is the first total resistance, such as Figure 11As shown, the characteristic that the channel resistance in the linear region is affected by the gate-source voltage (VGS), while other parasitic resistances other than the channel resistance 11 are not affected by the gate-source voltage, is adopted. A linear fit is performed on the three calculated first total resistances R1, R2, and R3, as well as 1 / Vod1, 1 / Vod2, and 1 / Vod3 to obtain a first fitting line. The intersection of the first fitting lines is the first test resistance.

[0121] It should be noted that the above step S17 can be implemented in various ways, which are not specifically limited.

[0122] Figure 12 FIG. 1 is a flow chart showing a method for calculating a second total resistance according to an exemplary embodiment. Figure 12 As shown, in one embodiment, in the above step S17, the above determining the second total resistance when the preset number of field effect transistors are connected in series may include:

[0123] S171. Determine the current data between the source region and each drain region and the drain voltage of each drain region when the preset number of field effect transistors are connected in series.

[0124] S173. Generate a second total resistance corresponding to each field effect transistor based on the current data between the one source region and each drain region and the drain voltage of each drain region.

[0125] In this embodiment, structurally, the preset number of field-effect transistors connected in series include a source region and a preset number of drain regions. However, during the test, there is only one actual working drain region. The source region can be connected to each drain region to measure the current data between the source region and each drain region, as well as the drain voltage of each drain region. After determining the current data between the source region and each drain region and the drain voltage of each drain region, the corresponding second total resistance can be calculated according to the formula Vd / Id=R, where Vd refers to the drain voltage of each drain region, and Id refers to the current data between the source region and each drain region.

[0126] In other implementations, in order to improve the test accuracy of the second total resistance, abnormal current data may be filtered out, and unfiltered current data and the corresponding drain voltage may be calculated to generate the second total resistance.

[0127] The embodiment of the present application achieves accurate testing of the second total resistance by setting a source region and a preset number of drain regions in series, and connecting different drain regions respectively through a drain region to test the current and drain voltage between the one source region and the different drain regions, thereby further improving the convenience and feasibility of extracting the source-drain parasitic resistance.

[0128] It should be noted that since linear fitting is required during the test process of the second test resistor, in order to verify the fitting effect of the linear fitting, improve the accuracy of the linear fitting and the feasibility of the fitting results, and thereby improve the convenience and feasibility of extracting the second test resistor, the number of the preset number of field effect transistors connected in series can be at least three.

[0129] The following describes step S17 by taking the field effect transistor as FinFET and the number of FinFETs connected in series as three as an example:

[0130] Continue as Figure 6 As shown, three FinFETs can be connected in series, connecting the source region 4 and the first drain region 51 to measure the current data between the source region 4 and the first drain region 51 to obtain Id1, and at the same time measuring the voltage of the first drain region 51 to obtain Vd1. At this time, the source region 4 is not connected to the second drain region 52 and the third drain region 53; connecting the source region 4 and the second drain region 52 to measure the current data between the source region 4 and the second drain region 52 to obtain Id2, and at the same time measuring the voltage of the second drain region 52 to obtain Vd2. At this time, the source region 4 is not connected to the first drain region 51 and the third drain region 53; connecting the source region 4 and the third drain region 53 to obtain Id3 with the current data between the source region 4 and the third drain region 53, and at the same time measuring the voltage of the third drain region 53 to obtain Vd3. At this time, the source region 4 is not connected to the first drain region 51 and the third drain region 53. Finally, the corresponding second total resistances R1, R2, and R3 are calculated by Vd / Id=R, where R1=Vd1 / Id1, R2=Vd2 / Id2, and R3=Vd3 / Id3.

[0131] Continue as Figure 7As shown, five FinFETs can be connected in series, connecting the source region 4 and the first drain region 51 to measure the current data between the source region 4 and the first drain region 51 to obtain Id1, and at the same time measuring the voltage of the first drain region 51 to obtain Vd1. At this time, the source region 4 is not connected to the second drain region 52 and the third drain region 53; connecting the source region 4 and the third drain region 53 to measure the current data between the source region 4 and the third drain region 53 to obtain Id2, and at the same time measuring the voltage of the third drain region 53 to obtain Vd2. At this time, the source region 4 is not connected to other drain regions; connecting the source region 4 and the fifth drain region 55 to obtain Id3 with the current data between the source region 4 and the fifth drain region 55, and at the same time measuring the voltage of the fifth drain region 55 to obtain Vd3. At this time, the source region 4 is not connected to other drain regions. Finally, the corresponding second total resistances R1, R2, and R3 are calculated by Vd / Id=R, where R1=Vd1 / Id1, R2=Vd2 / Id2, and R3=Vd3 / Id3. It should be noted that when the number of field-effect transistors connected in series is greater than three, at least three field-effect transistors can be selected from them to extract the second test resistance, and this is not specifically limited.

[0132] In an optional embodiment, the above step S19 can be implemented in various ways, which are not specifically limited.

[0133] Figure 13 FIG. 1 is a flow chart showing a process of testing a second test resistor according to an exemplary embodiment. Figure 13 As shown, in one embodiment, in the above step S19, performing linear fitting on the number of the preset number of field effect transistors connected in series and the second total resistance to obtain the second test resistance may include:

[0134] S191. Use the target number as the third coordinate on the first coordinate axis and the second total resistance as the fourth coordinate on the second coordinate axis; the target number is determined based on the number of the preset number of field effect transistors connected in series.

[0135] S193. Perform linear fitting on the third coordinate and the fourth coordinate to obtain a second fitting straight line.

[0136] S195. Generate the second test resistor according to the intersection of the second fitting straight line and the second coordinate axis.

[0137] The second test resistance is determined by the rear winding resistance 6 , the middle lead resistance 7 and the contact resistance 8 .

[0138] In this embodiment, in order to improve the convenience and feasibility of extracting the second test resistor and the source-drain parasitic resistance, in the above step S191, the target number can be determined based on the number of the preset number of field effect transistors connected in series, and the target number can be any number between 1 and the preset number. More specifically, the target number can refer to the number of field effect transistors in the preset number of field effect transistors connected in series. For example, Figure 6 As shown, the number of the preset number of field effect transistors connected in series is three, and the target number can be 1, 2 and 3, where "1" refers to Figure 6 The first FinFET in the circuit, i.e. the FinFET corresponding to the first drain region 51, “2” refers to Figure 6 The second FinFET in the figure, i.e. the FinFET corresponding to the second drain region 52, “3” refers to Figure 6 The third FinFET in the embodiment is the FinFET corresponding to the third drain region 53. For another example, Figure 7 As shown, the number of the preset number of field effect transistors connected in series is five, and the target number can be 1, 3 and 5, where "1" refers to Figure 7 The first FinFET in the circuit, i.e. the FinFET corresponding to the first drain region 51, “3” refers to Figure 7 The third FinFET in the figure, i.e. the FinFET corresponding to the third drain region 53, “5” refers to Figure 7 The fifth FinFET in the circuit, namely the FinFET corresponding to the fifth drain region 55.

[0139] Alternatively, the target quantity can be used as the third coordinate on the first coordinate axis, and the second total resistance can be used as the fourth coordinate on the second coordinate axis. Alternatively, the first coordinate axis and the second coordinate axis are different coordinate axes, and both can be either the horizontal axis or the vertical axis. In one embodiment, the first coordinate axis is the horizontal axis and the second coordinate axis is the vertical axis. In another embodiment, the first coordinate axis is the vertical axis and the second coordinate axis is the horizontal axis.

[0140] Optionally, in the above step S193, the third coordinate and the fourth coordinate can be linearly fitted based on the least squares method, the pyplot fitting function, the neural network fitting function and other fitting methods to obtain the second fitting straight line, which is not specifically limited.

[0141] Optionally, in the above step S195, the intersection of the second fitting straight line and the second coordinate axis can be obtained. In one way, the coordinates of the intersection can be directly used as the second test resistance. In another way, in order to further improve the test accuracy of the second test resistance, a reference value for the second test resistance can be pre-set. If the difference between the second test resistance and the reference value is large, refitting is performed until the difference between the second test resistance and the reference value is less than a preset difference threshold. It should be noted that when the first coordinate axis is the horizontal axis and the second coordinate axis is the vertical axis, the second test resistance is the intersection of the second fitting straight line and the vertical axis. When the first coordinate axis is the vertical axis and the second coordinate axis is the horizontal axis, the second test resistance is the intersection of the second fitting straight line and the horizontal axis.

[0142] It should be noted that the second test resistance is determined by the rear winding resistance 6, the middle lead resistance 7, the contact resistance 8 and the source-drain parasitic resistance. In one embodiment, Rres=Rbeol+Rmol+Rcon.

[0143] Since the second total resistance of the preset number of field effect transistors after series connection can be expressed as: Rtotal = n (Repi + Rsp + Rch) + Rres, n is the number of the preset number of field effect transistors after series connection, that is, it can be understood as the form of y = kx + b, wherein y corresponds to Rtotal, k corresponds to Repi + Rsp + Rch, n corresponds to x, and b corresponds to Rres, that is, Rres can be understood as the intercept. Therefore, by fitting the number of the preset number of field effect transistors and the second total resistance, the intersection of the second fitting straight line and the second coordinate axis (i.e., Rres) can be accurately determined. The sum of the sum of all resistances except the channel resistance (Rch) and the source-drain resistance (Repi + Rsp), thereby improving the test accuracy, test convenience and test feasibility of the second test resistance.

[0144] In the following, the above step S19 is described by taking the field effect transistor as a fin field effect transistor, the first coordinate axis as the horizontal axis, the second coordinate axis as the vertical axis, and the number of the preset number of fin field effect transistors as three as an example:

[0145] Figure 14 FIG. 1 is a schematic diagram showing a method of fitting to obtain a second test resistance according to an exemplary embodiment. Figure 14 As shown, the horizontal axis is the target number, the vertical axis is the total second total resistance, and the linear fitting is performed. The vertical axis intercept is the sum of all resistances (Rres) except the channel resistance (Rch) and the source-drain resistance (Repi+Rsp), that is, Rres=Rcon+Rmol+Rbeol.

[0146] Optionally, the above step S111 can be implemented in various ways, which are not specifically limited.

[0147] In an optional embodiment, in step S111, performing source-drain parasitic resistance analysis on the first test resistor and the second test resistor to obtain the source-drain parasitic resistance of the field effect transistor may include:

[0148] A difference between the first test resistor and the second test resistor is determined.

[0149] The source-drain parasitic resistance is generated according to a difference between the first test resistor and the second test resistor.

[0150] In this embodiment, after obtaining the first test resistor and the second test resistor in the above manner, in order to improve the testing convenience and feasibility of the source-drain parasitic resistance, the calculation formulas of the first test resistor and the second test resistor can be combined and decomposed into smaller component parasitic resistances to perform source-drain parasitic resistance analysis. Specifically, the difference between the first test resistor and the second test resistor can be calculated. Since Rext = Rbeol + Rmol + Rcon + Repi + Rsp, and the second test resistor Rres = Rbeol + Rmol + Rcon, the difference between the two is calculated to obtain Rext - Rres = Repi + Rsp. Since it is difficult to separate them in the actual testing process, the difference between the two can be directly used as the source-drain parasitic resistance (Repi + Rsp). Since the first test resistance is the sum of the parasitic resistances excluding the channel resistance 11, and the second test resistance is the sum of the parasitic resistances excluding the channel resistance 11 and the source-drain resistance, the parasitic source-drain resistance (Repi+Rsp) can be accurately and conveniently extracted through the difference between the two; thus, in the overall parasitic source-drain resistance extraction process, the source-drain parasitic resistance can be extracted through a single CPP and gate length combination, without the need to set multiple CPP and gate length combinations, thereby improving the extraction accuracy, extraction efficiency, and extraction convenience of the source-drain parasitic resistance and reducing the extraction cost of the source-drain parasitic resistance.

[0151] Figure 15 FIG. 1 is a flow chart showing a method for determining channel resistance according to an exemplary embodiment. Figure 15 As shown, in some embodiments, the above method may further include an operation of determining a channel resistance, and the operation of determining the channel resistance may include:

[0152] S201. Determine a second total resistance based on the second test resistance and a target resistance; the target resistance is determined based on the source-drain parasitic resistance, the channel resistance, and the number of the preset number of field-effect transistors.

[0153] S203 . Determine the slope of the second fitting straight line according to the second total resistance, the number of the preset number of field effect transistors connected in series, and the intersection of the second fitting straight line and the vertical axis.

[0154] S205 . Generate the channel resistance based on the slope and the source-drain parasitic resistance.

[0155] Optionally, in the above step S201, the second total resistance after the preset number of field effect transistors are connected in series can be determined based on the second test resistance and the target resistance, wherein the target resistance can be determined based on the source-drain parasitic resistance, the channel resistance and the number of the preset number of field effect transistors.

[0156] In one embodiment, the target resistance = n(Repi+Rsp+Rch), where n is the number of the preset number of field effect transistors. Accordingly, the second total resistance can be expressed as: Rtotal = n(Repi+Rsp+Rch)+Rres.

[0157] Optionally, in step S203, continue to refer to Figure 14 , since the second total resistance can be expressed as Rtotal=n(Repi+Rsp+Rch)+Rres, and the embodiment of the present application obtains a linear equation (y=kx+b) through linear fitting, wherein y corresponds to Rtotal, k corresponds to Repi+Rsp+Rch, b corresponds to Rres, and n corresponds to x, that is, n can be directly used as the independent variable x, and the coefficient of x Repi+Rsp+Rch can be understood as the slope.

[0158] Optionally, in the above step S205 , the difference between the slope and the source-drain parasitic resistance may be calculated to obtain the channel resistance, and the calculation formula is as follows: Rch=slope−(Repi+Rsp).

[0159] Since the slope of the second fitting line can reflect the sum of the source-drain parasitic resistance and the channel resistance 11, the channel resistance 11 is accurately generated by the slope of the second fitting line and the source-drain parasitic resistance, thereby improving the generation efficiency, generation accuracy, and generation convenience of the channel resistance 11. Thus, by combining the two methods of extracting resistance in the above-mentioned segmented extraction, different components are extracted separately, and then combined with each other to decompose the parasitic resistance of smaller components, the total resistance can be split into three parts: Rmol+Rbeol+Rcon, Repi+Rsp, and Rch, thereby effectively monitoring the source-drain resistance Repi+Rsp.

[0160] The following describes the overall method for processing source-drain parasitic resistance by taking a FinFET as an example, with three different overdrive voltages and three predetermined number of FinFETs connected in series.

[0161] 1. Source-drain parasitic resistance separation

[0162] Divide the FinFET parasitic resistance to be measured into different components (Rbeol, Rmol, Rcon, Repi, Rsp, Rch).

[0163] 2. Design a structure with three FinFET sources and drains connected in series. For details, see Figure 6 .

[0164] 3. Extract the first test resistance

[0165] 1) According to the pre-set series structure, the source and drain of three FinFETs are connected in series, and any FinFET is selected to measure the V T And three overdrive voltages: measure the threshold voltage and three different gate-source voltages, and calculate the difference between the three gate-source voltages and the threshold voltage to obtain three overdrive voltages.

[0166] 2) Extract the drain currents Idlin1, idlin2, and idlin3 of any FinFET at three overdrive voltages (Vod1, Vod2, and Vod3) in the linear region. Using Vd / Idlin=R, calculate the three first total resistances (Rtotal) R1, R2, and R3, where Vod1 / Idlin1=R1, Vod2 / Idlin2=R2, and Vod3 / Idlin3=R3.

[0167] 3) Performing linear fitting on the three calculated first total resistances R1, R2, R3, and 1 / Vod1, 1 / Vod2, 1 / Vod3 to obtain a first fitting straight line, where the coordinates of the intersection point of the first fitting straight line are the first test resistance.

[0168] 4. Extract the second test resistor

[0169] 4) Measure the current data and drain voltage between the source and drain regions of three FinFETs connected in series: Connect one drain region to different drain regions during the test to measure the current between the source region and the different drain regions, as well as the voltage of the different drain regions. Finally, calculate the corresponding second total resistance R1, R2, and R3 using Vd / Id=R, where R1=Vd1 / Id1, R2=Vd2 / Id2, and R3=Vd3 / Id3.

[0170] 5) With the target number as the horizontal axis and the total second resistance as the vertical axis, a linear fit is performed. The intercept on the vertical axis is the sum of all resistances (Rres) excluding the channel resistance (Rch) and the source-drain resistance (Repi + Rsp), i.e., Rres = Rcon + Rmol + Rbeol. The target number is determined based on the predetermined number of field-effect transistors connected in series.

[0171] In addition, since the total resistance can be expressed as Rtotal=n(Repi+Rsp+Rch)+Rres, where n is the number of FinFETs connected in series, the slope can be expressed as (Repi+Rsp+Rch).

[0172] 6) Use Repi + Rsp = Rext – Rres to calculate the source-drain resistance (Repi + Rsp), and use Rch = slope – (Repi + Rsp) to calculate the channel resistance (Rch).

[0173] Therefore, the total resistance can be divided into three parts: Rmol+Rbeol+Rcon, Repi+Rsp, and Rch, so as to effectively detect the source-drain resistance Repi+Rsp.

[0174] It should be noted that the process of extracting the source-drain parasitic resistance of MOSFET is the same as that of extracting the source-drain parasitic resistance of FinFET, and will not be repeated here.

[0175] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0176] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for processing source-drain parasitic resistance, characterized in that: include: Providing a preset number of field effect transistors; Determining a first total resistance of any one of the preset number of field effect transistors under different overdrive voltages; Performing linear fitting on the different over-driving voltages and the first total resistances under the different over-driving voltages to obtain a first test resistance; the first test resistance is determined as a parasitic resistance excluding a channel resistance distributed in the channel; determining a second total resistance when the preset number of field effect transistors are connected in series; Performing linear fitting on the number of the preset number of field effect transistors connected in series and the second total resistance to obtain a second test resistance; the second test resistance is determined as a parasitic resistance other than the channel resistance and the source-drain parasitic resistance; A source-drain parasitic resistance analysis process is performed on the first test resistor and the second test resistor to obtain the source-drain parasitic resistance of the field effect transistor.

2. The method according to claim 1, characterized in that The determining of a first total resistance of any one of the preset number of field effect transistors under different overdrive voltages includes: determining a drain current of any one of the field effect transistors under different overdrive voltages in a linear region; Based on the different over-driving voltages and the drain currents at the different over-driving voltages, a first total resistance at the different over-driving voltages is generated.

3. The method according to claim 2, characterized in that Before determining the drain current of any one of the field effect transistors under different overdrive voltages in the linear region, the method further includes: determining a threshold voltage and a gate-source voltage of any one of the field effect transistors; The different over-driving voltages are generated according to the gate-source voltage and the threshold voltage of any one of the field effect transistors.

4. The method according to claim 2, characterized in that The different over-driving voltages are at least three over-driving voltages.

5. The method according to claim 1, wherein After providing a preset number of field effect transistors, the method further includes: Splitting the parasitic resistance of any one of the field effect transistors into a rear winding resistance, a middle lead resistance, a contact resistance, a source-drain parasitic resistance, and a channel resistance; The performing linear fitting on the different over-driving voltages and the first total resistance under the different over-driving voltages to obtain a first test resistance includes: Using the reciprocals of the different over-driving voltages as first coordinates on a first coordinate axis, and using the first total resistances under the different over-driving voltages as second coordinates on a second coordinate axis; Performing linear fitting on the first coordinate and the second coordinate to obtain a first fitting straight line; generating the first test resistor according to an intersection of the first fitting straight line and the second coordinate axis; The first test resistance is determined by the rear winding resistance, the middle lead resistance, the contact resistance and the source-drain parasitic resistance.

6. The method according to any one of claims 1 to 5, characterized in that The preset number of field effect transistors connected in series include a source region and a preset number of drain regions, and determining a second total resistance when the preset number of field effect transistors are connected in series includes: determining current data between the source region and each drain region and a drain voltage of each drain region when the preset number of field effect transistors are connected in series; A second total resistance corresponding to each field effect transistor is generated according to the current data between the one source region and each drain region and the drain voltage of each drain region.

7. The method according to any one of claims 1 to 5, characterized in that After providing a preset number of field effect transistors, the method further includes: Splitting the parasitic resistance of any one of the field effect transistors into a rear winding resistance, a middle lead resistance, a contact resistance, a source-drain parasitic resistance, and a channel resistance; The performing linear fitting on the number of the preset number of field effect transistors connected in series and the second total resistance to obtain the second test resistance includes: Taking the target number as the third coordinate on the first coordinate axis and taking the second total resistance as the fourth coordinate on the second coordinate axis; the target number is determined based on the number of the preset number of field effect transistors connected in series; Performing linear fitting on the third coordinate and the fourth coordinate to obtain a second fitting straight line; generating the second test resistance according to an intersection of the second fitting straight line and the second coordinate axis; The second test resistance is determined by the rear winding resistance, the middle lead resistance and the contact resistance.

8. The method according to claim 6, characterized in that The number of the preset number of field effect transistors connected in series is at least three.

9. The method according to any one of claims 1 to 5, characterized in that The performing source-drain parasitic resistance analysis on the first test resistor and the second test resistor to obtain the source-drain parasitic resistance of the field effect transistor includes: determining a difference between the first test resistor and the second test resistor; The source-drain parasitic resistance is generated according to a difference between the first test resistor and the second test resistor.

10. The method according to claim 7, characterized in that The method further comprises: Determining the second total resistance is determined based on the second test resistance and a target resistance; the target resistance is determined based on the source-drain parasitic resistance, the channel resistance, and the number of the preset number of field-effect transistors; determining a slope of the second fitting straight line according to the second total resistance, the number of the preset number of field effect transistors connected in series, and an intersection point of the second fitting straight line and the second coordinate axis; The channel resistance is generated based on the slope and the source-drain parasitic resistance.

11. A source-drain parasitic resistance structure of a field effect transistor, the field effect transistor comprising a gate region, a source-drain region, and a lead-out layer, the lead-out layer being in contact with the source-drain region, and one lead-out layer being provided between two adjacent gate regions, characterized in that: The source-drain parasitic resistance structure is applied to the source-drain parasitic resistance processing method according to any one of claims 1 to 10, and the source-drain parasitic resistance includes the back-end winding resistance distributed in the metal interconnect line, the middle lead resistance distributed in the lead-out layer, the contact resistance distributed between the source-drain region and the lead-out layer, the source-drain parasitic resistance distributed in the source-drain region and between the source-drain region and the channel, and the channel resistance distributed in the channel.

12. A test structure, characterized in that: The test structure is used to test the source-drain parasitic resistance of the field-effect transistor according to any one of claims 1 to 10, the test structure comprising a preset number of field-effect transistors connected in series; the field-effect transistor comprising a gate region, a source-drain region, and a lead-out layer, the lead-out layer being in contact with the source-drain region, one lead-out layer being provided between two adjacent gate regions, the length between two adjacent gate regions being one and only one, and the length of the gate region being one and only one; Any one of the preset number of field effect transistors connected in series is used for testing to obtain the first test resistor, and the preset number of field effect transistors connected in series are used for testing to obtain the second test resistor.

13. The test structure according to claim 12, characterized in that The preset number of field effect transistors connected in series include a source region and a preset number of drain regions. The one drain region is used to be connected to different drain regions during testing to test the current between the one source region and the different drain regions.

14. The test structure according to claim 12, characterized in that The number of the preset number of field effect transistors connected in series is at least three.

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