Reconfigurable multi-mode intelligent computing circuit and computing device

Abstract

The invention relates to a reconfigurable multi-mode intelligent computing circuit and computing equipment. The reconfigurable multi-mode intelligent computing circuit comprises a reconfigurable adder circuit which is used for executing any one of the following operations under the control of a control circuit: addition, subtraction, direct connection, accumulation, comparison or cyclic comparison; the reconfigurable memory is used for storing data under the control of the control circuit, or performing numerical value searching under the control of the control circuit; the reconfigurable data path comprises at least one handshake interface unit, and the handshake interface unit is connected with the reconfigurable adder circuit and the reconfigurable memory and used for transmitting data under the control of the control circuit; and the control circuit is used for controlling the reconfigurable adder circuit, the reconfigurable memory and the reconfigurable data path according to the configuration information. By adopting the circuit, the chip area can be effectively reduced, and the power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of digital circuit technology, and in particular to a reconfigurable multi-mode intelligent computing circuit and computing device. Background Art

[0002] In a convolutional neural network, after convolution, post-processing calculations such as batch norm, activation, pooling, and residuals are required. These calculations require a separate circuit structure for each part.

[0003] In the prior art, separately designing computing circuits for post-processing calculations such as batch norm, activation, pooling, and residual in neural networks results in a larger chip area and higher power consumption. Summary of the Invention

[0004] Based on this, it is necessary to provide a reconfigurable multi-mode intelligent computing circuit and computing device that can effectively reduce chip area and lower power consumption.

[0005] In a first aspect, an embodiment of the present application provides a reconfigurable multi-mode intelligent computing circuit, comprising: a reconfigurable adder circuit, the reconfigurable adder circuit being used to perform any of the following operations under the control of a control circuit: addition, subtraction, pass-through, accumulation, comparison, or cyclic comparison; a reconfigurable memory, the reconfigurable memory being used to store data under the control of the control circuit, or to perform numerical lookup under the control of the control circuit; a reconfigurable data path, the reconfigurable data path comprising at least one handshake interface unit, the handshake interface unit being connected to the reconfigurable adder circuit and the reconfigurable memory, and being used to transmit data under the control of the control circuit; and a control circuit, the control circuit being used to control the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path according to configuration information.

[0006] In one embodiment, a reconfigurable adder circuit includes: multiple selection circuits, an adder, a negation circuit, and a register; the selection circuit includes a first selection circuit, a second selection circuit, a third selection circuit, and a fourth selection circuit; the input end of the first selection circuit is respectively connected to the output end of the register and a first data input bus, and the output end of the first selection circuit is respectively connected to the input end of the negation circuit, the input end of the second selection circuit, and the input end of the third selection circuit; the input end of the second selection circuit is respectively connected to the output end of the negation circuit, the output end of the first selection circuit, and the output end of the register, and the output end of the second selection circuit is connected to the input end of the adder; the input end of the third selection circuit is connected to the output end of the first selection circuit, the output end of the adder, and the second data input bus, and the output end of the third selection circuit is connected to the input end of the fourth selection circuit; the input end of the fourth selection circuit is connected to the output end of the adder, the output end of the third selection circuit, and the second data input bus, and the output end of the fourth selection circuit is connected to the input end of the register.

[0007] In one embodiment, the reconfigurable multi-mode intelligent computing circuit further includes a multiplication circuit, which is connected to the reconfigurable data path and the reconfigurable adder circuit; the reconfigurable data path includes a first handshake interface unit, a second handshake interface unit, a third handshake interface unit, a fourth handshake interface unit, a fifth handshake interface unit and a sixth handshake interface unit; the first handshake interface unit is a one-to-many handshake interface unit, the input end of the first handshake interface unit is used to read input data under the control of the control circuit, and the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit and the third handshake interface unit; the second handshake interface unit is a many-to-many handshake interface unit, the input end of the second handshake interface unit is used to read input data under the control of the control circuit, and the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit and the third handshake interface unit; the second handshake interface unit is a many-to-many handshake interface unit, and the input end of the second handshake interface unit is used to read input data under the control of the control circuit. The end is connected to the first coefficient, the input data, the output end of the multiplication circuit and the output end of the sixth handshake interface unit, the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit, and the input end of the second handshake interface unit is used to read at least one of the following data under the control of the control circuit: the first coefficient, the input data, the output data of the multiplication circuit, and the output data of the sixth handshake interface unit; the third handshake interface unit is a many-to-many handshake interface unit, the input end of the third handshake interface unit is connected to the second coefficient, the output end of the first handshake interface unit, the output end of the sixth handshake interface unit and the output end of the reconfigurable adder circuit, and the output end of the third handshake interface unit is connected to the input end of the multiplication circuit , the input end of the third handshake interface unit is used to read at least one of the following data under the control of the control circuit: the second coefficient, the input data, the output data of the sixth handshake interface unit, and the output data of the reconfigurable adder circuit; the fourth handshake interface unit is a many-to-one handshake interface unit, the input end of the fourth handshake interface unit is connected to the output end of the multiplication circuit and the output end of the reconfigurable adder circuit, the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory, and the input end of the fourth handshake interface unit is used to read at least one of the following data under the control of the control circuit: the output data of the multiplication circuit and the output data of the reconfigurable adder circuit; the fifth handshake interface unit is a many-to-one handshake interface unit, The input end of the fifth handshake interface unit is connected to the sixth handshake interface unit, the output end of the multiplication circuit and the output end of the reconfigurable adder circuit. The output end of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit. The input end of the fifth handshake interface unit is used to read at least one of the following data under the control of the control circuit: the output data of the sixth handshake interface unit, the output data of the multiplication circuit, and the output data of the reconfigurable adder circuit; the sixth handshake interface unit is a one-to-many handshake interface unit, the input end of the sixth handshake interface unit is connected to the output end of the reconfigurable memory, and the output end of the sixth handshake interface unit is connected to the second handshake interface unit, the third handshake interface unit and the fifth handshake interface unit.

[0008] In one embodiment, the input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the output end of the first handshake interface unit is connected to the input end of the third handshake interface unit; the input end of the third handshake interface unit is specifically used to read input data and the second coefficient under the control of the control circuit, the output end of the third handshake interface unit is connected to the input end of the multiplication circuit, and the output end of the multiplication circuit is connected to the input end of the second handshake interface unit; the input end of the second handshake interface unit is specifically used to read the output data and the first coefficient of the multiplication circuit under the control of the control circuit, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform an addition operation on the output data of the multiplication circuit and the first coefficient under the control of the control circuit; the input end of the fifth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output end of the fifth handshake interface unit is specifically used to output the output data of the reconfigurable adder circuit, and the output data of the reconfigurable adder circuit is the normalized result of the input data.

[0009] In one embodiment, the input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit, and the input data is preset table data; the input end of the second handshake interface unit is specifically used to read the first coefficient and input data under the control of the control circuit, the first coefficient is 0, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform a pass-through operation under the control of the control circuit; the input end of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, the output data of the reconfigurable adder circuit is the input data, and the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory; the reconfigurable memory is specifically used to store the preset table data under the control of the control circuit.

[0010] In one embodiment, the input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit; the input end of the second handshake interface unit is specifically used to read the first coefficient and input data under the control of the control circuit, the first coefficient is 0, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform an addition operation on the input data and the first coefficient under the control of the control circuit; the input end of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, the output data of the reconfigurable adder circuit is the input data, and the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory; the reconfigurable memory is specifically used to perform a numerical search based on the input data under the control of the control circuit, and the output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit; the input end of the fifth handshake interface unit is specifically used to read the output data of the sixth handshake interface unit under the control of the control circuit, and the output end of the fifth handshake interface unit is used to output a calculation result under the control of the control circuit, and the calculation result is a numerical search result.

[0011] In one embodiment, the input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the third handshake interface unit, and the input data is a first data group; the input end of the third handshake interface unit is specifically used to read input data and a second coefficient under the control of the control circuit, the output end of the third handshake interface unit is connected to the input end of the multiplication circuit, and the output end of the multiplication circuit is connected to the input end of the fourth handshake interface unit; the input end of the fourth handshake interface unit is specifically used to read output data of the multiplication circuit under the control of the control circuit, and the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory; the reconfigurable memory is specifically used to store output data of the multiplication circuit under the control of the control circuit; the input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the multiplication circuit The output end of the handshake interface unit is connected to the input end of the second handshake interface unit, and the input data is a second data group; the reconfigurable memory is also used to search for the output data of the multiplication circuit under the control of the control circuit, and the output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit; the input end of the second handshake interface unit is specifically used to read the input data and the output data of the sixth handshake interface unit under the control of the control circuit, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform a subtraction operation on the input data and the output data of the sixth handshake interface unit under the control of the control circuit; the input end of the fifth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output end of the fifth handshake interface unit is used to output a calculation result under the control of the control circuit, and the calculation result is a residual calculation result.

[0012] In one embodiment, the input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit, and the input data is all data in the target feature map; the input end of the second handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform an accumulation operation on the input data under the control of the control circuit; the input end of the third handshake interface unit is specifically used to read the output result and the first coefficient of the reconfigurable adder circuit under the control of the control circuit, the output end of the third handshake interface unit is connected to the input end of the multiplication circuit, and the first coefficient is determined according to the number of data in the target feature map; the input end of the fifth handshake interface unit is specifically used to read the output data of the multiplication circuit under the control of the control circuit, and the output end of the fifth handshake interface unit is specifically used to output the output data of the multiplication circuit, and the output data of the multiplication circuit is the global average pooling result of the input data.

[0013] In one embodiment, the input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit, and the input data includes a row of data of each pooling window in the target feature map; the input end of the second handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform a cyclic comparison operation on the input data under the control of the control circuit; the input end of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, the output data of the reconfigurable adder circuit is the temporary maximum value or temporary minimum value of each pooling window, the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory; the reconfigurable memory is specifically used to store the temporary maximum value or temporary minimum value of each pooling window under the control of the control circuit.

[0014] In one embodiment, the input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit, and the input data includes the next row of data of each pooling window in the target feature map; the reconfigurable memory is specifically used to find the temporary maximum value or temporary minimum value of each pooling window under the control of the control circuit, and the output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit; the input end of the second handshake interface unit is specifically used to read the input data and the output data of the sixth handshake interface unit under the control of the control circuit, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform a comparison operation on the first value in the input data and the output data of the sixth handshake interface unit under the control of the control circuit, and temporarily store the comparison result in the register, and perform a comparison operation on the first value in the input data and the output data of the sixth handshake interface unit according to the remaining value in the input data and the comparison result. The result performs a cyclic comparison operation; the input end of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output data of the reconfigurable adder circuit is the temporary maximum value or temporary minimum value of each pooling window. The output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory; the reconfigurable memory is specifically used to store the temporary maximum value or temporary minimum value of each pooling window under the control of the control circuit until the data comparison in each pooling window is completed. The reconfigurable memory is specifically used to output the temporary maximum value or temporary minimum value under the control of the control circuit. The output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit; the input end of the fifth handshake interface unit is specifically used to read the output data of the sixth handshake interface unit under the control of the control circuit. The output end of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit, and the calculation result is the maximum pooling result or the minimum pooling result.

[0015] In a second aspect, an embodiment of the present application provides a computing device, which includes the reconfigurable multi-mode intelligent computing circuit described in any one of the first aspects above.

[0016] The reconfigurable multi-mode intelligent computing circuit includes a reconfigurable adder circuit, which is used to perform any of the following operations under the control of a control circuit: addition, subtraction, direct addition, accumulation, comparison, or cyclic comparison; a reconfigurable memory, which is used to store data under the control of the control circuit, or to perform numerical lookup under the control of the control circuit; a reconfigurable data path, which includes at least one handshake interface unit, which is connected to the reconfigurable adder circuit and the reconfigurable memory and is used to transmit data under the control of the control circuit; and a control circuit, which is used to control the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path according to configuration information. By configuring the handshake interface, the reconfigurable adder circuit, and the reconfigurable memory in the data path through the control circuit, the direction of data flow is changed, and the circuit can flexibly switch to any computing mode without requiring a separate computing circuit for each post-processing. This effectively reduces chip area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a schematic diagram of a reconfigurable multi-mode intelligent computing circuit in one embodiment;

[0019] Figure 2 A schematic diagram of the structure of a one-to-many handshake interface unit in one embodiment;

[0020] Figure 3 A schematic diagram of the structure of a many-to-one handshake interface unit in one embodiment;

[0021] Figure 4 A schematic diagram of the structure of a many-to-many handshake interface unit in one embodiment;

[0022] Figure 5 is a schematic diagram of a reconfigurable memory in one embodiment;

[0023] Figure 6 is a schematic diagram of a reconfigurable adder circuit in one embodiment;

[0024] Figure 7 A schematic diagram of a reconfigurable multi-mode intelligent computing circuit for performing normalization calculations in one embodiment;

[0025] Figure 8A schematic diagram of a reconfigurable multi-mode intelligent computing circuit for performing activation computing in one embodiment;

[0026] Figure 9 is a schematic diagram of a reconfigurable multi-mode intelligent computing circuit for performing residual calculation in one embodiment;

[0027] Figure 10 Schematic diagram of a reconfigurable multi-mode intelligent computing circuit for performing global mean pooling calculations in one embodiment;

[0028] Figure 11 Schematic diagram of a reconfigurable multi-mode intelligent computing circuit that performs maximum pooling or minimum pooling calculations in one embodiment. DETAILED DESCRIPTION

[0029] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0031] It will be understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor without departing from the scope of this application. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0032] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0033] It is understood that “at least one” refers to one or more, “a plurality” refers to two or more, and “at least a portion of an element” refers to a portion or all of an element.

[0034] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0035] In a convolutional neural network, after convolution, post-processing calculations such as batch norm, activation, pooling, and residuals are required. These calculations require a separate circuit structure for each part.

[0036] In the prior art, separately designing computing circuits for post-processing calculations such as batch norm, activation, pooling, and residuals in neural networks results in a larger chip area and higher power consumption.

[0037] In view of this, an embodiment of the present application provides a reconfigurable multi-mode intelligent computing circuit that can effectively reduce chip area and lower power consumption.

[0038] In an exemplary embodiment, Figure 1 As shown, a reconfigurable multi-mode intelligent computing circuit 10 is provided. The reconfigurable multi-mode intelligent computing circuit 10 includes a reconfigurable adder circuit 100, a reconfigurable memory 200, a reconfigurable data path 300, and a control circuit 400. The reconfigurable adder circuit 100 is configured to perform any of the following operations under the control of the control circuit 400: addition, subtraction, pass-through, accumulation, comparison, or cyclic comparison. The reconfigurable memory 200 is configured to store data or perform value lookup under the control of the control circuit 400. The reconfigurable data path 300 includes at least one handshake interface unit, which is connected to both the reconfigurable adder circuit and the reconfigurable memory and is configured to transmit data under the control of the control circuit 400. The control circuit 400 is configured to control the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path according to configuration information.

[0039] Optionally, the control circuit may receive external configuration information and control the reconfigurable adder circuit, the reconfigurable memory and the reconfigurable data path according to the configuration information.

[0040] In one possible implementation, the configuration information may be a configuration instruction, indicating a function that needs to be implemented by the reconfigurable multi-mode intelligent computing circuit. For example, the configuration information may be to configure the reconfigurable multi-mode intelligent computing circuit to implement normalized calculation, or to configure the reconfigurable multi-mode intelligent computing circuit to implement pooled calculation. The control circuit may determine the configuration sub-information of the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path based on the configuration instruction.

[0041] In another possible implementation, the configuration information may include multiple configuration sub-information, corresponding to the configuration of the reconfigurable adder circuit, the reconfigurable memory and the reconfigurable data path respectively. For example, the configuration information may include configuring the reconfigurable adder circuit to implement addition operations, configuring the reconfigurable memory to store data, etc.

[0042] Optionally, the handshake interface unit may be an interface mechanism based on a handshake protocol, used to transmit data between the reconfigurable adder, the reconfigurable memory, the input interface, and the output interface, and the data transmission is controlled by the handshake protocol. The handshake protocol may include the following signals: a valid signal, a ready signal, a request signal, and an acknowledge signal. The sender pulls high the valid signal to indicate that the data is valid, and the receiver pulls high the ready signal to indicate that it is ready to receive data. The sender sends a request signal to indicate that it wishes to send data, and the receiver sends an acknowledge signal to indicate that it has successfully received the data.

[0043] Optionally, when transmitting data from a data source to a destination, the handshake interface unit may include a one-to-many handshake interface unit, a many-to-one handshake interface unit, and a many-to-many handshake interface unit.

[0044] Optionally, the handshake interface unit includes a data bus and at least one selection circuit.

[0045] For example, Figure 2 As shown, the one-to-many handshake interface unit can transmit data from one data source to multiple destinations, and one destination can receive the data during the transmission process; Figure 3 As shown, the many-to-one handshake interface unit can transmit data from multiple data sources to one destination end, and during the transmission process, the data of one data source can be transmitted to the destination end; Figure 4 As shown, the many-to-many handshake interface unit can transmit data from multiple data sources to multiple destinations, and can perform multiple one-to-one pairings and transmit simultaneously during the transmission process.

[0046] Optionally, the reconfigurable memory includes a selection circuit and a memory, such as Figure 5As shown, the input end of the selection circuit is connected to the address bus or the write data bus, the output end of the selection circuit is connected to the address control signal of the memory, and the write data end of the memory is connected to the write data bus.

[0047] For example, when the reconfigurable memory stores data under the control of the control circuit, that is, when the reconfigurable memory is in memory mode, the selection circuit selects to connect to the address bus under the control of the control circuit, the data is loaded by the write data bus, and the read data is output by the read data bus, and the read and write enable end of the memory controls the memory to perform read and write operations.

[0048] For example, when the reconfigurable memory searches for data under the control of the control circuit, that is, when the reconfigurable memory is in search mode, the selection circuit chooses to connect to the write data bus under the control of the control circuit, and the read and write enable end of the memory controls the memory to perform read operations. When write data is input, the data at the corresponding address location is read out and output by the read data bus.

[0049] The reconfigurable multi-mode intelligent computing circuit includes a reconfigurable adder circuit, which is used to perform any of the following operations under the control of a control circuit: addition, subtraction, direct addition, accumulation, comparison, or cyclic comparison; a reconfigurable memory, which is used to store data under the control of the control circuit, or to perform numerical lookup under the control of the control circuit; a reconfigurable data path, which includes at least one handshake interface unit, which is connected to the reconfigurable adder circuit and the reconfigurable memory and is used to transmit data under the control of the control circuit; and a control circuit, which is used to control the reconfigurable adder circuit, the reconfigurable memory, and the reconfigurable data path according to configuration information. By configuring the handshake interface, the reconfigurable adder circuit, and the reconfigurable memory in the data path through the control circuit, the direction of data flow is changed, and the circuit can flexibly switch to any computing mode without requiring a separate computing circuit for each post-processing. This effectively reduces chip area and power consumption.

[0050] In an exemplary embodiment, Figure 6 As shown, the reconfigurable adder circuit includes: multiple selection circuits, adders, negation circuits and registers.

[0051] Optionally, the selection circuit may be a multiplexer that selects one of the multiple input signals as an output according to the control of the control circuit.

[0052] Optional, such as Figure 6As shown, the selection circuit includes a first selection circuit Mux0, a second selection circuit Mux1, a third selection circuit Mux2, and a fourth selection circuit Mux3; the input end of the first selection circuit Mux0 is respectively connected to the output end of the register and the first data input bus, and the output end of the first selection circuit Mux0 is respectively connected to the input end of the negation circuit, the input end of the second selection circuit Mux1, and the input end of the third selection circuit Mux2; the input end of the second selection circuit Mux1 is respectively connected to the output end of the negation circuit, the output end of the first selection circuit Mux0, and the output end of the register, and the output end of the second selection circuit Mux1 is connected to the input end of the adder; the input end of the third selection circuit Mux2 is connected to the output end of the first selection circuit Mux0, the output end of the adder, and the second data input bus, and the output end of the third selection circuit Mux2 is connected to the input end of the fourth selection circuit Mux3; the input end of the fourth selection circuit Mux3 is connected to the output end of the adder, the output end of the third selection circuit Mux2, and the second data input bus, and the output end of the fourth selection circuit Mux3 is connected to the input end of the register.

[0053] Optionally, the process of the reconfigurable adder performing different operations under the control of the control circuit is described below in conjunction with the structural diagram of the reconfigurable adder circuit.

[0054] When the reconfigurable adder performs an addition operation, input terminal 0 of the first selection circuit Mux0 is connected to the first data input bus, the output terminal of the first selection circuit Mux0 is connected to input terminal 2 of the second selection circuit Mux1, the output terminal of the second selection circuit Mux1 is connected to the input terminal of the adder, the input terminal of the adder is also connected to the second data input bus, the output terminal of the adder is connected to input terminal 0 of the fourth selection circuit Mux3, and the output terminal of the fourth selection circuit Mux3 is connected to the input terminal of the register. In this way, the reconfigurable adder can perform an addition operation on the data of the first data input bus and the data of the second data input bus, and the calculated sum is stored in the register and output.

[0055] When the reconfigurable adder performs a subtraction operation, input terminal No. 0 of the first selection circuit Mux0 is connected to the first data input bus, and the output terminal of the first selection circuit Mux0 is connected to the input terminal of the negation circuit, and a negation operation is performed on the data of the first data input bus. The output terminal of the negation circuit is connected to input terminal No. 1 of the second selection circuit Mux1, and the output terminal of the second selection circuit Mux1 is connected to the input terminal of the adder. The input terminal of the adder is also connected to the second data input bus. The output terminal of the adder is connected to input terminal No. 0 of the fourth selection circuit Mux3, and the output terminal of the fourth selection circuit Mux3 is connected to the input terminal of the register. In this way, the reconfigurable adder can calculate the data of the second data input bus minus the data of the first data input bus, and store the difference in the register and output it.

[0056] When the reconfigurable adder performs a pass-through operation, input terminal 2 of the third selection circuit Mux4 is connected to the second data input bus, and the output terminal of the third selection circuit Mux4 is connected to the input terminal of the register, so that the data of the second data input bus can be directly stored in the register.

[0057] When the reconfigurable adder performs an accumulation operation, the reconfigurable adder can be first configured to perform a pass-through operation, store the first value in the register, and then configure the reconfigurable adder to perform the addition operation, connect the output end of the register to the No. 0 input end of the second selection circuit Mux1, connect the output end of the second selection circuit to the input end of the adder, and the input end of the adder is also connected to the second selection input bus. An addition operation is performed on the data input by the second selection input bus and the data in the register output, the output end of the adder is connected to the No. 0 input end of the fourth selection circuit Mux3, and the output end of the fourth selection circuit Mux3 is connected to the input end of the register. Repeat the above process to connect the output end of the register to the input end of the second selection circuit Mux1 to perform the accumulation operation.

[0058] When the reconfigurable adder performs a comparison operation, the reconfigurable adder can be first configured to perform a subtraction operation, compare the data of the first data input bus and the second data input bus, and connect the output end of the adder to the control end of the third selection circuit Mux2. When comparing the maximum value, if the sign bit of the output end of the adder is positive, the input end 1 of the third selection circuit Mux2 is connected to the second data input bus, the output end of the third selection circuit Mux2 is connected to the input end 1 of the fourth selection circuit Mux3, and the output end of the fourth selection circuit Mux3 is connected to the input end of the register, that is, the larger value is the data of the second data input bus; if the sign bit of the output end of the adder is negative, the input end 0 of the third selection circuit Mux2 is connected to the output end of the first selection circuit Mux0, the input end 0 of the first selection circuit Mux0 is connected to the first data input bus, the output end of the third selection circuit Mux2 is connected to the input end 1 of the fourth selection circuit Mux3, and the output end of the fourth selection circuit Mux3 is connected to the input end of the register, that is, the larger value is the data of the first data input bus. When comparing the minimum values, if the sign bit at the adder output is positive, the third selection circuit Mux2 selects the data from the first data input bus and inputs it to the input of the fourth selection circuit Mux3; if the sign bit at the adder output is negative, the third selection circuit Mux2 selects the data from the second data input bus and inputs it to the input of the fourth selection circuit Mux3.

[0059] When the reconfigurable adder performs a cyclic comparison operation, a group of data can be input through the second data input bus. The reconfigurable adder is first configured to perform a pass-through operation, and the first data is stored in the register in the pass-through mode. The output end of the register is connected to the input end No. 1 of the first selection circuit Mux0. Then, the reconfigurable adder is configured to perform a comparison operation, and the first data is compared with the second data. The comparison result is stored in the register, and iterative comparison is performed until the comparison of a group of data is completed.

[0060] By controlling the selection circuits through the controller and adjusting the data transmission direction, the reconfigurable adder circuit can perform any operation such as addition, subtraction, direct addition, accumulation, comparison or cyclic comparison.

[0061] In an exemplary embodiment, Figure 7 As shown, a multiplication circuit is also included, and the multiplication circuit is connected to the reconfigurable data path and the reconfigurable adder circuit.

[0062] Optional, such as Figure 7As shown, the reconfigurable data path includes a first handshake interface unit, a second handshake interface unit, a third handshake interface unit, a fourth handshake interface unit, a fifth handshake interface unit and a sixth handshake interface unit; the first handshake interface unit is a one-to-many handshake interface unit, the input end of the first handshake interface unit is used to read input data under the control of the control circuit, and the output end of the first handshake interface unit is connected to the input ends of the second handshake interface unit and the third handshake interface unit; the second handshake interface unit is a many-to-many handshake interface unit, the input end of the second handshake interface unit is connected to the first coefficient, input data, the output end of the multiplication circuit and the output end of the sixth handshake interface unit, The output end of the handshake interface unit is connected to the input end of the reconfigurable adder circuit, and the input end of the second handshake interface unit is used to read at least one of the following data under the control of the control circuit: the first coefficient, the input data, the output data of the multiplication circuit, and the output data of the sixth handshake interface unit; the third handshake interface unit is a many-to-many handshake interface unit, and the input end of the third handshake interface unit is connected to the second coefficient, the output end of the first handshake interface unit, the output end of the sixth handshake interface unit, and the output end of the reconfigurable adder circuit, the output end of the third handshake interface unit is connected to the input end of the multiplication circuit, and the input end of the third handshake interface unit is used to read under the control of the control circuit. At least one of the following data: a second coefficient, input data, output data of the sixth handshake interface unit, and output data of the reconfigurable adder circuit; the fourth handshake interface unit is a many-to-one handshake interface unit, the input end of the fourth handshake interface unit is connected to the output end of the multiplication circuit and the output end of the reconfigurable adder circuit, the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory, and the input end of the fourth handshake interface unit is used to read at least one of the following data under the control of the control circuit: the output data of the multiplication circuit and the output data of the reconfigurable adder circuit; the fifth handshake interface unit is a many-to-one handshake interface unit, the input end of the fifth handshake interface unit is connected to the first The six handshake interface units, the output ends of the multiplication circuit and the output end of the reconfigurable adder circuit are all connected. The output end of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit. The input end of the fifth handshake interface unit is used to read at least one of the following data under the control of the control circuit: the output data of the sixth handshake interface unit, the output data of the multiplication circuit, and the output data of the reconfigurable adder circuit; the sixth handshake interface unit is a one-to-many handshake interface unit, the input end of the sixth handshake interface unit is connected to the output end of the reconfigurable memory, and the output end of the sixth handshake interface unit is connected to the second handshake interface unit, the third handshake interface unit and the fifth handshake interface unit.

[0063] Optional, such as Figure 7As shown, reconfigurable data can switch data paths under the control of the control circuit. When the configuration information changes with the data information, the data path is a dynamic path. When the configuration information is static, that is, the data path no longer changes within a period of time, it is a static path. Any handshake interface unit in the embodiment of the present application supports both static and dynamic configurations.

[0064] Optionally, each handshake interface unit determines which type of data to read under the control of the control circuit.

[0065] The following describes the process of the reconfigurable multi-mode intelligent computing circuit executing different mode calculations under the control of the control circuit, in conjunction with the circuit schematic diagram of the reconfigurable multi-mode intelligent computing circuit.

[0066] In an exemplary embodiment, when performing normalization calculations, such as Figure 7 As shown, exemplarily, the input end of the first handshake interface unit HS-S-MUX0 is specifically used to read input data under the control of the control circuit, and the output end (output end No. 1) of the first handshake interface unit HS-S-MUX0 is connected to the input end (input end No. 1) of the third handshake interface unit HS-SD-MUX2; the input end of the third handshake interface unit HS-SD-MUX2 is specifically used to read input data and the second coefficient (input end No. 1 reads input data, and input end No. 0 reads the second coefficient) under the control of the control circuit, the output end (output end No. 0 and output end No. 1) of the third handshake interface unit HS-SD-MUX2 is connected to the input end of the multiplication circuit, and the output end of the multiplication circuit is connected to the input end (input end No. 2) of the second handshake interface unit HS-SD-MUX1; the second handshake interface unit The input end of HS-SD-MUX1 is specifically used to read the output data and the first coefficient of the multiplication circuit under the control of the control circuit (input end No. 2 reads the input data, and input end No. 0 reads the first coefficient), and the output end (output end No. 0 and output end No. 1) of the second handshake interface unit HS-SD-MUX1 is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform an addition operation on the output data of the multiplication circuit and the first coefficient under the control of the control circuit; the input end (input end No. 1) of the fifth handshake interface unit HS-D-MUX4 is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output end of the fifth handshake interface unit is specifically used to output the output data of the reconfigurable adder circuit, and the output data of the reconfigurable adder circuit is the normalized result of the input data.

[0067] Alternatively, the normalized calculation formula can be expressed as , the second coefficient is , the first coefficient is , For input data, is the output data of the reconstructed adder circuit.

[0068] In an exemplary embodiment, when performing activation calculations, complex activation functions such as sigmoid and tanh exist in the post-processing calculation process of the neural network. If the calculation is performed directly, a large amount of computing resources will be required. However, the direct mapping method based on the lookup table is easier to implement. When calculating the activation value, the lookup table is used for mapping, which can be divided into two processes. First, the lookup table is stored in the memory, and then the data to be processed is input as the address into the address bus of the memory for search.

[0069] Exemplarily, when the lookup table is stored in the memory, as shown in FIG. Figure 8 As shown, the input end of the first handshake interface unit HS-S-MUX0 is specifically used to read input data under the control of the control circuit. The output end (output end 0) of the first handshake interface unit HS-S-MUX0 is connected to the input end (input end 1) of the second handshake interface unit HS-SD-MUX1. The input data is the preset table data. The input end of the second handshake interface unit HS-SD-MUX1 is specifically used to read the first coefficient and input data under the control of the control circuit (input end 0 reads the first coefficient, and input end 1 reads the input data). The first coefficient is 0. The output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform a pass-through operation under the control of the control circuit; the input end (input end No. 1) of the fourth handshake interface unit HS-D-MUX3 is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output data of the reconfigurable adder circuit is the input data. The output end of the fourth handshake interface unit HS-D-MUX3 is connected to the input end of the reconfigurable memory; the reconfigurable memory is specifically used to store preset table data under the control of the control circuit.

[0070] For example, when the data to be processed is input as an address into the address bus of the memory for searching, as shown in FIG. Figure 8As shown, at this time, the input data is the data to be calculated, rather than the preset table data. The input end of the first handshake interface unit HS-S-MUX0 is specifically used to read the input data under the control of the control circuit. The output end (output end 0) of the first handshake interface unit HS-S-MUX0 is connected to the input end (input end 1) of the second handshake interface unit HS-SD-MUX1; the input end of the second handshake interface unit HS-SD-MUX1 is specifically used to read the first coefficient and input data under the control of the control circuit (input end 0 reads the first coefficient, input end 1 reads the input data), the first coefficient is 0, the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform an addition operation on the input data and the first coefficient under the control of the control circuit; the fourth handshake interface unit HS- The input end (input end No. 1) of D-MUX3 is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit. The output data of the reconfigurable adder circuit is the input data. The output end of the fourth handshake interface unit HS-D-MUX3 is connected to the input end of the reconfigurable memory; the reconfigurable memory is specifically used to perform numerical search according to the input data under the control of the control circuit. The output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit HS-S-MUX5; the input end (input end No. 2) of the fifth handshake interface unit HS-D-MUX4 is specifically used to read the output data of the sixth handshake interface unit HS-D-MUX5 under the control of the control circuit. The output end of the fifth handshake interface unit HS-D-MUX4 is used to output the calculation result under the control of the control circuit. The calculation result is the numerical search result.

[0071] In an exemplary embodiment, when performing residual calculation, it is necessary to sequentially subtract the first feature map FmapA from the second feature map FmapB. The calculation formula can be expressed as: ,in, is a constant value. The feature map can be divided into multiple groups of data according to the depth of the reconfigurable memory. The length of each group of data does not exceed the depth of the reconfigurable memory. When performing residual calculation, it can be divided into two processes. The first step is to input a group of data (the first data group) of the second feature map FmapB into the multiplier through the first handshake interface unit and the third handshake interface unit. The third handshake interface unit reads the input data and the second coefficient and outputs them to the multiplier for multiplication operation. , and is output from the output end of the multiplier, input into the reconfigurable memory through the fourth handshake interface unit, and the processing result corresponding to the first data group is stored; in the second step, a group of data (the second data group) of the first feature map FmapA is input into the storable adder circuit through the first handshake interface unit and the second handshake interface unit, the storable adder performs a subtraction operation, reads the processing result of the first data group from the reconfigurable memory, and inputs into the storable adder circuit through the sixth handshake interface unit and the second handshake interface unit, subtracts the two groups of data in turn, and outputs the subtraction result through the fifth handshake node unit.

[0072] Among them, a group of data of the feature map FmapA and a group of data of the feature map FmapB have the same position in the two feature maps.

[0073] For example, when processing a set of data of the second feature map, as Figure 9 As shown, the input end of the first handshake interface unit HS-S-MUX0 is specifically used to read input data under the control of the control circuit. The output end (output end 1) of the first handshake interface unit HS-S-MUX0 is connected to the input end (input end 1) of the third handshake interface unit HS-SD-MUX2, and the input data is the first data group. The input end of the third handshake interface unit HS-SD-MUX2 is specifically used to read the input data and the second coefficient (input end 0 reads the first coefficient, and input end 1 reads the input data) under the control of the control circuit. The output end of the third handshake interface unit HS-SD-MUX2 is connected to the input end of the multiplication circuit, and the output end of the multiplication circuit is connected to the input end (input end 0) of the fourth handshake interface unit HS-SD-MUX3. The input end (input end 0) of the fourth handshake interface unit HS-D-MUX3 is specifically used to read the output data of the multiplication circuit under the control of the control circuit. The output end of the fourth handshake interface unit HS-D-MUX3 is connected to the input end of the reconfigurable memory. The reconfigurable memory is specifically used to store the output data of the multiplication circuit under the control of the control circuit.

[0074] Exemplarily, when performing a subtraction operation, the input end of the first handshake interface unit HS-S-MUX0 is specifically used to read input data under the control of the control circuit, the output end (output end 0) of the first handshake interface unit HS-S-MUX0 is connected to the input end (input end 1) of the second handshake interface unit HS-SD-MUX1, and the input data is the second data group; the reconfigurable memory is also used to search for the output data of the multiplication circuit under the control of the control circuit, and the output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit HS-DMUX5; the input end of the second handshake interface unit HS-SD-MUX1 is specifically used to read the input data and the sixth handshake interface unit under the control of the control circuit. The output data of the reconfigurable adder circuit is read (input terminal No. 1 reads input data, input terminal No. 3 is connected to output terminal No. 0 of the sixth handshake interface unit to read output data), the output terminal of the second handshake interface unit HS-SD-MUX1 is connected to the input terminal of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform a subtraction operation on the input data and the output data of the sixth handshake interface unit under the control of the control circuit; the input terminal (input terminal No. 1) of the fifth handshake interface unit HS-D-MUX4 is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output terminal of the fifth handshake interface unit HS-D-MUX4 is used to output a calculation result under the control of the control circuit, and the calculation result is a residual calculation result.

[0075] In an exemplary embodiment, when performing pooling calculations, since the pooling calculations in the neural network post-processing calculation process include maximum pooling, minimum pooling, and mean pooling operations on the target feature map, pooling calculations of sliding windows and pooling calculations of global windows can be performed. When the sliding window is one, it can be understood as a global window.

[0076] Optionally, mean pooling can be performed by cumulatively summing all eigenvalues in the sliding window and then multiplying by a constant to obtain the mean pooling result. The constant is the inverse of the number of eigenvalues in the sliding window. For example, Figure 10 As shown, taking one sliding window as an example, the input end of the first handshake interface unit HS_S_MUX0 is specifically used to read input data under the control of the control circuit, the output end (output end 0) of the first handshake interface unit HS_S_MUX0 is connected to the input end (input end 1) of the second handshake interface unit HS_SD_MUX1, and the input data is all data in the target feature map; the input end of the second handshake interface unit HS_SD_MUX1 is specifically used to read input data under the control of the control circuit, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit;

[0077] The reconfigurable adder circuit is specifically used to perform an addition operation on the input data under the control of the control circuit; the input end of the third handshake interface unit HS_SD_MUX2 is specifically used to read the output result and the first coefficient of the reconfigurable adder circuit under the control of the control circuit (input end No. 0 reads the first coefficient, and input end No. 2 reads the output result of the reconfigurable adder circuit), the output end of the third handshake interface unit HS_SD_MUX2 is connected to the input end of the multiplication circuit, and the first coefficient is determined according to the number of data in the target feature map; the input end (output end No. 0) of the fifth handshake interface unit HS_D_MUX4 is specifically used to read the output data of the multiplication circuit under the control of the control circuit, the output end of the fifth handshake interface unit HS_D_MUX4 is specifically used to output the output data of the multiplication circuit, and the output data of the multiplication circuit is the global average pooling result of the input data.

[0078] Among them, the first coefficient is the reciprocal of the number of data in the target feature map.

[0079] Optionally, when performing maximum pooling or minimum pooling on the target feature map, the maximum value or minimum value of each window in the sliding window can be determined by first determining the temporary maximum value or temporary minimum value in the first row of data in the sliding window, storing the temporary maximum value or temporary minimum value in a reconfigurable memory, and then comparing the obtained temporary maximum value or temporary minimum value with the second row of data in the sliding window until all rows in the window are compared.

[0080] For example, Figure 11As shown, taking 3 sliding windows as an example, when determining the temporary maximum value or the temporary minimum value, the input end of the first handshake interface unit HS_S_MUX0 is specifically used to read the input data under the control of the control circuit, and the output end (output end 0) of the first handshake interface unit HS_S_MUX0 is connected to the input end (input end 1) of the second handshake interface unit HS_SD_MUX1, and the input data includes a row of data of each pooling window in the target feature map; the input end (input end 1) of the second handshake interface unit HS_SD_MUX1 is specifically used to read the input data under the control of the control circuit, and the second handshake interface unit HS_SD_MUX1 The output end of X1 is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform a cyclic comparison operation on the input data under the control of the control circuit; the input end (input end No. 1) of the fourth handshake interface unit HS_D_MUX3 is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output data of the reconfigurable adder circuit is the temporary maximum value or temporary minimum value of each pooling window. The output end of the fourth handshake interface unit HS_D_MUX3 is connected to the input end of the reconfigurable memory; the reconfigurable memory is specifically used to store the temporary maximum value or temporary minimum value of each pooling window under the control of the control circuit.

[0081] Optional, such as Figure 11 As shown, addresses 0, 1, and 2 sequentially store the temporary maximum value or temporary minimum value calculated by each sliding window.

[0082] Optionally, after the cyclic comparison of the first row of data in each sliding window is completed, it is necessary to compare the temporary maximum value or temporary minimum value of the first row of data with the temporary maximum value or temporary minimum value of the other rows of data.

[0083] For example, Figure 11As shown, the input end of the first handshake interface unit HS_S_MUX0 is specifically used to read input data under the control of the control circuit, the output end (output end 0) of the first handshake interface unit HS_S_MUX0 is connected to the input end (input end 1) of the second handshake interface unit HS_SD_MUX1, and the input data includes the next row of data of each pooling window in the target feature map; the reconfigurable memory is specifically used to find the temporary maximum value or temporary minimum value of each pooling window under the control of the control circuit, and the output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit HS_D_MUX5; The input end of the second handshake interface unit HS_SD_MUX1 is specifically used to read the input data and the output data of the sixth handshake interface unit under the control of the control circuit (input end 1 reads the input data, input end 3 is connected to output end 0 of the sixth handshake interface unit to read the output data), and the output end of the second handshake interface unit HS_SD_MUX1 is connected to the input end of the reconfigurable adder circuit; the reconfigurable adder circuit is specifically used to perform a comparison operation on the first value in the input data and the output data of the sixth handshake interface unit HS_D_MUX5 under the control of the control circuit, and temporarily store the comparison result. The memory is stored in the register, and a cyclic comparison operation is performed according to the residual value in the input data and the comparison result; the input end (input end 1) of the fourth handshake interface unit HS_D_MUX5 is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output data of the reconfigurable adder circuit is the temporary maximum value or temporary minimum value of each pooling window. The output end of the fourth handshake interface unit HS_D_MUX3 is connected to the input end of the reconfigurable memory; the reconfigurable memory is specifically used to store the temporary maximum value or temporary minimum value of each pooling window under the control of the control circuit until the data in each pooling window is According to the comparison, the reconfigurable memory is specifically used to output a temporary maximum value or a temporary minimum value under the control of the control circuit, and the output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit HS_D_MUX5; the input end (input end No. 2) of the fifth handshake interface unit HS_D_MUX4 is specifically used to read the output data (output end No. 2) of the sixth handshake interface unit HS_D_MUX5 under the control of the control circuit, and the output end of the fifth handshake interface unit HS_D_MUX4 is used to output the calculation result under the control of the control circuit, and the calculation result is the maximum pooling result or the minimum pooling result.

[0084] In one embodiment, the present application provides a computing device, which includes the reconfigurable multi-mode intelligent computing circuit described in any one of the above embodiments.

[0085] In the description of this specification, reference to the terms "some embodiments" or "other embodiments" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0086] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A reconfigurable multi-mode intelligent computing circuit, characterized in that: include: A reconfigurable adder circuit, the reconfigurable adder circuit being configured to perform any of the following operations under the control of a control circuit: addition, subtraction, pass-through, accumulation, comparison, or cyclic comparison; a reconfigurable memory, the reconfigurable memory being used to store data under the control of a control circuit, or to perform value lookup under the control of the control circuit; A reconfigurable data path, the reconfigurable data path comprising at least one handshake interface unit, the handshake interface unit being connected to both the reconfigurable adder circuit and the reconfigurable memory, and being configured to transmit data under the control of a control circuit; A control circuit is used to control the reconfigurable adder circuit, the reconfigurable memory and the reconfigurable data path according to configuration information.

2. The reconfigurable multi-mode intelligent computing circuit according to claim 1, characterized in that: The reconfigurable adder circuit includes: a plurality of selection circuits, an adder, a negation circuit and a register; The selection circuit includes a first selection circuit, a second selection circuit, a third selection circuit and a fourth selection circuit; The input end of the first selection circuit is connected to the output end of the register and the first data input bus respectively, and the output end of the first selection circuit is connected to the input end of the negation circuit, the input end of the second selection circuit and the input end of the third selection circuit respectively; The input end of the second selection circuit is connected to the output end of the negation circuit, the output end of the first selection circuit and the output end of the register respectively, and the output end of the second selection circuit is connected to the input end of the adder; The input end of the third selection circuit is connected to the output end of the first selection circuit, the output end of the adder and the second data input bus, and the output end of the third selection circuit is connected to the input end of the fourth selection circuit; An input end of the fourth selection circuit is connected to an output end of the adder, an output end of the third selection circuit, and the second data input bus, and an output end of the fourth selection circuit is connected to an input end of the register.

3. The reconfigurable multi-mode intelligent computing circuit according to any one of claims 1 to 2, characterized in that: Also included is a multiplication circuit, wherein the multiplication circuit is connected to both the reconfigurable data path and the reconfigurable adder circuit; The reconfigurable data path includes a first handshake interface unit, a second handshake interface unit, a third handshake interface unit, a fourth handshake interface unit, a fifth handshake interface unit and a sixth handshake interface unit; The first handshake interface unit is a one-to-many handshake interface unit, the input end of the first handshake interface unit is used to read input data under the control of the control circuit, and the output end of the first handshake interface unit is connected to the input ends of the second handshake interface unit and the third handshake interface unit; The second handshake interface unit is a many-to-many handshake interface unit, an input end of the second handshake interface unit is connected to the first coefficient, input data, the output end of the multiplication circuit and the output end of the sixth handshake interface unit, an output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit, and the input end of the second handshake interface unit is used to read at least one of the following data under the control of the control circuit: the first coefficient, input data, output data of the multiplication circuit, and output data of the sixth handshake interface unit; The third handshake interface unit is a many-to-many handshake interface unit, an input end of the third handshake interface unit is connected to the second coefficient, the output end of the first handshake interface unit, the output end of the sixth handshake interface unit and the output end of the reconfigurable adder circuit, the output end of the third handshake interface unit is connected to the input end of the multiplication circuit, and the input end of the third handshake interface unit is used to read at least one of the following data under the control of the control circuit: the second coefficient, input data, output data of the sixth handshake interface unit, and output data of the reconfigurable adder circuit; The fourth handshake interface unit is a many-to-one handshake interface unit, an input end of the fourth handshake interface unit is connected to both the output end of the multiplication circuit and the output end of the reconfigurable adder circuit, an output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory, and the input end of the fourth handshake interface unit is used to read at least one of the following data under the control of the control circuit: output data of the multiplication circuit and output data of the reconfigurable adder circuit; The fifth handshake interface unit is a many-to-one handshake interface unit, an input end of the fifth handshake interface unit is connected to the sixth handshake interface unit, an output end of the multiplication circuit, and an output end of the reconfigurable adder circuit, the output end of the fifth handshake interface unit is used to output a calculation result under the control of the control circuit, and the input end of the fifth handshake interface unit is used to read at least one of the following data under the control of the control circuit: output data of the sixth handshake interface unit, output data of the multiplication circuit, and output data of the reconfigurable adder circuit; The sixth handshake interface unit is a one-to-many handshake interface unit, the input end of the sixth handshake interface unit is connected to the output end of the reconfigurable memory, and the output end of the sixth handshake interface unit is connected to the second handshake interface unit, the third handshake interface unit and the fifth handshake interface unit.

4. The reconfigurable multi-mode intelligent computing circuit according to claim 3, characterized in that: The input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the output end of the first handshake interface unit is connected to the input end of the third handshake interface unit; The input end of the third handshake interface unit is specifically used to read the input data and the second coefficient under the control of the control circuit, the output end of the third handshake interface unit is connected to the input end of the multiplication circuit, and the output end of the multiplication circuit is connected to the input end of the second handshake interface unit; The input end of the second handshake interface unit is specifically used to read the output data of the multiplication circuit and the first coefficient under the control of the control circuit, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; The reconfigurable adder circuit is specifically configured to perform an addition operation on the output data of the multiplication circuit and the first coefficient under the control of the control circuit; The input end of the fifth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output end of the fifth handshake interface unit is specifically used to output the output data of the reconfigurable adder circuit, and the output data of the reconfigurable adder circuit is the normalized result of the input data.

5. The reconfigurable multi-mode intelligent computing circuit according to claim 3, characterized in that: The input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit, and the input data is preset table data; The input end of the second handshake interface unit is specifically used to read the first coefficient and input data under the control of the control circuit, the first coefficient is 0, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; The reconfigurable adder circuit is specifically configured to perform a through operation under the control of the control circuit; The input end of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, the output data of the reconfigurable adder circuit is the input data, and the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory; The reconfigurable memory is specifically used to store the preset table data under the control of the control circuit.

6. The reconfigurable multi-mode intelligent computing circuit according to claim 5, characterized in that: The input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, and the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit; The input end of the second handshake interface unit is specifically used to read the first coefficient and input data under the control of the control circuit, the first coefficient is 0, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; The reconfigurable adder circuit is specifically configured to perform an addition operation on the input data and the first coefficient under the control of the control circuit; The input end of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, the output data of the reconfigurable adder circuit is the input data, and the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory; The reconfigurable memory is specifically used to perform value search according to the input data under the control of the control circuit, and the output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit; The input end of the fifth handshake interface unit is specifically used to read the output data of the sixth handshake interface unit under the control of the control circuit, and the output end of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit, and the calculation result is a numerical search result.

7. The reconfigurable multi-mode intelligent computing circuit according to claim 3, characterized in that: The input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the third handshake interface unit, and the input data is a first data group; The input end of the third handshake interface unit is specifically used to read the input data and the second coefficient under the control of the control circuit, the output end of the third handshake interface unit is connected to the input end of the multiplication circuit, and the output end of the multiplication circuit is connected to the input end of the fourth handshake interface unit; The input end of the fourth handshake interface unit is specifically used to read the output data of the multiplication circuit under the control of the control circuit, and the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory; The reconfigurable memory is specifically used to store the output data of the multiplication circuit under the control of the control circuit; The input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit, and the input data is a second data group; The reconfigurable memory further searches for output data of the multiplication circuit under the control of the control circuit, and the output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit; The input end of the second handshake interface unit is specifically used to read the input data and the output data of the sixth handshake interface unit under the control of the control circuit, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; The reconfigurable adder circuit is specifically configured to perform a subtraction operation on the input data and the output data of the sixth handshake interface unit under the control of the control circuit; The input end of the fifth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, and the output end of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit, and the calculation result is the residual calculation result.

8. The reconfigurable multi-mode intelligent computing circuit according to claim 3, characterized in that: The input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit, and the input data is all data in the target feature map; The input end of the second handshake interface unit is specifically used to read input data under the control of the control circuit, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; The reconfigurable adder circuit is specifically configured to perform an accumulation operation on the input data under the control of the control circuit; The input end of the third handshake interface unit is specifically used to read the output result of the reconfigurable adder circuit and the first coefficient under the control of the control circuit, the output end of the third handshake interface unit is connected to the input end of the multiplication circuit, and the first coefficient is determined according to the number of data in the target feature map; The input end of the fifth handshake interface unit is specifically used to read the output data of the multiplication circuit under the control of the control circuit, and the output end of the fifth handshake interface unit is specifically used to output the output data of the multiplication circuit, and the output data of the multiplication circuit is the global average pooling result of the input data.

9. The reconfigurable multi-mode intelligent computing circuit according to claim 3, characterized in that: The input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit, and the input data includes a row of data of each pooling window in the target feature map; The input end of the second handshake interface unit is specifically used to read input data under the control of the control circuit, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; The reconfigurable adder circuit is specifically configured to perform a cyclic comparison operation on the input data under the control of the control circuit; The input end of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, the output data of the reconfigurable adder circuit being the temporary maximum value or the temporary minimum value of each pooling window, and the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory; The reconfigurable memory is specifically configured to store a temporary maximum value or a temporary minimum value of each pooling window under the control of the control circuit.

10. The reconfigurable multi-mode intelligent computing circuit according to claim 9, characterized in that: The input end of the first handshake interface unit is specifically used to read input data under the control of the control circuit, the output end of the first handshake interface unit is connected to the input end of the second handshake interface unit, and the input data includes the next row of data of each pooling window in the target feature map; The reconfigurable memory is specifically configured to search for a temporary maximum value or a temporary minimum value of each pooling window under the control of the control circuit, and the output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit; The input end of the second handshake interface unit is specifically used to read the input data and the output data of the sixth handshake interface unit under the control of the control circuit, and the output end of the second handshake interface unit is connected to the input end of the reconfigurable adder circuit; The reconfigurable adder circuit is specifically configured to perform a comparison operation on a first value in the input data and output data of the sixth handshake interface unit under the control of the control circuit, temporarily store the comparison result in a register, and perform a cyclic comparison operation based on the remaining values in the input data and the comparison result; The input end of the fourth handshake interface unit is specifically used to read the output data of the reconfigurable adder circuit under the control of the control circuit, the output data of the reconfigurable adder circuit being the temporary maximum value or the temporary minimum value of each pooling window, and the output end of the fourth handshake interface unit is connected to the input end of the reconfigurable memory; The reconfigurable memory is specifically used to store the temporary maximum value or the temporary minimum value of each pooling window under the control of the control circuit until the data comparison in each pooling window is completed, and the reconfigurable memory is specifically used to output the temporary maximum value or the temporary minimum value under the control of the control circuit, and the output end of the reconfigurable memory is connected to the input end of the sixth handshake interface unit; The input end of the fifth handshake interface unit is specifically used to read the output data of the sixth handshake interface unit under the control of the control circuit, and the output end of the fifth handshake interface unit is used to output the calculation result under the control of the control circuit, and the calculation result is the maximum pooling result or the minimum pooling result.

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