Time sequence adjusting method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a time sequence adjustment method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining an abnormal time sequence arc in an integrated circuit based on the received design data of the integrated circuit; and determining that the integrated circuit has a static time sequence defect in response to the plurality of stages of time sequence arcs propagated to the abnormal time sequence arc, and performing time sequence adjustment according to the stage delay of the abnormal time sequence arc and the stage delay of the plurality of stages of time sequence arcs. By implementing the embodiment of the invention, the current defect based on graph analysis can be accurately identified, and elimination of the current defect based on graph analysis is realized through time sequence adjustment.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a timing adjustment method, device, electronic device, and storage medium. Background Art

[0002] An integrated circuit (IC) is an electronic device composed of circuit components such as resistors, capacitors, diodes, and transistors. Before a chip is tape-out, multiple checks are required, with timing checking being the most critical and requiring the most human resources. Timing checks are typically performed through static timing analysis (STA), ensuring that the circuit achieves timing closure under various process corners and functional modes.

[0003] The core methodology of current static timing analysis is: first, use Graph Based Analysis (GBA) to perform a more pessimistic and conservative fast analysis of circuit timing and screen out the critical path; then use Path Based Analysis (PBA) on the critical path to obtain accurate timing analysis results of the critical path.

[0004] However, in today's advanced processes, GBA reports circuit gate delays that are more optimistic than PBA reports. This can cause static timing analysis to miss critical paths with potential violations, leading to static timing analysis failures and even IC tape-out failures. Summary of the Invention

[0005] The embodiments of the present application disclose a timing adjustment method, device, electronic device and storage medium, which can accurately detect and eliminate defects currently based on graph analysis.

[0006] To solve the above technical problems, the present application provides a timing adjustment method, which includes:

[0007] Obtaining abnormal timing arcs in the integrated circuit based on received design data of the integrated circuit;

[0008] In response to determining that a static timing defect exists in the integrated circuit based on several stage timing arcs propagating to the abnormal timing arc, timing adjustment is performed based on the stage delay of the abnormal timing arc and the stage delays of the several stage timing arcs.

[0009] In some embodiments, obtaining abnormal timing arcs in the integrated circuit based on received design data of the integrated circuit includes:

[0010] determining, based on the design data, a gate delay of each unit gate in the integrated circuit under different input signal transition times and output loads;

[0011] Based on the gate delay of each unit gate under different input signal conversion times and output loads, an abnormal unit gate is determined, and a timing arc where the abnormal unit gate is located is determined as the abnormal timing arc.

[0012] In some embodiments, determining an abnormal unit gate based on the gate delay of each unit gate under different input signal conversion times and output loads includes:

[0013] If, under any output load of the unit gate, the input signal conversion time is longer and the gate delay is shorter, the unit gate is determined to be an abnormal unit gate.

[0014] In some embodiments, in response to determining that a static timing defect exists in the integrated circuit based on several stage timing arcs that propagate to the abnormal timing arc, performing timing adjustment based on the stage delay of the abnormal timing arc and the stage delays of the several stage timing arcs includes:

[0015] If any one of the multiple levels of timing arcs that propagate to the abnormal timing arc contains multiple line timing arcs, it is determined that the integrated circuit has a static timing defect;

[0016] Timing adjustment is performed according to the stage delay of the abnormal timing arc and the stage delays of the plurality of stage timing arcs.

[0017] In some embodiments, the performing timing adjustment according to the stage delay of the abnormal timing arc and the stage delays of the plurality of stage timing arcs includes:

[0018] determining the stage delay of the abnormal timing arc according to the delay of the line timing arc and the delay of the gate timing arc in the abnormal timing arc;

[0019] determining the stage delays of the plurality of stage timing arcs according to the delays of the line timing arcs and the delays of the gate timing arcs in the plurality of stage timing arcs;

[0020] determining a maximum level delay and a minimum level delay according to the level delay of the abnormal timing arc and the level delays of the plurality of level timing arcs;

[0021] Based on the inspection type, timing adjustment is performed according to the maximum stage delay or the minimum stage delay.

[0022] In some embodiments, the method further comprises:

[0023] If the component propagating to the previous-level timing arc of the abnormal timing arc is a port, it is determined that the abnormal timing arc does not have a static timing defect.

[0024] In some embodiments, the design data includes at least a depth perception coefficient; and the number of levels of the plurality of timing arcs propagated to the abnormal timing arc is determined according to the depth perception coefficient.

[0025] The present application also provides a timing adjustment device, comprising:

[0026] a marking module, configured to obtain abnormal timing arcs in the integrated circuit based on received design data of the integrated circuit;

[0027] The adjustment module is configured to, in response to determining that a static timing defect exists in the integrated circuit based on the plurality of stage timing arcs propagated to the abnormal timing arc, perform timing adjustment based on the stage delay of the abnormal timing arc and the stage delays of the plurality of stage timing arcs.

[0028] The present application also provides an electronic device, including a storage medium and a controller, characterized in that a computer program is stored on the storage medium, and when the computer program is executed by the controller, the steps of the timing adjustment method described above are implemented.

[0029] The present application also provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the timing adjustment method described above are implemented.

[0030] Compared with the related art, the embodiments of the present application have the following beneficial effects:

[0031] The timing adjustment method, apparatus, electronic device, and storage medium of the present application include the following steps: obtaining an abnormal timing arc in the integrated circuit based on received integrated circuit design data; determining the presence of a static timing defect in the integrated circuit based on several level timing arcs propagated to the abnormal timing arc; and performing timing adjustment based on the level delay of the abnormal timing arc and the level delays of several level timing arcs. The technical solution of the application, based on the integrated circuit design data, identifies the abnormal timing arc from the timing arcs contained in the integrated circuit, traces back several level timing arcs preceding the abnormal timing arc, and determines whether the integrated circuit has a static timing defect based on the level delays of the traced level timing arcs. This accurately identifies the current graph analysis-based defect, and then, if a static timing defect exists, performs timing adjustment based on the level delay of the abnormal timing arc and the level delays of the traced level timing arcs, thereby eliminating the current graph analysis-based defect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of a multi-stage timing arc in an embodiment of the present application;

[0033] Figure 2 is a flow chart of a timing adjustment method in an embodiment of the present application;

[0034] Figure 3a It is an integrated circuit diagram including an abnormal timing arc in an embodiment of the present application;

[0035] Figure 3b is another integrated circuit diagram including an abnormal timing arc in an embodiment of the present application;

[0036] Figure 3c is another integrated circuit diagram including an abnormal timing arc in an embodiment of the present application;

[0037] Figure 4 It is a structural diagram of the timing adjustment device in an embodiment of the present application. DETAILED DESCRIPTION

[0038] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. The terms used herein in the specification of the present invention are intended solely for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items. In the present invention, "each" includes one and more than two.

[0040] In the field of integrated circuits, an integrated circuit (IC) is an electronic device composed of circuit components such as resistors, capacitors, diodes, and transistors. With the continued advancement of Moore's Law, the number of transistors has increased dramatically. The emergence of very large-scale integration (VLSI) has made computer-aided design (CAD) and electronic design automation (EDA) essential tools for IC design.

[0041] Before a chip is tape-out, the IC design undergoes back-end layout and routing, generating a layout file based on the Graphic Design System (GDS). This file undergoes a sign-off process to ensure that timing, design rule checks, power consumption, and IR drop meet functional requirements. Timing checking is the most critical step and requires the largest investment in human resources. This is typically performed through static timing analysis (STA), ensuring that the circuit achieves timing closure under various process corners and functional modes.

[0042] Today's advanced integrated circuits (ICs) contain tens of billions of transistors, resulting in static timing analysis often requiring weeks or even longer. For commercial ICs and advanced chips, time to market (TTM) significantly impacts the viability of a product. Therefore, while ensuring the completeness of the analysis scenario, efforts must be made to shorten the time required for static timing analysis.

[0043] For chips with a billion transistors or more, it's impossible to exhaustively and accurately calculate all timing paths. The core methodology of current static timing analysis is to first use Graph Based Analysis (GBA) to quickly analyze circuit timing in a more pessimistic and conservative manner, identifying critical paths. Then, use Path Based Analysis (PBA) on these critical paths to obtain accurate timing analysis results for these paths.

[0044] The results of timing analysis are reflected in the slack of the timing path. The slack is the numerical difference between the data path time and the clock path time. The positive or negative relationship of the difference depends on the check type—the setup check and the hold check. The data path and clock path times are composed of the delays of the timing arcs (TimingArc)—including the net / wire timing arcs (Net / Wire Timing Arc) and the gate timing arcs (Gate Timing Arc), and the values of other constraints. Among them, a wire arc delay (Wire Arc Delay) and a gate arc delay (Gate Arc Delay) constitute a stage delay (Stage Delay). Therefore, the path time can also be considered to be composed of stage delays and other constraint values.

[0045] Figure 1 Schematic diagram of multi-stage timing arc in the embodiment of the present application. Figure 1 As shown, there are two stages from inv1 / to aoi1 / ZN. Each stage consists of one gate timing arc and one line timing arc.

[0046] Graph-based analysis uses the most pessimistic signal transition time (Slew) as the output signal transition time for all timing arcs of a cell gate. Graph-based analysis assumes that more pessimistic transition times, when propagated to the next stage, will result in more pessimistic line and cell delays. However, in many timing models, gate delay as a function of signal transition time is not a monotonically increasing function, especially in cells with small output load capacitance. Therefore, in current advanced processes, GBA reports circuit gate delays that are more optimistic than PBA. This can cause static timing analysis to miss critical paths with potential violations, leading to static timing analysis failures and even IC tape-out failures. Timing model files for current mainstream processes contain numerous such cell models.

[0047] In an integrated circuit, standard cell gate G1 exists in the data path of a timing path ending at E1, and this data path consists of only this single cell gate. In this case, the worst path slack (Worst Path Slack) reported by graph analysis for endpoint E1 is positive. Therefore, under this check type, static timing analysis for endpoint E1 converges, eliminating the need for further precise path-based analysis or even physical simulation. However, if G0 propagates another timing arc, causing the output signal transition time of G0 to increase, the analyzed gate delay of G1 can be increased, resulting in a negative timing path slack. Chip designers will then need to redesign the corresponding circuits and constraints to ensure proper chip operation. Using traditional graph-based analysis, such scenarios would introduce unassessable defects in the chip.

[0048] This phenomenon of gate delay being non-monotonic with respect to signal transition time is common in gates with strong drive capabilities. In the back-end design of a chip with 10,000,000 standard gates, there are numerous local circuits where strong gates drive gates with smaller loads. Technicians discovered that current GBA analysis results in six paths that would otherwise violate PBA being unreported. These six paths pose an unassessed risk to the chip. Such defects are even more numerous in chips with hundreds of millions of standard gates. Therefore, to address this technical problem, the present invention provides a timing adjustment method.

[0049] See also Figure 2 , Figure 2 FIG. 1 is a flow chart of the timing adjustment method in the embodiment of the present application. Figure 2 As shown, the timing adjustment method of the present application includes the following steps:

[0050] 210. Obtain abnormal timing arcs in the integrated circuit based on the received design data of the integrated circuit.

[0051] In an embodiment of the present application, a technician can transmit the design data of the integrated circuit to a terminal device or application that performs timing adjustment through a server, terminal device, storage device or other input method. Among them, the design data of the integrated circuit refers to a file or data that describes the specific implementation structure of the integrated circuit, defines various performance indicators of the integrated circuit, and detects whether the integrated circuit has static timing defects. The design data of the integrated circuit includes at least a standard cell gate timing model, a gate-level netlist (Gate-Level Netlist) composed of logical connection relationships after instantiation of the standard cell gate, a design constraint file, and a perception depth coefficient.

[0052] A standard cell gate timing model is a mathematical model used in integrated circuit design to describe the timing characteristics of logic cells (such as logic gates and flip-flops) under different operating conditions. This model is typically stored as a Liberty file, an industry standard in the field of electronic design automation (EDA). A gate-level netlist is the output file of logic synthesis in the integrated circuit design process, representing the specific implementation structure of the circuit in a hardware description language (such as Verilog or VHDL). By instantiating standard cells (such as logic gates and flip-flops) from a process library and their interconnections, a high-level behavioral level (RTL) description is converted into a low-level, physically implementable circuit structure. A design constraint file is a key input file in the integrated circuit (IC) design process, used to define circuit performance metrics such as timing, area, and power consumption, guiding electronic design automation (EDA) tools in logic synthesis, place and route, and timing verification.

[0053] Among them, the timing arc is the signal propagation path between two nodes (such as logic unit pins or connection endpoints) in an integrated circuit, which contains the timing information of the starting point and the end point. The timing arc includes a line timing arc and a gate timing arc. The line timing arc refers to the transmission delay caused by the signal passing through the physical connection (such as the unit output end to the load input end), and the gate timing arc refers to the delay of the signal from input to output through the unit gate. In an embodiment of the present application, the integrated circuit includes several timing paths, and each timing path contains several unit gates. The timing path refers to the logical path through which the signal propagates from the starting point to the end point in the digital circuit design. According to the design data of the received integrated circuit, it is judged one by one whether there are abnormal timing arcs in the timing path. After the abnormal timing arc is identified, it can be marked in the gate-level netlist. Among them, the abnormal timing arc refers to the timing path in the circuit timing analysis, which may affect the circuit function and the change of the delay and input signal conversion time value in the timing model does not meet the requirements.

[0054] 220. In response to determining that a static timing defect exists in the integrated circuit based on the plurality of stage timing arcs propagating to the abnormal timing arc, perform timing adjustment based on the stage delay of the abnormal timing arc and the stage delays of the plurality of stage timing arcs.

[0055] In this application, each line timing arc and the connected gate timing arc constitute a first-level timing arc. For example, see Figure 1 There are two levels of timing arcs from inv1 / to aoi1 / ZN. Specifically, the timing arc of the inv1 unit gate and the timing arc of the connecting line at the output end of the inv1 unit gate constitute one level of timing arc, and the timing arc of the and1 unit gate and the timing arc of the connecting line at the output end of the and1 unit gate constitute another level of timing arc.

[0056] In the embodiments of the present application, after identifying and marking abnormal timing arcs in an integrated circuit, for each abnormal timing arc, the propagation of the abnormal timing arc to the previous level can be traced. Specifically, the presence of a static timing defect in the integrated circuit can be determined based on the component type of the previous-level timing arc that propagated to the abnormal timing arc, or based on whether the timing arc chain that propagated to the abnormal timing arc is unique. A timing arc chain refers to a link consisting of three or more line timing arcs and gate timing arcs.

[0057] For each abnormal timing arc, if the integrated circuit is determined to have no static timing defect based on the timing arcs that propagate to several stages of the abnormal timing arc, then no timing adjustment is required for the integrated circuit or the timing path where the abnormal timing arc resides. If the integrated circuit is determined to have a static timing defect based on the timing arcs that propagate to several stages of the abnormal timing arc, then timing adjustment is performed on the integrated circuit or the timing path where the abnormal timing arc resides based on the stage delay of the abnormal timing arc and the stage delays of the timing arcs that propagate to the abnormal timing arc.

[0058] In the embodiments of this application, static timing defects refer to design timing violations discovered during static timing analysis (STA), which may cause the circuit to not operate properly at the target frequency. Stage delay refers to a parameter used in digital circuit design to describe the time required for a signal to propagate within a certain logic stage. It mainly consists of two parts: the delay of the gate timing arc and the delay of the line timing arc. Timing adjustment refers to the operation of adjusting design data based on the delay characteristics of the integrated circuit to eliminate static timing defects.

[0059] By adopting the above embodiment, an abnormal timing arc is identified from the timing arcs included in the integrated circuit based on the design data of the integrated circuit, and the timing arcs of several levels preceding the abnormal timing arc are traced back. If it is determined that a static timing defect exists in the integrated circuit based on the level delay of each level of the traced timing arcs, the current defect based on graph analysis is accurately identified, and then timing adjustment is performed based on the level delay of the abnormal timing arc and the level delay of each level of the traced timing arcs, thereby eliminating the current defect based on graph analysis.

[0060] In some embodiments, the design data includes at least a depth perception coefficient; and the number of levels of the plurality of timing arcs propagated to the abnormal timing arc is determined according to the depth perception coefficient.

[0061] In an embodiment of the present application, after inputting the design data such as the Liberty file, gate-level netlist, and design constraint file of the integrated circuit into the application, the technician also needs to input the depth perception coefficient N into the application. The depth perception coefficient N can be determined by the user. The depth perception coefficient N determines the number of levels of timing arcs that are traced back to the abnormal timing arc in this application. For example, if the depth perception coefficient N = 3, then after identifying and marking the abnormal timing arc, the timing arcs 3 levels before the abnormal timing arc are traced; if the depth perception coefficient N = 2, then the timing arcs 2 levels before the abnormal timing arc are traced.

[0062] In the embodiments of this application, a larger depth perception coefficient N indicates a deeper path depth, higher accuracy, and more machine resources are consumed for analyzing the same path; vice versa. Within different chip manufacturing process nodes, the larger the depth perception coefficient N, the higher the percentage of current GBA defects that can be eliminated by this invention. In other words, if the depth perception coefficient N is sufficiently large, this application can theoretically ensure that within a given process node, even with billions of timing paths, the calculation will not miss any timing paths that violate the graph analysis. This allows users to invest more resources in critical path analysis, reducing the waste of resources required for rollbacks and rework.

[0063] In some embodiments, obtaining abnormal timing arcs in the integrated circuit based on the received design data of the integrated circuit in step 210 may include the following steps:

[0064] Based on the design data, determine the gate delay of each unit gate in the integrated circuit under different input signal transition times and output loads;

[0065] Based on the gate delay of each unit gate under different input signal conversion times and output loads, the abnormal unit gate is determined, and the timing arc where the abnormal unit gate is located is determined as the abnormal timing arc.

[0066] In an embodiment of the present application, after a technician transmits the design data of an integrated circuit to a terminal device or application that performs timing adjustment, the application then determines, based on the received design data of the integrated circuit, whether there are abnormal timing arcs along each timing path. Specifically, the design data of the integrated circuit includes data for each unit gate on each timing path of the integrated circuit, specifically the gate delay of each unit gate under different input signal transition times and different output loads. The technician can pre-set rules for abnormal timing arcs. For example, if the gate delay is within a specific range under a specific input signal transition time and a specific load, the unit gate can be determined to be an abnormal unit gate; or if the gate delay changes within a certain range of signal transition times and a certain range of output loads, the unit gate can be determined to be an abnormal unit gate; these are not specifically limited here. Therefore, based on the gate delay changes of each unit gate under different input signal transition times and different output loads, each unit gate on each timing path of the integrated circuit is tested. If an abnormal unit gate is detected, the timing arc containing the abnormal unit gate is determined to be an abnormal timing arc. The gate timing arc of the abnormal unit gate may be determined as the abnormal timing arc, or the stage timing arc where the abnormal unit gate is located may be determined as the abnormal timing arc.

[0067] In the embodiments of the present application, a unit gate refers to a unit circuit used to implement basic logical operations and compound operations in an integrated circuit. These unit circuits mainly include AND gates, OR gates, NOT gates, NAND gates, NOR gates, AND-NOR gates, XOR gates, etc. in terms of logical functions. They are basic functional elements of integrated circuits and are constructed from electronic components such as transistors. They can be combined into complex logical operation systems to achieve a mapping relationship between software and hardware. Input signal conversion time refers to the time required for an input signal to change from one logic level to another in a digital integrated circuit. Gate delay refers to the time required for a signal to pass through a logic gate. Output load refers to the external device or component connected to the output end of the circuit. An abnormal unit gate refers to a unit gate whose corresponding gate delay value or change does not meet the rules.

[0068] By using the above embodiment, abnormal timing arcs in an integrated circuit can be accurately detected, so that whether there are static timing defects in the integrated circuit can be accurately determined based on the abnormal timing arcs, and the timing of the integrated circuit with static timing defects can be adjusted more quickly to eliminate defects based on the graph analysis method.

[0069] In some embodiments, the step of determining an abnormal unit gate based on the gate delay of each unit gate under different input signal conversion times and output loads may specifically include the following steps:

[0070] If the input signal conversion time of the unit gate is larger and the gate delay is smaller under any output load, the unit gate is determined to be an abnormal unit gate.

[0071] In the integrated circuit (IC) field, graph-based analysis uses the most pessimistic signal transition time (Slew) as the output signal transition time for all timing arcs of a cell gate. Graph-based analysis assumes that more pessimistic transition times, when propagated to the next stage, will result in more pessimistic line and cell delays. However, in many timing models, gate delay as a function of signal transition time is not a monotonically increasing function, especially in cells with small output load capacitance. Therefore, in current advanced processes, GBA reports circuit gate delays that are more optimistic than PBA. This can cause static timing analysis to miss critical paths with potential violations, leading to static timing analysis failures and even IC tape-out failures. Timing model files for current mainstream processes contain numerous such cell models.

[0072] For example, the data for unit gate G1 includes the input signal transition time (Slew), the output load (Load), and the unit gate delay values for different input signal transition times and output loads. When load = a1 and the input signal transition time is within the range (b1, c1), the gate delay decreases as the signal transition time increases. Traditional graph-based analysis assumes that the previous unit gate G0 has multiple timing arcs, each causing an output signal transition time (Output Slew) to propagate to its output pin, and then propagates to the input pin of the currently analyzed unit gate G1 through wire attenuation. For setup checks, graph-based analysis propagates the maximum G0 output signal transition. If the input signal transition time (Slew) is a1 and the output load (Load) is within the range (b1, c1), the gate delay of G1 derived from traditional graph-based analysis is more optimistic than the gate delays caused by other timing arcs of the previous gate G0. Therefore, current GBA does not achieve the goal of analyzing the most pessimistic scenario.

[0073] Therefore, after inputting gate delay data for a unit gate under different input signal transition times and output loads as design data for the integrated circuit into a terminal device or application, the relationship between the gate delay and the input signal transition time for each unit gate under various output loads is used to determine whether the unit gate is abnormal. Specifically, for each unit gate, if the gate delay decreases as the input signal transition time increases under any output load, i.e., the gate delay does not monotonically increase as the input signal transition time increases, the unit gate is determined to be abnormal. If the gate delay increases as the input signal transition time increases under any output load, i.e., the gate delay monotonically increases as the input signal transition time increases, the unit gate is normal. Based on this determination method, unit gates on the timing path are identified to determine abnormal timing arcs.

[0074] By adopting the above judgment method, abnormal unit gates can be detected quickly and accurately, and then abnormal timing arcs in the integrated circuit can be accurately detected, so that the presence of static timing defects in the integrated circuit can be accurately determined based on the abnormal timing arcs, further improving the accuracy of eliminating defects based on the graph analysis method.

[0075] In some embodiments, step 220, in response to determining that a static timing defect exists in the integrated circuit based on the multiple stage timing arcs that propagate to the abnormal timing arc, and performing timing adjustment based on the stage delay of the abnormal timing arc and the stage delays of the multiple stage timing arcs, may include the following steps:

[0076] If the fault propagates to several levels of timing arcs of the abnormal timing arc, and any level of timing arc contains multiple line timing arcs, it is determined that a static timing defect exists in the integrated circuit;

[0077] Timing adjustment is performed according to the stage delay of the abnormal timing arc and the stage delays of several stage timing arcs.

[0078] In the embodiments of this application, Figure 3a is an integrated circuit diagram including an abnormal timing arc in an embodiment of the present application, Figure 3b is another integrated circuit diagram including an abnormal timing arc in an embodiment of the present application, Figure 3c This is another integrated circuit diagram including an abnormal timing arc in the embodiment of the present application.

[0079] See also Figure 3a, it is detected that the unit gate and1 is an abnormal unit gate. Specifically, under a specific load, when the input signal conversion time of the A2 input terminal of the unit gate and1 increases, the gate delay does not change monotonically. Therefore, the section and1 / A2->and1 / Z of the unit gate and1 in the data path can be determined as an abnormal timing arc. At this time, the embodiment of the present application needs to determine whether the depth perception coefficient N is greater than 0. This is because if the depth perception coefficient N = 0, there is no need to trace back the several levels of timing arcs that propagate to the abnormal timing arc, so it is impossible to perform timing adjustment based on the level delay of the abnormal timing arc and the level delay of the several levels of timing arcs traced back. Therefore, the depth perception coefficient N must be greater than 0.

[0080] exist Figure 3a In the example, the depth perception coefficient N=1, that is, the depth perception coefficient N>0, then it is necessary to trace back the previous level timing arc of the abnormal timing arc and1 / A2->and1 / Z, that is, Figure 3a From inv1 / I->and1 / A2, it can be seen that the previous timing arc inv1 / I->and1 / A2 of the abnormal timing arc and1 / A2->and1 / Z contains only one line timing arc. In other words, the stage delay of the abnormal timing arc and1 / A2->and1 / Z and the stage delay of the previous timing arc inv1 / I->and1 / A2 are also unique. In this case, timing adjustment cannot be performed based on the stage delay of the abnormal timing arc and1 / A2->and1 / Z and the stage delay of the previous timing arc inv1 / I->and1 / A2. Therefore, it cannot be determined that the integrated circuit has a static timing defect based on the abnormal timing arc and1 / A2->and1 / Z. Therefore, there is no need to perform timing adjustment on the integrated circuit based on the stage delay of the abnormal timing arc and1 / A2->and1 / Z and the stage delay of the previous timing arc.

[0081] See also Figure 3b , it is detected that the unit gate buf1 is an abnormal unit gate. Specifically, under a specific load, when the input signal conversion time of the I input terminal of the unit gate buf1 increases, the gate delay does not change monotonically. Therefore, the section buf1 / I->buf1 / Z of the unit gate buf1 in the data path can be determined as an abnormal timing arc. In this embodiment, the depth perception coefficient N=1, so it is necessary to trace back to the previous level timing arc that propagates to the abnormal timing arc buf1 / I->buf1 / Z, that is, Figure 3bFrom mux1 / I0->buf1 / I, mux1 / I1->buf1 / I, mux1 / I2->buf1 / I, and mux1 / I3->buf1 / I, it can be seen that the previous-stage timing arc mux1 / I0->buf1 / I of the abnormal timing arc buf1 / I->buf1 / Z contains four line timing arcs. In other words, because mux1 in the previous stage has multiple timing arcs whose endpoints are mux1 / Z of the stage where buf1 is located, timing adjustment can be performed based on the stage delay of the abnormal timing arc and1 / A2->and1 / Z and the stage delay of the previous-stage timing arc inv1 / I->and1 / A2. Based on the abnormal timing arc buf1 / I->buf1 / Z, it is determined that the integrated circuit has a static timing defect.

[0082] After determining that a static timing defect exists in the integrated circuit, an optimal sum of the stage delays is selected based on the stage delay of the abnormal timing arc buf1 / I->buf1 / Z and the stage delays of the previous stage timing arcs mux1 / I0->buf1 / I, mux1 / I1->buf1 / I, mux1 / I2->buf1 / I, and mux1 / I3->buf1 / I, to perform timing adjustment on the integrated circuit. Specifically, based on the stage delay of the abnormal timing arc buf1 / I->buf1 / Z and the stage delays of the previous stage timing arcs mux1 / I0->buf1 / I, mux1 / I1->buf1 / I, mux1 / I2->buf1 / I, and mux1 / I3->buf1 / I, an input signal conversion time corresponding to the optimal sum of the stage delays is selected as the input signal conversion time of the unit gate buf1, and timing adjustment is then performed based on the input signal conversion time.

[0083] By adopting the above embodiment, it is possible to accurately determine whether static timing defects exist in an integrated circuit, thereby further improving the accuracy of eliminating defects based on a graph analysis method.

[0084] In some embodiments, the timing adjustment method in the embodiments of the present application may further include the following steps:

[0085] If the component propagating to the previous-level timing arc of the abnormal timing arc is a port, it is determined that the abnormal timing arc does not have a static timing defect.

[0086] See also Figure 3c , it is detected that the unit gate mux1 is an abnormal unit gate. Specifically, under a specific load, when the input signal conversion time of the I0 input terminal of the unit gate mux1 increases, the gate delay does not change monotonically. Therefore, the section mux1 / I0->mux1 / Z of the unit gate mux1 in the data path can be determined as an abnormal timing arc. Figure 3cIn the example, the depth perception coefficient N = 2, and the abnormal timing arc mux1 / I0->mux1 / Z exists in the data path. However, the previous stage driving the unit gate is a port, and there is no current design circuit element before the port. This is actually equivalent to N = 1. Since the port does not have multiple timing arcs that propagate multiple signal conversion times, the timing arc chain that propagates to the abnormal timing arc is unique. Therefore, it is impossible to determine whether the integrated circuit has a static timing defect based on the abnormal timing arc mux1 / I0->mux1 / Z. Therefore, there is no need to adjust the timing of the integrated circuit based on the stage delay of the abnormal timing arc mux1 / I0->mux1 / Z and the stage delay of the previous stage timing arc.

[0087] By adopting the above embodiment, it is possible to quickly determine the situation where it is impossible to determine the presence of a static timing defect based on the abnormal timing arc, thereby achieving rapid screening of each marked abnormal timing arc and saving required computing resources.

[0088] In some embodiments, the step of adjusting the timing according to the stage delay of the abnormal timing arc and the stage delays of several stage timing arcs may specifically include the following steps:

[0089] Determine the stage delay of the abnormal timing arc according to the delay of the line timing arc and the delay of the gate timing arc in the abnormal timing arc;

[0090] Determining the stage delays of the plurality of stage timing arcs according to the delays of the line timing arcs and the delays of the gate timing arcs in the plurality of stage timing arcs;

[0091] Determine the maximum level delay and the minimum level delay according to the level delay of the abnormal timing arc and the level delays of several level timing arcs;

[0092] Based on the check type, timing adjustments are made based on maximum stage delay or minimum stage delay.

[0093] In an embodiment of the present application, in the process of determining that an integrated circuit has a static timing defect and performing timing adjustment based on the stage delay of the abnormal timing arc and the stage delays of several traced stage timing arcs, the input signal conversion times of all input pins that can be propagated to the input pin of the abnormal timing arc can be first propagated and the stage delays of the first 1 (first N) stage timing arcs can be calculated, and the input signal conversion time that maximizes the subsequent stage delay can be selected as the output conversion time of the gate.

[0094] Assume N = 1. A timing arc exists in unit gate G1. The input pin of this arc is driven by the output pin Z0 of the previous unit gate G0. G0 has a timing arc (arc_1, arc_2, arc_3…arc_m…arc_last) with endpoint Z0. Arc_m propagates an input signal transition time to the input pin G1 / I1 of the next delayed stage. The stage delay of the stage containing the timing arc, Tstage, is equal to fg1(arc_m). The stage delay of the stage before the timing arc, Tprev, is equal to fg0(arc_m).

[0095] Depending on the type of check, the optimal sum of stage delays required for timing adjustment varies. In the embodiment of the present application, the check types include setup checks and hold checks. In the maximum path analysis represented by the data path of the setup check, selecting a larger output signal transition time based on graph analysis results in a larger stage delay; in the minimum path analysis represented by the data path of the hold check, selecting a smaller output signal transition time based on graph analysis results in a smaller stage delay.

[0096] Therefore, for setup check, the optimal sum of stage delays required for timing adjustment is worst_arc=max(Tstage+Tprev). For hold check, the optimal sum of stage delays required for timing adjustment is worst_arc=min(Tstage+Tprev).

[0097] By adopting the above embodiment, the optimal sum of stage delays required for timing adjustment can be quickly selected according to different inspection categories, further improving the effect of eliminating defects currently based on graph analysis.

[0098] Figure 4 Schematic diagram of the structure of the timing adjustment device in the embodiment of the present application. Figure 4 As shown, the present application also provides a timing adjustment device, comprising:

[0099] a marking module 410 for obtaining abnormal timing arcs in the integrated circuit based on received design data of the integrated circuit;

[0100] The adjustment module 420 is configured to determine that a static timing defect exists in the integrated circuit according to the multiple stage timing arcs propagating to the abnormal timing arc, and perform timing adjustment according to the stage delay of the abnormal timing arc and the stage delays of the multiple stage timing arcs.

[0101] In some embodiments, the marking module 410 is further configured to:

[0102] Based on the design data, determine the gate delay of each unit gate in the integrated circuit under different input signal transition times and output loads;

[0103] Based on the gate delay of each unit gate under different input signal conversion times and output loads, the abnormal unit gate is determined, and the timing arc where the abnormal unit gate is located is determined as the abnormal timing arc.

[0104] In some embodiments, the marking module 410 is further configured to:

[0105] If the input signal conversion time of the unit gate is larger and the gate delay is smaller under any output load, the unit gate is determined to be an abnormal unit gate.

[0106] In some embodiments, the adjustment module 420 is further configured to:

[0107] If the fault propagates to several levels of timing arcs of the abnormal timing arc, and any level of timing arc contains multiple line timing arcs, it is determined that a static timing defect exists in the integrated circuit;

[0108] Timing adjustment is performed according to the stage delay of the abnormal timing arc and the stage delays of several stage timing arcs.

[0109] In some embodiments, the adjustment module 420 is further configured to:

[0110] Determine the stage delay of the abnormal timing arc according to the delay of the line timing arc and the delay of the gate timing arc in the abnormal timing arc;

[0111] Determining the stage delays of the plurality of stage timing arcs according to the delays of the line timing arcs and the delays of the gate timing arcs in the plurality of stage timing arcs;

[0112] Determine the maximum level delay and the minimum level delay according to the level delay of the abnormal timing arc and the level delays of several level timing arcs;

[0113] Based on the check type, timing adjustments are made based on maximum stage delay or minimum stage delay.

[0114] In some embodiments, the adjustment module 420 is further configured to:

[0115] If the component propagating to the previous-level timing arc of the abnormal timing arc is a port, it is determined that the abnormal timing arc does not have a static timing defect.

[0116] In some embodiments, the design data includes at least a depth perception coefficient; and the number of levels of the plurality of timing arcs propagated to the abnormal timing arc is determined according to the depth perception coefficient.

[0117] The present application also provides an electronic device, including a storage medium and a controller, wherein a computer program is stored on the storage medium, and when the computer program is executed by the controller, the steps of the timing adjustment method in the above embodiment are implemented.

[0118] The present application also provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the timing adjustment method in the above embodiment are implemented.

[0119] An embodiment of the present application discloses a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to enable a computer to execute any one of the timing adjustment methods disclosed in the embodiments of the present application.

[0120] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A timing adjustment method, characterized in that: The method comprises: Obtaining abnormal timing arcs in the integrated circuit based on received design data of the integrated circuit; In response to determining that a static timing defect exists in the integrated circuit based on several stage timing arcs propagating to the abnormal timing arc, timing adjustment is performed based on the stage delay of the abnormal timing arc and the stage delays of the several stage timing arcs.

2. The timing adjustment method according to claim 1, wherein: The step of obtaining an abnormal timing arc in the integrated circuit based on the received design data of the integrated circuit includes: determining, based on the design data, a gate delay of each unit gate in the integrated circuit under different input signal transition times and output loads; Based on the gate delay of each unit gate under different input signal conversion times and output loads, an abnormal unit gate is determined, and a timing arc where the abnormal unit gate is located is determined as the abnormal timing arc.

3. The timing adjustment method according to claim 2, wherein: The determining of abnormal unit gates based on the gate delay of each unit gate under different input signal conversion times and output loads includes: If, under any output load of the unit gate, the input signal conversion time is longer and the gate delay is shorter, the unit gate is determined to be an abnormal unit gate.

4. The timing adjustment method according to claim 1, wherein: In response to determining that a static timing defect exists in the integrated circuit according to the plurality of stage timing arcs propagated to the abnormal timing arc, timing adjustment is performed according to the stage delay of the abnormal timing arc and the stage delays of the plurality of stage timing arcs, including: If any one of the multiple levels of timing arcs that propagate to the abnormal timing arc contains multiple line timing arcs, it is determined that the integrated circuit has a static timing defect; Timing adjustment is performed according to the stage delay of the abnormal timing arc and the stage delays of the plurality of stage timing arcs.

5. The timing adjustment method according to claim 4, characterized in that: The performing timing adjustment according to the stage delay of the abnormal timing arc and the stage delays of the plurality of stage timing arcs includes: determining the stage delay of the abnormal timing arc according to the delay of the line timing arc and the delay of the gate timing arc in the abnormal timing arc; determining the stage delays of the plurality of stage timing arcs according to the delays of the line timing arcs and the delays of the gate timing arcs in the plurality of stage timing arcs; determining a maximum level delay and a minimum level delay according to the level delay of the abnormal timing arc and the level delays of the plurality of level timing arcs; Based on the inspection type, timing adjustment is performed according to the maximum stage delay or the minimum stage delay.

6. The timing adjustment method according to claim 1, wherein: The method further comprises: If the component propagating to the previous-level timing arc of the abnormal timing arc is a port, it is determined that the abnormal timing arc does not have a static timing defect.

7. The timing adjustment method according to any one of claims 1 to 6, characterized in that: The design data at least includes a depth perception coefficient; the number of levels of timing arcs propagated to the abnormal timing arc is determined according to the depth perception coefficient.

8. A timing adjustment device, characterized in that: The device comprises: a marking module, configured to obtain abnormal timing arcs in the integrated circuit based on received design data of the integrated circuit; The adjustment module is configured to, in response to determining that a static timing defect exists in the integrated circuit based on the plurality of stage timing arcs propagated to the abnormal timing arc, perform timing adjustment based on the stage delay of the abnormal timing arc and the stage delays of the plurality of stage timing arcs.

9. An electronic device comprising a storage medium and a controller, characterized in that: The storage medium stores a computer program, which, when executed by the controller, implements the steps of the timing adjustment method according to any one of claims 1 to 7.

10. A storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the steps of the timing adjustment method according to any one of claims 1 to 7.

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