Process of forming thin semiconductor layer bonded to processing substrate and electronic device including thin semiconductor layer

Abstract

The invention relates to a process of forming a thin semiconductor layer bonded to a processing substrate and an electronic device including the thin semiconductor layer. In one aspect, a method may include bonding a carrier substrate to a first major surface of a donor substrate; generating a laser damaged region within the donor substrate; bonding a process substrate to a second major surface of the donor substrate, wherein the second major surface is opposite the first major surface; and separating (1) the device portions of the process substrate and the donor substrate and (2) the remainder of the carrier substrate and the donor substrate from each other. In another aspect, an electronic device may include a device portion of a SiC substrate, where the device portion includes at least a portion of an electronic circuit element. A processing substrate may be bonded to the device portion, wherein the processing substrate may withstand processing conditions when manufacturing the electronic device.

Description

Technical Field

[0001] The present disclosure relates to processes and electronic devices, and more particularly, to processes for forming a thin semiconductor layer bonded to a processing substrate and electronic devices including the thin semiconductor layer. Background Art

[0002] Electronic devices can be manufactured using semiconductor materials. Some semiconductor materials can be relatively expensive, or shortages of any particular semiconductor material can create problems in producing electronic devices within the timeframes required to meet customer expectations. Techniques exist for producing relatively thin layers of semiconductor material from relatively thick semiconductor material substrates. Such relatively thin layers can be difficult to process using typical manufacturing processes. A need exists for robust processes for producing relatively thin layers of semiconductor material that can withstand semiconductor manufacturing processes. Summary of the Invention

[0003] According to one aspect of the present disclosure, a method is provided, comprising: bonding a carrier substrate to a first major surface of a donor substrate; generating a laser damaged region within the donor substrate; bonding a processing substrate to a second major surface of the donor substrate, wherein the second major surface is opposite to the first major surface; and separating (1) a device portion of the processing substrate and the donor substrate from (2) a remaining portion of the carrier substrate and the donor substrate.

[0004] According to another aspect of the present disclosure, a method is provided. The method includes: bonding a carrier substrate to a donor substrate; generating a laser damaged region within the donor substrate; bonding a processing substrate to the donor substrate; separating (1) a device portion of the processing substrate and the donor substrate from (2) a remaining portion of the carrier substrate and the donor substrate; doping a portion of the device portion with a dopant; and activating the dopant to form a doped region from the portion of the device portion, wherein the activation is performed at a temperature of at least 1500°C.

[0005] According to another aspect of the present disclosure, an electronic device is provided. The electronic device includes: a device portion of a SiC substrate, wherein the device portion has a first main surface and a second main surface opposite the first main surface, and the device portion includes at least a portion of an electronic circuit element and a terminal electrically coupled to the electronic circuit element, wherein the terminal is along or on the first main surface of the device portion; and a processing substrate bonded to the second main surface of the device portion, wherein the processing substrate has a thickness of no greater than 250 microns and a melting point greater than 1500°C. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Implementations are shown by way of example in the drawings and are not limited thereto.

[0007] Figure 1 Included are process flows for producing relatively thin layers of semiconductor material and fabricating finished electronic devices from the relatively thin layers.

[0008] Figure 2 Included is an illustration of a cross-sectional view of a carrier substrate and a donor substrate prior to bonding.

[0009] Figure 3 Includes an illustration of a cross-sectional view of a carrier substrate and a donor substrate after bonding.

[0010] Figure 4 Included are illustrations of cross-sectional views of a carrier substrate and a donor substrate during generation of laser damage in the donor substrate.

[0011] Figure 5 Includes a diagram of a top view of a donor substrate showing the relationship between the laser direction and the cleavage plane.

[0012] Figure 6 Includes a diagram of a top view of a donor substrate showing the relationship between the laser direction and multiple cleaved planes.

[0013] Figure 7 Includes illustration of a cross-sectional view of a processed substrate and a carrier-donor workpiece prior to bonding.

[0014] Figure 8 An illustration of a cross-sectional view of a processed substrate and a carrier-donor workpiece after bonding is included.

[0015] Figure 9 An illustration includes a cross-sectional view of a workpiece including a process substrate and a device portion of a donor substrate and another workpiece including a carrier substrate and a remaining portion of the donor substrate after separation of the workpieces.

[0016] Figure 10 An illustration of a cross-sectional view of a workpiece including a device portion including a process substrate and a donor substrate after polishing the device portion.

[0017] Figure 11 Including after forming the vertical transistor Figure 10 An illustration of a cross-sectional view of a portion of a workpiece.

[0018] Figure 12 Including after forming transistors and resistors Figure 10 An illustration of a cross-sectional view of a portion of a workpiece.

[0019] Figure 13 An illustration including a cross-sectional view of a portion of a workpiece including a terminal wire bonded to a lead.

[0020] Figure 14 An illustration includes a cross-sectional view of a portion of a workpiece including a terminal and a conductive bump contacting the terminal.

[0021] The skilled person realizes that the elements in the drawings are shown for simplicity and are not necessarily drawn to scale. For example, the sizes of some elements in the drawings may be magnified relative to other elements to help improve the understanding of the specific implementation of the inventive concept. DETAILED DESCRIPTION

[0022] The following description, in conjunction with the accompanying drawings, is provided to assist in understanding the teachings disclosed herein. The following description will focus on specific implementations and specific implementations of the teachings. This emphasis is provided to assist in describing the teachings and should not be construed as limiting the scope or applicability of the teachings. However, other implementations may be employed based on the teachings as disclosed in this application.

[0023] As used herein, length and width are measured along or parallel to the major surface of a substrate or semiconductor layer, and depth, height, and thickness are measured perpendicular to the major surface of a substrate or semiconductor layer.

[0024] The term "electrically coupled" is intended to mean the connection, linking, or association of two or more electronic components, circuits, systems, or any combination of the following: (1) at least one electronic component, (2) at least one circuit, or (3) at least one system, in such a way that a signal (e.g., an electric current, voltage, or optical signal) can be partially or completely transferred from one to the other. A subset of "electrically coupled" may include an electrical connection between two electronic components. In a circuit diagram, a node corresponds to an electrical connection between electronic components. Thus, an electrical connection is a specific type of electrical coupling; however, not all electrical couplings are electrical connections. Other types of electrical coupling include capacitive coupling, resistive coupling, and inductive coupling.

[0025] The terms "horizontal," "lateral," and variations thereof are used in directions along or parallel to the major surface of a substrate or semiconductor layer, and the terms "vertical," "height," "depth," and variations thereof are used in directions perpendicular to the major surface of a substrate or semiconductor layer. Two laterally offset objects may be at the same or different heights.

[0026] The terms "overlapping," "disjointed," and variations thereof refer to at least portions of regions or other features that lie along a vertical line perpendicular to the plane defined by the major surfaces. Components or features that overlap or are disjointed from one another may or may not be in physical contact with one another.

[0027] The term "semiconductor component" is intended to refer to the material of a substrate, layer, or region that provides semiconductor properties to such substrate, layer, or region. This material may or may not include dopants. For example, an n-type doped Si layer and a p-type doped Si layer have the same semiconductor component, namely Si. However, an n-type doped Si layer and an n-type doped GaN layer have different semiconductor compositions because Si and GaN provide semiconductor properties and are different from each other.

[0028] Unless expressly stated otherwise, the boundary between a relatively heavily doped region or layer and an immediately adjacent relatively lightly doped region or layer of the same conductivity type is where the doping concentration between the regions or layers is 1.1 times higher than the peak doping concentration of the relatively lightly doped region or layer.

[0029] The terms "on," "overlying," and "over" may be used to indicate that two or more elements are in direct physical contact with each other. However, "over" may also mean that two or more elements are not in direct contact with each other. For example, "over" may mean that one element is above another element, but the elements are not in contact with each other and there may be another element or elements between the two elements.

[0030] The terms "comprises," "comprising," "having," "containing," or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that includes a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. In addition, unless expressly specified to the contrary, "or" refers to an inclusive or, not an exclusive or. For example, a condition A or B is satisfied by any of the following: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), and both A and B are true (or exist).

[0031] Additionally, "a" or "an" is used to describe an element, component, or other feature described herein. This is for convenience only and to give a general sense of the scope of the inventive concept. The description should be considered to include one, at least one, or the singular includes the plural, and vice versa, unless otherwise expressly stated. For example, where a single item is described herein, more than one item may be used in place of the single item. Similarly, where more than one item is described herein, the more than one item may be replaced by a single item.

[0032] The use of the words "about," "approximately," or "substantially" is intended to mean that the value of a parameter is close to the specified value or position. However, slight differences may prevent the value or position from being exactly as specified. Therefore, from the ideal goal of being exactly as described, differences of up to ten percent (10%) for values (and up to twenty percent (20%) for semiconductor doping concentrations) are reasonable differences.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concepts pertain. The materials, methods, and examples are illustrative only and not intended to be limiting. Where not described herein, many details regarding specific materials and processing actions are conventional and can be found in textbooks and other sources in the semiconductor and electronics arts.

[0034] A laser damaged region can be generated within a donor substrate. The device portion of the donor substrate can be along one side of the laser damaged region, and the remaining portion of the donor substrate can be along the opposite side of the laser damaged region. When the donor substrate is separated along the laser damaged region, the donor substrate can be bonded to a carrier substrate and a processing substrate. The device portion of the donor substrate can be used to manufacture electronic devices, wherein this manufacturing is performed while the processing substrate is bonded to the device portion. The device portion can have a greater thickness than that obtained using H + The semiconductor layer formed by the implantation technique is thicker and thinner than that of a stand-alone slice (without a processed substrate or other supporting substrate). Another device portion can be generated from the remaining portion of the donor substrate. This process is very suitable for semiconductor materials that are much more expensive than single-crystal Si or semiconductor materials that are difficult to grow epitaxial layers. This process is suitable for donor substrates with SiC semiconductor components.

[0035] In one aspect, a method may include: bonding a carrier substrate to a first major surface of a donor substrate; generating a laser damaged region within the donor substrate; bonding a processing substrate to a second major surface of the donor substrate, wherein the second major surface is opposite to the first major surface; and separating (1) the processing substrate and a device portion of the donor substrate from (2) the carrier substrate and a remaining portion of the donor substrate.

[0036] In another aspect, a method may include: bonding a carrier substrate to a donor substrate; generating a laser damaged region within the donor substrate; bonding a processing substrate to the donor substrate; separating (1) a device portion of the processing substrate and the donor substrate from (2) a remaining portion of the carrier substrate and the donor substrate; doping a portion of the device portion with a dopant; and activating the dopant to form a doped region from the portion of the device portion, wherein the activation is performed at a temperature of at least 1500°C.

[0037] In yet another aspect, an electronic device may include a device portion of a SiC substrate, wherein the device portion has a first main surface and a second main surface opposite the first main surface, and the device portion includes at least a portion of an electronic circuit element and a terminal electrically coupled to the electronic circuit element, wherein the terminal is along or on the first main surface of the device portion. The electronic device may further include a processing substrate bonded to the second main surface of the device portion, wherein the processing substrate has a thickness of no greater than 250 microns and a melting point greater than 1500°C.

[0038] Figure 1 A process flow for manufacturing an electronic device using a relatively thin layer of semiconductor material obtained from a donor substrate. The donor substrate is the source of the relatively thin layer of semiconductor material. The semiconductor material can have a semiconductor composition and be single crystalline. Examples of the semiconductor composition can be SiC, III-V semiconductors (e.g., GaAs or GaN, etc.), or II-VI semiconductors. SiC can be difficult to grow, and relatively high temperatures (e.g., 1500° C. to 1800° C.) can be used to activate one or more dopants implanted into the SiC. Although many of the descriptions address specific issues related to SiC, the concepts described herein can be extended to other semiconductor compositions.

[0039] The process described below uses a carrier substrate and a processing substrate. The materials used for the processing substrate, and possibly the carrier substrate, can depend on the semiconductor composition of the donor substrate, the bonding and separation operations, and the electronic device fabrication. During at least a portion of the electronic device fabrication, the processing substrate is processed using a thin layer of semiconductor material from the donor substrate. In a specific implementation, the donor substrate has a semiconductor composition that is single-crystalline SiC, which can be of the 3C, 4H, or 6H polytype.

[0040] The thin semiconductor material layer and the processing substrate can be exposed to temperatures ranging from room temperature (e.g., 20°C to 25°C) to the maximum temperature to which the thin semiconductor material layer and the processing substrate will be exposed. For SiC, dopants can be activated at temperatures in the range of 1500°C to 1800°C. In addition, epitaxial growth of SiC can be performed at temperatures in the same range. Thus, the processing substrate will be exposed to heat for activating dopants implanted into the thin semiconductor material layer and, if a SiC epitaxial layer is being grown, to heat during epitaxial growth.

[0041] If the difference between the coefficient of thermal expansion (CTE) of the thin semiconductor material layer and the processing substrate is too large, the thin semiconductor material layer may be damaged when the thin semiconductor material layer and the processing substrate are cycled between room temperature and the maximum temperature during the manufacturing process. Due to the large temperature range, the higher CTE of the thin semiconductor material layer or the processing substrate is at most twice the lower CTE of the other of the thin semiconductor material layer or the processing substrate.

[0042] When the thin layer of semiconductor material and the processing substrate have the same semiconductor composition, the higher CTE is the same as the lower CTE. When the donor substrate (the source of the thin layer of semiconductor material) has a SiC semiconductor composition and the processing substrate is Si3N4, the higher CTE is about 1.5 times the lower CTE. The melting point of Si3N4 is about 1900°C. Therefore, when the donor substrate is doped or undoped single crystal SiC, the processing substrate may include SiC or Si3N4. In specific embodiments, the processing substrate may include single crystal SiC that meets all specifications for manufacturing electronic devices, multicrystalline SiC, or a single crystal SiC ingot in which the ingot does not meet all specifications for manufacturing electronic devices ("failed SiC").

[0043] For all implementations, the processing substrate need not be SiC or Si3N4. For example, the donor substrate may be doped or undoped single crystal GaN or doped or undoped single crystal GaAs, etc. In addition to SiC and Si3N4, another material that can be used for the processing substrate may include sapphire, spinel, boron carbide, refractory metal, refractory metal nitride, or refractory metal oxide, as long as SiC, Si3N4, sapphire, spinel, boron carbide, the refractory metal, the refractory metal nitride, or the refractory metal oxide has a melting point higher than the highest temperature to which it will be exposed and has a CTE that is sufficiently close to the CTE of the material in the donor substrate.

[0044] The material used for the carrier substrate has a wider range than that of the processing substrate. The carrier substrate will not be processed during the manufacture of the electronic device and will therefore not be exposed to the relatively high temperatures that the processing substrate will reach. In addition to the aforementioned materials, many other materials can also be used. Exemplary materials may include Si (single crystal or polycrystalline) or SiO2-based materials such as quartz, fused silica, or glass.

[0045] The process may include Figure 1 The bonding surfaces of the carrier substrate and the donor substrate are prepared at block 102 in FIG. Before bonding, each substrate may have a surface having a root mean square surface roughness R of at most 0.5 nm for a 150 mm or 200 mm diameter substrate. RMS, nanotopography of up to 5 nm, local flatness of up to 0.5 microns, and substrate warpage of up to 300 microns. The limit of substrate warpage may depend in part on the material composition of the substrate, the size of the substrate (width or diameter if generally circular), or both. Grinding, lapping, polishing, or a combination thereof of the bonding surface may be performed to meet the criteria previously discussed. If any or all of the criteria cannot be met, a different substrate may be substituted.

[0046] The donor substrate 220 includes a major surface 222 and a major surface 224 opposite the major surface 222. The major surfaces 222 and 224 of the donor substrate 220 may be ground, lapped, polished, or a combination thereof. If the grinding, lapped, polished, or a combination thereof of the major surface 222 is performed after the laser damage zone is generated and before the subsequent bonding operation, the donor substrate 220 can be separated along the laser damage zone. A technician may perform testing using another donor substrate having substantially the same composition and average depth of the laser damage zone to ensure that the donor substrate can withstand grinding, lapped, polished, or a combination thereof after the laser damage zone is formed.

[0047] After any or all of the criteria are met, the bonding surface of the substrate may be cleaned. In a specific example, RCA cleaning may be performed. If a SiO2-based substrate is used, the oxide removal portion of the RCA cleaning may be omitted. Another cleaning process may be used to clean the bonding surface of the substrate. Figure 2 Included are illustrations of the carrier substrate 200 and the donor substrate 220 after the bonding surface has been prepared.

[0048] The process may include Figure 1 The carrier substrate and the donor substrate are bonded to each other at block 104 in FIG. The substrate bonding can be performed in a wafer-to-wafer bonding system available from EV Group Europe Asia / Pacific GmbH, St. Florianam Inn, Austria. The bonding can be performed at a temperature in the range of room temperature to 600° C., a down pressure in the range of 0.03 kPa to 350 kPa, and an ambient pressure less than atmospheric pressure. In a specific implementation, the bonding can be performed at room temperature, a down pressure in the range of 30 kPa to 350 kPa, and an ambient pressure of 1×10 -9 The bonding is performed at an ambient pressure in the range of mbar to 10 mbar. Figure 3 The interface 320 in FIG. 1 is bonded to the upper surface of the carrier substrate 200 .

[0049] The process may further include Figure 1 At block 122 , a laser damaged region is generated within the donor substrate. Figure 4A cross-sectional view is included as the laser 402 generates a laser damaged zone 420 within the donor substrate 220. The laser energy 404 can be focused at a desired depth within the donor substrate 220. In specific implementations, the laser energy can be red, near infrared (IR), or both radiation spectra. In the same or different implementations, a yttrium aluminum garnet (YAG) laser or a sapphire laser can be used. The YAG laser can be doped with Nd (peak emission at 1064 nm), Yb (peak emission at 1030 nm), or Cr (emission in the range of 1350 nm to 1550 nm). The sapphire laser can be doped with Ti and have peak radiation emission in the range of from 620 nm to 1100 nm. A frequency doubler, tripler, or quadrupler can be used, if needed or desired. For example, for an Nd:YAG laser, the emission frequency can be doubled to achieve radiation at 532 nm, tripled to achieve radiation at 355 nm, and quadrupled to achieve radiation at 266 nm. A skilled artisan can select the materials used for the laser and whether a frequency multiplier should be used to generate the laser damage zone 420.

[0050] The laser 402, the bonded workpiece including the donor substrate 220 and the carrier substrate 200, or both the laser 402 and the bonded workpiece may move during the laser damage generation operation. This movement is caused by Figure 4 In the laser damaged region 420 , the energy from the laser causes damage to the crystal of the donor substrate 220 .

[0051] The donor substrate 220 may have one or more sets of cleavage planes intersecting the major surface 222 of the donor substrate 220, wherein each set of cleavage planes has a corresponding crystal direction. Figure 4 , damage from the laser 402 should not propagate significantly in the vertical direction, as such cracks could extend through a significant portion or all of the thickness of the donor substrate 220 above, below, or both above and below the laser damaged region 420. To reduce the risk of forming vertical cracks, the laser or the workpiece can be moved so as to move in a direction that is not along the crystallographic directions corresponding to a set of cleavage planes.

[0052] Figure 5A top view of a donor substrate 220 and crystal directions 522 corresponding to a set of cleavage planes intersecting the major surface 222 of the donor substrate 220 is included. The relative motion of the laser 402 and the donor substrate 220 is illustrated by arrow 502 and is referred to as the laser direction. Prior to generating the laser damaged region 420, the workpiece with the donor substrate 220 can be rotated so that the laser direction 502 is perpendicular to the crystal direction 522. Due to manufacturing tolerances, the laser 402 can be traversed in the laser direction 502 within 5% of being perpendicular to the crystal direction 522. The laser 402 is traversed multiple times along spaced lines that are within 5% of being perpendicular to the crystal direction 522.

[0053] Figure 5 A donor substrate 220 is included having a single set of cleaved planes that intersect a major surface 222 of the donor substrate 220 and are parallel to each other. In another implementation, the donor substrate 220 may have multiple sets of cleaved planes. Figure 6 A top view of the donor substrate 220 and crystal directions 622 and 624 are included. Crystal directions 622 may correspond to one set of cleavage planes that intersect the major surface 222 of the donor substrate 220, and crystal directions 624 may correspond to another set of cleavage planes that intersect the major surface 222 of the donor substrate 220.

[0054] The intersection of crystal directions 622 and 624 at major surface 222 forms two angles: an acute angle α and an obtuse angle β. The relative motion of laser 402 relative to donor substrate 220 is indicated by arrow 602 and is referred to as the laser direction. To reduce the likelihood of crack propagation in the vertical direction during the creation of laser damaged zone 420, the workpiece with donor substrate 220 can be rotated so that laser direction 602 bisects obtuse angle β. Due to manufacturing tolerances, laser 402 can traverse along laser direction 602 within 5% of the bisected angle. Laser 402 is traversed multiple times along spaced lines that are within 5% of the bisect of obtuse angle β.

[0055] In another embodiment, the workpiece with the donor substrate 220 can be rotated so that the laser direction 602 bisects the acute angle α. Due to manufacturing tolerances, the laser 402 can be traversed in the laser direction 602 within 5% of the bisected angle. The laser 402 is traversed multiple times along spaced lines that are within 5% of the bisected acute angle α. The bisected angle based on the obtuse angle β will be closer to perpendicular to the two sets of cleavage planes. If the obtuse angle β is not bisected, the bisected angle based on the acute angle α provides an alternative.

[0056] The average depth of the laser damaged region 420 can be selected based on the thickness of the device portion of the donor substrate 220 in the finished electronic device. The thickness of the device portion of the donor substrate 220 can be in the range of 11 microns to 150 microns. In a specific implementation, the thickness of the device portion of the donor substrate 220 can be in the range of 11 microns to 95 microns. The latter range can be useful when the device portion may include the drift region of a power transistor, where the voltage difference between the current-carrying electrodes or regions (drain-to-source voltage or collector-to-emitter voltage) is at least 200V when the power transistor is turned off.

[0057] The subsequent separation operation is performed, and after separation, some laser damage from the laser damaged region 420 will be present in the device portion and the remaining portion of the donor substrate 220. The laser damage along the device portion and the remaining portion of the donor substrate 220 can be removed before they are further processed. Therefore, the average depth of the laser damaged region 420 from the major surface 222 is greater than the thickness of the device portion of the donor substrate 220 in the finished electronic device. The power of the laser can be adjusted to achieve the average depth of the laser damaged region 420.

[0058] The laser 402 may traverse the workpiece multiple times while creating the laser damage region 420. Each pass may be spaced apart from its nearest neighbor or pair of nearest neighbors by a distance ranging from 20 microns to 500 microns. More closely spaced passes may make subsequent separation easier; however, more passes may increase the time it takes to create the laser damage region 420. A skilled artisan may determine the spacing of the passes to achieve a desired balance between ease of separation and the processing time required to create the laser damage 420.

[0059] The process may include Figure 1 The bonding surfaces of the processing substrate and the donor substrate are prepared at block 142. Figure 7 , the main surface 222 of the donor substrate 220 will be bonded to the bottom surface of the processing substrate 700. Before bonding the donor substrate 220 and the upper surface of the carrier substrate 200, the preparation of the bottom surface of the processing substrate 700 can be substantially the same as the preparation of the upper surface of the carrier substrate 200. The main surface 222 can have the same Figure 1 Thus, the workpiece including the carrier substrate 200 and the donor substrate 220 may only require cleaning of the major surface 222 without grinding, lapping, or polishing.

[0060] The process may include Figure 1The processing substrate and the donor substrate are bonded to each other at block 144 in FIG. The substrate bonding can be performed in a wafer-to-wafer bonding system available from EV Group Europe Asia / Pacific GmbH, St. Florianam Inn, Austria. The bonding can be performed at a temperature in the range of room temperature to 600° C., a down pressure in the range of 0.03 kPa to 350 kPa, and an ambient pressure less than atmospheric pressure. In a specific implementation, the bonding can be performed at room temperature, a down pressure in the range of 30 kPa to 350 kPa, and an ambient pressure of 1×10 -9 The bonding is performed at an ambient pressure in the range of mbar to 10 mbar. The bonding conditions may be different or the same for different materials. Thus, the bonding conditions when bonding the processed substrate 700 to the donor substrate 220 may be the same or different than when bonding the carrier substrate 200 to the donor substrate 220. The main surface 222 is along Figure 8 The interface 820 in FIG. 8 is bonded to the lower surface of the processed substrate 700 .

[0061] The process may further include Figure 1 The bonded substrates are separated along the laser damaged area at block 162. Figure 8 and Figure 9 The separation occurs along the laser damaged area 420 to form a workpiece including the processing substrate 700, the device portion 922 of the donor substrate 220, and a portion 921 of the laser damaged area 420, and another workpiece including the carrier substrate 200, the remaining portion 924 of the donor substrate 220, and a portion 923 of the laser damaged area 420. The separation can be performed using acoustic energy, thermal cycling, or mechanical separation. The acoustic energy may include applying Figure 8 The workpiece is shown placed in an ultrasonic or megasonic bath.

[0062] Thermal cycling may include Figure 8 In another embodiment, the thermal cycle may include bringing the workpiece from room temperature to an elevated temperature and back to room temperature. Figure 8 When the workpiece is brought to an elevated or low temperature, the elevated or low temperature may be affected by: the thickness, CTE, or both thickness and CTE of the substrate 200, 220, 700; the location, thickness, and quality of the laser damaged region 420 (e.g., the spacing between laser channels when generating the laser damaged region 420); another material (if used) that is in contact or not in contact with the processing substrate 700 or the carrier substrate 200; or any combination thereof.

[0063] In one embodiment, the spacing between the laser channels can be relatively small, for example, 10 to 20 microns. During the separation operation, the workpiece can be exposed to a temperature relatively closer to room temperature (e.g., as low as -30°C for the low temperature or as high as +70°C for the elevated temperature). In another embodiment, the spacing between the laser channels can be relatively large, for example, 300 to 1000 microns. During the separation operation, the workpiece can be exposed to a temperature relatively far from room temperature (e.g., as low as -200°C or as high as +900°C).

[0064] In the same or different embodiments, a material may be in contact with substrate 200 or 700, wherein the material and the substrate coupled to the material have different CTEs. In a specific embodiment, the material may be a polymer that contacts substrate 200 or 700, and the combination of substrates 200, 220, and 700 and the material may be placed in contact with liquid N2 or liquid Ar or exposed to a gas having a temperature below -50°C (e.g., a gas vaporized from liquid N2 or liquid Ar or a gas sublimated from CO2). In another specific embodiment, a metal or metal alloy may be attached to or formed along the exposed main surface of substrate 200 or 700. A workpiece including substrates 200, 220, and 700 and the metal or metal alloy may be exposed to an environment having a relatively higher temperature than the polymer. For example, the workpiece may be exposed to an environment of 500°C. For either or both implementations, the difference in CTE of the material and the substrate most closely coupled to the material may cause the substrate to become slightly concave or convex and allow sufficient force to separate the donor substrate 220 along the laser damaged region 420 .

[0065] Other techniques utilizing thermal processing may be used. The selected technique should allow the donor substrate 220 to be separated along the laser damaged region 420 without significantly adversely affecting the donor substrate 220 at locations spaced apart from the laser damaged region 420. For example, a crack extending through the thickness of the device portion 922 or the remainder portion 924 may not allow the device portion 922 or the remainder portion 924 to be further processed. A skilled artisan may perform experiments utilizing a particular technique to determine whether the particular technique can be used without significantly adversely affecting the device portion 922 or the remainder portion 924.

[0066] A mechanical force may be used during the separation operation. The force may include pulling the substrates 200 and 700 apart, applying a torque to the substrate 200 or 700 while holding the other of the substrates 200 and 700 in place, applying an angular force to the substrate similar to a peeling action, or inserting a wedge along the laser damaged area 420. Other mechanical forces may be used if necessary or desired. In a specific implementation, the mechanical force may be used in conjunction with another separation technique (e.g., acoustic energy or thermal processing) to help facilitate separation. In this specific implementation, the mechanical force alone may not be sufficient to perform the separation. If only the mechanical force is used to perform the separation, significant damage to the device portion 922, the remaining portion 924, or both is more likely to occur.

[0067] The process may include Figure 1 The device portion of the donor substrate is polished at frame 182. The workpiece may include the device portion 922 of the donor substrate and the processing substrate 700. After separation, a portion 921 of the laser damaged area 420 is removed along the exposed surface of the device portion 922 of the donor substrate. The damage can be removed by polishing. If necessary or desired, grinding or lapping can be performed before polishing. After polishing, the main surface 1022 of the device portion 922 can have a surface as previously described. Figure 1 The surface properties described in block 102 of FIG. When removing the laser damage, bonding the processed substrate 700 and the device portion 922 together reduces the likelihood of cracking or breaking the device portion 922 compared to removing the laser damage from the device portion 922 in the absence of the processed substrate 700 .

[0068] For a workpiece comprising the remainder 924 of the donor substrate and the carrier substrate 200, the process may include polishing the remainder 924 of the donor substrate. After separation, a portion 923 of the laser damaged area 420 is removed along the exposed surface of the remainder 924 of the donor substrate. The damage may be removed by polishing. If necessary or desired, grinding or lapping may be performed before polishing. After polishing, the exposed major surface of the remainder 924 may have a surface as previously described. Figure 1 The surface properties described in block 102 of the donor substrate are obtained. If the remaining portion 924 is thick enough to produce another device portion, a workpiece including the remaining portion 924 and the carrier substrate 200 can be used to produce another device portion from the remaining portion 924. Another processed substrate can have its bonding surface prepared as previously described. The process continues at block 144, where another processed substrate is bonded to the remaining portion 924 of the donor substrate. If the remaining portion 924 is too thin, the workpiece can be discarded, or the remaining portion 924 can be removed and the carrier substrate 200 can be reused.

[0069] Returning to the workpiece including the device portion 922 of the donor substrate and the processed substrate 700, the process may further include Figure 1The device portion 922 of the donor substrate at block 184 is used to manufacture an electronic device. Many different types of electronic devices can be manufactured using a workpiece comprising the device portion 922 of the donor substrate and the processed substrate 700. The following examples are intended to illustrate, but not to limit, the inventive concepts as defined in the appended claims. Many other electronic devices can be manufactured.

[0070] Figure 11 Included is a cross-sectional view of a portion of a workpiece including a device portion 922 and a processed substrate 700. The workpiece may be used to manufacture electronic devices that may include power transistors. Figure 11 The features in FIG. 1 are not drawn to scale so that the features of the transistor structure of the power transistor can be more easily understood. Figure 11 In the embodiment of the present invention, the source electrode 1180 is electrically coupled to the source region 1126 and the body contact region 1156. The source region 1126 and the body contact region 1156 are heavily doped to form an ohmic contact with the source electrode 1180. The body region 1136 is located below the source region 1126 and the body contact region 1156 and extends to the sidewalls of the gate trench. The portion of the body region 1136 at the sidewalls of the gate trench comprises the channel region of the transistor structure. The dopant concentration of the source region 1136 can be between 1×10 15 atoms / cm 3 to 1×10 17 atoms / cm 3 The dopant concentration can be selected to achieve the desired threshold voltage of the transistor structure. The shielding region 1132 is located along the bottom of the gate trench and helps reduce the voltage along the bottom of the trench. The shielding region 1132 can be Figure 11 The shielding region 1132 may have a moderate dopant concentration, such as 1×10 16 atoms / cm 3 to 1×10 18 atoms / cm 3 If needed or desired, the dopant concentration of the main region 1136, the shielding region 1132, or both the main region 1136 and the shielding region 1132 can be outside the stated range.

[0071] The doped region may be formed from a portion of the device portion 922 of the donor substrate. The portion of the device portion 922 below the body region 1136 and the shielding region 1132 may be the drift region of the power transistor. The source region 1126 and the device portion 922 may have the same conductivity type, such as n-type, and the body contact region 1156, the body region 1136, and the shielding region 1132 may have opposite conductivity types, such as p-type.

[0072] In a specific implementation, device portion 922 may have a SiC semiconductor composition. Activating dopants in SiC is performed at a substantially higher temperature than activating dopants in Si. After doping device portion 922 for source region 1126, body contact region 1156, body region 1136, and shield region 1132, and prior to forming source electrode 1180, drain electrode 1190, and features within the gate trench, dopants within the workpiece may be activated during an anneal at a temperature in the range of 1500° C. to 1800° C. for a duration in the range of 10 minutes to 30 minutes. Such high temperatures may limit the materials used for processing substrate 700. For example, processing substrate 700 may not include single crystal silicon, polycrystalline silicon (polySi), or SiO2-based materials, as these materials may melt or deform during annealing. In a specific implementation, processing substrate 700 may include heavily doped polycrystalline SiC (polySiC) or heavily doped substandard SiC. In this particular implementation, the fabricated substrate 700 may be part of the drain region of the power transistor.

[0073] The workpiece may be patterned to define the gate trench before or after performing an anneal to activate the dopant. After the anneal, a gate dielectric layer 1122 and a gate electrode 1124 may be formed within the gate trench. The gate dielectric layer 1122 may include an oxide, a nitride, an oxynitride, or a combination thereof. The gate electrode 1124 may include a conductive material, such as heavily doped polySi or W. The gate electrode 1124 is recessed within the gate trench to reduce gate-source capacitance. An insulating layer 1170 may be formed over the source region 1126, the body contact region 1156, and within the remainder of the gate trench. The insulating layer 1170 may include a single film or multiple films, wherein any of the single film or the multiple films includes an oxide, a nitride, or an oxynitride. The portion of the insulating layer 1170 outside the gate trench is removed using chemical mechanical polishing (CMP) or a resist etch back technique.

[0074] The source electrode 1180 may be formed by depositing a conductive layer and patterning the conductive layer to form the source electrode 1180. The back side of the workpiece may be ground, polished, or etched to remove a portion of the processed substrate 700, thereby forming a remaining portion of the processed substrate 700, such as Figure 11 The remaining portion of the processed substrate 700 is shown. Figure 11 , and has a thickness in the range of 20 microns to 200 microns. A drain electrode 1190 is attached or formed along the bottom surface of the processed substrate 700. More transistor structures (not shown) may be formed, where such more transistor structures are part of the power transistor or a different power transistor. A substantially finished electronic device has been formed.

[0075] Can include Figure 11 The transistor structure workpiece is singulated into dies, and the dies can be packaged. In a specific implementation, the packaged dies can be discrete devices.

[0076] In another embodiment, the power transistor may be an insulated gate bipolar transistor (IGBT). The IGBT may have Figure 11 The structure shown is substantially the same; however, the device portion 922 may include a heavily doped region of the same conductivity type as the device portion 922 along the interface with the process substrate 700, and the process substrate 700 may be heavily doped and have the opposite conductivity type. For example, the heavily doped region may be n-type, and the process substrate 700 may be p-type.

[0077] In further implementations, the device portion 922 of the donor substrate can be fabricated to form an integrated circuit. Figure 12 The electronic device 1200 includes a switching circuit. Although not shown, the processing substrate 700 is bonded to the device portion 922 of the donor substrate. The electronic device 1200 includes a V resistor 1242 electrically coupled to the resistor 1242. DD Terminal 1292, V electrically coupled to source region 1226 of transistor 1220 SS terminal 1296, a gate terminal 1294 electrically coupled to the gate electrode 1224 of the transistor 1220, and an output terminal 1298 electrically coupled to the drain region 1222 of the transistor 1220 and the resistor 1242. Although not shown, the device portion 922 may be coupled to V SS Terminal 1296.

[0078] In a particular implementation, the switching circuit can be an inverter, wherein the gate terminal 1294 is the input terminal of the inverter. The transistor 1220 can be an n-channel enhancement mode insulated gate field effect transistor, and the resistor 1242 can have a relatively high resistance. When the transistor 1220 is off, the output terminal 1298 can be substantially at V DD When transistor 1220 is turned on, the voltage on output terminal 1298 is pulled down and becomes substantially V SS Thus, when the voltage on the gate terminal 1294 is relatively low, the voltage at the output terminal 1298 is relatively high, and when the voltage on the gate terminal 1294 is relatively high, the voltage at the output terminal 1298 is relatively low.

[0079] In a specific implementation, the device portion 922 may have a SiC semiconductor component. Figure 12A doped region is implanted into the device portion 922 of the donor substrate before any of the other features shown in FIG. The doped region may include a drain region 1222 and a source region 1226, and may include an optional doped region (not shown) between the drain region 1222 and the source region 1226 to adjust the threshold voltage (V TH ), the formation of a lightly doped drain (LDD) adjacent to the drain region 1222 and the source region 1226, or V TH The conductivity type of the drain region 1222 and the source region 1226 can be opposite to the conductivity type of the device portion 922. For example, the drain region 1222 and the source region 1226 can be n-type doped, and the device portion 922 can be p-type doped. Figure 11 Annealing is performed for the time and temperature described for electronic device 1100 in order to activate the dopants implanted into device portion 922 .

[0080] The device portion 922 may be patterned to define trenches for shallow trench isolation (STI) 1202. Defining the trenches may be performed before or after annealing to activate dopants. The material for STI 1202 may include one or more films of oxide, nitride, or oxynitride. The material may be deposited within the trenches and over the drain region 1222, source region 1226, and device portion 922 of the donor substrate. A portion of the material outside the trenches is removed by CMP or resist etch-back techniques to form STI 1202.

[0081] A gate dielectric layer 1228 is formed over the active region of transistor 1220 and STI 1202. Gate dielectric layer 1228 may include an oxide, a nitride, or an oxynitride. Gate dielectric layer 1228 is patterned to define an opening where resistor 1242 will contact drain region 1222. A polySi layer may be formed over gate dielectric layer 1228 and within the opening extending through gate dielectric layer 1228. The polySi layer may be doped or undoped. When the polySi layer is doped, its dopant concentration may correspond to the dopant concentration of resistor 1242. Alternatively, the undoped polySi layer may be blanket doped (without a resist mask present on the workpiece during doping) to achieve the dopant concentration of resistor 1242. A resist mask may be formed over the location where the body of resistor 1242 will be formed, and the exposed portions of the polySi layer correspond to the locations where the terminal connections of gate electrode 1224 and resistor 1242 will be formed (corresponding to the locations where conductive vias 1280 contact resistor 1242). The exposed portions of the polySi layer are heavily doped, and the resist mask is removed. The polySi layer may be patterned to form resistor 1242 and gate electrode 1224. At this point, many other electronic components may be formed, including other transistors, other resistors, and capacitors.

[0082] An interlayer dielectric (ILD) layer 1270 is formed over the workpiece and may include one or more films comprising oxide, nitride, or oxynitride. The ILD layer 1270 may be planarized using CMP or resist etch-back techniques. The ILD layer 1270 may be patterned to define contact openings in which conductive vias 1280 are formed. Figure 12 As shown, contact openings are formed at resistor 1242, drain region 1222, and source region 1226. Although not shown, the contact openings extend to gate electrode 1224. Before forming the remainder of the conductive via, the exposed portions of resistor 1242, drain region 1222, gate electrode 1224, and source region 1226 may or may not be silicided. Further fabrication is performed to form at least one or more ILDs, at least one interconnect level, and optionally one or more levels of conductive vias. Inductors may or may not be formed. Inductors may be formed from interconnects at different interconnect levels and conductive vias connecting interconnects at different levels, or they may be planar inductors formed from a conductive layer.

[0083] A passivation layer or polyimide layer may be formed on the uppermost interconnect level and patterned to expose terminals (external terminals). Terminals 1292 , 1294 , 1296 , 1298 may be external terminals or internal terminals connected to other electronic components or other circuits within electronic device 1200 .

[0084] The electronic device 1200 may include many other electronic components and circuits and may be an integrated circuit. The integrated circuit may be a solid-state memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, and magnetoresistive random access memory (MRAM)), a microprocessor, a microcontroller, a graphics processing unit, a digital signal processor, a field programmable gate array (FPGA) or a semiconductor element, a power transistor, a charge coupled device (CCD), or an image sensor, etc.

[0085] The electronic devices, such as electronic devices 1100 or 1200, can be ground, polished, or etched to thin or remove the processing substrate 700. In a specific implementation, a portion of the processing substrate 700 is removed, but not all of it. The remaining portion of the processing substrate 700 can have a thickness in the range of 11 microns to 200 microns. In a specific implementation, the thickness can be in the range of 20 microns to 95 microns, so that the combination of the device portion 922 of the donor substrate 220 and the remaining portion of the processing substrate 700 has sufficient thickness to withstand the forces during singulation and assembly operations and still allow the workpiece to be singulated without complication. The workpiece can be singulated into dies, each of which includes an electronic device.

[0086] Figure 13 13. A cross-sectional view of an electronic device 1300 and leads 1360 of a lead frame. The electronic device 1300 includes the remaining portion of the processed substrate 700, the device portion 922 of the donor substrate, an electronic component region 1320 formed at least partially within an upper portion of the device portion 922, an ILD layer 1370, and terminals 1380. The electronic component region 1320 may include transistors, resistors, capacitors, or a combination thereof. In practice, the electronic component region 1320 may include thousands of transistor structures and many resistors and capacitors. In practice, the combination of the ILD layer 1370 and the terminals 1380 may be one or more ILD layers and one or more interconnect levels. Thus, Figure 13 13. It is a simplified diagram of an actual electronic device and is used to simplify the understanding of post-manufacturing operations. The terminal can be exposed along the upper surface of the electronic device and is represented by terminal 1380. Lead 1390 can be bonded to terminal 1380 and lead 1360 to allow the voltage or signal from the outside of the tube core to be received by terminal 1380 or the voltage or signal from the electronic device 1300 to be transmitted to the outside of the tube core via terminal 1380. Other terminals and leads can be wire bonded. The combination of electronic device 1300 and leads (including lead 1360) can be encapsulated by molding compound or can be sealed in a ceramic package.

[0087] Figure 14The electronic device 1400 is substantially the same as the electronic device 1300 (except that the conductive bump 1460 is formed on the terminal 1380). Figure 14 As shown, the conductive bumps may be reflowed, or not reflowed at this stage in the process. Electronic device 1400 may contact or be in close proximity to a printed wiring or circuit board or another tube core. The other tube core may be substantially the same as or significantly different from the electronic device 1400. The conductive bumps (including conductive bumps 1460) may be reflowed to electrically couple the electronic device 1400 to such printed wiring or circuit board or other tube core. Before or after the electronic device 1400 is electrically coupled to the printed wiring or circuit board or other tube core, the electronic device 1400 may be or may not be encapsulated by molding compound, or may be sealed in a ceramic package.

[0088] Many other assemblies (post-wafer fabrication operations) may be performed instead or in conjunction with wire bonding or conductive bumping. After reading this specification, a skilled person will be able to determine the post-fabrication process to meet the needs or expectations of a particular application.

[0089] Many electrical couplings are described above. Any or all of the electrical couplings may be electrical connections, where an electrical connection is a specific type of electrical coupling. For example, Figure 11 , the source electrode 1180 is electrically connected to the source region 1126 and the body contact region 1156. The drain electrode 1190 is electrically connected to the processing substrate 700. The gate terminal (at Figure 11 (not shown) can be electrically connected to the gate electrode 1124. Figure 12 One end of the resistor 1242 is electrically connected to V DD The other end of the terminal 1292 is electrically connected to the source region 1226 and the output terminal 1298. For the electronic device 1200, the substrate 700 is processed (in Figure 12 (not shown) can be electrically connected to ground.

[0090] The device portion of the donor substrate can have a thickness that is very suitable for manufacturing electronic devices. +The implantation process produces thicker slices, which in practice may be limited to a thickness of less than 10 microns. The donor substrate can be joined to a processing substrate before the device and the remainder of the donor substrate are separated from each other. The processing substrate allows the device portion of the donor substrate to have a thickness that would otherwise be too thin to withstand the handling and processing conditions when manufacturing electronic components within the device portion in the absence of a processing substrate or another substrate that provides mechanical support for the device portion. In the absence of the processing substrate, independent SiC slices can be 350 microns thick or thicker in order to withstand the handling and processing conditions of the manufacturing process. The process as described herein can produce more device portions than independent SiC slices from SiC ingots because the thickness of these device portions can be significantly thinner than the independent SiC slices.

[0091] Furthermore, because the donor substrate and the processing substrate are bonded together before the separation operation, a post-separation bonding operation is avoided.

[0092] The processing substrate can be selected from a variety of materials, provided that the selected material can withstand the highest processing temperature used in the fabrication process and has a CTE reasonably close to the CTE of the device portion of the donor substrate.

[0093] Many different aspects and implementations are possible. Some of those aspects and implementations are described below. After reading this specification, those skilled in the art will recognize that those aspects and implementations are merely illustrative and do not limit the scope of the inventive concept. Implementations may be based on any one or more of the implementations listed below.

[0094] Specific implementation 1 A method may include: bonding a carrier substrate to a first major surface of a donor substrate; generating a laser damaged area within the donor substrate; bonding a processing substrate to a second major surface of the donor substrate, wherein the second major surface is opposite to the first major surface; and separating (1) the device portion of the processing substrate and the donor substrate from (2) the remaining portion of the carrier substrate and the donor substrate.

[0095] Implementation 2 The method according to Implementation 1 further includes heating the processing substrate and the device portion at a temperature of at least 1500° C. after separating (1) the processing substrate and the device portion of the donor substrate and (2) the carrier substrate and the remaining portion of the donor substrate from each other.

[0096] Implementation 3 The method according to Implementation 1, wherein after the carrier substrate is bonded to the first major surface of the donor substrate, the donor substrate has a set of cleavage planes intersecting the first major surface along a crystal direction, and generating the laser damaged zone includes: moving the laser laterally in a laser direction that is within 5% of perpendicular to the crystal direction.

[0097] Implementation 4 The method according to Implementation 1, wherein after the carrier substrate is bonded to the first major surface of the donor substrate, the donor substrate has a first set of first cleavage planes and a second set of second cleavage planes, wherein the first set of first cleavage planes intersects the first major surface along a first crystal direction, the second set of second cleavage planes intersects the first major surface along a second crystal direction, and the first crystal direction and the second crystal direction intersect at an angle along the first major surface of the donor substrate, and generating the laser damage zone includes: traversing the laser in a laser direction that is within 5% of bisecting the angle.

[0098] Implementation 5 The method according to Implementation 1 further includes: polishing the device portion of the donor substrate after separating (1) the processing substrate and the device portion of the donor substrate and (2) the carrier substrate and the remaining portion of the donor substrate from each other.

[0099] Embodiment 6: The method according to embodiment 5, wherein after polishing the device portion, the device portion has a thickness in a range of 11 micrometers to 99 micrometers.

[0100] Embodiment 7 The method according to embodiment 5 further includes forming an electronic circuit element at least partially within the device portion of the donor substrate.

[0101] Implementation 8 The method according to Implementation 1, wherein separating (1) the device portion of the processing substrate and the donor substrate from (2) the remaining portion of the carrier substrate and the donor substrate includes: exposing the carrier substrate, the donor substrate and the processing substrate to acoustic energy.

[0102] Implementation 9 The method according to Implementation 1, wherein separating the device portion of the processing substrate and the donor substrate from the remaining portion of the carrier substrate and the donor substrate comprises heating, cooling, or heating and cooling the carrier substrate, the donor substrate, and the processing substrate.

[0103] Specific implementation 10 According to the method of specific implementation 1, separating the device portion of the processing substrate and the donor substrate from the remaining portion of the carrier substrate and the donor substrate includes: applying mechanical force to the carrier substrate, the donor substrate and the processing substrate.

[0104] Embodiment 11: The method according to embodiment 1, wherein the donor substrate comprises single crystal SiC, and the processing substrate comprises SiC or Si3N4.

[0105] Specific implementation 12 is a method according to specific implementation 1, wherein the processing substrate includes sapphire, spinel, boron carbide, refractory metal, refractory metal nitride or refractory metal oxide, wherein sapphire, spinel, boron carbide, the refractory metal, the refractory metal nitride or the refractory metal oxide has a melting point of at least 1500°C and has a thermal expansion coefficient in the range of 50% to 150% of the thermal expansion coefficient of the donor substrate.

[0106] Specific implementation 13 A method may include: bonding a carrier substrate to a donor substrate; generating a laser damaged region within the donor substrate; bonding a processing substrate to the donor substrate; separating (1) a device portion of the processing substrate and the donor substrate from (2) a remaining portion of the carrier substrate and the donor substrate; doping a portion of the device portion with a dopant; and activating the dopant to form a doped region from the portion of the device portion, wherein the activation is performed at a temperature of at least 1500°C.

[0107] Embodiment 14 The method according to Embodiment 13 further includes: singulating the device portion and the processed substrate to form a plurality of dies after annealing the device portion and the processed substrate.

[0108] Specific implementation 15 The method according to specific implementation 14 further includes: wire-bonding the leads of the lead frame and the terminals of a specific tube core among the multiple tube cores; or forming a conductive bump above the terminal of the specific tube core so that the conductive bump and the terminal are electrically coupled to each other.

[0109] Embodiment 16. The method of embodiment 14, wherein a particular die of the plurality of dies includes a plurality of transistor structures.

[0110] Specific embodiment 17: An electronic device may include: a device portion of a SiC substrate and a processing substrate. The device portion may have a first main surface and a second main surface opposite the first main surface, and the device portion includes at least a portion of an electronic circuit element and a terminal electrically coupled to the electronic circuit element, wherein the terminal is along or on the first main surface of the device portion. The processing substrate may be bonded to the second main surface of the device portion, wherein the processing substrate has a thickness of no greater than 250 micrometers and a melting point greater than 1500°C.

[0111] Embodiment 18 The electronic device according to Embodiment 17 further includes a conductive bump electrically coupled to the terminal.

[0112] Embodiment 19 The electronic device according to Embodiment 17 further includes: a lead; and a wire bonded to the terminal and the lead.

[0113] Embodiment 20: The electronic device according to embodiment 17, wherein the device portion has a thickness in the range of 11 micrometers to 150 micrometers, and the processed substrate has a thickness in the range of 20 micrometers to 200 micrometers.

[0114] Embodiment 21. The electronic device according to embodiment 17, wherein the processed substrate has a thermal expansion coefficient in a range of 50% to 150% of the thermal expansion coefficient of SiC.

[0115] It should be noted that not all activities described above in the general description or examples are required, that a portion of a specific activity may not be required, and that one or more additional activities may be performed in addition to those described. Also, the order in which the activities are listed is not necessarily the order in which the activities are performed.

[0116] While benefits, other advantages, and solutions to problems have been described above with respect to specific implementations, none of these benefits, advantages, solutions to problems, nor any features that may make any benefit, advantage, or solution apparent, should be construed as critical, required, or essential features of any or all of the claims.

[0117] The description and illustrations of the specific implementations described herein are intended to provide a general understanding of the structures of the various specific implementations. The description and illustrations are not intended to be an exhaustive and comprehensive description of all elements and features of the devices and systems using the structures or methods described herein. Separate specific implementations may also be provided in combination in a single specific implementation. On the contrary, the various features described in the context of a single specific implementation for the sake of simplicity may also be provided individually or in any sub-combination. In addition, reference to values expressed as ranges includes all values within the range. Many other specific implementations are apparent only to those skilled in the art after reading this specification. Other specific implementations may be used and derived from this disclosure so that structural replacements, logical replacements, or other changes can be made without departing from the scope of this disclosure. Therefore, this disclosure should be considered exemplary, not restrictive.

Claims

1. A method comprising: bonding a carrier substrate to the first major surface of the donor substrate; generating a laser damaged region in the donor substrate; bonding a processing substrate to a second major surface of the donor substrate, wherein the second major surface is opposite the first major surface; as well as (1) the process substrate and the device portion of the donor substrate and (2) the carrier substrate and the remaining portion of the donor substrate are separated from each other.

2. The method according to claim 1, further comprising: The process substrate and the device portion are heated at a temperature of at least 1500° C. after separating (1) the process substrate and the device portion of the donor substrate and (2) the carrier substrate and the remaining portion of the donor substrate from each other.

3. The method according to claim 1, wherein: After bonding the carrier substrate to the first major surface of the donor substrate, the donor substrate has a set of cleavage planes intersecting the first major surface along crystal directions, and Generating the laser damaged region includes traversing a laser in a laser direction that is within 5% of a perpendicular direction to the crystal.

4. The method according to claim 1, wherein: After bonding the carrier substrate to the first major surface of the donor substrate, the donor substrate has a first set of first cleavage planes and a second set of second cleavage planes, wherein the first set of first cleavage planes intersect the first major surface along a first crystal direction, the second set of second cleavage planes intersect the first major surface along a second crystal direction, and the first crystal direction and the second crystal direction intersect at an angle along the first major surface of the donor substrate, and Generating the laser damaged zone includes traversing the laser in a laser direction that is within 5% of bisecting the angle.

5. The method according to claim 1, further comprising: The device portion of the donor substrate is polished after (1) the process substrate and the device portion of the donor substrate and (2) the carrier substrate and the remaining portion of the donor substrate are separated from each other. The method according to claim 5 , wherein after polishing the device portion, the device portion has a thickness in a range of 11 μm to 99 μm.

7. The method according to claim 5, further comprising: An electronic circuit element is formed at least partially within the device portion of the donor substrate.

8. The method of claim 1 , wherein separating (1) the processing substrate and the device portion of the donor substrate and (2) the carrier substrate and the remaining portion of the donor substrate from each other comprises: The carrier substrate, the donor substrate, and the processing substrate are exposed to acoustic energy.

9. The method of claim 1 , wherein separating the device portion of the process substrate and the donor substrate from the remaining portion of the carrier substrate and the donor substrate comprises: The carrier substrate, the donor substrate, and the processing substrate are heated, cooled, or both heated and cooled.

10. The method of claim 1, wherein separating the device portion of the process substrate and the donor substrate from the remaining portion of the carrier substrate and the donor substrate comprises: A mechanical force is applied to the carrier substrate, the donor substrate, and the processing substrate.

11. The method of claim 1, wherein the donor substrate comprises single crystal SiC, and the processing substrate comprises SiC or Si3N4.

12. The method of claim 1 , wherein the processing substrate comprises sapphire, spinel, boron carbide, a refractory metal, a refractory metal nitride, or a refractory metal oxide, wherein sapphire, spinel, boron carbide, the refractory metal, the refractory metal nitride, or the refractory metal oxide has a melting point of at least 1500° C. and has a thermal expansion coefficient in the range of 50% to 150% of the thermal expansion coefficient of the donor substrate.

13. A method comprising: bonding the carrier substrate to the donor substrate; generating a laser damaged region in the donor substrate; bonding a processing substrate to the donor substrate; separating (1) the processing substrate and the device portion of the donor substrate and (2) the carrier substrate and the remaining portion of the donor substrate from each other; doping a portion of the device portion with a dopant; as well as The dopant is activated to form a doped region from the portion of the device portion, wherein the activation is performed at a temperature of at least 1500°C.

14. The method according to claim 13, further comprising: The device portion and the process substrate are singulated to form a plurality of dies after annealing the device portion and the process substrate.

15. The method according to claim 14, further comprising: wire bonding leads of a lead frame and terminals of a particular die of the plurality of dies to each other; or Conductive bumps are formed over the terminals of the specific die such that the conductive bumps and the terminals are electrically coupled to each other. The method of claim 14 , wherein a particular die of the plurality of dies comprises a plurality of transistor structures.

17. An electronic device, comprising: The device portion of the SiC substrate includes: The device portion has a first major surface and a second major surface opposite the first major surface, and the device portion includes at least a portion of an electronic circuit element and a terminal electrically coupled to the electronic circuit element, wherein the terminal is along or on the first major surface of the device portion; and An engineered substrate is bonded to the second main surface of the device portion, wherein the engineered substrate has a thickness of not greater than 250 micrometers and a melting point greater than 1500°C.

18. The electronic device according to claim 17, further comprising: A conductive bump is electrically coupled to the terminal.

19. The electronic device according to claim 17, further comprising: lead; and A wire is bonded to the terminal and the lead. 20 . The electronic device according to claim 17 , wherein the device portion has a thickness in a range of 11 to 150 micrometers, and the processed substrate has a thickness in a range of 20 to 200 micrometers.

21. The electronic device of claim 17, wherein the engineered substrate has a thermal expansion coefficient in a range of 50% to 150% of a thermal expansion coefficient of SiC.

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