Chip packaging structure and packaging method

Abstract

The invention relates to the technical field of semiconductors, and provides a chip packaging structure and a packaging method.The chip packaging structure comprises a heat dissipation side plate, a keying bottom plate, a plastic packaging bottom plate, a substrate chip layer, a combined packaging unit, a first heat dissipation gap plate, a second heat dissipation gap plate and an integrated insulation connecting plate; the upper side of the substrate chip layer is connected with the combined packaging unit through the integrated insulation connecting plate, the first heat dissipation gap plate is arranged between the substrate chip layer and the integrated insulation connecting plate, and the second heat dissipation gap plate is arranged between the integrated insulation connecting plate and the combined packaging unit. The two ends of the first heat dissipation gap plate and the two ends of the second heat dissipation gap plate are connected with the heat dissipation side plates in an attached mode, the two sets of heat dissipation side plates are arranged, the two sets of heat dissipation side plates are connected to the two sides of the combined packaging unit and the two sides of the keying bottom plate in a keying mode, and the heat dissipation side plates are fixedly connected with the lower side of the keying bottom plate through the plastic packaging bottom plate. The heat dissipation device can effectively dissipate heat of a complex integrated chip, and is compact in space structure and convenient to use.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip packaging structure and a packaging method. Background Art

[0002] As Moore's Law reaches its limits, numerous industry giants are turning their attention to advanced packaging. Rewiring, a crucial component of advanced packaging technology, has attracted significant research interest due to its high yield and high-density wiring. With the growing demand for higher functionality, improved performance, and greater energy efficiency, the pursuit of smaller packaging structures at lower manufacturing costs has become a key technology priority.

[0003] As disclosed in application number: CN202410277107.4, a packaging substrate, a chip packaging structure and a chip packaging method, the packaging substrate includes: a glass substrate, a conductive through-hole is provided in the glass substrate; a first packaging unit; the first packaging unit includes: a first plastic packaging layer, located on the first surface of the glass substrate; a first redistribution layer, located on the side of the first plastic packaging layer away from the glass substrate, and electrically connected to the first end of the conductive through-hole.

[0004] As disclosed in application number: CN201910456012.8, a chip packaging structure and a chip packaging method, the chip packaging structure includes: a chip, a positioning groove is provided on the back of the chip; a substrate, a positioning bump is provided on the upper surface of the substrate; the chip is bonded to the upper surface of the substrate, and the positioning bump is inserted into the positioning groove; a plastic encapsulation layer, located on the upper surface of the substrate, and plastic-encapsulating the chip; a rewiring layer, located on the upper surface of the plastic encapsulation layer, and electrically connected to the chip; a solder ball bump, located on the upper surface of the rewiring layer, and electrically connected to the rewiring layer.

[0005] However, existing integrated chips have a high degree of integration, but the heat dissipation capacity of the chips decreases after integration, and integrated heat dissipation cannot be performed for multiple chips. Summary of the Invention

[0006] In order to solve the problem that the existing integrated chips have high integration, but the heat dissipation capacity of the chips decreases after integration, and integrated heat dissipation cannot be performed for multiple chips, the present invention provides a chip packaging structure and packaging method to solve this problem.

[0007] In order to achieve the above object, the present invention provides the following technical solutions: A chip packaging structure includes: a heat dissipation side plate, a bonding bottom plate, a plastic packaging bottom plate, a base chip layer, a combined packaging unit, a first heat dissipation gap plate, a second heat dissipation gap plate and an integrated insulating connecting plate. The base chip layer is bonded to the bonding bottom plate, the upper side of the base chip layer is connected to the combined packaging unit via the integrated insulating connecting plate, the first heat dissipation gap plate is arranged between the base chip layer and the integrated insulating connecting plate, the second heat dissipation gap plate is arranged between the integrated insulating connecting plate and the combined packaging unit, both ends of the first heat dissipation gap plate and the second heat dissipation gap plate are fitted and connected to the heat dissipation side plate, two groups of heat dissipation side plates are provided, the two groups of heat dissipation side plates are bonded to both sides of the combined packaging unit and the bonding bottom plate, and the heat dissipation side plate and the lower side of the bonding bottom plate are fixedly connected via the plastic packaging bottom plate.

[0008] Preferably, the first heat dissipation gap plate includes: a first heat dissipation vertical plate, a first heat dissipation horizontal plate and a snap-in plate. The first heat dissipation vertical plate, the first heat dissipation horizontal plate and the snap-in plate are an integrated structure. The first heat dissipation horizontal plate is connected to one side of the snap-in plate through the first heat dissipation vertical plate, and the other side of the snap-in plate is fit-connected to the second heat dissipation gap plate. The first heat dissipation horizontal plate is provided with multiple groups of first through holes for allowing the air signal to lead out of the terminal. The first heat dissipation vertical plate and the snap-in plate form a snap-in groove, which is snap-connected to the integrated insulating connection plate.

[0009] Preferably, the second heat dissipation gap plate includes: a second heat dissipation vertical plate and a second heat dissipation horizontal plate, the second heat dissipation vertical plate and the second heat dissipation horizontal plate are an integrated structure, two groups of second heat dissipation vertical plates are provided, the two groups of second heat dissipation vertical plates are arranged at both ends of the second heat dissipation horizontal plate, the outer side of the lower part of the second heat dissipation vertical plate is connected to the first heat dissipation vertical plate through a clamping plate, the outer side of the upper part of the second heat dissipation vertical plate is connected to the heat dissipation side plate, and the second heat dissipation horizontal plate is provided with multiple groups of second through holes for allowing the air signal to lead out of the terminal.

[0010] Preferably, a plurality of heat dissipation holes are provided on the outer side of the heat dissipation side plate, and the heat dissipation holes are provided at the connection between the heat dissipation side plate and the first heat dissipation gap plate and the second heat dissipation gap plate.

[0011] Preferably, the first heat dissipation gap plate and the second heat dissipation gap plate are hollow structures, and are made of transparent heat-conducting metal, which is filled with expansion alloy.

[0012] Preferably, the combined packaging unit includes: a lower signal lead-out head, a glass substrate, a plastic sealing plate, an insulating dielectric plate, a cable and an upper signal lead-out head, the lower signal lead-out head is arranged on the lower side of the glass substrate, the glass substrate is fixedly connected to the insulating dielectric plate through the plastic sealing plate, the upper signal lead-out head is arranged on the upper side of the insulating dielectric plate, the lower signal lead-out head and the upper signal lead-out head are connected by a cable passing through the glass substrate, the plastic sealing plate and the insulating dielectric plate, and a through hole for avoiding the lower signal lead-out head and the upper signal lead-out head is provided on the heat dissipation gap plate.

[0013] Preferably, the insulating dielectric plate is bonded to the heat dissipation side plate.

[0014] Preferably, multiple groups of combined packaging units, first heat dissipation gap plates, second heat dissipation gap plates and integrated insulating connecting plates are provided, and one group of combined packaging units is stacked on another group of combined packaging units through the first heat dissipation gap plates, second heat dissipation gap plates and integrated insulating connecting plates.

[0015] A chip packaging method comprises the following steps: S1: The glass substrate is fixedly connected to the insulating dielectric plate through the plastic sealing plate, a lower signal lead is provided on the lower side of the glass substrate, and an upper signal lead is provided on the upper side of the insulating dielectric plate, and the lower signal lead and the upper signal lead are electrically connected via a wiring passing through the glass substrate, the plastic sealing plate, and the insulating dielectric plate to form a combined packaging unit; S2: placing the base chip layer on the bonding substrate through bonding; S3: placing an integrated insulating connection plate on the base chip layer, and placing a first heat dissipation gap plate between the integrated insulating connection plate and the base chip layer; S4: placing the combined packaging unit on the integrated insulating connecting plate, and placing the second heat dissipation gap plate between the integrated insulating connecting plate and the combined packaging unit; S5: Bonding the upper and lower parts of the two sets of heat dissipation side plates to the base chip layer and the assembled packaging unit respectively; S6: Use the plastic base plate to plastic-seal the heat dissipation side plate and the key base plate.

[0016] The advantages of the present invention are: by arranging the first heat dissipation gap plate and the second heat dissipation gap plate, the present invention can effectively absorb the heat between the stacked integrated chips and bring the heat out of the chips. At the same time, by arranging the integrated insulating connecting plate, the first heat dissipation gap plate and the second heat dissipation gap plate can be effectively arranged without affecting the wiring, thereby improving space utilization and transmission speed. By arranging the plastic packaging bottom plate, the heat dissipation side plate and the key bottom plate, it is convenient to package and connect the integrated chips, thereby improving structural stability and installation convenience. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which constitute part of the present invention, are provided to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are provided to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings: Figure 1 It is a structural schematic diagram of the present invention; Figure 2 It is a structural schematic diagram of multiple groups of combined packaging units of the present invention; Figure 3 It is a structural schematic diagram of the first heat dissipation gap plate of the present invention; Figure 4is a structural schematic diagram of the second heat dissipation gap plate of the present invention; Figure 5 It is a schematic diagram of the structure inside the first heat dissipation gap plate of the present invention; Figure 6 It is a structural schematic diagram of the combined packaging unit of the present invention; Figure 7 It is a structural schematic diagram of the heat dissipation side plate of the present invention.

[0018] Description of reference numerals: 1. Heat dissipation side plate; 2. Keying base plate; 3. Plastic sealing base plate; 4. Base chip layer; 5. Combined packaging unit; 6. First heat dissipation gap plate; 7. Second heat dissipation gap plate; 8. Integrated insulating connection plate; 61. First heat dissipation vertical plate; 62. First heat dissipation horizontal plate; 63. Snap-on plate; 64. First through hole; 71. Second heat dissipation vertical plate; 72. Second heat dissipation horizontal plate; 73. Second through hole; 11. Heat dissipation hole; 51. Lower signal lead-out head; 52. Glass substrate; 53. Plastic sealing plate; 54. Insulating dielectric plate; 55. Cable; 56. Upper signal lead-out head. DETAILED DESCRIPTION

[0019] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0020] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0021] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0022] Example 1, combined with Figure 1 To explain: A chip packaging structure includes: a heat dissipation side plate 1, a bonding base plate 2, a plastic package base plate 3, a base chip layer 4, a combined packaging unit 5, a first heat dissipation gap plate 6, a second heat dissipation gap plate 7 and an integrated insulating connection plate 8.

[0023] The base chip layer 4 is bonded to the bonding base plate 2, and the base chip layer 4 is fixed to the bonding base plate 2 by bonding, thereby improving the reliability and vibration resistance of the connection.

[0024] The upper side of the substrate chip layer 4 is connected to the combined packaging unit 5 via an integrated insulating connecting plate 8. The combined packaging unit 5 is a pre-packaged unit, and the use of a modular approach can improve the integration of the package and simplify the subsequent assembly process.

[0025] A first heat dissipation gap plate 6 is positioned between the base chip layer 4 and the integrated insulating connecting plate 8, while a second heat dissipation gap plate 7 is positioned between the integrated insulating connecting plate 8 and the combined packaging unit 5. Both ends of the first and second heat dissipation gap plates 6 and 7 are bonded to the heat dissipation side plate 1. The provision of these first and second heat dissipation gap plates 6 and 7 provides multiple heat dissipation paths. Heat can be conducted from the base chip layer 4 through the first heat dissipation gap plate 6 to the heat dissipation side plate 1, or through the integrated insulating connecting plate 8 and then through the second heat dissipation gap plate 7 to the heat dissipation side plate 1, thereby improving heat dissipation capacity. The provision of heat dissipation gap plates between chip layers effectively improves heat dissipation without significantly increasing the overall height of the package.

[0026] Two sets of heat dissipation side panels 1 are provided, keyed to both sides of the combined packaging unit 5 and the keyed base plate 2. The heat dissipation side panels 1 and the keyed base plate 2 are fixedly connected on their undersides by the plastic-encapsulated base plate 3. The heat dissipation side panels 1 are used to secure the mounting positions of the first heat dissipation gap plate 6 and the second heat dissipation gap plate 7, and provide heat dissipation clearances for the first and second heat dissipation gap plates 6 and 7. The two sets of heat dissipation side panels 1 are distributed on both sides of the packaging unit, significantly increasing the heat exchange area with the external environment and helping to dissipate heat more quickly. To improve heat dissipation, a cooling fan can be installed around the integrated chip.

[0027] Example 2, based on Example 1, combined with Figure 3 、 Figure 4 and Figure 5 To explain: The first heat dissipation gap plate 6 includes: a first heat dissipation vertical plate 61, a first heat dissipation horizontal plate 62 and a clamping plate 63. The first heat dissipation vertical plate 61, the first heat dissipation horizontal plate 62 and the clamping plate 63 are an integrated structure, and the structural strength is improved through the integrated structure design.

[0028] The first heat dissipation horizontal plate 62 is connected to one side of the clamping plate 63 through the first heat dissipation vertical plate 61 , and the other side of the clamping plate 63 is fitted and connected to the second heat dissipation gap plate 7 . The clamping plate 63 is used to limit the horizontal position of the second heat dissipation gap plate 7 .

[0029] The first heat dissipation horizontal plate 62 is provided with a plurality of first through holes 64 for vacating the signal lead-out terminals. The first through holes 64 can provide physical channels for the signal lead-out terminals, thereby facilitating signal lead-out.

[0030] The first heat dissipation riser 61 and the snap-on plate 63 form a snap-on groove, which snaps into engagement with the integrated insulating connecting plate 8. This snap-on arrangement allows the integrated insulating connecting plate 8 and the first heat dissipation riser 61 to be quickly and accurately placed into position during assembly, and then connected to the adjacent heat dissipation side plate 1, thereby improving assembly efficiency.

[0031] The second heat dissipation gap plate 7 includes: a second heat dissipation vertical plate 71 and a second heat dissipation horizontal plate 72. The second heat dissipation vertical plate 71 and the second heat dissipation horizontal plate 72 are an integrated structure. Two groups of second heat dissipation vertical plates 71 are provided. The two groups of second heat dissipation vertical plates 71 are arranged at both ends of the second heat dissipation horizontal plate 72. The outer side of the lower part of the second heat dissipation vertical plate 71 is connected to the first heat dissipation vertical plate 61 through the clamping plate 63, and the outer side of the upper part of the second heat dissipation vertical plate 71 is connected to the heat dissipation side plate 1. The second heat dissipation horizontal plate 72 is provided with multiple groups of second through holes 73 for allowing the air signal to lead out of the terminal.

[0032] The first and second heat dissipation gap plates 6 and 7 are hollow structures made of transparent thermally conductive metal and filled with an expansion alloy. The endpoints of the expansion alloy can be observed through the transparent thermally conductive metal, thereby determining the actual chip temperature. The chip temperature is used to determine whether physical heat dissipation is required. The expansion alloy can be an expansion fluid metal such as mercury, and the transparent thermally conductive metal can be zinc oxide.

[0033] Example 3, based on Example 2, combined with Figure 7 To explain: The outer side of the heat dissipation side plate 1 is provided with multiple groups of heat dissipation holes 11, which are arranged at the connection between the heat dissipation side plate 1 and the first heat dissipation gap plate 6 and the second heat dissipation gap plate 7. The provision of heat dissipation holes 11 effectively improves the heat dissipation capacity of the first heat dissipation gap plate 6 and the second heat dissipation gap plate 7, thereby improving the heat dissipation effect. The heat dissipation holes 11 also allow observation of the first heat dissipation gap plate 6 and the second heat dissipation gap plate 7, facilitating multi-functional expansion, such as temperature monitoring.

[0034] Example 4, based on Example 3, combined with Figure 2 and Figure 6 To explain: The combined packaging unit 5 includes: a lower signal lead 51, a glass substrate 52, a plastic sealing plate 53, an insulating dielectric plate 54, a cable 55, and an upper signal lead 56. The lower signal lead 51 is arranged on the lower side of the glass substrate 52, and the glass substrate 52 is fixedly connected to the insulating dielectric plate 54 via the plastic sealing plate 53. The upper signal lead 56 is arranged on the upper side of the insulating dielectric plate 54. The lower signal lead 51 and the upper signal lead 56 are connected by a cable that passes through the glass substrate 52, the plastic sealing plate 53, and the insulating dielectric plate 54. The cable 55 constitutes a signal path between the lower signal lead 51 and the upper signal lead 56. By providing a relatively direct path, the bends and length of signal transmission can be reduced, which helps to reduce signal delay and crosstalk. The provision of the insulating dielectric plate 54 can further provide an additional insulation layer, thereby ensuring good electrical isolation between the cable 55 and the upper and lower signal leads, preventing short circuits and improving the electrical reliability of the package.

[0035] The glass substrate 52 is combined with the insulating dielectric plate 54 through the plastic sealing plate 53 to form a relatively strong and flat composite structure, which can provide a stable laying base for the cable 55 and also provide reliable support for the upper and lower signal lead-out heads.

[0036] As a relatively independent module, the combined packaging unit 5 can be conveniently integrated with other parts, thereby improving the flexibility of the entire packaging design.

[0037] The insulating dielectric plate 54 is keyed to the heat dissipation side plate 1. This arrangement improves structural stability.

[0038] Multiple groups of combined packaging units 5, first heat dissipation gap plates 6, second heat dissipation gap plates 7, and integrated insulating connection plates 8 are provided. One group of combined packaging units 5 is stacked on another group of combined packaging units 5 via the first heat dissipation gap plates 6, second heat dissipation gap plates 7, and integrated insulating connection plates 8. This arrangement allows multiple groups of combined packaging units 5 to be integrated, thereby improving chip integration.

[0039] A chip packaging method comprises the following steps: S1: The glass substrate 52 is fixedly connected to the insulating dielectric plate 54 via the plastic sealing plate 53. A lower signal lead 51 is provided on the lower side of the glass substrate 52, and an upper signal lead 56 is provided on the upper side of the insulating dielectric plate 54. The lower signal lead 51 and the upper signal lead 56 are electrically connected via a wiring 55 passing through the glass substrate 52, the plastic sealing plate 53, and the insulating dielectric plate 54 to form a combined packaging unit 5. S2: The base chip layer 4 is placed on the bonding base plate 2 by bonding; S3: placing the integrated insulating connecting plate 8 on the base chip layer 4, and placing the first heat dissipation gap plate between the integrated insulating connecting plate 8 and the base chip layer 4; S4: placing the combined packaging unit 5 on the integrated insulating connecting plate 8, and placing the second heat dissipation gap plate 7 between the integrated insulating connecting plate 8 and the combined packaging unit 5; S5: Bonding the upper and lower parts of the two sets of heat dissipation side plates 1 to the base chip layer 4 and the assembly packaging unit 5 respectively; S6: Use the plastic bottom plate 3 to plastic-seal and fix the heat dissipation side plate 1 and the key bottom plate 2.

[0040] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention; therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the claims are intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any minor modifications, equivalent replacements, and improvements made to the above embodiments based on the technical essence of the present invention shall be included in the scope of protection of the technical solution of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A heat dissipation side plate (1), a keying base plate (2), a plastic sealing base plate (3), a base chip layer (4), a combined packaging unit (5), a first heat dissipation gap plate (6), a second heat dissipation gap plate (7) and an integrated insulating connecting plate (8); the base chip layer (4) is keyed to the keying base plate (2); the upper side of the base chip layer (4) is connected to the combined packaging unit (5) through the integrated insulating connecting plate (8); the first heat dissipation gap plate (6) is arranged between the base chip layer (4) and the integrated insulating connecting plate (8); the second heat dissipation gap plate (7) is arranged between the integrated insulating connecting plate (8) and the combined packaging unit (5); both ends of the first heat dissipation gap plate (6) and the second heat dissipation gap plate (7) are fitted and connected to the heat dissipation side plate (1); two groups of heat dissipation side plates (1) are provided; the two groups of heat dissipation side plates (1) are keyed to both sides of the combined packaging unit (5) and the keying base plate (2); the heat dissipation side plate (1) and the lower side of the keying base plate (2) are fixedly connected through the plastic sealing base plate (3).

2. The chip packaging structure according to claim 1, wherein: The first heat dissipation gap plate (6) comprises: a first heat dissipation vertical plate (61), a first heat dissipation horizontal plate (62) and a snap-on plate (63); the first heat dissipation vertical plate (61), the first heat dissipation horizontal plate (62) and the snap-on plate (63) are an integrated structure; the first heat dissipation horizontal plate (62) is connected to one side of the snap-on plate (63) through the first heat dissipation vertical plate (61); the other side of the snap-on plate (63) is fitted and connected to the second heat dissipation gap plate (7); a plurality of first through holes (64) for allowing the air signal to lead out of the terminal are provided on the first heat dissipation horizontal plate (62); the first heat dissipation vertical plate (61) and the snap-on plate (63) form a snap-on groove, and the snap-on groove is snap-oned to the integrated insulating connection plate (8).

3. The chip packaging structure according to claim 2, wherein: The second heat dissipation gap plate (7) includes: a second heat dissipation vertical plate (71) and a second heat dissipation horizontal plate (72). The second heat dissipation vertical plate (71) and the second heat dissipation horizontal plate (72) are an integrated structure. Two groups of second heat dissipation vertical plates (71) are provided. The two groups of second heat dissipation vertical plates (71) are provided at both ends of the second heat dissipation horizontal plate (72). The lower outer side of the second heat dissipation vertical plate (71) is connected to the first heat dissipation vertical plate (61) through a clamping plate (63). The upper outer side of the second heat dissipation vertical plate (71) is connected to the heat dissipation side plate (1). The second heat dissipation horizontal plate (72) is provided with multiple groups of second through holes (73) for allowing the air signal to lead out the terminal.

4. The chip packaging structure according to claim 1, wherein: A plurality of groups of heat dissipation holes (11) are provided on the outside of the heat dissipation side plate (1), and the heat dissipation holes (11) are provided at the connection between the heat dissipation side plate (1), the first heat dissipation gap plate (6), and the second heat dissipation gap plate (7).

5. The chip packaging structure according to claim 1, wherein: The first heat dissipation gap plate (6) and the second heat dissipation gap plate (7) are hollow structures. The first heat dissipation gap plate (6) and the second heat dissipation gap plate (7) are made of transparent heat-conducting metal and are filled with expansion alloy.

6. The chip packaging structure according to claim 1, wherein: The combined packaging unit (5) comprises: a lower signal lead-out head (51), a glass substrate (52), a plastic sealing plate (53), an insulating dielectric plate (54), a flat cable (55) and an upper signal lead-out head (56), wherein the lower signal lead-out head (51) is arranged on the lower side of the glass substrate (52), the glass substrate (52) is fixedly connected to the insulating dielectric plate (54) through the plastic sealing plate (53), and the upper signal lead-out head (56) is arranged on the upper side of the insulating dielectric plate (54), the lower signal lead-out head (51) and the upper signal lead-out head (56) are connected by a flat cable passing through the glass substrate (52), the plastic sealing plate (53) and the insulating dielectric plate (54), and a through hole for avoiding the lower signal lead-out head (51) and the upper signal lead-out head (56) is provided on the heat dissipation gap plate.

7. The chip packaging structure according to claim 6, characterized in that: The insulating dielectric plate (54) is keyed to the heat dissipation side plate (1).

8. The chip packaging structure according to claim 1, wherein: Multiple groups of combined packaging units (5), first heat dissipation gap plates (6), second heat dissipation gap plates (7), and integrated insulating connecting plates (8) are provided, and one group of combined packaging units (5) is stacked on another group of combined packaging units (5) via the first heat dissipation gap plates (6), second heat dissipation gap plates (7), and integrated insulating connecting plates (8).

9. A chip packaging method, characterized in that: The following steps are involved: S1: The glass substrate (52) is fixedly connected to the insulating dielectric plate (54) through the plastic sealing plate (53), a lower signal lead-out head (51) is provided on the lower side of the glass substrate (52), and an upper signal lead-out head (56) is provided on the upper side of the insulating dielectric plate (54), so that the lower signal lead-out head (51) and the upper signal lead-out head (56) are electrically connected through a wiring (55) passing through the glass substrate (52), the plastic sealing plate (53) and the insulating dielectric plate (54), thereby forming a combined packaging unit (5); S2: arranging the base chip layer (4) on the bonding base plate (2) by bonding; S3: arranging the integrated insulating connecting plate (8) on the base chip layer (4), and arranging the first heat dissipation gap plate between the integrated insulating connecting plate (8) and the base chip layer (4); S4: arranging the combined packaging unit (5) on the integrated insulating connecting plate (8), and arranging the second heat dissipation gap plate (7) between the integrated insulating connecting plate (8) and the combined packaging unit (5); S5: bonding the upper and lower parts of the two sets of heat dissipation side plates (1) to the base chip layer (4) and the integrated package unit (5) respectively; S6: Use the plastic bottom plate (3) to plastic-seal and fix the heat dissipation side plate (1) and the key bottom plate (2).

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