Trench gate MOSFET and manufacturing method thereof, unit cell structure manufacturing method and test method

Abstract

The invention relates to a trench gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a manufacturing method, a unit cell structure manufacturing method and a testing method in the technical field of semiconductors. The trench gate MOSFET comprises a channel layer, more than two groups of trenches formed in the channel layer, a first current circulation layer, a second current circulation layer, a gate dielectric layer and a gate electrode, the first current flowing layer is located at the bottom of the groove, and the first current flowing layer extends to the upper surface of the groove along the non-channel side of the groove; the second current flowing layer is arranged close to one side of the channel of the groove, and the second current flowing layer is located on the upper surface of the channel layer; the gate dielectric layer covers the first current flowing layer and the second current flowing layer and is in contact with a part of the side wall of the groove; and the gate electrode covers the gate dielectric layer and is filled in the trench, so that the problem that the influence of parasitic resistance cannot be avoided in a manner that a trench gate constructs a long channel by re-etching a plane gate is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench gate MOSFET and a manufacturing method thereof, a unit cell structure manufacturing method, and a testing method thereof. Background Art

[0002] The core of a metal oxide semiconductor field effect transistor (MOSFET) is the oxide semiconductor interface. The characteristics of the oxide semiconductor interface at the channel directly affect the device's channel mobility, affecting the MOSFET's channel on-state characteristic resistance, and thus affecting the MOSFET's on-state characteristic resistance. Therefore, it is desirable to accurately evaluate the device's channel mobility.

[0003] At present, MOSFET devices are mainly divided into two types: planar gate MOSFET and trench gate MOSFET. Channel mobility is the core parameter of power devices. Generally, planar channel mobility is achieved by increasing the channel length to increase the channel resistance to avoid the influence of parasitic resistance on mobility. To achieve the increase in channel length, it is only necessary to increase the distance between the source electrode and the drain electrode by modifying the layout. The method is simple and easy to implement.

[0004] However, for trench-gate MOSFETs, since their channel and semiconductor are located inside the semiconductor, the trench depth is generally less than 2 μm, and the channel length is usually less than the trench depth. If a longer channel is to be achieved, it is necessary to etch a deep trench. Therefore, for trench-type devices, it is impossible to avoid the influence of parasitic resistance by constructing a long channel by replicating the planar gate. In other words, it is impossible to increase the channel length directly through layout, and the channel length cannot be effectively increased. Summary of the Invention

[0005] In response to the shortcomings of the prior art, the present invention provides a trench gate MOSFET and its manufacturing method, unit cell structure manufacturing method, and testing method, which solves the problem that the trench gate cannot avoid the influence of parasitic resistance by replicating the long channel of the planar gate structure.

[0006] In order to solve the above technical problems, the present invention is solved by the following technical solutions: A trench field-effect transistor comprising a channel layer, two or more groups of trenches formed in the channel layer, a first current circulation layer, a second current circulation layer, a gate dielectric layer, and a gate electrode, wherein the depth of the two or more groups of trenches is less than the depth of the channel layer; The first current circulation layer is located at the bottom of the trench, and the first current circulation layer also extends along the non-channel side of the trench to the upper surface of the trench; The second current circulation layer is arranged close to a channel side of the trench, and the second current circulation layer is located on the upper surface of the channel layer, and the depth of the second current circulation layer is less than the depth of the trench; The gate dielectric layer covers the first current circulation layer and the second current circulation layer, and is disposed in contact with a portion of the sidewall of the trench; The gate electrode covers the gate dielectric layer and fills the trench; In two adjacent groups of trenches, the first current circulation layer in one group of trenches is arranged in contact with the second current circulation layer in the other group of trenches.

[0007] Optionally, the thickness of the gate dielectric layer on the sidewall on the non-channel side is equal to the thickness of the gate dielectric layer on the sidewall on the channel side.

[0008] Optionally, the thickness of the gate dielectric layer on the sidewall on the non-channel side is set to be greater than the thickness of the gate dielectric layer on the sidewall on the channel side.

[0009] Optionally, a current shielding layer is further included, which is embedded in the first current circulation layer and contacts the sidewall of the non-channel side of the trench, and is also in contact with the gate dielectric layer.

[0010] Optionally, the doping concentration of the current screening layer is greater than 1×10 19 cm -3 , and the current screening layer is doped with the first conductive type.

[0011] Optionally, the effective conductive channel length formed in each group of the grooves is 0.3 μm to 2.0 μm.

[0012] Optionally, the depth of the first current circulation layer at the bottom of the trench is greater than 0.1 μm; and the width of the first current circulation layer at the non-channel side close to the trench sidewall is greater than 0.2 μm.

[0013] Optionally, the depth of the second current circulation layer is 0.1-0.2 μm.

[0014] Optionally, it also includes a source electrode, a drain electrode, a first contact area and a second contact area, and the source electrode, the drain electrode, the first contact area and the second contact area are all located on the upper surface of the channel layer, the second contact area is arranged in contact with the side wall of the first contact area, the source electrode is arranged in contact with the second contact area and a part of the first contact area, and an ohmic contact is formed; the drain electrode is arranged in contact with a part of the first contact area, and an ohmic contact is formed; the first contact area is arranged in contact with the first current circulation layer, and the first contact area is also arranged in contact with the second current circulation layer, and the first contact area forms a current circulation path with the first current circulation layer and the second current circulation layer.

[0015] Optionally, it also includes an epitaxial layer, a substrate layer and a substrate electrode, the epitaxial layer is located on the lower surface of the channel layer, the substrate layer is located on the lower surface of the epitaxial layer, the substrate electrode is located on the lower surface of the substrate layer, and the second current flow layer is not arranged in contact with the substrate layer.

[0016] Optionally, the channel layer and the second contact region are both doped with a first conductivity type, and the first current circulation layer, the second current circulation layer, the first contact region, the epitaxial layer and the substrate layer are all doped with a second conductivity type opposite to the first conductivity type.

[0017] A method for testing the channel mobility of a trench field effect transistor, the method being used to test the trench field effect transistor as described in any one of the above, comprising the following steps: Applying a constant drain-source voltage between the drain electrode and the source electrode of the trench field effect transistor, and applying a gate-source voltage to the gate electrode; measuring the drain current and generating a drain current-gate-source voltage variation curve based on the drain current and the gate-source voltage; Calculating the transconductance based on the drain current-gate-source voltage variation curve, and obtaining the total effective conductive channel length, the unit area capacitance of the gate dielectric layer, and the dimension length along the channel width direction of the trench field effect transistor; The field effect mobility of the channel carriers is calculated based on the transconductance, the total effective channel length, the capacitance per unit area, and the dimension length.

[0018] A method for testing the channel mobility of a trench field effect transistor, the method being used to test the trench field effect transistor as described in any one of the above, comprising the following steps: Applying a constant gate-source voltage to the gate electrode of the trench field effect transistor, and applying a drain-source voltage between the drain electrode and the source electrode; measuring the drain current, and generating a drain current-drain voltage variation curve based on the drain-source voltage and the drain current; Calculating the on-resistance based on the slope of the drain current-drain voltage variation curve in the drain-source low voltage region, and obtaining the total effective conductive channel length, unit area capacitance of the gate dielectric layer, dimension length along the channel width direction, and threshold voltage of the trench field effect transistor; The effective mobility of channel carriers is calculated based on the gate-source voltage, the total effective conductive channel length, the volume per unit area, the dimension length, the threshold voltage, and the on-resistance.

[0019] A method for manufacturing a unit cell structure of a trench field effect transistor, the method for manufacturing a unit cell structure being used to prepare a unit cell structure formed by a channel layer, a first current flow layer, a second current flow layer, a gate dielectric layer, a gate electrode, an epitaxial layer, a substrate layer, and a substrate electrode as described in any one of the above, comprising the following steps: Obtaining a substrate layer, and forming an epitaxial layer on the substrate layer by epitaxial growth; forming a channel layer on the epitaxial layer by epitaxial growth or ion implantation, transferring a groove pattern in the channel layer by photolithography, and then forming a groove by etching; forming a first current circulation layer by ion implantation at the bottom of the trench and the trench sidewall region on the non-channel side, and forming a second current circulation layer by ion implantation at the trench sidewall region of the trench; forming a gate dielectric layer on the sidewall and bottom of the trench by thermal oxidation or deposition; A gate electrode is formed in the trench by low pressure chemical vapor deposition or atomic layer deposition, and the gate electrode covers the gate dielectric layer.

[0020] Optionally, after forming the first current flow layer in the bottom of the trench and the trench sidewall region on the non-channel side by ion implantation, the method further includes the following steps: A current shielding layer is formed on a sidewall region of the first current circulation layer close to a non-channel side of the trench by ion sidewall implantation.

[0021] A method for manufacturing a trench field effect transistor, the method being used to prepare the trench field effect transistor as described in any one of the above, comprising the following steps: growing an epitaxial layer on the substrate layer and forming a channel layer by in-situ doping or ion implantation; forming a trench in the channel layer by photolithography and etching processes, and sequentially forming a first current circulation layer and a second current circulation layer in the trench by a selective ion implantation process; forming a gate dielectric layer in the trench by a thermal oxidation process or a deposition process, and forming a gate electrode by depositing a conductive material and performing photolithographic etching; forming an insulating dielectric layer on the gate electrode and penetrating the insulating dielectric layer to generate a first contact region and a second contact layer, wherein the first contact region is electrically connected to the first current circulation layer and the second current circulation layer, and the second contact region is electrically connected to the source side region; forming a drain electrode on the first contact region and forming a source electrode on the second contact region; The drain electrode and the source electrode are annealed to form an ohmic contact, and a substrate electrode is formed on the back side of the substrate layer.

[0022] Optionally, the method further includes forming a current shielding layer in the trench by a selective ion implantation process, and the second contact region is electrically connected to the current shielding layer or the source side region.

[0023] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects: By forming more than two groups of grooves in the channel layer and providing a first current circulation layer and a second current circulation layer, the first current circulation layer is located at the bottom of the groove, and the first current circulation layer also extends along the non-channel side of the groove to the upper surface of the groove; the second current circulation layer is provided close to the channel side of the groove, and the second current circulation layer is located on the upper surface of the channel layer, and the depth of the second current circulation layer is less than the depth of the groove, thereby forming an effective conductive channel length on the channel side of each group of grooves. Since the total effective conductive channel length of the device is equal to the sum of the effective conductive channel lengths at multiple groups of grooves, and since the total effective conductive channel length is proportional to the channel resistance, as the total effective conductive channel length increases, the total channel resistance of the device increases, thereby increasing the proportion of the channel resistance in the total resistance of the device, and the proportion of the parasitic resistance in the total resistance of the device will decrease, thereby reducing the impact of the parasitic resistance on the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 This is a schematic diagram of the structure of a trench field effect transistor proposed in the first embodiment; Figure 2 This is a schematic structural diagram of a unit cell structure in a trench field effect transistor proposed in the first embodiment; Figure 3 The two groups proposed in this embodiment Figure 2 The schematic diagram of the structure of the unit cell structure shown in FIG. Figure 4 This is a schematic structural diagram of a unit cell structure in a trench field effect transistor proposed in the second embodiment; Figure 5 This is a schematic structural diagram of a unit cell structure in a trench field effect transistor proposed in the third embodiment; Figure 6 This is a current flow diagram of a trench field effect transistor proposed in the third embodiment when it is turned on; Figure 7 This is a test structure layout of a trench field effect transistor proposed in the fourth embodiment; Figure 8 This is a test structure layout of a trench field effect transistor in different crystal orientations proposed in the fourth embodiment; Figure 9 A comparison diagram of a test method for channel mobility of a trench field effect transistor proposed in the fifth embodiment and a simulated mobility; Figure 10 This is a diagram showing the sensitivity of unit cell structures with different numbers of series connections to parasitic resistance proposed in the fifth embodiment.

[0026] Figure numerals: 1. channel layer; 2. first current flow layer; 3. second current flow layer; 4. gate dielectric layer; 5. gate electrode; 6. current shielding layer; 7. epitaxial layer; 8. substrate layer; 9. substrate electrode; 10. first contact region; 11. second contact region; 12. source electrode; 13. drain electrode. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below with reference to the examples. The following examples are intended to explain the present invention but the present invention is not limited to the following examples.

[0028] Example 1 like Figure 1 As shown, a trench field effect transistor includes two or more unit cell structures connected in series along the current flow direction, and the two or more unit cell structures connected in series include a channel layer 1, a trench formed in the channel layer 1, a first current flow layer 2, a second current flow layer 3, a gate dielectric layer 4 and a gate electrode 5, wherein: Figure 1 Where n is an integer greater than or equal to 2, and the depth d of the trench is less than the depth of the channel layer 1 .

[0029] Specifically, this embodiment provides a structural setting of a unit cell structure, such as Figure 2 As shown, the first current circulation layer 2 in the unit cell structure is located at the bottom of the trench, and the first current circulation layer 2 also extends along the non-channel side of the trench to the upper surface of the trench; the second current circulation layer 3 is arranged close to the channel side of the trench, and the second current circulation layer 3 is located on the upper surface of the channel layer 1, and the depth of the second current circulation layer 3 is less than the depth of the trench; the gate dielectric layer 4 covers the first current circulation layer 2 and the second current circulation layer 3, and is arranged in contact with part of the side wall of the trench, and the thickness of the gate dielectric layer 4 on the side wall of the non-channel side is equal to the thickness of the gate dielectric layer 4 on the side wall of the channel side; the gate electrode 5 covers the gate dielectric layer 4 and fills the trench; in two adjacent groups of trenches, the first current circulation layer 2 in one group of trenches is arranged in contact with the second current circulation layer 3 in the other group of trenches.

[0030] It should be noted that if Figure 2 As shown, in this embodiment, the depth Deep1 of the first current circulation layer 2 located at the bottom part of the trench is greater than 0.1μm; and the width Width of the first current circulation layer 2 located on the non-channel side near the trench sidewall is greater than 0.2μm, so that by setting the depth of the first current circulation layer 2 at the bottom part of the trench, when the current is turned on, the current flowing through the first current circulation layer 2 avoids the interface position of the gate dielectric layer 4 located at the bottom of the trench; by setting the width of the first current circulation layer 2 located on the non-channel side near the trench sidewall, the current flow path will not be forced to approach the trench sidewall due to being too narrow, thereby avoiding the channel similar to this place from participating in the current conduction, and further avoiding the current on the non-channel side from being added to the total current.

[0031] like Figure 2 As shown, the depth of the second current circulation layer 3 in this embodiment is 0.1μm~0.2μm, so as to prevent the current flowing through the second current circulation layer 3 from avoiding the interface position of the gate dielectric layer 4 when the current is turned on. The depth Deep2 of the second current circulation layer 3 is set to be less than 0.2μm, thereby avoiding affecting the channel length due to excessive depth.

[0032] On the other hand, since the unit cell structure of the present application is applied to trench gate MOSFET devices, the effective conductive channel length formed in the trench in each unit cell structure is Set to 0.3μm~2.0μm.

[0033] In addition, in addition to two or more groups of unit cell structures connected in series, the trench field effect transistor of this embodiment also includes a source electrode 12, a drain electrode 13, a first contact area 10 and a second contact area 11, and the source electrode 12, the drain electrode 13, the first contact area 10 and the second contact area 11 are all located on the upper surface of the channel layer 1, the second contact area 11 is arranged in contact with the side wall of the first contact area 10, the source electrode 12 is arranged in contact with the second contact area 11 and a portion of the first contact area 10, and an ohmic contact is formed; the drain electrode 13 is arranged in contact with a portion of the first contact area 10, and an ohmic contact is formed; the first contact area 10 is arranged in contact with the first current circulation layer 2, and the first contact area 10 is also arranged in contact with the second current circulation layer 3, and the first contact area 10 forms a current flow path with the first current circulation layer 2 and the second current circulation layer 3; wherein the source electrode 12 and the drain electrode 13 can be metal nickel, aluminum, titanium, etc., and the ohmic contact is formed by laser annealing or rapid thermal annealing.

[0034] The trench field effect transistor also includes an epitaxial layer 7, a substrate layer 8 and a substrate electrode 9. The epitaxial layer 7 is located on the lower surface of the channel layer 1, the substrate layer 8 is located on the lower surface of the epitaxial layer 7, the substrate electrode 9 is located on the lower surface of the substrate layer 8, and the second current flow layer 3 is not arranged in contact with the substrate layer 8.

[0035] It should be noted that the channel layer 1 and the second contact region 11 are both doped with the first conductivity type, the first current circulation layer 2, the second current circulation layer 3, the first contact region 10, the epitaxial layer 7 and the substrate layer 8 are all doped with the second conductivity type opposite to the first conductivity type, and the doping concentration of the first current circulation layer 2, the second current circulation layer 3, the first contact region 10 and the second contact region 11 is set to 1×10 19 cm -3 ~1×10 21 cm -3 The doping concentration setting of the first contact region 10 and the second contact region 11 can improve the performance of the ohmic contact and reduce the ohmic contact resistivity.

[0036] like Figure 3 As shown, this embodiment takes the setting of two groups of unit cell structures connected in series as an example. At this time, a gate voltage is applied to the gate to open the channel, and a voltage is applied to the drain. During this process, the source potential is maintained at 0V. At this time, a current from the drain to the source will be formed in the trench field effect transistor formed. The flow path of the unit cell structure is: first flowing through the first current flow layer 2, then through the channel layer 1 on the side wall of the trench, and then flowing through the second current flow layer 3. Since in the series structure, in the adjacent unit cell structures, the second current flow layer 3 of one group of unit cell structures is contacted with the first current flow layer 2 of the other group of unit cell structures, therefore, the current flowing through the second current flow layer 3 will continue to flow through the first current flow layer 2 in the adjacent unit cell structure, thereby forming a flow path when the unit cell structures are connected in series.

[0037] The present application avoids the influence of parasitic resistance by setting two or more unit cell structures in series, so that the trench field effect transistor does not need to construct a long channel by replicating the planar gate. Specifically, the present application does not adopt the method of constructing a long channel to avoid the influence of parasitic resistance, but sets two or more groups of unit cell structures so that the total effective conductive channel length L of the device is equal to the effective conductive channel length of n unit cell structures. The sum is: Since the total effective conductive channel length is proportional to the channel resistance, as the total effective conductive channel length increases, the total channel resistance of the device increases, thereby increasing the proportion of channel resistance in the total device resistance. The proportion of parasitic resistance in the total device resistance will decrease, thereby reducing the impact of parasitic resistance on the device.

[0038] Example 2

[0039] like Figure 4 As shown, the difference between this embodiment and the first embodiment is that the thickness T of the gate dielectric layer 4 on the sidewall of the non-channel side is ox Greater than the thickness t of the gate dielectric layer 4 on the sidewall of the channel ox The gate electrode 5 is arranged to be fully isolated from the side wall of the non-channel side, thereby preventing the channel at this position from forming a current path when a voltage is applied to the gate, thereby affecting the extraction of channel measurement parameters of the device.

[0040] Specifically, according to the threshold voltage formula: , where NA and tox are the doping concentration of the channel layer 1 and the thickness of the oxide layer (gate dielectric layer 4) at the channel, respectively. Therefore, when the thickness of the gate dielectric layer 4 becomes thicker, the threshold voltage will become larger. By increasing the thickness, the formation of a current path at the sidewall on the non-channel side when the gate voltage is applied is avoided.

[0041] Example 3

[0042] like Figure 5 As shown, the difference between this embodiment and the first embodiment is that the trench field effect transistor of this embodiment further includes a current shielding layer 6, which is embedded in the first current flow layer 2, and the current shielding layer 6 is in contact with the sidewall of the non-channel side of the trench, and is also in contact with the gate dielectric layer 4, and the doping concentration of the current shielding layer 6 is greater than 1×10 19 cm -3 , and the current-screening layer 6 is doped with the first conductivity type.

[0043] In this embodiment, a current screening layer 6 with a higher concentration is provided to increase the threshold voltage of the sidewall on the non-channel side, so that when a current path is formed there, the channel located at the current screening layer 6 remains completely off, forming a non-channel.

[0044] Furthermore, if Figure 6 As shown, this embodiment takes a trench field effect transistor formed by two groups of unit cell structures connected in series as an example to provide a current flow path when the current is turned on. When a current shielding layer 6 is provided in the first current flow layer 2, since the doping concentration of the current shielding layer 6 is greater than 1×10 19 cm -3 , if a conductive path is to be formed here, the gate voltage needs to be large enough and greater than the threshold voltage at this position. However, according to the threshold voltage formula, when the doping concentration is set at 1×10 19 cm -3When the threshold voltage Vth is large, it will not be turned on within the test voltage range, such as within 25V. However, during the test, when the thickness of the gate dielectric layer 4 is 50nm, the channel at the target channel has already been turned on, and no larger gate voltage will be applied, thereby avoiding damage to the gate dielectric layer 4 at this time; at the same time, the channel here is avoided from participating in conduction, thereby achieving effective separation of the sidewall channels on both sides of the trench.

[0045] It should be noted that, in this embodiment, when the device is turned on, Figure 6 As shown, the current flows through the drain electrode 13, and then flows through the first contact area 10, the first current circulation layer 2, the channel layer 1 and the second current circulation layer 3 in sequence, and then flows through the first current circulation layer 2, the channel layer 1 and the second current circulation layer 3 in the adjacent unit cell structure, and finally enters the source to realize the opening of the device.

[0046] Example 4

[0047] A method for testing the channel mobility of a trench field effect transistor is provided. The method is used to test the trench field effect transistor according to any one of the first to third embodiments.

[0048] like Figure 7 As shown, it is a top view of a trench field effect transistor when n unit cell structures are connected in series. Each unit cell structure has a single-sided channel to provide a current flow path. A source electrode 12 and a gate electrode 5 are provided on both sides of the trench field effect transistor. Figure 7 The trench structure referred to herein refers to the sum of all structures formed within the trench. In this case, the test includes the following steps: S1, applying a constant drain-source voltage between the drain electrode 13 and the source electrode 12 of the trench field effect transistor, and applying a gate-source voltage to the gate electrode 5; S2. measuring the drain current and generating a drain current-gate-source voltage variation curve based on the drain current and the gate-source voltage; S3. Calculate the transconductance based on the drain current-gate-source voltage variation curve, and obtain the total effective conductive channel length of the trench field effect transistor, the unit area capacitance of the gate dielectric layer 4, and the dimension length along the channel width direction. The length of the device along the channel width direction is the length of the device in the projection direction. The calculation formula for transconductance is: ; S4, based on transconductance , total effective channel length L, capacitance per unit area , size length Calculate the field effect mobility of the channel carriers. The formula for calculating the field effect mobility of the channel carriers is: .

[0049] In step S1, the drain-source voltage Vds remains unchanged between 0.02V and 0.1V. When the thickness of the gate dielectric layer 4 is 50nm, the gate-source voltage Vg is applied and is set to scan from 0V to 25V. In step S2, 0.1V or 0.5V can be set as a step size test to obtain a drain current-gate-source voltage change curve (also expressed as an Id-Vg curve in this embodiment). It should be noted that the test process at this time is only an exemplary process. The specific test needs to follow the test specifications of the gate characteristic curve of the MOSFET and be adjusted according to device characteristics such as the thickness of the oxide layer, the doping concentration of the channel layer 1, etc.

[0050] On the other hand, the above method is a test of the channel mobility of a trench field effect transistor in one crystal orientation. Since trench field effect transistors have multiple crystal orientations, in actual operation, in order to improve the test accuracy, it is also possible to Figure 8 As shown, each independent trench field effect transistor is rotated by a certain angle, so that the mobility of the channel in different crystal directions of the semiconductor can be tested in the same set of layouts. For example, taking silicon carbide as an example, with its flat edge as 0°, when the trench field effect transistor is rotated 90°, the mobility in the two crystal directions of (11-20) and (-1-120) can be tested.

[0051] Example 5

[0052] A method for testing the channel mobility of a trench field effect transistor, the method being used to test the trench field effect transistor according to any one of the first to third embodiments, comprising the following steps: S1, applying a constant gate-source voltage to the gate electrode 5 of the trench field effect transistor, and applying a drain-source voltage between the drain electrode 13 and the source electrode 12; S2. measuring the drain current and generating a drain current-drain voltage change curve based on the drain-source voltage and the drain current; S3. Calculate the on-resistance based on the slope of the drain current-drain voltage curve in the drain-source low voltage region, and obtain the total effective conductive channel length of the trench field effect transistor, the unit area capacitance of the gate dielectric layer 4, the dimension length along the channel width direction, and the threshold voltage. The on-resistance is calculated as follows: ; S4, based on gate-source voltage , total effective conductive channel length L, volume per unit area, dimension length W, threshold voltage , the on-resistance Rt is used to calculate the effective mobility of the channel carriers, where the calculation formula for the effective mobility is: .

[0053] In step S1 , the drain-source voltage Vds is set to change from 0V to 0.1V, thereby measuring the drain voltage and obtaining a drain current-drain voltage change curve (also expressed as an Id-Vds curve in this embodiment) in step S2 .

[0054] like Figure 9 As shown, in this embodiment, the number of unit cell structures connected in series is five, and the ohmic contact resistance is 1×10 -4 mΩcm 2 As an example, a comparison chart of the effective mobility of channel carriers and the effective mobility of channel carriers obtained by simulation is formed according to the test method of this embodiment. Figure 9 It can be seen that the mobility calculated by the test at this time has a more consistent data trend than the simulated mobility, and the degree of data deviation is smaller.

[0055] like Figure 10 As shown, this embodiment also uses a current change rate diagram when different ohmic contact resistivities are set and different numbers of unit cell structures are connected in series, and under ideal conditions without the influence of parasitic resistance, to demonstrate the sensitivity of the number of unit cell structures with different numbers of series connections to the parasitic resistance. Figure 10 It can be seen that when the number of unit cell structures connected in series increases, its sensitivity to parasitic resistance decreases, that is, increasing the number of unit cells connected in series can effectively avoid the influence of parasitic resistance on the extracted channel resistance and improve the accuracy of the test. When one hundred unit cell structures of the present application are connected in series, and the ohmic contact resistivity is 1×10 -2 mΩcm 2 When the number of unit cells in series is increased, the current change rate drops to below 40%. Compared with the structure of two unit cells in series, the current change rate is greatly improved when it is close to 100%. It can be foreseen that the test accuracy will be further increased when the number of unit cells in series is further increased.

[0056] Example 6

[0057] A method for manufacturing a unit cell structure of a trench field effect transistor, the method for manufacturing a unit cell structure being used to prepare a unit cell structure formed by a channel layer 1, a first current circulation layer 2, a second current circulation layer 3, a gate dielectric layer 4, a gate electrode 5, an epitaxial layer 7, a substrate layer 8, and a substrate electrode 9 as described in any one of the first to third embodiments, comprising the following steps: S1, obtaining a substrate layer 8, and forming an epitaxial layer 7 on the substrate layer 8 by epitaxial growth; S2. forming a channel layer 1 on the epitaxial layer 7 by epitaxial growth or ion implantation, transferring a groove pattern in the channel layer 1 by photolithography, and then forming a groove by etching; S3, forming a first current circulation layer 2 by ion implantation at the bottom of the trench and the trench sidewall region on the non-channel side, and forming a second current circulation layer 3 by ion implantation at the trench sidewall region on the channel side of the trench; S4, forming a gate dielectric layer 4 on the sidewalls and bottom of the trench by thermal oxidation or deposition; S5 forms a gate electrode 5 in the trench by low pressure chemical vapor deposition or atomic layer deposition, and the gate electrode 5 covers the gate dielectric layer 4 .

[0058] According to the above preparation steps, the Figure 2 or Figure 4 The unit cell structure shown.

[0059] Example 7

[0060] The difference between this embodiment and the sixth embodiment is that after forming the first current circulation layer 2 by ion implantation at the bottom of the trench and the sidewall region of the trench on the non-channel side, this embodiment further includes the following steps: forming a current shielding layer 6 by ion sidewall implantation at the sidewall region of the first current circulation layer 2 close to the non-channel side of the trench, thereby forming Figure 5 The unit cell structure shown, including the current screening layer 6, can increase the threshold voltage of the sidewall on the non-channel side, so that when a current path is formed there, the channel located at the current screening layer 6 remains completely off, forming a non-channel.

[0061] Example 8

[0062] A method for manufacturing a trench field effect transistor, the method being used to prepare the trench field effect transistor according to any one of the first to third embodiments, comprising the following steps: An epitaxial layer 7 is grown on a substrate layer 8, and a channel layer 1 is formed by in-situ doping or ion implantation; A trench is formed in the channel layer 1 by photolithography and etching processes, and a first current circulation layer 2 and a second current circulation layer 3 are sequentially formed in the trench by a selective ion implantation process; A gate dielectric layer 4 is formed in the trench by a thermal oxidation process or a deposition process, and a gate electrode 5 is formed by depositing a conductive material and then photolithographically etching; An insulating dielectric layer is formed on the gate electrode 5 and penetrates the insulating dielectric layer to generate a first contact region 10 and a second contact layer, wherein the first contact region 10 is electrically connected to the first current circulation layer 2 and the second current circulation layer 3, and the second contact region 11 is electrically connected to the source side region; A drain electrode 13 is formed on the first contact region 10 , and a source electrode 12 is formed on the second contact region 11 ; The drain electrode 13 and the source electrode 12 are annealed to form an ohmic contact, and a substrate electrode 9 is formed on the back surface of the substrate layer 8 .

[0063] Embodiment 9

[0064] The difference between this embodiment and embodiment eight is that this embodiment also includes forming a current shielding layer 6 in the trench through a selective ion implantation process. At this time, the second contact area 11 is electrically connected to the current shielding layer 6 or the source side area, thereby forming a trench field effect transistor with a current shielding layer 6. The trench field effect transistor including the current shielding layer 6 can increase the threshold voltage of the side wall on the non-channel side, so that when a current path is formed there, the channel located at the current shielding layer 6 remains in a completely off state, forming a non-channel.

[0065] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form or substance. It should be pointed out that ordinary technicians in this technical field can make several improvements and supplements without departing from the method of the present invention. These improvements and supplements should also be regarded as the scope of protection of the present invention. Any equivalent changes, modifications and evolutions made by technicians familiar with this profession without departing from the spirit and scope of the present invention by using the technical content disclosed above are all equivalent embodiments of the present invention; at the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A trench field effect transistor, characterized in that comprising a channel layer, two or more groups of trenches formed in the channel layer, a first current circulation layer, a second current circulation layer, a gate dielectric layer, and a gate electrode, wherein the depth of the two or more groups of trenches is less than the depth of the channel layer; The first current circulation layer is located at the bottom of the trench, and the first current circulation layer also extends along the non-channel side of the trench to the upper surface of the trench; The second current circulation layer is arranged close to a channel side of the trench, and the second current circulation layer is located on the upper surface of the channel layer, and the depth of the second current circulation layer is less than the depth of the trench; The gate dielectric layer covers the first current circulation layer and the second current circulation layer, and is disposed in contact with a portion of the sidewall of the trench; The gate electrode covers the gate dielectric layer and fills the trench; In two adjacent groups of trenches, the first current circulation layer in one group of trenches is arranged in contact with the second current circulation layer in the other group of trenches.

2. A trench field effect transistor according to claim 1, characterized in that: The thickness of the gate dielectric layer on the sidewall on the non-channel side is equal to the thickness of the gate dielectric layer on the sidewall on the channel side.

3. The trench field effect transistor according to claim 1, wherein: The thickness of the gate dielectric layer on the sidewall on the non-channel side is set to be greater than the thickness of the gate dielectric layer on the sidewall on the channel side.

4. A trench field effect transistor according to any one of claims 1 to 3, characterized in that: It also includes a current shielding layer, which is embedded in the first current circulation layer and contacts the sidewall of the non-channel side of the trench. The current shielding layer is also in contact with the gate dielectric layer.

5. The trench field effect transistor according to claim 4, characterized in that: The doping concentration of the current screening layer is greater than 1×10 19 cm -3 , and the current screening layer is doped with the first conductive type.

6. The trench field effect transistor according to claim 5, characterized in that: The effective conductive channel length formed in each group of the grooves is 0.3 μm to 2.0 μm.

7. The trench field effect transistor according to claim 5, characterized in that: The depth of the first current circulation layer at the bottom of the trench is greater than 0.1 μm; and the width of the first current circulation layer at the non-channel side close to the trench sidewall is greater than 0.2 μm.

8. The trench field effect transistor according to claim 5, characterized in that: The second current circulation layer has a depth of 0.1 to 0.2 μm.

9. A trench field effect transistor according to any one of claims 5 to 8, characterized in that: The channel layer further comprises a source electrode, a drain electrode, a first contact region, and a second contact region, wherein the source electrode, the drain electrode, the first contact region, and the second contact region are all located on the upper surface of the channel layer, the second contact region is arranged in contact with a sidewall of the first contact region, and the source electrode is arranged in contact with the second contact region and a portion of the first contact region to form an ohmic contact; The drain electrode is disposed in contact with a portion of the first contact region to form an ohmic contact; The first contact region is disposed in contact with the first current circulation layer, and the first contact region is also disposed in contact with the second current circulation layer. The first contact region, the first current circulation layer, and the second current circulation layer form a current circulation path.

10. The trench field effect transistor according to claim 9, characterized in that: It also includes an epitaxial layer, a substrate layer and a substrate electrode, the epitaxial layer is located on the lower surface of the channel layer, the substrate layer is located on the lower surface of the epitaxial layer, the substrate electrode is located on the lower surface of the substrate layer, and the second current flow layer is not arranged in contact with the substrate layer.

11. The trench field effect transistor according to claim 10, characterized in that: The channel layer and the second contact region are both doped with a first conductive type, and the first current circulation layer, the second current circulation layer, the first contact region, the epitaxial layer and the substrate layer are all doped with a second conductive type opposite to the first conductive type.

12. A method for testing the channel mobility of a trench field effect transistor, characterized in that: The testing method is used to test the trench field effect transistor according to any one of claims 1 to 11, comprising the following steps: Applying a constant drain-source voltage between the drain electrode and the source electrode of the trench field effect transistor, and applying a gate-source voltage to the gate electrode; measuring the drain current and generating a drain current-gate-source voltage variation curve based on the drain current and the gate-source voltage; Calculating the transconductance based on the drain current-gate-source voltage variation curve, and obtaining the total effective conductive channel length, the unit area capacitance of the gate dielectric layer, and the dimension length along the channel width direction of the trench field effect transistor; The field effect mobility of the channel carriers is calculated based on the transconductance, the total effective channel length, the capacitance per unit area, and the dimension length.

13. A method for testing the channel mobility of a trench field effect transistor, characterized in that: The testing method is used to test the trench field effect transistor according to any one of claims 1 to 11, comprising the following steps: Applying a constant gate-source voltage to the gate electrode of the trench field effect transistor, and applying a drain-source voltage between the drain electrode and the source electrode; measuring the drain current, and generating a drain current-drain voltage variation curve based on the drain-source voltage and the drain current; Calculating the on-resistance based on the slope of the drain current-drain voltage variation curve in the drain-source low voltage region, and obtaining the total effective conductive channel length, unit area capacitance of the gate dielectric layer, dimension length along the channel width direction, and threshold voltage of the trench field effect transistor; The effective mobility of channel carriers is calculated based on the gate-source voltage, the total effective conductive channel length, the volume per unit area, the dimension length, the threshold voltage, and the on-resistance.

14. A method for manufacturing a unit cell structure of a trench field effect transistor, characterized in that: The unit cell structure manufacturing method is used to prepare a unit cell structure formed by a channel layer, a first current circulation layer, a second current circulation layer, a gate dielectric layer, a gate electrode, an epitaxial layer, a substrate layer, and a substrate electrode as claimed in any one of claims 1 to 11, comprising the following steps: Obtaining a substrate layer, and forming an epitaxial layer on the substrate layer by epitaxial growth; forming a channel layer on the epitaxial layer by epitaxial growth or ion implantation, transferring a groove pattern in the channel layer by photolithography, and then forming a groove by etching; forming a first current circulation layer by ion implantation at the bottom of the trench and the trench sidewall region on the non-channel side, and forming a second current circulation layer by ion implantation at the trench sidewall region of the trench; forming a gate dielectric layer on the sidewall and bottom of the trench by thermal oxidation or deposition; A gate electrode is formed in the trench by low pressure chemical vapor deposition or atomic layer deposition, and the gate electrode covers the gate dielectric layer.

15. The method for manufacturing a unit cell structure of a trench field effect transistor according to claim 14, wherein: After forming a first current flow layer in the bottom of the trench and the sidewall region of the trench on the non-channel side by ion implantation, the method further includes the following steps: A current shielding layer is formed on a sidewall region of the first current circulation layer close to a non-channel side of the trench by ion sidewall implantation.

16. A method for manufacturing a trench field effect transistor, characterized in that: The manufacturing method is used to prepare the trench field effect transistor according to any one of claims 1 to 11, comprising the following steps: growing an epitaxial layer on the substrate layer and forming a channel layer by in-situ doping or ion implantation; forming a trench in the channel layer by photolithography and etching processes, and sequentially forming a first current circulation layer and a second current circulation layer in the trench by a selective ion implantation process; forming a gate dielectric layer in the trench by a thermal oxidation process or a deposition process, and forming a gate electrode by depositing a conductive material and performing photolithographic etching; forming an insulating dielectric layer on the gate electrode and penetrating the insulating dielectric layer to generate a first contact region and a second contact layer, wherein the first contact region is electrically connected to the first current circulation layer and the second current circulation layer, and the second contact region is electrically connected to the source side region; forming a drain electrode on the first contact region and forming a source electrode on the second contact region; The drain electrode and the source electrode are annealed to form an ohmic contact, and a substrate electrode is formed on the back side of the substrate layer.

17. The method for manufacturing a trench field effect transistor according to claim 16, wherein: The method further includes forming a current shielding layer in the trench by a selective ion implantation process, wherein the second contact region is electrically connected to the current shielding layer or the source side region.

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