Display panel

Abstract

The invention provides a display panel. The display panel comprises a substrate, a plurality of light-emitting units and a metal isolation structure, the light-emitting units are arranged on the substrate in an array mode, each light-emitting unit at least comprises a first light-emitting unit of a first light-emitting color, a second light-emitting unit of a second light-emitting color and a third light-emitting unit of a third light-emitting color, and the first light-emitting units, the second light-emitting units and the third light-emitting units are sequentially stacked on the substrate. Projections of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit on the substrate are not overlapped; the metal isolation structure sequentially penetrates through layers where the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are located, is insulated from epitaxial layers of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit and the first electrode, and comprises a first groove, a second groove and a third groove. The first light-emitting unit, the second light-emitting unit and the third light-emitting unit are located in the first groove, the second groove and the third groove respectively.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel. Background Art

[0002] Light-emitting diode (LED)-based display panels are a new type of display technology that uses micron-sized LEDs as pixels and can be applied to devices such as augmented reality (AR).

[0003] In the related art, a display panel based on light emitting diodes has a crosstalk problem. Summary of the Invention

[0004] The present disclosure provides a display panel that can solve the crosstalk problem existing in display panels. The technical solution is as follows:

[0005] In one aspect, a display panel is provided, comprising:

[0006] a substrate, a plurality of light-emitting units, and a metal isolation structure;

[0007] A plurality of light-emitting unit arrays are arranged on the substrate, each of the light-emitting units includes at least a first light-emitting unit of a first light-emitting color, a second light-emitting unit of a second light-emitting color, and a third light-emitting unit of a third light-emitting color, the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are sequentially stacked on the substrate, and projections of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit on the substrate do not overlap;

[0008] The first electrode of the first light-emitting unit, the first electrode of the second light-emitting unit, and the first electrode of the third light-emitting unit are electrically connected to the substrate respectively, and the second electrode of the first light-emitting unit, the second electrode of the second light-emitting unit, and the second electrode of the third light-emitting unit are electrically connected to the metal isolation structure;

[0009] The metal isolation structure passes through the layers where the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are located in sequence, and is insulated from the epitaxial layers and the first electrode of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit. The metal isolation structure includes a first groove, a second groove and a third groove, and the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are respectively located in the first groove, the second groove and the third groove.

[0010] Optionally, the metal isolation structure is a dock metal isolation structure. Optionally, the second electrode of the first light-emitting unit and the second electrode of the second light-emitting unit are embedded in the side walls of the metal isolation structure, and the second electrode of the third light-emitting unit covers the top surface of the metal isolation structure.

[0011] Optionally, the first light emitting unit is a red light emitting unit, the second light emitting unit is a green light emitting unit, and the third light emitting unit is a blue light emitting unit.

[0012] Optionally, the cross-sectional area of the first groove is greater than the cross-sectional area of the second groove, and the cross-sectional area of the first groove is greater than the cross-sectional area of the third groove.

[0013] Optionally, the first groove, the second groove and the third groove are all rounded rectangles.

[0014] Optionally, the sidewall thickness of the metal isolation structure is 0.1-2 μm.

[0015] Optionally, the first light-emitting unit, the second light-emitting unit and the third light-emitting unit each include: a bonding metal layer and an epitaxial layer stacked in sequence;

[0016] The bonding metal layer, the first electrode, the epitaxial layer and the second electrode are stacked in sequence.

[0017] Optionally, the display panel further includes a planarization layer, and the planarization layer includes a first planarization layer, a second planarization layer, and a third planarization layer;

[0018] The first planarization layer is located between the bonding metal layer and the epitaxial layer of the first light-emitting unit and the metal isolation structure;

[0019] The second planarization layer is located between the bonding metal layer and the epitaxial layer of the second light-emitting unit and the metal isolation structure;

[0020] The third planarization layer is located between the bonding metal layer and the epitaxial layer of the third light emitting unit and the metal isolation structure.

[0021] Optionally, the bonding metal layer of the first light-emitting unit is electrically connected to the substrate, the bonding metal layer of the second light-emitting unit is electrically connected to the substrate through the first planarization layer via a first conductive column, and the bonding metal layer of the third light-emitting unit is electrically connected to the substrate through the second conductive column through the second planarization layer and the first planarization layer.

[0022] The technical solutions provided by the embodiments of the present disclosure have the following beneficial effects:

[0023] In the embodiment of the present disclosure, each light-emitting unit in the display panel includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit. The projections of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit on the substrate do not overlap, and the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are isolated from each other by a metal isolation structure, thereby avoiding the mutual influence of light between the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit, effectively avoiding the occurrence of pixel crosstalk, and improving the color consistency and contrast of the display panel. The second electrode of the first light-emitting unit, the second electrode of the second light-emitting unit, and the second electrode of the third light-emitting unit are all electrically connected to the metal isolation structure. On the one hand, the second electrodes of the first to third light-emitting units are connected together to form a common electrode. On the other hand, the connection is achieved through the metal isolation structure, which simplifies the connection structure of the electrodes. In addition, the metal isolation structure provides support and protection for the light-emitting unit, making the structure of the light-emitting unit more stable and improving the yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 is a top view of a display panel provided by an embodiment of the present disclosure;

[0026] Figure 2 is a top view of a light-emitting unit in a display panel provided by an embodiment of the present disclosure;

[0027] Figure 3 is a structural diagram of a display panel provided by an embodiment of the present disclosure;

[0028] Figure 4 is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0029] Figure 5 is a flow chart of another method for manufacturing a display panel provided by an embodiment of the present disclosure;

[0030] Figure 6 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0031] Figure 7 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0032] Figure 8 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0033] Figure 9 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0034] Figure 10 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0035] Figure 11 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0036] Figure 12 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0037] Figure 13 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0038] Figure 14 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0039] Figure 15 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0040] Figure 16 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure;

[0041] Figure 17 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure.

[0042] The reference numerals are as follows:

[0043] 100: substrate; 200: light-emitting unit; 300: metal isolation structure; 500: planarization layer; 600: passivation layer;

[0044] 201: first light-emitting unit; 202: second light-emitting unit; 203: third light-emitting unit; 301: first groove; 302: second groove; 303: third groove; 401: first conductive pillar; 402: second conductive pillar; 501: first planarization layer; 502: second planarization layer; 503: third planarization layer; 701: first electrode; 702: second electrode; 211: bonding metal layer; 212: epitaxial layer; 2121: first semiconductor layer; 2122: active layer; 2123: second semiconductor layer;

[0045] 30a: first layer of the metal isolation structure; 30b: second layer of the metal isolation structure; 30c: third layer of the metal isolation structure; 10a: groove; 10b: first through hole; 10c: second through hole; 101: connection hole. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0047] Figure 1 is a top view of a display panel provided by an embodiment of the present disclosure. Figure 1 The display panel includes: a substrate 100 and a plurality of light-emitting units 200 , wherein the plurality of light-emitting units 200 are arranged in an array on the substrate 100 .

[0048] Figure 2 is a top view of a light emitting unit in a display panel provided by an embodiment of the present disclosure. Figure 2 , the display panel further includes: a metal isolation structure 300 .

[0049] Each light-emitting unit 200 includes at least a first light-emitting unit 201 of a first light-emitting color, a second light-emitting unit 202 of a second light-emitting color, and a third light-emitting unit 203 of a third light-emitting color. The first light-emitting unit 201, the second light-emitting unit 202, and the third light-emitting unit 203 are stacked in sequence on the substrate 100, and the projections of the first light-emitting unit 201, the second light-emitting unit 202, and the third light-emitting unit 203 on the substrate 100 do not overlap.

[0050] Figure 3 4 is a structural diagram of a display panel provided in an embodiment of the present disclosure. Figure 3 yes Figure 2 The cross-section diagram of A-A' in Figure 3 The first electrode 701 of the first light-emitting unit 201, the first electrode 701 of the second light-emitting unit 202 and the first electrode 701 of the third light-emitting unit 203 are respectively electrically connected to the substrate 100, and the second electrode 702 of the first light-emitting unit 201, the second electrode 702 of the second light-emitting unit 202 and the second electrode 702 of the third light-emitting unit 203 are all electrically connected to the metal isolation structure 300.

[0051] The metal isolation structure 300 sequentially passes through the layers of the first light-emitting unit 201 , the second light-emitting unit 202 and the third light-emitting unit 203 and is insulated from the epitaxial layers of the first light-emitting unit 201 , the second light-emitting unit 202 and the third light-emitting unit 203 and the first electrode 701 .

[0052] See also Figure 2 and Figure 3The metal isolation structure 300 includes a first groove 301, a second groove 302 and a third groove 303, and the first light-emitting unit 201, the second light-emitting unit 202 and the third light-emitting unit 203 are respectively located in the first groove 301, the second groove 302 and the third groove 303.

[0053] In the embodiment of the present disclosure, each light-emitting unit in the display panel includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit. The projections of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit on the substrate do not overlap, and the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are isolated from each other by a metal isolation structure, thereby avoiding the mutual influence of light between the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit, effectively avoiding the occurrence of pixel crosstalk, and improving the color consistency and contrast of the display panel. The second electrode of the first light-emitting unit, the second electrode of the second light-emitting unit, and the second electrode of the third light-emitting unit are all electrically connected to the metal isolation structure. On the one hand, the second electrodes of the first to third light-emitting units are connected together to form a common electrode. On the other hand, the connection is achieved through the metal isolation structure, which simplifies the connection structure of the electrodes. In addition, the metal isolation structure provides support and protection for the light-emitting unit, making the structure of the light-emitting unit more stable and improving the yield of the display panel.

[0054] In the disclosed embodiment, the metal isolation structure 300 is a docking metal isolation structure. The docking metal isolates multiple light-emitting units from each other, preventing light crosstalk between them. The docking metal provides good electrical conductivity, ensuring electrical signal transmission between electrodes. Furthermore, the docking metal isolation structure provides support and protection for the light-emitting units, making them more stable during manufacturing and use, and reducing the risk of damage from external forces or environmental factors.

[0055] In the disclosed embodiment, the second electrodes of the first light-emitting unit 201 and the second electrode of the second light-emitting unit 202 are embedded in the sidewalls of the metal isolation structure 300, and the second electrode of the third light-emitting unit 203 covers the top surface of the metal isolation structure 300. This structural design, combined with the fabrication process of the metal isolation structure, allows the metal isolation structure to be fabricated in a stacked manner, facilitating fabrication while ensuring electrical connection between the electrodes and the metal isolation structure.

[0056] In the embodiment of the present disclosure, the first light emitting unit 201 is a red light emitting unit, the second light emitting unit 202 is a green light emitting unit, and the third light emitting unit 203 is a blue light emitting unit. Red, green, and blue are the three primary colors. By setting up red, green, and blue light emitting units, full color display can be achieved.

[0057] In other implementations, the light-emitting unit 200 may include other light-emitting units in addition to the first to third display units, such as a fourth light-emitting unit, which may be a white light-emitting unit.

[0058] In the disclosed embodiment, the cross-sectional area of the first groove 301 is greater than that of the second groove 302, which in turn is greater than that of the third groove 303. The light-emitting units are located within the grooves, with the first groove being used to house the red light-emitting unit. The red light-emitting efficiency is most affected by chip size; smaller chip size results in lower efficiency, while larger chip size can improve red light-emitting efficiency.

[0059] In the embodiment of the present disclosure, the first groove 301, the second groove 302 and the third groove 303 are all rounded rectangles. The rounded corners can reduce the stress of the metal isolation layer and increase the service life of the metal isolation layer.

[0060] In other embodiments, the first groove 301 , the second groove 302 and the third groove 303 may also be in other shapes, such as circular, elliptical, etc.

[0061] In other implementations, the colors of the first light-emitting unit 201 , the second light-emitting unit 202 , and the third light-emitting unit 203 may also be other combinations.

[0062] In the disclosed embodiment, the sidewall thickness of the metal isolation structure 300 can be 0.1 to 2 μm. This thickness can better prevent light from interfering with each other between the first, second, and third light-emitting units, effectively preventing pixel crosstalk. Furthermore, this thickness allows the metal isolation structure to form a stable electrical connection with the electrode.

[0063] Exemplarily, the sidewall thickness of the metal isolation structure 300 is 1 μm.

[0064] In the embodiment of the present disclosure, the first light-emitting unit 201 , the second light-emitting unit 202 and the third light-emitting unit 203 all include: a bonding metal layer 211 and an epitaxial layer 212 .

[0065] The bonding metal layer 211 , the first electrode 701 , the epitaxial layer 212 and the second electrode 702 are stacked in sequence.

[0066] The bonding metal layer ensures that the epitaxial layer can be bonded to the substrate, and the bonding metal layer can form an electrical connection.

[0067] In this implementation, the light-emitting unit has a simple structure, and the bonding layer facilitates the fabrication of the stacked display panel.

[0068] like Figure 3As shown, one side of the epitaxial layer 212 is connected to the first electrode 701 , and the first electrode 701 is connected to the bonding metal layer 211 .

[0069] In the embodiment of the present disclosure, the display panel further includes a planarization layer 500, which includes a first planarization layer 501, a second planarization layer 502, and a third planarization layer 503. The first planarization layer 501, the second planarization layer 502, and the third planarization layer 503 are stacked in sequence.

[0070] The first planarization layer 501 is located between the bonding metal layer 211 and the epitaxial layer 212 of the first light-emitting unit 201 and the metal isolation structure 300. That is, a portion of the first planarization layer 501 is located between the bonding metal layer 211 and the metal isolation structure 300, and another portion is located between the epitaxial layer 212 and the metal isolation structure 300.

[0071] The second planarization layer 502 is located between the bonding metal layer 211 and the epitaxial layer 212 of the second light emitting unit 202 and the metal isolation structure 300 .

[0072] The third planarization layer 503 is located between the bonding metal layer 211 and the epitaxial layer 212 of the third light emitting unit 203 and the metal isolation structure 300 .

[0073] In this implementation, the planarization layer can protect the light-emitting unit, prevent short circuits, and ensure the stability of electrical connections.

[0074] In the embodiment of the present disclosure, the bonding metal layer 211 of the first light-emitting unit 201 is electrically connected to the substrate 100, the bonding metal layer 211 of the second light-emitting unit 202 is electrically connected to the substrate 100 through the first planarization layer 501 via the first conductive column 401, and the bonding metal layer 211 of the third light-emitting unit 203 is electrically connected to the substrate 100 through the second conductive column 402 through the second planarization layer 502 and the first planarization layer 501.

[0075] In this implementation, the bonding metal layer passes through the transparent medium layer via the conductive column to form an electrical connection between the light-emitting unit and the substrate, avoiding mutual shading of different light-emitting units, ensuring the display effect of the display panel while ensuring the stability of the electrical connection.

[0076] like Figure 3 As shown, the first planarization layer 501 includes a portion located in the first groove 301, a portion located in the second groove 302, and a portion located in the third groove 303. The portion located in the first groove 301 surrounds the metal bonding layer 211, the first electrode 701, and the epitaxial layer 212 in the first light-emitting unit 201, the portion located in the second groove 302 is penetrated by the first conductive pillar 401, and the portion located in the third groove 303 is penetrated by the second conductive pillar 402.

[0077] The second planarization layer 502 includes a portion located in the first groove 301, a portion located in the second groove 302, and a portion located in the third groove 303. The portion located in the first groove 301 is a plane, the portion located in the second groove 302 surrounds the metal bonding layer 211, the first electrode 701, and the epitaxial layer 212 in the second light-emitting unit 202, and the portion located in the third groove 303 is penetrated by the second conductive pillar 402.

[0078] The third planarization layer 503 includes a portion located in the first groove 301, a portion located in the second groove 302, and a portion located in the third groove 303. The portions located in the first groove 301 and the second groove 302 form a plane, and the portion located in the third groove 303 surrounds the metal bonding layer 211, the first electrode 701, and the epitaxial layer 212 in the third light-emitting unit 203.

[0079] In the embodiment of the present disclosure, the first conductive pillar 401 and the second conductive pillar 402 may be cylinders.

[0080] In other embodiments, the first conductive pillar 401 and the second conductive pillar 402 may also be prisms, which is not limited in the present disclosure.

[0081] In the embodiment of the present disclosure, the display panel further includes a passivation layer 600, which is disposed on the metal isolation structure 300 and covers the third planarization layer 503 and the second electrode 702 of the third light-emitting unit 203. The passivation layer protects the light-emitting unit, prevents leakage and short circuits of the electrodes, and ensures the stability of the electrical connection.

[0082] In the embodiment of the present disclosure, the second electrode 702 of the first light-emitting unit 201, the second electrode of the second light-emitting unit 202, and the second electrode 702 of the third light-emitting unit 203 are in the shape of elongated strips. The elongated strip-shaped electrodes facilitate electrical connection between the electrodes and the substrate, thereby improving electrical performance.

[0083] In other examples, the shape of the second electrode 702 may also be other shapes, such as a circle.

[0084] In the embodiment of the present disclosure, the substrate 100 is a complementary metal-oxide-semiconductor (CMOS) substrate.

[0085] Exemplarily, the CMOS substrate includes a thin film transistor circuit, and the thin film transistor is used as a switch to control the on / off state and current level of each light emitting unit.

[0086] like Figure 3 As shown, the substrate 100 also has connection holes 101, which can be used to connect electrodes, substrates and other structures.

[0087] In the embodiment of the present disclosure, the epitaxial layer 212 includes a first semiconductor layer 2121 , an active layer 2122 , and a second semiconductor layer 2123 , which are stacked in sequence.

[0088] In the embodiment of the present disclosure, the first semiconductor layer 2121 may be an N-type semiconductor layer, the second semiconductor layer 2123 may be a P-type semiconductor layer, and the active layer 2122 may be a multi-quantum well layer.

[0089] For example, the first semiconductor layer 2121 of the first light-emitting unit 201 can be an N-type AlInGaP layer, the second semiconductor layer 2123 can be a P-type AlInGaP layer, and the active layer 2122 can include a plurality of periodically alternating stacked AlInGaP quantum well layers and AlInGaP quantum barrier layers; the first semiconductor layer 2121 of the second light-emitting unit 202 and the third light-emitting unit 203 can be an N-type GaN layer, the second semiconductor layer 2123 can be a P-type GaN layer, and the active layer 2122 can be an InGaN / GaN multiple quantum well structure.

[0090] In another example, the first semiconductor layer 2121 may be a P-type semiconductor layer, the second semiconductor layer 2123 may be an N-type semiconductor layer, and the active layer 2122 may be a multi-quantum well layer.

[0091] In the embodiment of the present disclosure, the bonding metal layer 211 may be an Au or Au alloy layer, which can ensure the bonding effect on the one hand and the conductive performance on the other hand.

[0092] In the embodiment of the present disclosure, the second electrode may be an indium tin oxide (ITO) electrode.

[0093] Optionally, the first light-emitting unit 201 , the second light-emitting unit 202 and the third light-emitting unit 203 may further include: an ohmic contact layer, which is provided between the bonding metal layer 211 and the epitaxial layer 212 .

[0094] In the embodiment of the present disclosure, the first conductive pillar 401 and the second conductive pillar 402 may be docking conductive pillars.

[0095] In the embodiment of the present disclosure, the planarization layer 500 may be a SiO 2 layer.

[0096] In the embodiment of the present disclosure, the passivation layer 600 may be a SiO 2 layer.

[0097] The above-mentioned light-emitting unit film layer structure is only an example. In other implementations, the light-emitting unit film may further include more or fewer film layers.

[0098] Figure 4This is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure. Figure 4 , the method steps include:

[0099] S11. Provide a substrate.

[0100] S12. Make multiple light-emitting units on the substrate, and the multiple light-emitting units are arranged in an array on the substrate, each of the light-emitting units includes at least a first light-emitting unit of a first light-emitting color, a second light-emitting unit of a second light-emitting color, and a third light-emitting unit of a third light-emitting color, the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are stacked on the substrate in sequence, and the projections of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit on the substrate do not overlap; the first electrode of the first light-emitting unit, the first electrode of the second light-emitting unit, and the first electrode of the third light-emitting unit are electrically connected to the substrate respectively, and the second electrode of the first light-emitting unit, the second electrode of the second light-emitting unit, and the second electrode of the third light-emitting unit are all electrically connected to the metal isolation structure; the metal isolation structure passes through the layer where the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are located in sequence, and is insulated from the epitaxial layer and the first electrode of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit, and the metal isolation structure includes a first groove, a second groove, and a third groove, and the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are located in the first groove, the second groove, and the third groove respectively.

[0101] In the embodiment of the present disclosure, each light-emitting unit in the display panel includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit. The projections of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit on the substrate do not overlap, and the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are isolated from each other by a metal isolation structure, thereby avoiding the mutual influence of light between the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit, effectively avoiding the occurrence of pixel crosstalk, and improving the color consistency and contrast of the display panel. The second electrode of the first light-emitting unit, the second electrode of the second light-emitting unit, and the second electrode of the third light-emitting unit are all electrically connected to the metal isolation structure. On the one hand, the second electrodes of the first to third light-emitting units are connected together to form a common electrode. On the other hand, the connection is achieved through the metal isolation structure, which simplifies the connection structure of the electrodes. In addition, the metal isolation structure provides support and protection for the light-emitting unit, making the structure of the light-emitting unit more stable and improving the yield of the display panel.

[0102] Figure 5 This is a flow chart of another method for manufacturing a display panel provided by an embodiment of the present disclosure. Figure 5 , the method steps include:

[0103] S21. Provide a substrate.

[0104] In the embodiment of the present disclosure, the substrate is a complementary metal-oxide-semiconductor (CMOS) substrate.

[0105] Exemplarily, the CMOS substrate includes a thin film transistor circuit, and the thin film transistor is used as a switch to control the on / off state and current level of each light emitting unit.

[0106] The first step is to form a substrate passivation layer on the surface of the substrate.

[0107] In the embodiment of the present disclosure, the substrate passivation layer may be a SiO2 passivation layer.

[0108] The second step is to open holes in the passivation layer of the substrate.

[0109] In the embodiment of the present disclosure, a hole is opened in the passivation layer of the substrate, and a docking metal is filled in the through hole to form a docking plug.

[0110] S22. Bonding a first epitaxial film layer on the substrate.

[0111] In one example, step S22 includes:

[0112] In the first step, a bonding metal layer is deposited on the substrate.

[0113] In the embodiment of the present disclosure, the bonding metal layer may be an Au or Au alloy layer, which can ensure the bonding effect on the one hand and the conductive performance on the other hand.

[0114] In the second step, a first epitaxial film layer, a first electrode and a bonding metal layer are sequentially formed on the temporary substrate.

[0115] In the embodiment of the present disclosure, the first epitaxial film layer may be a red light first epitaxial film layer, a green light first epitaxial film layer, or a blue light first epitaxial film layer.

[0116] In the embodiment of the present disclosure, the temporary substrate may be a GaAs substrate.

[0117] In the embodiment of the present disclosure, the first epitaxial film layer includes a first semiconductor layer, an active layer and a second semiconductor layer.

[0118] In the embodiment of the present disclosure, the first semiconductor layer may be an N-type semiconductor layer, and the second semiconductor layer may be a P-type semiconductor layer.

[0119] For example, when the first epitaxial film layer is a red light first epitaxial film layer, the first semiconductor layer may be an N-type AlInGaP layer, and the second semiconductor layer may be a P-type AlInGaP layer;

[0120] When the first epitaxial film layer is a green light first epitaxial film layer or a blue light first epitaxial film layer, the first semiconductor layer may be an N-type GaN layer, and the second semiconductor layer may be a P-type GaN layer.

[0121] In another example, the first semiconductor layer may be a P-type semiconductor layer, and the second semiconductor layer may be an N-type semiconductor layer.

[0122] In the embodiment of the present disclosure, the active layer may be a multi-quantum well layer. For example, when the first epitaxial film layer is a red light first epitaxial film layer, the multi-quantum well layer may include a plurality of periodically alternately stacked AlInGaP quantum well layers and AlInGaP quantum barrier layers.

[0123] When the first epitaxial film layer is a green light first epitaxial film layer or a blue light first epitaxial film layer, the multi-quantum well layer may include a plurality of InGaN quantum well layers and GaN quantum barrier layers that are alternately stacked in a periodic manner.

[0124] In the embodiment of the present disclosure, the first electrode may be a P electrode.

[0125] In the third step, the bonding metal layer of the temporary substrate and the bonding metal layer of the base plate are bonded together, and the temporary substrate is removed.

[0126] S23 , performing patterning on the first epitaxial film layer to form an epitaxial layer of the first light-emitting unit.

[0127] Exemplarily, the first epitaxial film layer, the first electrode and the bonding metal layer are etched to obtain the epitaxial layer, the first electrode and the bonding metal layer of the first light-emitting unit.

[0128] Figure 6 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 6 The first light emitting unit 201 is located on the substrate 100 . The first light emitting unit 201 includes a bonding metal layer 211 , a first electrode 701 and an epitaxial layer 212 . The epitaxial layer 212 includes a first semiconductor layer 2121 , an active layer 2122 and a second semiconductor layer 2123 .

[0129] S24 , manufacturing a first planarization layer, wherein the first planarization layer surrounds the first light emitting unit.

[0130] In the embodiment of the present disclosure, the first planarization layer may be a SiO 2 layer.

[0131] In the embodiment of the present disclosure, the thickness of the first planarization layer may be 0.1-5 μm.

[0132] Exemplarily, the thickness of the first planarization layer is 3 μm.

[0133] In the embodiment of the present disclosure, the thickness of the first planarization layer is greater than the thickness of the epitaxial layer of the first light emitting unit, thereby achieving the purpose of planarization.

[0134] In the embodiment of the present disclosure, the first planarization layer is polished by chemical mechanical polishing (CMP) to form a flat surface.

[0135] In the embodiment of the present disclosure, the thickness of the first planarization layer after polishing may be 0.1-3 μm.

[0136] Exemplarily, the thickness of the first planarization layer after polishing is 2 μm.

[0137] S25 , performing a patterning process on the first planarization layer.

[0138] Figure 7 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 7 The first planarization layer 501 has a groove 10a for forming the metal isolation structure 300 , a first through hole 10b for forming the first conductive column 401 , and a second through hole 10c for forming the second conductive column 402 .

[0139] In the embodiment of the present disclosure, the grooves and the through holes are formed by etching the first planarization layer.

[0140] S26 , manufacturing a first layer of the metal isolation structure, a first conductive pillar, and a first portion of the second conductive pillar.

[0141] Figure 8 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 8 The first layer 30a of the metal isolation structure 300 is formed with three grooves, wherein the first light-emitting unit 201 and the surrounding first planarization layer 501 are located in the first groove 301 on the far left, the middle second groove 302 includes the first planarization layer 501 and the first conductive column 401, and the right third groove 303 includes the first planarization layer 501 and the first part of the second conductive column 402.

[0142] It should be noted that the metal isolation structure 300 of the embodiment of the present disclosure is formed by stacking three layers. During the stacking process, the depths of the first groove 301 , the second groove 302 and the third groove 303 gradually increase.

[0143] In the embodiment of the present disclosure, docking metal is used to fill the through-hole to form the first conductive pillar and the first portion of the second conductive pillar.

[0144] In an embodiment of the present disclosure, a docking metal is used to fill the groove to form a first layer of the metal isolation structure.

[0145] S27. Fabricate a second electrode of the first light-emitting unit.

[0146] Figure 9 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 9 The second electrode 702 of the first light emitting unit 201 is located on the first planarization layer 501 and is electrically connected to the metal isolation structure.

[0147] In one example, step S27 includes:

[0148] In the first step, an indium tin oxide (ITO) layer is deposited on the surface of the first light emitting unit.

[0149] The second step is to pattern the ITO and remove excess ITO to obtain the second electrode of the first light-emitting unit.

[0150] In other embodiments, the second electrode of the light-emitting unit may also be made of other transparent conductive materials.

[0151] S28. Bond a second epitaxial film layer on the first planarization layer.

[0152] In one example, step S28 includes:

[0153] In the first step, a bonding metal layer is deposited on the first planarization layer.

[0154] In the embodiment of the present disclosure, the bonding metal layer may be an Au or Au alloy layer, which can ensure the bonding effect on the one hand and the conductive performance on the other hand.

[0155] In the second step, a second epitaxial film layer, a first electrode and a bonding metal layer are sequentially formed on the temporary substrate.

[0156] In the embodiment of the present disclosure, the second epitaxial film layer may be a green light second epitaxial film layer, a blue light second epitaxial film layer, or a red light second epitaxial film layer.

[0157] In the embodiment of the present disclosure, the temporary substrate may be a Si substrate or a sapphire substrate.

[0158] Exemplarily, the temporary substrate is a Si substrate.

[0159] In the embodiment of the present disclosure, the second epitaxial film layer includes a first semiconductor layer, an active layer and a second semiconductor layer.

[0160] In the embodiment of the present disclosure, the first semiconductor layer may be an N-type semiconductor layer, and the second semiconductor layer may be a P-type semiconductor layer.

[0161] For example, when the second epitaxial film layer is the red light first epitaxial film layer, the first semiconductor layer may be an N-type AlInGaP layer, and the second semiconductor layer may be a P-type AlInGaP layer;

[0162] When the second epitaxial film layer is a green light second epitaxial film layer or a blue light second epitaxial film layer, the first semiconductor layer may be an N-type GaN layer, and the second semiconductor layer may be a P-type GaN layer.

[0163] In another example, the first semiconductor layer may be a P-type semiconductor layer, and the second semiconductor layer may be an N-type semiconductor layer.

[0164] In the embodiment of the present disclosure, the active layer may be a multi-quantum well layer. For example, when the second epitaxial film layer is a red light second epitaxial film layer, the multi-quantum well layer may include a plurality of periodically alternately stacked AlInGaP quantum well layers and AlInGaP quantum barrier layers.

[0165] When the second epitaxial film layer is a green light second epitaxial film layer or a blue light second epitaxial film layer, the multi-quantum well layer may include a plurality of InGaN quantum well layers and GaN quantum barrier layers that are alternately stacked in a periodic manner.

[0166] In the third step, the bonding metal layer of the temporary substrate and the bonding metal layer of the first planarization layer are bonded together, and the temporary substrate is removed.

[0167] S29, performing patterning on the second epitaxial film layer to form an epitaxial layer of the second light-emitting unit.

[0168] Illustratively, the second epitaxial film layer, the first electrode and the bonding metal layer are etched to obtain the epitaxial layer, the first electrode and the bonding metal layer of the second light-emitting unit.

[0169] Figure 10 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 10 The second light emitting unit 202 is located on the first planarization layer 501 . The second light emitting unit 202 includes a bonding metal layer 211 , a first electrode 701 and an epitaxial layer 212 . The epitaxial layer 212 includes a first semiconductor layer 2121 , an active layer 2122 and a second semiconductor layer 2123 .

[0170] S30 , manufacturing a second planarization layer, wherein the second planarization layer surrounds the second light emitting unit.

[0171] In the embodiment of the present disclosure, the second planarization layer may be a SiO 2 layer.

[0172] In the embodiment of the present disclosure, the thickness of the second planarization layer may be 0.1-5 μm.

[0173] Exemplarily, the thickness of the second planarization layer is 3 μm.

[0174] In the embodiment of the present disclosure, the thickness of the second planarization layer is greater than the thickness of the epitaxial layer of the second light emitting unit, thereby achieving the purpose of planarization.

[0175] In the embodiment of the present disclosure, the second planarization layer is polished by chemical mechanical polishing (CMP) to form a flat surface.

[0176] In the embodiment of the present disclosure, the thickness of the second planarization layer after polishing may be 0.1-3 μm.

[0177] Exemplarily, the thickness of the second planarization layer after polishing is 2 μm.

[0178] S31 , performing patterning processing on the second planarization layer.

[0179] Figure 11 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 11 A groove 10 a for forming the metal isolation structure 300 and a second through hole 10 c for forming the second conductive pillar 402 are formed on the second planarization layer 502 .

[0180] In the embodiment of the present disclosure, the grooves and the through holes are formed by etching the second planarization layer.

[0181] S32 , manufacturing a second layer of the metal isolation structure and a second portion of the second conductive pillar.

[0182] Figure 12 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 12 The second layer 30b of the metal isolation structure 300 is formed with three grooves, wherein the second light-emitting unit 202 and the surrounding second planarization layer 502 are located in the middle second groove 302, the first groove 302 on the far left includes the second planarization layer 502, and the third groove 303 on the right includes the second planarization layer 502 and the second part of the second conductive column 402.

[0183] It should be noted that the metal isolation structure 300 of the embodiment of the present disclosure is formed by stacking three layers. During the stacking process, the depths of the first groove 301 , the second groove 302 and the third groove 303 gradually increase.

[0184] In the embodiment of the present disclosure, the second portion of the second conductive pillar is formed by filling the through hole with a docking metal.

[0185] In the embodiment of the present disclosure, a docking metal is used to fill the groove to form the second layer of the metal isolation structure.

[0186] S33: fabricate a second electrode of the second light-emitting unit.

[0187] Figure 13 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 13 The second electrode 702 of the second light emitting unit 202 is located on the second planarization layer 502 and is electrically connected to the metal isolation structure.

[0188] In one example, step S33 includes:

[0189] In the first step, an indium tin oxide (ITO) layer is deposited.

[0190] The second step is to pattern the ITO and remove excess ITO to obtain the second electrode of the second light-emitting unit.

[0191] In the embodiment of the present disclosure, the second electrode of the second light emitting unit is embedded in the sidewall of the metal isolation structure.

[0192] S34 , bonding a third epitaxial film layer on the second planarization layer.

[0193] In one example, step S34 includes:

[0194] In the first step, a bonding metal layer is deposited on the second planarization layer.

[0195] In the embodiment of the present disclosure, the bonding metal layer may be an Au or Au alloy layer, which can ensure the bonding effect on the one hand and the conductive performance on the other hand.

[0196] In the second step, a third epitaxial film layer, a first electrode and a bonding metal layer are formed on the temporary substrate at the same time.

[0197] In the embodiment of the present disclosure, the third epitaxial film layer may be a blue light third epitaxial film layer, a red light third epitaxial film layer, or a green light third epitaxial film layer.

[0198] In the embodiment of the present disclosure, the temporary substrate may be a Si substrate or a sapphire substrate.

[0199] Exemplarily, the temporary substrate is a Si substrate.

[0200] In the embodiment of the present disclosure, the third epitaxial film layer includes a first semiconductor layer, an active layer, and a second semiconductor layer.

[0201] In the embodiment of the present disclosure, the first semiconductor layer may be an N-type semiconductor layer, and the second semiconductor layer may be a P-type semiconductor layer.

[0202] For example, when the third epitaxial film layer is a red light third epitaxial film layer, the first semiconductor layer may be an N-type AlInGaP layer, and the second semiconductor layer may be a P-type AlInGaP layer;

[0203] When the third epitaxial film layer is a green light third epitaxial film layer or a blue light third epitaxial film layer, the first semiconductor layer may be an N-type GaN layer, and the second semiconductor layer may be a P-type GaN layer.

[0204] In another example, the first semiconductor layer may be a P-type semiconductor layer, and the second semiconductor layer may be an N-type semiconductor layer.

[0205] In the embodiment of the present disclosure, the active layer may be a multi-quantum well layer. For example, when the third epitaxial film layer is a red light third epitaxial film layer, the multi-quantum well layer may include a plurality of periodically alternately stacked AlInGaP quantum well layers and AlInGaP quantum barrier layers.

[0206] When the third epitaxial film layer is a green light third epitaxial film layer or a blue light third epitaxial film layer, the multi-quantum well layer may include a plurality of InGaN quantum well layers and GaN quantum barrier layers that are alternately stacked in a periodic manner.

[0207] In the third step, the bonding metal layer of the temporary substrate and the bonding metal layer of the second planarization layer are bonded together, and the temporary substrate is removed.

[0208] S35 , performing patterning on the third epitaxial film layer to form an epitaxial layer of a third light-emitting unit.

[0209] Illustratively, the third epitaxial film layer, the first electrode and the bonding metal layer are etched to obtain the epitaxial layer, the first electrode and the bonding metal layer of the third light-emitting unit.

[0210] Figure 14 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 14 The third light emitting unit 203 is grown on the second planarization layer 502. The third light emitting unit 203 includes a bonding metal layer 211, a first electrode 701 and an epitaxial layer 212. The epitaxial layer 212 includes a first semiconductor layer 2121, an active layer 2122 and a second semiconductor layer 2123.

[0211] S36 , manufacturing a third planarization layer, wherein the third planarization layer surrounds the third light-emitting unit.

[0212] In the embodiment of the present disclosure, the third planarization layer may be a SiO 2 layer.

[0213] In the embodiment of the present disclosure, the thickness of the third planarization layer may be 0.1-5 μm.

[0214] Exemplarily, the thickness of the third planarization layer is 3 μm.

[0215] In the embodiment of the present disclosure, the thickness of the third planarization layer is greater than the thickness of the epitaxial layer of the third light-emitting unit, thereby achieving the purpose of planarization.

[0216] In the embodiment of the present disclosure, the third planarization layer is polished by chemical mechanical polishing (CMP) to form a flat surface.

[0217] In the embodiment of the present disclosure, the thickness of the third planarization layer after polishing may be 0.1-3 μm.

[0218] Exemplarily, the thickness of the third planarization layer after polishing is 2 μm.

[0219] S37 , performing a patterning process on the third planarization layer.

[0220] Figure 15 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 15 A groove 10 a for fabricating the metal isolation structure 300 is formed on the third planarization layer 503 .

[0221] In the embodiment of the present disclosure, the groove is formed by etching the third planarization layer.

[0222] S38. Make the third layer of the metal isolation structure.

[0223] Figure 16 This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 16 ,

[0224] The third layer 30c of the metal isolation structure 300 is formed with three grooves 10a, wherein the third light-emitting unit 301 and the surrounding third planarization layer 503 are located in the third groove 303 on the far right, the first groove 301 on the far left includes the third planarization layer 503, and the second groove 302 in the middle includes the third planarization layer 503.

[0225] It should be noted that the metal isolation structure 300 of the embodiment of the present disclosure is formed by stacking three layers. During the stacking process, the depths of the first groove 301 , the second groove 302 and the third groove 303 gradually increase.

[0226] In the embodiment of the present disclosure, a docking metal is used to fill the groove to form the third layer of the metal isolation structure.

[0227] S39, manufacturing the second electrode of the third light-emitting unit.

[0228] Figure 17This is a structural diagram of a display panel manufacturing process provided by an embodiment of the present disclosure. Figure 17 , the second electrode 702 of the third light emitting unit 203 is located on the third planarization layer 503 .

[0229] In one example, step S39 includes:

[0230] In the first step, an indium tin oxide (ITO) layer is deposited.

[0231] The second step is to pattern the ITO and remove excess ITO to obtain the second electrode of the third light-emitting unit.

[0232] S40, making a passivation layer, where the passivation layer is on the surface of the planarization layer.

[0233] Through step S40, the final structure is obtained as follows Figure 3 shown.

[0234] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises: a substrate (100), a plurality of light-emitting units (200) and a metal isolation structure (300); A plurality of light-emitting units (200) are arranged in an array on the substrate (100), each of the light-emitting units (200) comprising at least a first light-emitting unit (201) of a first light-emitting color, a second light-emitting unit (202) of a second light-emitting color, and a third light-emitting unit (203) of a third light-emitting color; the first light-emitting unit (201), the second light-emitting unit (202), and the third light-emitting unit (203) are sequentially stacked on the substrate (100); and projections of the first light-emitting unit (201), the second light-emitting unit (202), and the third light-emitting unit (203) on the substrate (100) do not overlap; The first electrode (701) of the first light-emitting unit (201), the first electrode (701) of the second light-emitting unit (202), and the first electrode (701) of the third light-emitting unit (203) are electrically connected to the substrate (100), respectively; the second electrode (702) of the first light-emitting unit (201), the second electrode (702) of the second light-emitting unit (202), and the second electrode (702) of the third light-emitting unit (203) are all electrically connected to the metal isolation structure (300); The metal isolation structure (300) sequentially passes through the layers where the first light-emitting unit (201), the second light-emitting unit (202) and the third light-emitting unit (203) are located, and is insulated from the epitaxial layers and the first electrodes of the first light-emitting unit (201), the second light-emitting unit (202) and the third light-emitting unit (203). The metal isolation structure (300) comprises a first groove (301), a second groove (302) and a third groove (303). The first light-emitting unit (201), the second light-emitting unit (202) and the third light-emitting unit (203) are respectively located in the first groove (301), the second groove (302) and the third groove (303).

2. The display panel according to claim 1, wherein: The metal isolation structure (300) is a docking metal isolation structure.

3. The display panel according to claim 1, wherein: The second electrode (702) of the first light-emitting unit (201) and the second electrode (702) of the second light-emitting unit (202) are embedded in the side walls of the metal isolation structure (300), and the second electrode (702) of the third light-emitting unit (203) covers the top surface of the metal isolation structure (300).

4. The display panel according to any one of claims 1 to 3, characterized in that: The first light-emitting unit (201) is a red light-emitting unit, the second light-emitting unit (202) is a green light-emitting unit, and the third light-emitting unit (203) is a blue light-emitting unit.

5. The display panel according to claim 4, wherein: The cross-sectional area of the first groove (301) is greater than the cross-sectional area of the second groove (302), and the cross-sectional area of the first groove (301) is greater than the cross-sectional area of the third groove (303).

6. The display panel according to any one of claims 1 to 3, characterized in that: The first groove (301), the second groove (302) and the third groove (303) are all rounded rectangles.

7. The display panel according to any one of claims 1 to 3, characterized in that: The sidewall thickness of the metal isolation structure (300) is 0.1-2 μm.

8. The display panel according to any one of claims 1 to 3, characterized in that: The first light-emitting unit (201), the second light-emitting unit (202) and the third light-emitting unit (203) all include: a bonding metal layer (211) and an epitaxial layer (212); The bonding metal layer (211), the first electrode (701), the epitaxial layer (212) and the second electrode (702) are stacked in sequence.

9. The display panel according to claim 8, wherein: The display panel further comprises a planarization layer (500), wherein the planarization layer (500) comprises a first planarization layer (501), a second planarization layer (502), and a third planarization layer (503); The first planarization layer (501) is located between the bonding metal layer (211) and the epitaxial layer (212) of the first light-emitting unit (201) and the metal isolation structure (300); The second planarization layer (502) is located between the bonding metal layer (211) and the epitaxial layer (212) of the second light-emitting unit (202) and the metal isolation structure (300); The third planarization layer (503) is located between the bonding metal layer (211) and the epitaxial layer (212) of the third light-emitting unit (203) and the metal isolation structure (300).

10. The display panel according to claim 8, wherein The bonding metal layer (211) of the first light-emitting unit (201) is electrically connected to the substrate (100), the bonding metal layer (211) of the second light-emitting unit (202) is electrically connected to the substrate (100) through the first planarization layer (501) via a first conductive column (401), and the bonding metal layer (211) of the third light-emitting unit (203) is electrically connected to the substrate (100) through the second planarization layer (502) and the first planarization layer (501) via a second conductive column (402).

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