Global shutter pixel with vertical integrated multiphase charge transfer

Abstract

An image sensor may include a plurality of pixels, each of the plurality of pixels may include a photodiode having a charge accumulation region ("PD"), a floating diffusion region ("FD"), and a charge transfer region vertically between the PD and the FD. The vertical charge transfer region may include a first charge modulation region ("P1"), a second charge modulation region ("P2"), and a third charge modulation region ("P3"). The image sensor may operate in a global shutter mode in which the P2 may serve as an in-pixel charge storage region to temporarily store charge during its transfer from PD to FD via P1, P2, and P3.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors and, more particularly, to pixels of image sensors with vertically integrated multi-phase charge transfer for image capture in global shutter mode. Background Art

[0002] Related technical description

[0003] Image capture devices (such as cameras) are widely used in various electronic devices, such as mobile devices (e.g., smart phones, tablet computers, laptop computers, etc.), robotic equipment, or security monitoring equipment. The image capture device may include an image sensor having a plurality of light-collecting pixels. Each pixel may include a photodiode. The image capture device may capture light from the environment and transmit the light to the image sensor. When exposed to light, the photodiode of the pixel may accumulate charge. During readout, one or more transistors may be used to read out the charge of the photodiode from the photodiode to generate an analog image signal. The analog image signal may be converted into a digital signal and further processed to produce an image. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 Shown are top views and cross-sectional views of an example pixel of an image sensor, according to some embodiments.

[0005] Figure 2 An example implementation of a control gate for a pixel of an image sensor is shown, according to some embodiments.

[0006] Figure 3 An example implementation of a vertical gate region of a pixel of an image sensor is shown according to some embodiments.

[0007] Figures 4A to 4D Example timing diagrams are shown of control signals and potential distributions for pixels of an image sensor to illustrate charge transfer, according to some embodiments.

[0008] Figure 5A A cross-sectional view of an example pixel and a top view of an image sensor are shown, according to some embodiments.

[0009] Figure 5B Example control signals applied to different components of multiple pixels of an image sensor are shown, according to some embodiments.

[0010] Figure 6 Shown are top and cross-sectional views of another example pixel of an image sensor, according to some embodiments.

[0011] Figure 7 An example isolation structure for a pixel of an image sensor is shown, according to some embodiments.

[0012] Figure 8 Example segmented pixels for autofocus applications are shown according to some embodiments.

[0013] Figure 9 Shown are top and cross-sectional views of another example pixel of an image sensor, according to some embodiments.

[0014] Figure 10 Shown are top and cross-sectional views of another example pixel of an image sensor, according to some embodiments.

[0015] Figure 11 Shown are top and cross-sectional views of another example pixel of an image sensor, according to some embodiments.

[0016] Figure 12 is a block diagram of an example image capture device according to some embodiments.

[0017] Figure 13 is a flow chart illustrating an example method for operating an image sensor in a global shutter mode using an in-pixel charge storage region, according to some embodiments.

[0018] Figure 14 Schematic representations of example devices that may include an image capture device (eg, a camera) having an image sensor including pixels having the disclosed in-pixel charge storage regions are illustrated in accordance with some embodiments.

[0019] Figure 15 Illustrated is a schematic block diagram of an example computing device (referred to as a computer system) that may include or host an image capture device (e.g., a camera) having an image sensor that includes pixels having disclosed intra-pixel charge storage regions, according to some embodiments.

[0020] This specification includes references to "one embodiment" or "an embodiment." The appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0021] The term "comprising" is open-ended. As used in the appended claims, the term does not exclude additional structures or steps. Consider the following recited claim: "An apparatus comprising one or more processor units..." Such a claim does not exclude the apparatus from including additional components (e.g., a network interface unit, graphics circuitry, etc.).

[0022] "Configured to," various units, circuits, or other components may be described or recited as "configured to" perform one or more tasks. In such contexts, "configured to" is used to imply a structure (e.g., a circuit) that performs the one or more tasks during operation by indicating that the unit / circuit / component includes the structure. Thus, the unit / circuit / component is said to be configured to perform the task even when the specified unit / circuit / component is not currently operational (e.g., not turned on). The units / circuits / components used with the "configured to" language include hardware—e.g., circuits, memories storing program instructions that can be executed to implement the operation, etc. Reference to a unit / circuit / component being "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) with respect to that unit / circuit / component. Additionally, "configured to" may include a general structure (e.g., a general circuit) manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the one or more tasks to be solved. "Configured to" may also include adapting a manufacturing process (eg, a semiconductor fabrication facility) to produce a device (eg, an integrated circuit) suitable for implementing or performing one or more tasks.

[0023] "First," "Second," etc. As used herein, these terms act as labels for the nouns that precede them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, a buffer circuit may be described herein as performing a write operation for a "first" value and a "second" value. The terms "first" and "second" do not necessarily imply that the first value must be written before the second value.

[0024] "Based on." As used herein, this term is used to describe one or more factors that influence a determination. This term does not exclude additional factors that may influence the determination. That is, the determination may be based solely on these factors, or at least in part on these factors. Consider the phrase "A is determined based on B." In this case, B is a factor that influences the determination of A, and such a phrase does not exclude that the determination of A may also be based on C. In other examples, A may be determined based solely on B.

[0025] It will also be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are simply used to distinguish one element from another. For example, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact, without departing from the intended scope. Both the first contact and the second contact are contacts, but they are not the same contact.

[0026] The terms used in this description are only for the purpose of describing specific embodiments and are not intended to be limiting. As used in the specification and the appended claims, the singular forms "a", "an" and "the" are intended to also encompass the plural form, unless the context clearly indicates otherwise. It will also be understood that the terms "and / or" used herein refer to and encompass any and all possible combinations of one or more items in the items listed in association. It will also be understood that the terms "comprises" and / or "comprising" when used in this specification specify the presence of stated features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groupings.

[0027] As used herein, the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined that" or "if [stated condition or event] is detected" may be interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context. DETAILED DESCRIPTION

[0028] Various embodiments described herein relate to an image sensor operating in a global shutter mode. In some embodiments, the image sensor may include a plurality of light-gathering pixels, for example, the plurality of light-gathering pixels are organized into a pixel array having one or more pixel rows and one or more pixel columns. In some embodiments, the image sensor may be a CMOS (complementary metal oxide semiconductor) image sensor, a CCD (charge coupled device) image sensor, or the like. In some embodiments, the image sensor may be part of an image capture device (e.g., a camera), and further, the image capture device may be part of an electronic device (e.g., a mobile device (e.g., a smartphone, tablet, laptop, etc.), robotic equipment, or security monitoring equipment, etc.). In some embodiments, the pixels of the image sensor may each include at least one photodiode, the at least one photodiode including a charge accumulation region (hereinafter referred to as "PD"), a floating diffusion region (hereinafter referred to as "FD"), and a charge transfer region vertically located between the PD and the FD. When exposed to light, the PD may accumulate charge or photocarriers for each pixel. During readout, at least some of the charge can be transferred from the PD to the FD to generate an analog image signal (e.g., an analog voltage) at the FD, which can be further accessed at a pixel output line external to the pixel. In some embodiments, the analog image signal accessed via the pixel output line can be further processed (e.g., converted to digital using an analog-to-digital converter and digitally processed by an image signal processor (ISP)) to generate one or more images.

[0029] Generally speaking, a given image capture device can operate in either rolling shutter mode or global shutter mode. In rolling shutter mode, different rows of the pixel array of an image capture device's image sensor can be exposed to light at different times as a "wave" of readout sweeps across the image sensor. For example, pixels of the pixel array can be exposed, and their image signals can be read out sequentially (e.g., row by row, from the top to the bottom of the pixel array). For example, pixels in the same row can be read out simultaneously, while pixels in the same column but different rows can be read out one by one. Thus, in rolling shutter mode, the image sensor can record an image sequentially, row by row, rather than capturing the entire image all at once. In contrast, in a global shutter mode, all pixels can have the same exposure time, meaning that exposure for each pixel in the image sensor begins and ends simultaneously. Thus, the entire image can be recorded all at once. A rolling shutter mode can cause variations in the color and / or shading of the captured image because different "lines" of the image are recorded at different times. In some applications, such as high-speed filming or recording, this can cause significant interference and significantly impact the quality of the captured image. Therefore, in some embodiments, a global shutter mode may be preferred. However, in some embodiments, even if the exposure of the pixels of the image sensor ends simultaneously, their image signals can still be read out sequentially (e.g., row by row) like a rolling shutter. Therefore, the image sensor may require a "memory" to temporarily store the pixel's (a) charge (e.g., in the charge domain) and / or (b) analog or digital image signal (e.g., in the voltage domain) at the end of exposure until the individual pixels are read out.

[0030] To address this problem, in some embodiments, the pixels of the image sensor disclosed herein may each include an intra-pixel charge storage region. At the end of exposure, the charge may be transferred from the PD to the intra-pixel charge storage region. The charge may be temporarily stored there until the pixel is read out. During readout, the charge may be transferred from the intra-pixel charge storage region to the FD, from which analog image information may be further accessed via the pixel output line. Those skilled in the art will appreciate that the disclosed image sensor may provide several benefits. First, the image sensor may provide an intra-pixel charge storage region for each pixel to temporarily store the charge of the pixel, thereby enabling the image sensor to operate in global shutter mode. In addition, the "memory" is integrated as part of the pixel to store the charge inside the pixel, thereby eliminating or at least reducing other additional memory storage components (e.g., a memory chip on the image sensor, etc.). Therefore, this may reduce the number of components of the image sensor, reduce the area occupied by the image sensor, and / or increase the pixel density of the sensor.

[0031] Figure 1A top view and a cross-sectional view of an example pixel of an image sensor according to some embodiments are shown. As shown, in some embodiments, pixel 100 may be formed on or in a substrate 130 (e.g., a substrate made of silicon or other semiconductor materials). In some embodiments, pixel 100 may be one of a plurality of pixels of an image sensor of an image capture device (e.g., a CMOS image sensor, a CCD image sensor, etc.). In some embodiments, pixel 100 may include: one or more circuits (e.g., pixel readout circuitry) formed using one or more transistors for reading out image signals from pixel 100 to generate one or more analog signals (e.g., analog voltages) at a pixel output line; and / or other signal conditioning or processing circuitry. For purposes of illustration, Figure 1 The circuit is not shown.

[0032] like Figure 1 As shown, in some embodiments, pixel 100 may include: at least one photodiode including a charge accumulation region 102 (hereinafter referred to as "PD"); a floating diffusion region 104 (hereinafter referred to as "FD"); and at least one charge transfer region vertically formed between PD 102 and FD 104. Figure 1 As shown, in some embodiments, PD 102 and FD 104 can be arranged vertically relative to each other, for example, where PD 102 is placed below and at least partially overlaps FD 104, and FD 104 is placed near the top surface of pixel 100. In addition, in some embodiments, at least one charge transfer region can include multiple charge modulation regions, for example, phase 1 charge modulation region 106 (hereinafter referred to as "P1"), phase 2 charge modulation region 108 (hereinafter referred to as "P2"), and phase 3 charge modulation region 110 (hereinafter referred to as "P3"). Figure 1As shown, in some embodiments, P1 106, P2 108, and P3 110 can be vertically disposed on top of each other between PD 102 and FD 104. For example, P1 106 can be formed above PD 102 and at least partially overlap the PD, P2 108 can be formed above P1 106 and at least partially overlap P1, and P3 110 can be (a) formed above P2 108 and at least partially overlap P2, and (b) formed below FD 104 and at least partially overlap the FD. Thus, P1 106, P2 108, and P3 110 can be stacked together and collectively form a charge transfer region vertically between PD 102 and FD 104. In some embodiments, at least a portion of P3 110 can optionally be disposed away from FD 104 and separated from the FD by a physical gap. For example, in some embodiments, a physical gap may be located at a corner of P3 110 that meets FD 104. The physical gap may provide a potential barrier (eg, an electrostatic barrier) between P3 110 and FD 104 that may hinder charge transfer from P3 110 to FD 104.

[0033] In some embodiments, P1 106, P2 108, and P3 110 can each be controlled by a control signal (e.g., a control voltage) applied to its corresponding control gate. Furthermore, each control gate can include a vertical gate region (hereinafter referred to as "G") and an associated gate contact (hereinafter referred to as "GC"). For example, the control gate of P1 106 can include a first vertical gate region 112 (hereinafter referred to as "G1"), which can further be electrically connected to a first gate contact 122 (hereinafter referred to as "GC1") disposed within a gate control region 120. Similarly, the control gate of P2 108 may include a second vertical gate region 114 (hereinafter referred to as "G2") and a second gate contact (hereinafter referred to as "GC2") 124 disposed within the gate control region 120; the control gate of P3 110 may include a third vertical gate region 116 (hereinafter referred to as "G3") and a third gate contact 126 (hereinafter referred to as "G3") disposed within the gate control region 120. In some embodiments, G1 112, G2 114, and G3 116 may be formed using polysilicon material and buried within the substrate 130. In some embodiments, GC1 122, GC2 124, and GC3 126 may be formed using metal or polysilicon material and may serve as respective "electrodes" to receive control signals (e.g., control voltages) applied to G1 112, G2 114, and G3 116. Figure 1As shown, in some embodiments, pixel 100 can include region 132 that is isolated from substrate 130 by dielectric material 150 at an outer layer around the perimeter of pixel 100. In some embodiments, region 132 can be formed using polysilicon or a metal material. In some embodiments, region 132 can attract holes from PD 102, thereby promoting charge accumulation in PD 102 when PD 102 is exposed to light.

[0034] like Figure 1 As shown, in this example, G1 112, G2 114, and G3 116 may be vertically disposed on top of each other (so that only G3 116 is visible in the top view), laterally adjacent to their corresponding modulation zones P1 106, P2 108, and P3 110. Additionally, G1 112, G2 114, and G3 116 may not necessarily vertically overlap FD 104, as shown. Figure 1106, P2 108, and P3 110, as well as FD 102 (only laterally, as they do not vertically overlap FD 102, as described above). Thus, the potentials of P1 106, P2 108, and P3 110 can be individually modulated or controlled by corresponding control signals applied to G1 112, G2 114, and G3 116. For example, in some embodiments, the potential of P1 106 can be modulated by a control voltage signal applied to G1 112. For example, in some embodiments, P1 106 can be implanted with one or more p-type dopants. When a positive voltage is applied to G1 112, the positive voltage can repel holes in the layer of P1 106 that is adjacent to G1 112 away from G1 112, thereby creating a channel in the adjacent layer. As a result, charge can be transferred from PD 102 through the channel of P1 106. Similarly, in some embodiments, the potential of P2 108 can be modulated by a control voltage signal applied to G2 114, and a channel can be formed within P2 102 to further transfer charge through P2 108. Similarly, in some embodiments, the potential of P3 110 can be modulated by a voltage control signal applied to G3, and a channel can be formed within P3 110 to further transfer charge through P3 110. As described in more detail below, in some embodiments, P2 108 can serve as an intra-pixel charge storage area to temporarily store charge generated from PD 102. For example, at the end of exposure, charge may first be transferred from PD 102 to P2 108 via P1 106. The charge may be temporarily stored in P2 108 until readout of pixel 100. At readout, the charge may then be transferred from P2 108 to FD 104 via P3 110. Figure 1 As shown in , in this example, the pixel 100 can be configured to receive backside illumination. However, alternatively, in some embodiments, frontside illumination can be implemented.

[0035] In some embodiments, FD 104 may include a capacitor. Thus, the transfer of charge into FD 104 may generate an analog voltage between FD 104 and ground. The analog voltage may represent the image signal captured by pixel 100. The analog voltage of FD 104 may be further accessed and read out from FD 104 (e.g., using pixel readout circuitry formed from one or more transistors) to generate an analog voltage at a pixel output line external to pixel 100. In some embodiments, the image sensor may include multiple pixel output lines for reading out FD voltages from pixels in different columns (e.g., one pixel output line for each column in a row-by-row readout). In some embodiments, the image sensor may further include one or more analog-to-digital circuits to convert the analog voltages of the pixel output lines into digital signals. In some embodiments, the image sensor may further include a transfer circuit that transmits the digital signal to an external component (e.g., an image signal processor (ISP)) for further digital processing to generate an image.

[0036] Figure 2 An example implementation of a control gate for a pixel of an image sensor according to some embodiments is shown. As shown on the left side of the figure, in some embodiments, vertical gate regions G1 112, G2 114, and G3 116 can individually include extensions to the surface of substrate 130. For example, G1 112, G2 114, and G3 116 can each have an L-shaped geometry, buried within substrate 130, and extending to the surface of substrate 130. In addition, GC1 122, GC2 124, and GC3 126 can be attached to G1 112, G2 114, and G3 116 at the surface of substrate 130. Alternatively, as shown in FIG. Figure 2 As shown on the right side of , in some embodiments, G1 112, G2 114 and G3 116 can each have a horizontal I-shaped geometry, buried within the substrate 130, and GC1 122, GC2 124 and GC3 126 can extend within the substrate 130 to be electrically connected to G1 112, G2 114 and G3 116.

[0037] Figure 3 An example implementation of a vertical gate region of a pixel of an image sensor according to some embodiments is shown. Figure 1 The vertical grid area is different, such as Figure 3As shown on the left side of FIG, in some embodiments, the vertical gate regions G1, G2, and G3 of the pixel (e.g., the third vertical gate region G3 316 visible in the top view) can individually have a C-shaped geometry, thereby only partially (not completely) surrounding the FD 304 (laterally) and the corresponding charge modulation region. Similarly, each vertical gate region G1, G2, and G3 can be electrically connected to an associated gate contact (e.g., GC1, GC2, and GC3) to receive a corresponding control signal. Alternatively, as shown in FIG. Figure 3 As shown in the middle of , in some embodiments, the vertical gate regions of the pixel (e.g., the third vertical gate region G3 356 visible in the top view) can individually have an I-shaped geometry that is arranged close to FD344 and the corresponding charge modulation region. Figure 3 The cross-sectional view on the right represents a cross-sectional view of the C-shaped pixel and the I-shaped pixel described above. As shown in the cross-sectional view, the PD 342 and the FD 304 (for a C-shaped pixel) or 344 (for an I-shaped pixel) can still be arranged vertically relative to each other. Similarly, the charge transfer region vertically located between the PD and the FD can include multiple charge modulation regions (e.g., P1 346, P2 348, and P3 350) that are vertically stacked on top of each other. However, unlike Figure 1 Different from the above, P1, P2, P3 and FD may have smaller cross-sectional areas and thus only partially, rather than completely, overlap with PD 342. In some embodiments, different doping concentrations may be introduced into P1, P2 and P3 of C-shaped and I-shaped pixels by implantation or other methods to generate sufficient capacitance and promote vertical charge transfer. Figures 1 to 3 The examples are provided for illustration purposes only as non-limiting examples. In some embodiments, the various regions of a pixel may be formed and arranged in various ways. For example, in some embodiments, for a given pixel, a combination of Figures 1 to 3 According to different embodiments, some of the vertical gate regions of a pixel may be formed in a ring shape, while other vertical gate regions may be formed in a C shape.

[0038] Figures 4A to 4D An example timing diagram of control signals and potential distributions for pixels of an image sensor according to some embodiments is shown to illustrate charge transfer. Figure 4A , the horizontal axis represents time, and the vertical axis represents voltage control signals 422, 424, and 426 applied to the gate regions G1 412, G2 414, and G3 416 of the pixel. Figure 4A As shown, the operation of the pixel may include three periods 432, 434 and 436. During the first period 432, all pixels of the image sensor (including Figures 4A to 4DFor example, all pixels may begin to be exposed to light at the same time at time 442 and end the exposure at the same time at time 444. By being exposed, all pixels may generate and accumulate charge in their corresponding PD regions during period 432. Figure 4B 432 represents the potential distribution of different regions of the pixel of the image sensor corresponding to the period 432. Figure 4B As shown, during period 432, active control voltages 422, 424, and 426 are not applied to G1 412, G2 414, and G3 416 (or are applied by negative voltages, if desired). For example, G1 412, G2 414, and G3 416 can be biased at zero voltage (or negative voltage, if desired). Therefore, this indicates that charge can accumulate inside PD 402, and P1 406, P2 408, and P3 410 can be turned off. In some embodiments, different regions of the pixel can have different doping types and / or doping concentrations. For example, in some embodiments, PD 402 can be an n-type region formed with one or more n-type dopants, P1 406, P2 408, and P3 410 can be p-type regions formed with one or more p-type dopants, P1, P2, P3 can also be n-type regions with different doping concentrations, and FD 404 can be an n-type region formed with one or more n-type dopants. Therefore, as Figure 4B As shown in FIG. 4 , the potential distributions of PD 402, P1 406, P2 408, P3 410, and FD 404 may have a multi-step shape. In addition, in this example, P1 406, P2 408, and P3 410 may also have the same doping concentration. Figure 4B In the embodiment, when turned off, P1 406, P2 408, and P3 410 can have the same potential. Alternatively, in some embodiments, P1 406, P2 408, and P3 410 can have different doping concentrations, which can result in different potentials between these regions (e.g., in a multi-step shape).

[0039] During the second period 434, after exposure of all pixels of the image sensor ends, all pixels may simultaneously transfer charge from their PD regions to their in-pixel memory regions (e.g., their P2 regions). Figure 4A As shown, active control voltages 422 and 424 may be applied to G1 412 and G2 414, while active control voltage 426 may not be applied to G3 410. In other words, P1 406 and P2 408 may be turned on, while P3 410 may remain off. Figure 4AAs shown, a positive voltage may be applied to G1 412 and G2 414, while G3 416 may remain biased at zero voltage (or a negative voltage, if desired). As described above, in some embodiments, the positive voltage may repel holes in the adjacent layers of P1 406 and P2 408 away from P1 406 and P2 408, thereby allowing at least some of the charge to be transferred from PD 402 to P1 406 and P2 408. Additionally, as described above, when turned off, P1 406 and P2 408 may have the same potential. Therefore, in some embodiments, different values of voltage may be applied to G1 412 and G2 414, resulting in a stepped potential distribution between P1 406 and P2 408, as shown in FIG. Figure 4C 434. Thus, charge may be transferred from PD 402 to P2 408 via P1 406, as shown in FIG. Figure 4C As described above, in some embodiments, P1 406 and P2 408 may have different doping concentrations and therefore different potentials when turned off. Therefore, in this case, the same value of voltage may be applied to G1 412 and G2 414 to still maintain Figure 4C A stepped potential distribution is shown between P1 406 and P2 408 such that charge is transferred from PD 402 to P2 408 via P1 406 .

[0040] As described, once the charge is transferred to P2 408, P2 408 can be used as an intra-pixel charge storage area to temporarily store the charge there until the pixel is read out. Again, as described above, the pixels of the image sensor can be read out individually at corresponding times. For example, in a row-by-row readout mode, pixels in the same row can be read out simultaneously, while pixels in the same column but different rows can be read out sequentially one after another. Figure 4A As shown, at time 446, the pixel may be selected for readout. During the third period 436, active control voltages 424 and 426 may be applied to G2 414 and G3 416, while active control voltage 422 may not be applied to G1 412. In other words, P2 408 and P3 410 may be turned on, while P1 406 may be turned off. For example, Figure 4A As shown, positive voltages may be applied to G2 414 and G3 416, while G1 412 may be biased at zero voltage (or a negative voltage, if desired). Similar to the above description, different voltages may be applied to G2 414 and G3 416, thereby creating a stepped potential distribution between P2 408 and P3 410 to transfer charge from P2 408 to FD 404 via P3 410, as shown. Figure 4D436. Alternatively, P2 408 and P3 410 may have different doping concentrations, and the same voltage value may be applied to G2 414 and G3 416 to still maintain a stepped potential distribution between P2 408 and P3 410 to transfer charge from P2 408 to FD 404 via P3 410. Figure 4A As shown, in some embodiments, active control voltage 424 can be continuously applied to G2 414 during periods 434 and 436. Alternatively, in some embodiments, when charge has been transferred from PD 402 to P2 408, active control voltage 424 can be removed at the end of period 436 and then reapplied at or near the beginning of period 436 to transfer charge from P2 408 to FD 404, as shown. Figure 4A As shown by the dotted line. Figures 4A to 4D Using appropriate control signals, the image sensor can be controlled to operate in global shutter mode. All pixels of the image sensor can be simultaneously exposed during the same time interval and transfer the accumulated charge from their PD regions to an intra-pixel memory region (e.g., their P2 regions). The pixels can then be read out individually (e.g., during their respective rolling readout intervals), where charge can be transferred from the P2 regions of each pixel to their FD regions.

[0041] Figure 5A A cross-sectional view of an example pixel and a block diagram of an image sensor including readout and image signal processing circuitry according to some embodiments are shown. Figure 5A As shown, pixel 500 can be one of the multiple pixels of image sensor 550. In addition, as described above, in some embodiments, the multiple pixels can be organized into a pixel array having one or more pixel rows and one or more pixel columns. Similar to the pixels described above, pixel 500 can include at least one PD, FD and a vertical charge transfer region located between PD and FD, the vertical charge transfer region including P1, P2 and P3. In addition, for the purpose of illustration, Figure 5A At least some of the transistors that may be used to form pixel readout circuitry to read out image signals from pixel 500 are shown. For example, in some embodiments, the pixel readout circuitry may include a reset transistor ("RG") 542, a source follower transistor ("SF") 544, and a read select transistor ("RS") 546. Figure 5A As shown, FD can be coupled to a reset voltage VDD via RG 542. In some embodiments, RG 542 can be selectively turned on to reset the voltage of FD to VDD. Figure 5AAs shown, the FD may also be coupled to the SF 544 and one or more RS 546. In some embodiments, the SF 544 and the RS 546 may be turned on to couple the FD to a pixel output line, through which the voltage of the FD may be accessed and read out. In some embodiments, the SF 544 may provide a voltage buffer for the voltage of the FD, and the RS 546 may be selectively turned on to couple the FD to the pixel output line for reading out the voltage of the FD. During readout, the SF 544 and the RS 546 may first be turned on to couple the FD to the pixel output line. Next, the RG 542 may be turned on to reset the voltage of the FD to the reset voltage VDD. The voltage of the FD may be sampled, for example, using an amplifier and an analog-to-digital circuit 554, as a first sample of the voltage of the FD. Next, the RG 542 may be turned off, and the charge transfer region between the PD and the FD may be turned on to transfer charge from the PD to the FD, as described above in Figure 1 4 . As described above, the transfer of charge can generate an analog voltage across the capacitance C of the FD. As described above, the voltage of the FD can be accessed and read out again at the pixel output line via SF 544 and RS 546. The voltage of the FD can be sampled, for example, using an amplifier and analog-to-digital circuit 554, as a second sample of the voltage of the FD. The difference between the first sample and the second sample can be calculated to offset the reset voltage VDD, and the differential voltage can be determined as the final image signal from the pixel 500. The image signal can be further processed, for example, using a digital processing circuit 556. The image signal can be transmitted to an image signal processor (ISP) for processing to generate an image, for example, using a data transfer I / O circuit 558. In addition, as Figure 5A As shown, image sensor 550 may also include row logic and driver circuitry 552 and global logic and clock circuitry 560 to generate appropriate control signals for the multiple pixels of image sensor 550 .

[0042] Figure 5B Example control signals applied to different components of multiple pixels of image sensor 550 are shown, according to some embodiments. Figure 5B Shown above about Figures 4A to 4D Describes similar information, but for multiple pixels instead of a single pixel. For example, Figure 5B As shown, the control signals shown here include control signals applied to pixels of different rows (e.g., row 0, row 1, row 2, ..., row n). In this example, the image sensor 550 can operate in a global shutter mode. For example, all pixels can be exposed during a first period (e.g., an exposure period (similar to Figures 4A to 4D432). In addition, all pixels may simultaneously transfer the charge of their PD regions to their intra-pixel memory regions (e.g., their P2 regions) during a second period (e.g., a global shutter period (similar to period 434)). Furthermore, the pixels of the image sensor may be individually read out at corresponding times during a third period (e.g., a rolling readout period (similar to period 436)). Similar to the above description of Figures 4A to 4B As described in Figure 5B As shown, during the first period, no active control voltage may be applied to the control gates of the pixels of the image sensor 550, and thus all gates may be turned off so that the pixels may accumulate charge in their respective PD regions. Figure 4A and Figure 4C As described in Figure 5B As shown, during the second period, active control voltages may be applied to the control gates G1 and G2 of the pixels of the image sensor 550, and thus all pixels may simultaneously transfer charge from their corresponding PD regions to the P2 region via the P1 region. Figure 4A and Figure 4D As described in Figure 5B As shown, during the third period, active control voltages may be applied to the control gates G2 and G3 of the pixels of the image sensor 550 at the corresponding readout times, and thus the corresponding pixels may transfer charge from their corresponding P2 regions to the FD region via the P2 region. Figure 5A As described in , different control signals may be applied to transistors of corresponding pixels (eg, RST transistor and RS transistor) to select and read out corresponding pixels, such as Figure 5B In addition, Figure 5B As shown, these transistor control signals can be applied to pixels in different rows at different times to represent a rolling readout operation. For example, control signals can be applied to RSG[0] and RS[0] of pixels in row 0 before control signals are applied to RSG[1] and RS[1] of pixels in row 1, which means that pixels in row 0 can be read before pixels in row 1. As described above, during the second period, charge can be transferred from the PD region of all pixels to the P2 region simultaneously. However, pixels in different rows can be read out at different times. Therefore, the P2 region can act as an intra-pixel charge storage region to temporarily store the charge of each individual pixel.

[0043] Figure 6 1 shows a top view and a cross-sectional view of another example pixel of an image sensor according to some embodiments. Figure 6As shown, in some embodiments, the gate regions G1 612, G2 614, and G3 616 of the pixel 600 can be arranged in a hexagonal shape. In addition, G1 612, G2 614, and G3 616 can each be electrically connected to a gate contact (e.g., GC1 622, GC2 624, and GFC3 626). In addition, unlike the above-described pixels, in Figure 6 , GC1 622, GC2 624, and GFC3 626 may not necessarily overlap with each other. Instead, they may be placed around the perimeter of the hexagonal shape, wherein the gate region of each charge modulation region may include a first portion of the gate region connected to the first portion of the gate contact and a second portion of the gate region connected to the second portion of the gate contact, with each pair located at one of two opposite sides of the corresponding charge modulation region. For example, as shown in the cross-sectional view along AA', G1 612 of P1 606 may include a first G1 portion on the left side of P1 606 and a second G1 portion on the right side of the P1. The left G1 portion may be electrically connected to the first GC portion 622, and the right G1 portion may be electrically connected to the second GC portion 622, and the first GC portion and the second GC portion may be electrically connected to each other. In addition, as shown in FIG. Figure 6 As shown, in some embodiments, G1 612, G2 614, and G3 616 can be buried at different depths inside the substrate 630. For example, G1 612 can be buried at the deepest depth closer to the PD 602, G3 616 can be buried at the shallowest depth closer to the surface of the substrate 630, and G2 614 can be buried in the middle.

[0044] Figure 7 An example isolation structure for a pixel of an image sensor according to some embodiments is shown. The figure on the left shows a partial deep trench isolation (DTI) for a pixel according to some embodiments. As shown, in some embodiments, the DTI may include a region 732 formed using polysilicon or a metal material. In some embodiments, region 732 may be formed in a trench (filled with polysilicon or a metal material) isolated from substrate 730 by a dielectric material 750, and the trench may surround the PD region of the pixel. In some embodiments, region 732 may be biased to produce a passivation on the trench surface to isolate the pixel from other pixels next to it. Optionally, in some embodiments, the trench may be filled with a high-k dielectric material. In this case, region 732 may not necessarily need to be biased. The figure on the right shows an alternative isolation structure for the pixel, namely deep doped well isolation. As shown in the figure, the trench for region 752 may extend all the way to the surface of the pixel. The trench may be implanted with dopants to produce electrical isolation between pixels.

[0045] Figure 8 1 shows example segmented pixels for autofocus applications according to some embodiments. Figure 8 As shown, pixel 800 may include at least two PDs (left PD 802 and right PD 862). In some embodiments, PD 802 and PD 862 may be isolated from each other using one or more isolation structures. For example, Figure 8 As shown, in some embodiments, two PDs can be isolated by a partial deep trench isolation (DTI) region 832 located between PD 802 and PD 862 as described above. In some embodiments, each PD can be associated with an FD and a vertical charge transfer region (including P1, P2, and P3). For example, the left PD 802 can be associated with the left P1 (L-P1), the left P2 (L-P2), the left P3 (L-P3), and the left FD (L-FD), while the right PD 862 can be associated with the right P1 (R-P1), the right P2 (R-P2), the right P3 (R-P3), and the right FD (R-FD), similar to the above description in FIG. Figures 1 to 7 . Furthermore, the L-FD and R-FD can be electrically connected together so that image signals for the L-FD and R-FD can be read out to a pixel output line using the same pixel readout circuitry. During operation, gate regions LG1 (for L-P1) and RG1 (for R-P1) can receive control signals simultaneously or approximately simultaneously, and LG2 (for L-P2) and RG2 (R-P2) can receive control signals simultaneously or approximately simultaneously, so that charge can be transferred from PD 862 to the L-FD simultaneously with the charge transfer from PD 802 to the R-FD. However, gate regions LG3 (for L-P3) and RG3 (for R-P3) can receive control signals at different times, so that charge can be transferred from L-P2 to the L-FD and from R-P3 to the R-FD at different times. In other words, image signals for L-PD 802 and R-PD 862 of pixel 800 can be read out sequentially. In some embodiments, pixel 800 can be used for autofocus in an image capture device. For example, when light reaches pixel 800 at an angle, the amount of light captured by L-PD 802 and R-PD 862 may differ. Consequently, the two PDs may accumulate different amounts of charge, resulting in different output voltages during readout. In some embodiments, the difference between the output voltages from L-PD 802 and R-PD 862 can be used to adjust and / or perform autofocus of the image capture device.

[0046] Figure 9 1 shows a top view and a cross-sectional view of another example pixel of an image sensor according to some embodiments. Figure 9 As shown, in some embodiments, the vertical gate and DTI isolation of a pixel can be formed in the same trench. For example, in some embodiments, the gate regions (G1 912, G2 914, and G3 916) of pixel 900 can be formed in the same trench 930 within the substrate of pixel 900, as shown in FIG. Figure 9 G1 912, G2 914, and G3 916 can each receive a control signal (e.g., a control voltage) through an associated gate contact (e.g., GC1 922, GC2 924, and GC3 926). Figures 1 to 8 , pixel 900 may include PD 902, FD 904, and a vertical charge transfer region located between PD 902 and FD 904, and the vertical charge region may include multiple charge modulation regions P1 906, P2 908, and P3 910. In some implementations, pixel 900 may be operated in a global shutter mode similar to the pixels described above, where P2 908 may serve as an in-pixel charge storage region of pixel 900.

[0047] Figure 10 1 shows a top view and a cross-sectional view of another example pixel of an image sensor according to some embodiments. Figure 10 As shown, the structure of pixel 1000 can be similar to that of pixel 900. However, the P1, P2, P3, and FD regions of pixel 1000 can have smaller cross-sectional areas so that these regions only partially, rather than completely, overlap with the PD region below the PD region. In some embodiments, different doping concentrations can be introduced into P1, P2, and P3 by injection or other methods to generate sufficient capacitance and promote vertical charge transfer. Figure 10 As shown, in some embodiments, there can be a set of gate regions for adjacent pixels (not shown) on the right side of pixel 1000, which are disposed in trenches adjacent to pixel 1000. Thus, in some embodiments, there can be an isolation region 1032 between the gate regions (G1, G2, and G3) of pixel 1000 and the gate regions of another pixel. In some embodiments, isolation region 1032 can be implanted with dopants to provide isolation.

[0048] Figure 11 FIG10 illustrates a top view and a cross-sectional view of another example pixel of an image sensor according to some embodiments. In this example, FD 1104, P1 1106, P2 1108, and P3 1110 can be moved to the corners of the pixel (e.g., for PD 1102), for example, to the right corner of the pixel, as shown in FIG10. Figure 111108, thereby improving the PLS performance. Alternatively, the charge of PD 1102 may be directed to be correctly transferred to FD 1104 via P1 1106, P2 1108, and P3 1110, since these regions correspond to PD 1102, as shown in FIG. Figure 11 Similarly, for the pixel on the right (e.g., for PD 1162), the pixel may further include a doping region 1172 to prevent the charge from PD 1162 from being erroneously transferred from PD 1162 to P1 1106, P2 1108, P3 1110, and FD 1104. Alternatively, the charge of PD 1162 may be transferred to FD via P1, P2, and P3 at the right corner of the right pixel, as shown in FIG. Figure 11 In some embodiments, the doping type of doped regions 1152 and 1172 can be opposite to the doping type of PD 1102 and PD 1162 .

[0049] Figure 12 is a block diagram of an example image capture device according to some embodiments. Figure 12 As shown, in some embodiments, the image capture device 1200 may include one or more lenses 1202 and an image sensor 1204. In some embodiments, the image capture device 1200 may capture light from the environment, and the light may pass through the lens 1202 to reach the image sensor 1204. In some embodiments, the image sensor 1204 may include a plurality of pixels similar to the pixels described above, wherein each pixel may include an intra-pixel charge storage region for global shutter operation. Additionally, in some embodiments, the image capture device 1200 may include an infrared cut filter (IRCF) 1206 placed between the lens 1202 and the image sensor 1204 to block infrared light from reaching the image sensor 1204. Figure 12As shown, in this example, the image sensor 1204 and IRCF 1206 can be mounted on a substrate 1208, and the image sensor 1204 can be placed upside down to receive backside illumination. However, as described above, alternatively, in some embodiments, frontside illumination can be implemented on the image sensor 1204 having the pixels described above. In some embodiments, the image sensor 204 can be a CMOS image sensor.

[0050] Figure 13 is a flow chart illustrating an example method for operating an image sensor in global shutter mode using an in-pixel charge storage region according to some embodiments. Figure 13 As shown, in some embodiments, an image sensor including a plurality of pixels may be provided, as indicated by block 1302. In some embodiments, each pixel of the image sensor may include: (a) a photodiode including a charge accumulation region (PD); (b) a floating diffusion region (FD); and (c) a gate transfer region vertically located between the PD and the FD. In addition, in some embodiments, the vertical gate transfer region may further include (i) a plurality of charge modulation regions (P1, P2, and P3) vertically formed between the PD and the FD; and (ii) a control gate for the corresponding charge modulation region. As shown Figure 13 As shown, in some embodiments, for a particular one of the pixels, when exposed to light during a first period of time, the pixel can accumulate charge in its PD, as indicated by block 1304. As described above, in some embodiments, the image sensor can operate in a global shutter mode, and thus all pixels including the particular pixel can begin and end exposure simultaneously during the first period of time. Figure 13 As shown, in some embodiments, for a particular pixel, at least some of the charge of PD may be transferred from PD to P2 via P1 during the second time period, as indicated by block 1306. As described above, in some embodiments, the transfer of charge from PD to P2 may be a global operation for all pixels of the image sensor. In other words, all pixels, including the particular pixel, may simultaneously transfer their charge from PD to P2 during the second time period. Additionally, as described above, in some embodiments, P2 may act as an intra-pixel charge storage region for the particular pixel. Thus, once charge is transferred to P2, the charge may be temporarily stored there until the particular pixel is read out. Figure 13As shown, in some embodiments, the charge transferred to P2 can be further transferred from P2 to FD via P1 during a third period, as indicated by block 1308. As described above, even in global shutter mode, it may not be necessary to read out each pixel of the image sensor simultaneously. Instead, the pixels can be read out sequentially, row by row. Therefore, for a particular pixel, the third period for transferring charge from P2 to FD may be the same as or different from the readout period for another pixel.

[0051] Figure 14 A schematic representation of an example device 1400 that may include an image capture device (e.g., a camera) having an image sensor according to some embodiments is illustrated, the image sensor including pixels having intra-pixel charge storage regions as described above. In some embodiments, device 1400 may be a mobile device and / or a multifunction device. In various embodiments, device 1400 may be any of various types of devices, including, but not limited to, a personal computer system, a desktop computer, a laptop computer, a notebook computer, a tablet computer, an all-in-one computer, a tablet or netbook computer, a mainframe computer system, a handheld computer, a workstation, a network computer, a camera, a set-top box, a mobile device, an augmented reality (AR) and / or virtual reality (VR) head-mounted device, a consumer device, a video game controller, a handheld video game device, an application server, a storage device, a television, a video recording device, a peripheral device (such as a switch, a modem, a router), or generally any type of computing or electronic device.

[0052] In some embodiments, device 1400 may include a display system 1402 (e.g., including a display and / or a touch-sensitive surface) and / or one or more cameras 1404. In some non-limiting embodiments, display system 1402 and / or one or more forward-facing cameras 1404a may be disposed on the front side of device 1400, e.g., Figure 14 Additionally or alternatively, one or more rear-facing cameras 1404b may be disposed at the rear side of the device 1400. In some embodiments including multiple cameras 1404, some or all of the cameras may be identical or similar to one another. Additionally or alternatively, some or all of the cameras may be different from one another. In various embodiments, the location and / or arrangement of the cameras 1404 may differ from one another. Figure 14 Those cameras indicated in .

[0053] Among other things, the device 1400 may include a memory 1406 (e.g., including an operating system 1408 and / or application / program instructions 1410), one or more processors and / or controllers 1412 (e.g., including a CPU, a memory controller, a display controller, and / or a camera controller, etc.), and / or one or more sensors 1416 (e.g., an orientation sensor, a proximity sensor, and / or a position sensor, etc.). In some embodiments, the device 1400 may communicate with one or more other devices and / or services such as a computing device 1418, a cloud service 1420, etc. via one or more networks 1422. For example, the device 1400 may include a network interface (e.g., the network interface 810) that enables the device 1400 to transmit data to the network 1422 and to receive data from the network. Additionally or alternatively, the device 1400 may be capable of communicating with other devices via wireless communication using any of a variety of communication standards, protocols, and / or technologies.

[0054] Figure 15 A schematic block diagram illustrates an example computing device (referred to as computer system 1500) that may include or host an image capture device (e.g., a camera) having an image sensor that includes pixels having the intra-pixel charge storage regions described above, according to some embodiments. Furthermore, computer system 1500 may implement methods for controlling the operation of the camera and / or for performing image processing on images captured using the camera. In some embodiments, device 1400 (referred to herein as Figure 14 The computer system 1500 may include some or all of the functional components of the computer system 1500 described herein.

[0055] The computer system 1500 can be configured to perform any or all of the embodiments described above. In various embodiments, the computer system 1500 can be any of various types of devices, including, but not limited to, a personal computer system, a desktop computer, a laptop computer, a notebook computer, a tablet computer, an all-in-one computer, a tablet or netbook computer, a mainframe computer system, a handheld computer, a workstation, a network computer, a camera, a set-top box, a mobile device, an augmented reality (AR) and / or virtual reality (VR) headset, a consumer device, a video game controller, a handheld video game device, an application server, a storage device, a television, a video recording device, a peripheral device (such as a switch, a modem, a router), or generally any type of computing or electronic device.

[0056] In the illustrated embodiment, computer system 1500 includes one or more processors 1502 coupled to system memory 1504 via an input / output (I / O) interface 1506. Computer system 1500 also includes one or more cameras 1508 coupled to I / O interface 1506. Computer system 1500 also includes a network interface 1510 coupled to I / O interface 1506, as well as one or more input / output devices 1512 such as a cursor control device 1514, a keyboard 1516, and a display 1518. In some cases, it is contemplated that embodiments may be implemented using a single instance of computer system 1500, while in other embodiments, multiple such systems or multiple nodes comprising computer system 1500 may be configured to host different portions or instances of embodiments. For example, in one embodiment, some elements may be implemented via one or more nodes of computer system 1500 that are different from those nodes that implement other elements.

[0057] In various embodiments, computer system 1500 may be a uniprocessor system including one processor 1502 or a multiprocessor system including several processors 1502 (e.g., two, four, eight, or another suitable number). Processor 1502 may be any suitable processor capable of executing instructions. For example, in various embodiments, processor 1502 may be a general-purpose processor or an embedded processor that implements any of a variety of instruction set architectures (ISAs) such as the x86, PowerPC, SPARC, or MIPS ISAs, or any other suitable ISAs. Furthermore, in some embodiments, one or more of processors 1502 may include additional types of processors, such as a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), or the like. In a multiprocessor system, each processor in processor 1502 may, but need not, implement the same ISA. In some embodiments, computer system 1500 may be implemented as a system on a chip (SoC). For example, in some embodiments, processor 1502, memory 1504, I / O interface 1506 (e.g., architecture), etc. may be implemented in a single SoC comprising multiple components integrated into a single chip. For example, a SoC may include multiple CPU cores, a multi-core GPU, a multi-core neural engine, caches, one or more memories, etc., integrated into a single chip. In some embodiments, a SoC embodiment may implement a reduced instruction set computing (RISC) architecture or any other suitable architecture.

[0058] System memory 1504 can be configured to store program instructions 1520 accessible to processor 1502. In various embodiments, system memory 1504 can be implemented using any suitable memory technology, such as static random access memory (SRAM), synchronous dynamic RAM (SDRAM), non-volatile / flash-type memory, or any other type of memory. Additionally, existing camera control data 1522 of memory 1504 can include any of the information or data structures to implement the above-described techniques. In some embodiments, program instructions 1520 and / or data 1522 can be received, sent, or stored on different types of computer-accessible media separate from system memory 1504 or computer system 1500, or on similar media. In various embodiments, some or all of the functionality described herein can be implemented via such a computer system 1500.

[0059] In one embodiment, I / O interface 1506 can be configured to coordinate I / O traffic between processor 1502, system memory 1504, and any peripheral devices in the device (including network interface 1510 or other peripheral device interfaces, such as input / output devices 1512). In some embodiments, I / O interface 1506 can perform any necessary protocol, timing, or other data conversion to convert data signals from one component (e.g., system memory 1504) into a format suitable for use by another component (e.g., processor 1502). In some embodiments, I / O interface 1506 can include support for devices attached, for example, via various types of peripheral buses (such as variations of the Peripheral Component Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard). In some embodiments, the functionality of I / O interface 1506 can be divided into two or more separate components, such as a north bridge and a south bridge, for example. Furthermore, in some embodiments, some or all of the functionality of I / O interface 1506 (such as the interface to system memory 1504) can be incorporated directly into processor 1502.

[0060] The network interface 1510 can be configured to allow data to be exchanged between the computer system 1500 and other devices (e.g., carriers or proxy devices) attached to the network 1524, or between nodes of the computer system 1500. In various embodiments, the network 1524 can include one or more networks, including but not limited to a local area network (LAN) (e.g., an Ethernet or an intranet), a wide area network (WAN) (e.g., the Internet), a wireless data network, some other electronic data network, or some combination thereof. In various embodiments, the network interface 1510 can support communication via a wired or wireless general data network (such as any suitable type of Ethernet network); communication via a telecommunications / telephone network (such as an analog voice network or a digital fiber optic communication network); communication via a storage area network (such as a Fibre Channel SAN), or communication via any other suitable type of network and / or protocol.

[0061] In some embodiments, input / output devices 1512 may include one or more display terminals, keyboards, keypads, trackpads, scanning devices, voice or optical recognition devices, or any other device suitable for inputting or accessing data by one or more computer systems 1500. Multiple input / output devices 1512 may be present in computer system 1500 or may be distributed across various nodes of computer system 1500. In some embodiments, similar input / output devices may be separate from computer system 1500 and may interact with one or more nodes of computer system 1500 through a wired or wireless connection, such as through network interface 1510.

[0062] Those skilled in the art will appreciate that computer system 1500 is merely illustrative, and is not intended to limit the scope of the embodiments. Specifically, computer system and equipment may include any combination of hardware or software that can perform the functions indicated, including computers, network equipment, internet equipment, personal digital assistants, wireless telephones, pagers, etc. Computer system 1500 may also be connected to other devices not illustrated, or may alternatively be operated as an independent system. In addition, the functions provided by the illustrated components may be combined in fewer components or distributed in additional components in some embodiments. Similarly, in some embodiments, the functions of some components in the illustrated components may not be provided, and / or other additional functions may be available.

[0063] Those skilled in the art will also recognize that, although various items are illustrated as being stored in memory or on storage devices during use, for the purpose of memory management and data integrity, these items or parts thereof can be transferred between memory and other storage devices. Alternatively, in other embodiments, some or all of these software components can be executed in a memory on another device and communicate with the illustrated computer system via inter-computer communication. Some or all of the system components or data structures can also be stored on a computer-accessible medium or portable article (e.g., as instructions or structured data) to be read by a suitable drive, various examples of which are described above. In some embodiments, instructions stored on a computer-accessible medium separate from computer system 1500 can be transferred to computer system 1500 via a transmission medium or signal (such as an electrical signal, electromagnetic signal, or digital signal transmitted via a communication medium such as a network and / or wireless link). Various embodiments may also include receiving, sending, or storing instructions and / or data implemented according to the above description on a computer-accessible medium. Generally speaking, computer-accessible media may include non-transitory computer-readable storage media or memory media, such as magnetic or optical media, for example, disks or DVD / CD-ROMs, volatile or non-volatile media, such as RAM (e.g., SDRAM, DDR, RDRAM, SRAM, etc.), ROM, etc. In some embodiments, computer-accessible media may include transmission media or signals, such as electrical signals, electromagnetic signals, or digital signals transmitted via a communication medium, such as a network and / or a wireless link.

[0064] In different embodiments, the methods described herein can be implemented in software, hardware, or a combination thereof. In addition, the order of the method's frames can be changed, and various elements can be added, reordered, combined, omitted, modified, etc. For those skilled in the art who benefit from this disclosure, it is obvious that various modifications and changes can be made. The various embodiments described herein are intended to be illustrative and not restrictive. Many variations, modifications, additions, and improvements are possible. Therefore, multiple examples can be provided for the components described herein as a single example. The boundaries between the various components, operations, and data repositories are arbitrary to a certain extent, and specific operations are shown in the context of a specific example configuration. Other allocations of functions are contemplated and may fall within the scope of the appended claims. Finally, the structure and function presented as discrete components in the example configuration may be implemented as a combined structure or component. These and other variations, modifications, additions, and improvements may fall within the scope of the embodiments defined in the following claims.

Claims

1. An image sensor, comprising: a plurality of pixels, wherein each of the pixels comprises: at least one photodiode, the at least one photodiode comprising a charge accumulation region; at least one floating diffusion region; and at least one charge transfer region formed vertically between the charge accumulation region and the floating diffusion region, wherein the charge transfer region comprises a first charge modulation region, a second charge modulation region and a third charge modulation region, and The pixels are controlled as follows: accumulating charge in the charge accumulation region based on light exposure; transferring at least some of the charges from the charge accumulation region to the second charge modulation region via the first charge modulation region; and At least some of the charge is transferred from the second charge modulation region to the floating diffusion region via the third charge modulation region.

2. The image sensor according to claim 1, wherein: The first charge modulation region is formed above the charge accumulation region of the photodiode and at least partially overlaps the charge accumulation region; The second charge modulation region is formed above the first charge modulation region and at least partially overlaps the first charge modulation region; The third charge modulation region is formed above the second charge modulation region and at least partially overlaps the second charge modulation region; and The floating diffusion region is formed above the third charge modulation region and at least partially overlaps the third charge modulation region.

3. The image sensor according to claim 1, wherein: the first charge modulation region and the second charge modulation region being turned on to transfer the at least some charge from the charge accumulation region to the second charge modulation region via the first charge modulation region; and The second charge modulation region and the third charge modulation region are turned on to transfer the at least some charges from the second charge modulation region to the floating diffusion region via the third charge modulation region.

4. The image sensor according to claim 3, wherein: the first, second, and third charge modulation regions being turned on in response to respective positive voltages applied to respective gate control regions of the first, second, and third charge modulation regions; and The first, second, and third charge modulation regions are turned off in response to removing the respective positive voltages from respective gate control regions of the first, second, and third charge modulation regions.

5. The image sensor according to claim 4, wherein: The first charge modulation region, the second charge modulation region, and the third charge modulation region have the same concentration of dopants, such that: Respective positive voltages of different values are applied to respective gate control regions of the first charge modulation region and the second charge modulation region to generate a step potential distribution between the first charge modulation region and the second charge modulation region to transfer the at least some charges from the charge accumulation region to the second charge modulation region via the first charge modulation region; and Corresponding positive voltages of different values are applied to the corresponding gate control regions of the second charge modulation region and the third charge modulation region to generate a step potential distribution between the second charge modulation region and the third charge modulation region to transfer at least some of the charges from the second charge modulation region to the floating diffusion region via the third charge modulation region.

6. The image sensor according to claim 4, wherein: The first charge modulation region, the second charge modulation region, and the third charge modulation region have different concentrations of dopants to generate a step-type potential distribution between the first charge modulation region, the second charge modulation region, and the third charge modulation region, such that: Respective positive voltages of the same value are applied to the respective gate control regions of the first charge modulation region and the second charge modulation region to maintain the stepped potential distribution between the first charge modulation region and the second charge modulation region to transfer the at least some charges from the charge accumulation region to the second charge modulation region via the first charge modulation region; and Corresponding positive voltages of the same value are applied to the corresponding gate control regions of the second charge modulation region and the third charge modulation region to maintain the stepped potential distribution between the second charge modulation region and the third charge modulation region so as to transfer at least some of the charges from the second charge modulation region to the floating diffusion region via the third charge modulation region.

7. The image sensor of claim 4, wherein the corresponding gate control regions of the first charge modulation region, the second charge modulation region, and the third charge modulation region are formed in a shape that at least partially surrounds a lateral periphery of the floating diffusion region.

8. The image sensor according to claim 1, wherein: The plurality of pixels are organized into a pixel array to divide the pixels into a plurality of rows and a plurality of columns; and The plurality of pixels are controlled to operate in a global shutter mode such that: pixels in the plurality of rows and the plurality of columns simultaneously accumulate charge in their respective charge accumulation regions based on light exposure; pixels in the plurality of rows and the plurality of columns simultaneously transferring at least some of the charges from their respective charge accumulation regions to their respective second charge modulation regions via their respective first charge modulation regions; pixels in the same row simultaneously transfer the at least some of the charge from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions; and Pixels in different rows sequentially transfer the at least some of the charges from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions in the order of the rows. 9 . The image sensor according to claim 1 , wherein the charge accumulation region is an n-type region, the first charge modulation region, the second charge modulation region, and the third charge modulation region are p-type regions, and the floating diffusion region is an n-type region.

10. The image sensor of claim 1 , wherein the pixel further comprises a pixel readout circuit, the pixel readout circuit comprising at least one of: a reset switch for resetting the voltage of the floating diffusion region to a reset voltage, a source follower switch for buffering the voltage of the floating diffusion region, or a pixel selection switch for selectively coupling the floating diffusion region to a pixel output line for reading out the voltage of the floating diffusion region.

11. A system, comprising: one or more lenses; An image sensor, the image sensor comprising: a plurality of pixels configured to receive light passing through the lens, wherein each of the pixels comprises: at least one photodiode, the at least one photodiode comprising a charge accumulation region; at least one floating diffusion region; and at least one charge transfer region formed vertically between the charge accumulation region and the floating diffusion region, wherein the charge transfer region comprises a first charge modulation region, a second charge modulation region and a third charge modulation region, and The pixels are controlled as follows: accumulating charge in the charge accumulation region based on light exposure; transferring at least some of the charges from the charge accumulation region to the second charge modulation region via the first charge modulation region; and transferring the at least some of the charge from the second charge modulation region to the floating diffusion region via the third charge modulation region to generate an image signal at the floating diffusion region; and A circuit is provided for reading out image signals from the plurality of pixels.

12. The system of claim 11, wherein: The first charge modulation region is formed above the charge accumulation region of the photodiode and at least partially overlaps the charge accumulation region; The second charge modulation region is formed above the first charge modulation region and at least partially overlaps the first charge modulation region; The third charge modulation region is formed above the second charge modulation region and at least partially overlaps the second charge modulation region; and The floating diffusion region is formed above the third charge modulation region and at least partially overlaps the third charge modulation region.

13. The system of claim 1 , wherein: the first charge modulation region and the second charge modulation region being turned on to transfer the at least some charge from the charge accumulation region to the second charge modulation region via the first charge modulation region; and The second charge modulation region and the third charge modulation region are turned on to transfer the at least some charges from the second charge modulation region to the floating diffusion region via the third charge modulation region.

14. The system of claim 13, wherein: the first, second, and third charge modulation regions being turned on in response to respective positive voltages applied to respective gate control regions of the first, second, and third charge modulation regions; and The first, second, and third charge modulation regions are turned off in response to removing the respective positive voltages from respective gate control regions of the first, second, and third charge modulation regions.

15. The system of claim 14, wherein: The first charge modulation region, the second charge modulation region, and the third charge modulation region have the same concentration of dopants, such that: Respective positive voltages of different values are applied to respective gate control regions of the first charge modulation region and the second charge modulation region to generate a step potential distribution between the first charge modulation region and the second charge modulation region to transfer the at least some charges from the charge accumulation region to the second charge modulation region via the first charge modulation region; and Corresponding positive voltages of different values are applied to the corresponding gate control regions of the second charge modulation region and the third charge modulation region to generate a step potential distribution between the second charge modulation region and the third charge modulation region to transfer at least some of the charges from the second charge modulation region to the floating diffusion region via the third charge modulation region.

16. The system of claim 14, wherein: The first charge modulation region, the second charge modulation region, and the third charge modulation region have different concentrations of dopants to generate a step-type potential distribution between the first charge modulation region, the second charge modulation region, and the third charge modulation region, such that: Respective positive voltages of the same value are applied to the respective gate control regions of the first charge modulation region and the second charge modulation region to maintain the stepped potential distribution between the first charge modulation region and the second charge modulation region to transfer the at least some charges from the charge accumulation region to the second charge modulation region via the first charge modulation region; and Corresponding positive voltages of the same value are applied to the corresponding gate control regions of the second charge modulation region and the third charge modulation region to maintain the stepped potential distribution between the second charge modulation region and the third charge modulation region so as to transfer at least some of the charges from the second charge modulation region to the floating diffusion region via the third charge modulation region.

17. The system of claim 11, wherein: The plurality of pixels are organized into a pixel array to divide the pixels into a plurality of rows and a plurality of columns; and The plurality of pixels are controlled to operate in a global shutter mode such that: pixels in the plurality of rows and the plurality of columns simultaneously accumulate charge in their respective charge accumulation regions based on light exposure; pixels in the plurality of rows and the plurality of columns simultaneously transferring at least some of the charges from their respective charge accumulation regions to their respective second charge modulation regions via their respective first charge modulation regions; pixels in the same row simultaneously transfer the at least some of the charge from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions; and Pixels in different rows sequentially transfer the at least some of the charges from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions in the order of the rows.

18. A device comprising: An image capturing device, the image capturing device comprising: one or more lenses; An image sensor, the image sensor comprising: a plurality of pixels configured to receive light passing through the lens, wherein each of the pixels comprises: at least one photodiode, the at least one photodiode comprising a charge accumulation region; at least one floating diffusion region; and at least one charge transfer region formed vertically between the charge accumulation region and the floating diffusion region, wherein the charge transfer region comprises a first charge modulation region, a second charge modulation region and a third charge modulation region, and The pixels are controlled as follows: accumulating charge in the charge accumulation region based on light exposure; transferring at least some of the charges from the charge accumulation region to the second charge modulation region via the first charge modulation region; and transferring the at least some of the charge from the second charge modulation region to the floating diffusion region via the third charge modulation region to generate an image signal at the floating diffusion region; and circuitry for reading out image signals from the plurality of pixels; and An image signal processor is configured to process the image signal to generate one or more images.

19. The apparatus of claim 18, wherein: The first charge modulation region is formed above the charge accumulation region of the photodiode and at least partially overlaps the charge accumulation region; The second charge modulation region is formed above the first charge modulation region and at least partially overlaps the first charge modulation region; The third charge modulation region is formed above the second charge modulation region and at least partially overlaps the second charge modulation region; and The floating diffusion region is formed above the third charge modulation region and at least partially overlaps the third charge modulation region.

20. The apparatus of claim 18, wherein: The plurality of pixels are organized into a pixel array to divide the pixels into a plurality of rows and a plurality of columns; and The plurality of pixels are controlled to operate in a global shutter mode such that: pixels in the plurality of rows and the plurality of columns simultaneously accumulate charge in their respective charge accumulation regions based on light exposure; pixels in the plurality of rows and the plurality of columns simultaneously transferring at least some of the charges from their respective charge accumulation regions to their respective second charge modulation regions via their respective first charge modulation regions; pixels in the same row simultaneously transfer the at least some of the charge from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions; and Pixels in different rows sequentially transfer the at least some of the charges from their respective second charge modulation regions to their respective floating diffusion regions via their respective third charge modulation regions in the order of the rows.

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