Process parameter determination method and system for improving ultra-thin wafer scribing tape

Abstract

The present invention relates to the field of wafer processing and production technology, and in particular to a method and system for determining process parameters for improving ultra-thin wafer scribing tape, comprising: performing characteristic analysis on an ultra-thin wafer to be scribed to obtain wafer characteristic data; inputting the wafer characteristic data into a wafer scribing analysis model to obtain at least two scribing stages; for each scribing stage, using the corresponding target requirements and wafer characteristic data as mapping conditions, screening a pre-built scribing tool library to obtain the optimal tool corresponding to the scribing stage; and determining the optimal scribing process parameters corresponding to the scribing stage by considering the interaction between the tool parameters corresponding to the optimal tool and the wafer characteristic data. This method reduces heat accumulation during the cutting process, reduces tape residue, and improves product yield.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer processing and production, and in particular to a method and system for determining process parameters for improving ultra-thin wafer dicing tape. Background Art

[0002] With the continuous advancement of semiconductor technology, the wafer process has an increasing demand for feature size reduction and full-size 3D integration, and the wafer thickness is gradually developing towards ultra-thinness within 50 microns; this trend has put forward higher requirements for wafer thinning, dicing and back-end metallization processes; in the wafer dicing process, the problem of adhesive wire residue has become one of the main factors affecting product quality and yield; adhesive wire residue refers to the thin fibers or small particles left on the edge of the wafer or the cutting line during the wafer cutting process; these adhesive wires not only affect the quality and processing efficiency of the wafer, but may also cause damage to the cutting blades and equipment, thereby affecting the reliability of the product.

[0003] Existing processes often use fixed parameters such as spindle speed, blade speed and cutting depth, and do not dynamically adjust according to wafer characteristics; for example, when the spindle speed is too high or the cutting depth is unreasonable, it is easy to cause cutting heat accumulation, exacerbating the generation of rubber wire; at the same time, existing processes also regard scribing as a single process, without considering the differentiated needs of different cutting stages; in fact, ultra-thin wafer scribing requires the release of internal stress before completing material separation, and the existing process does not match the tools and parameters of each stage in stages, resulting in stress concentration and cutting defects, making it difficult to efficiently match the complex needs of ultra-thin wafers. Summary of the Invention

[0004] The present invention provides a method and system for determining process parameters for improving the ultra-thin wafer dicing tape, which can reduce heat accumulation during the cutting process, reduce tape residue, and improve product yield, and can effectively solve the problems in the background technology.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a method for determining process parameters for improving ultra-thin wafer scribing tape, comprising:

[0006] Perform characteristic analysis on ultra-thin wafers to be diced to obtain wafer characteristic data;

[0007] Inputting the wafer characteristic data into a wafer scribing analysis model to obtain at least two scribing stages;

[0008] For each dicing stage, the corresponding target requirements and the wafer characteristic data are used as mapping conditions, and a pre-built dicing tool library is screened to obtain the optimal tool corresponding to the dicing stage;

[0009] The interaction between the tool parameters corresponding to the optimal tool and the wafer characteristic data is considered to determine the optimal scribing process parameters corresponding to the scribing stage.

[0010] In combination with the first aspect, in a possible design, the scribing stage includes at least a stress relief stage and a separation stage.

[0011] In combination with the first aspect, in one possible design, the dicing process parameters include at least the spindle speed, the dicing blade height and the cutting speed.

[0012] In combination with the first aspect, in a possible design, the wafer characteristic data includes at least one of geometric characteristic parameters, material mechanical characteristic parameters, internal stress state parameters, and surface quality characteristic parameters.

[0013] In combination with the first aspect, in a possible design, the geometric characteristic parameter includes at least one of wafer thickness, warpage, scribe line width, and edge flatness.

[0014] In combination with the first aspect, in a possible design, the material mechanical characteristic parameter includes at least one of silicon substrate hardness, elastic modulus, fracture toughness, and thermal conductivity.

[0015] In combination with the first aspect, in a possible design, the internal stress state parameter includes at least one of residual stress distribution, thermal stress coefficient, and stress gradient.

[0016] In combination with the first aspect, in one possible design, the wafer dicing analysis model calculates the cutting depth corresponding to the wafer in the stress relief stage according to the internal stress state parameters and material mechanical property parameters of the wafer. The calculation formula is:

[0017] ;

[0018] in, Indicates the cutting depth during the stress relief stage, which is used to release residual stress rather than complete separation; Represents the material constitutive coefficient, which is calibrated by experiments; represents fracture toughness; Indicates wafer thickness; represents the maximum residual tensile stress; represents the normalized reference stress, which is a material-related constant for silicon wafers. s ref =0.7 s y , s y is the yield strength.

[0019] In combination with the first aspect, in a possible design, the wafer scribing analysis model calculates the cutting depth corresponding to the separation stage based on the geometric characteristic parameters and the material mechanical characteristic parameters, and the calculation formula is:

[0020] ;

[0021] in, Indicates the cutting depth during the separation phase; Indicates wafer thickness; represents the surface compensation coefficient; Indicates surface roughness; represents the fracture extension coefficient; represents fracture toughness; Represents the elastic modulus.

[0022] In a second aspect, the present invention further provides a process parameter determination system for improving ultra-thin wafer scribing tape, comprising:

[0023] Wafer characteristic analysis module, used to analyze the characteristics of ultra-thin wafers to be diced and obtain wafer characteristic data;

[0024] a scribing stage division module, configured to input the wafer characteristic data into a wafer scribing analysis model to obtain at least two scribing stages;

[0025] A tool selection module is used to select the optimal tool for each scribing stage by using the target requirements and the wafer characteristic data as mapping conditions and screening the tool library in advance;

[0026] The process parameter optimization module is used to consider the interaction between the tool parameters corresponding to the optimal tool and the wafer characteristic data to determine the optimal dicing process parameters corresponding to the dicing stage.

[0027] The technical solution of the present invention can achieve the following technical effects:

[0028] The present invention dynamically analyzes the wafer characteristics and adjusts the process parameters according to the analysis results, so that the entire dicing process can be optimized according to the specific conditions of the wafer, the flexibility and applicability of the process are improved, and it can better cope with different batches and types of wafers; the dicing process is divided into a stress relief stage and a separation stage, and refined tool and parameter selection is carried out for each stage, which can more effectively control the stress and cutting quality in the cutting process, reduce stress concentration and cutting defects, improve cutting accuracy and stability, and thus reduce rubber wire residue; by matching wafer characteristic data, the target requirements of the dicing stage with the tools in the tool library, and considering the interaction between tool parameters and wafer characteristics, it can realize comprehensive optimization of tools and process parameters, achieve better cutting effects, reduce rubber wire residue, and improve product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a logic flow chart of the process parameter determination method for improving the ultra-thin wafer scribing tape in the present invention;

[0030] Figure 2 This is a structural block diagram of the process parameter determination system for improving the ultra-thin wafer scribing tape in the present invention. DETAILED DESCRIPTION

[0031] The present application is described below in conjunction with the accompanying drawings.

[0032] like Figure 1 As shown, the process parameter determination method for improving the ultra-thin wafer scribing tape of the present invention specifically includes the following steps:

[0033] Step S100, performing characteristic analysis on the ultra-thin wafer to be diced to obtain wafer characteristic data;

[0034] Step S200: Inputting the wafer characteristic data into a wafer scribing analysis model to obtain at least two scribing stages; the scribing stages at least include a stress relief stage and a separation stage;

[0035] Step S300: For each scribing stage, the corresponding target requirement and the wafer characteristic data are used as mapping conditions, and a pre-built scribing tool library is screened to obtain the optimal tool corresponding to the scribing stage;

[0036] Step S400, considering the interaction between the tool parameters corresponding to the optimal tool and the wafer characteristic data, determine the optimal scribing process parameters corresponding to the scribing stage; the scribing process parameters include at least the spindle speed, scribing blade height and cutting speed.

[0037] In this embodiment, through the mapping logic of wafer characteristic data, dicing stage, tool determination, and parameter matching, characteristic data such as wafer thickness and material stress are used as the basis for decision-making throughout the entire process. For example, in the stress relief stage, high-density diamond tools are selected based on wafer characteristic data and matched with low spindle speed to release internal stress. In the separation stage, the cutting speed is dynamically adjusted based on tool parameters, forming a closed loop of characteristic analysis, stage matching, and parameter fine-tuning. This makes the process parameters no longer rely on empirical settings, but are deeply bound to the wafer characteristics. Compared with traditional fixed parameter processes, the residual adhesive wire rate is reduced.

[0038] The scribing analysis model breaks down the process into two stages: stress relief and separation. Differentiated strategies are tailored for each stage. The stress relief stage aims for low-energy, uniform stress release, using tools with smaller diamond particles and a stepped cutting pattern to avoid edge chipping caused by stress concentration. The separation stage aims for precise fracture control, selecting high-sharpness tools from the tool library, and optimizing spindle speed and tool height parameters to reduce cutting heat accumulation and achieve simultaneous control of edge chipping size and residual rubber wire.

[0039] In summary, this method matches wafer characteristic data, target requirements of the dicing stage with the tools in the tool library, and considers the interaction between tool parameters and wafer characteristics. It can achieve dynamic adjustment and optimization of tools and process parameters, reduce cutting defects and glue residues caused by inappropriate process parameters, and extend the service life of cutting blades and equipment, thereby achieving better cutting effects and improving product yield.

[0040] In some embodiments of the present invention, wafer characteristic data is a series of parameters obtained by performing characteristic analysis on the ultra-thin wafer to be sliced ​​that can characterize the characteristics of the wafer itself, and is used to reflect the physical, chemical, mechanical and other properties of the wafer; specifically, the wafer characteristic data includes at least one of geometric characteristic parameters, material mechanical characteristic parameters, internal stress state parameters and surface quality characteristic parameters.

[0041] More specifically, the geometric characteristic parameters include at least one of the following parameters:

[0042] Wafer thickness: refers to the vertical thickness of the entire wafer, with ultra-thin wafers ≤50μm. Laser interferometers or contact thickness gauges are used to measure multiple points and average the average value to ensure data accuracy. Thinner wafers have poorer rigidity, significantly increasing the risk of internal stress concentration during dicing, which can easily lead to edge cracking and adhesive residue. For example, the probability of adhesive residue forming on a 30μm-thick wafer is approximately 40% higher than on a 50μm wafer.

[0043] Warpage: This refers to the maximum height by which the wafer surface deviates from the ideal plane, reflecting the wafer flatness. Full wafer surface profile data is acquired through non-contact measurement using laser scanning or an optical profilometer. When warpage exceeds 10μm, the contact path between the cutting wheel and the wafer will shift, resulting in uneven cutting depth and the edge area being prone to forming glue threads due to localized stress overload.

[0044] Cutting street width: refers to the width of the preset cutting area on the wafer, which is usually determined by the designer. The actual width is measured by observing the microstructure of the cutting street using an optical microscope or scanning electron microscope. When the width is less than 50μm, a fine-grain diamond tool is required. If a coarse-grain tool is used, the material on both sides of the cutting street may be overcut, forming fine fibrous rubber filaments.

[0045] Edge flatness refers to the smoothness of the wafer edge profile, reflecting the quality of edge processing. This is determined by scanning the microscopic profile of the edge area using an atomic force microscope or optical inspection equipment. Jagged or notched edges can easily cause material tearing along these defects during cutting, leaving adhesive residues up to tens of microns in length, which can affect subsequent packaging processes.

[0046] The material mechanical characteristic parameters include at least one of the following parameters:

[0047] Silicon substrate hardness: refers to the material's ability to resist local plastic deformation, usually expressed in Vickers hardness. A nanoindenter is used to calculate the hardness by applying a load through the indenter and measuring the indentation depth. Wafers with silicon substrate hardness greater than 12 GPa require high-density diamond cutting tools. If the tool's wear resistance is insufficient, blade wear during cutting can cause the silicon material to tear, producing rubber filaments.

[0048] Elastic modulus: refers to the stress-strain ratio of a material during its elastic deformation phase, characterizing its stiffness. A dynamic mechanical analyzer is used to measure the material's deformation response by applying periodic loads. The higher the elastic modulus, the faster the stress release during cutting, which can easily lead to microcracks at the wafer edge. During crack propagation, silicon debris can be carried along to form rubber filaments.

[0049] Fracture toughness refers to a material's ability to resist crack propagation. Using the indentation fracture method, an indentation is made on the material surface and the crack propagation length is measured. When cutting ultra-thin silicon wafers with low fracture toughness, cracks tend to propagate disorderly along the cutting path, resulting in a rough cut surface and residual adhesive wire.

[0050] Thermal conductivity refers to the ability of a material to conduct heat. It is calculated using a laser thermal conductivity meter by measuring the propagation speed of heat pulses in the material. When wafers with a thermal conductivity of less than 100W / (m·K) are cut at high speeds, the cutting heat is difficult to diffuse quickly. The local temperature increase will soften the silicon material and form molten rubber residue.

[0051] The internal stress state parameter includes at least one of the following parameters:

[0052] Residual stress distribution: refers to the stress existing inside the wafer when no external force is applied, including compressive stress and tensile stress. The stress distribution is estimated by measuring the degree of lattice distortion using X-ray diffraction or Raman spectroscopy. When the residual stress in the edge area is greater than 150MPa, the concentrated release of stress during cutting can cause edge cracking. The cracked fragments rub against the silicon material in the cutting path to form glue filaments.

[0053] Thermal stress coefficient: refers to the stress increment caused by each 1°C temperature change. A thermal stress tester applies a temperature gradient to the wafer and measures the stress change. When cutting wafers with a high thermal stress coefficient, the heat generated by the friction of the cutter wheel can cause rapid stress fluctuations, causing the material to tear along the grain boundaries, forming glue-like residues.

[0054] Stress gradient: refers to the degree of stress difference between different areas of the wafer, reflecting the uniformity of stress distribution. Multi-point stress detection technology is used to select multiple measuring points on the wafer surface to calculate the stress difference. When the stress gradient is greater than 50MPa / mm, the wafer becomes inconsistent after cutting, and the materials on both sides of the cutting path are pulled due to uneven force, forming thin and long rubber filaments.

[0055] The surface quality characteristic parameters include at least one of the following parameters:

[0056] Surface roughness: refers to the unevenness of the microscopic geometric shape of the surface, usually expressed by the arithmetic mean deviation of the profile, Ra. Use an AFM or stylus profilometer to scan the wafer surface to obtain a roughness curve. When Ra>0.5μm, the surface pits are prone to absorb silicon debris produced by cutting. The debris mixes with the molten silicon to form glue filaments, which adhere to both sides of the cutting path.

[0057] Edge microcrack density: refers to the number of microcracks per unit length of the wafer edge, measured in pieces / mm. The edge area is observed at high magnification using an SEM or optical microscope to count the number of cracks. When the density is >5 pieces / mm, microcracks will propagate along the stress direction during cutting, with the crack tips tearing the silicon material to form adhesive filaments, which can lead to edge collapse in severe cases.

[0058] Initial crack length during dicing refers to the length of microcracks that pre-exist in the wafer material or are generated by the onset of cutting stress during the initial stages of wafer dicing. The wafer dicing area is observed using a high-resolution optical microscope. By adjusting the microscope's magnification, microcracks on the wafer surface and subsurface can be clearly seen, and the cracks are measured using image analysis software. The longer the initial crack length, the more likely the crack will extend in the cutting direction or in unintended directions during dicing. As the crack expands, it can tear the wafer material locally, producing tiny silicon fragments. These fragments are easily carried out by the cutting blade and adhere to the dicing path, forming adhesive filaments.

[0059] Oxide layer thickness: refers to the vertical thickness of the oxide layer on the wafer surface. It is measured using an ellipsometer based on the principle of light reflection interference. When the oxide layer thickness is greater than 1μm, its hardness is significantly different from that of the silicon substrate, and delamination is easily produced during cutting. Oxide layer fragments mix with silicon fibers to form rubber filaments.

[0060] Contaminant particle concentration: refers to the number of impurity particles per unit area on the wafer surface, measured in pieces / cm². A particle counter or energy dispersive X-ray spectrometer is used to analyze the composition and quantity of surface contaminants. When the particle concentration is high, the contaminants will increase wear on the cutter wheel, blunting the cutting edge, resulting in incomplete cutting of the silicon material and the formation of residual rubber wire.

[0061] In some embodiments of the present invention, the wafer dicing analysis model is based on the material mechanics theory and ultra-thin wafer cutting experimental data, and realizes the division of dicing stages by analyzing the mapping relationship between wafer characteristic data and stress evolution during the cutting process; the wafer dicing analysis model is based on the material mechanics theory, combined with historical experimental data of the ultra-thin wafer cutting process, and realizes the stage division by establishing a mapping relationship between wafer characteristics and cutting stress evolution; the wafer dicing analysis model integrates the stress field equation in elastic mechanics, and uses characteristic parameters such as wafer thickness, residual stress distribution, and material elastic modulus as boundary conditions to simulate the dynamic process of stress release and material separation during cutting; at the same time, it incorporates machine learning algorithms, and optimizes the threshold judgment logic of stage division through training of historical DOE experimental data, such as the optimal cutting stage parameters for wafers with different characteristics, to ensure that the model output matches the actual process requirements.

[0062] Specifically, the geometric characteristic parameters, material mechanical characteristic parameters, internal stress state parameters, and surface quality characteristic parameters of the ultra-thin wafer are used as input variables and input into the wafer dicing analysis model. The wafer dicing analysis model is processed using the following multi-physics field coupling algorithm:

[0063] Step S210: The wafer scribing analysis model calculates the corresponding cutting depth of the wafer at the initial stage of cutting based on the internal stress state parameters of the wafer and the mechanical properties of the material. Since ultra-thin wafers accumulate internal stress during the manufacturing process, if these stresses are not properly released at the beginning of scribing, stress concentration in the subsequent cutting process will lead to cutting defects and residual glue. By simulating the release of internal stress of the wafer at different cutting depths, the cutting depth of the stress relief stage is determined to ensure that the internal stress of the wafer can be effectively released during the cutting process of the stress relief stage, while avoiding other damage caused by excessive cutting. The specific calculation formula for the cutting depth of the stress relief stage is as follows:

[0064] ;

[0065] in, Indicates the cutting depth during the stress relief stage, which is used to release residual stress rather than complete separation; Represents the material constitutive coefficient, which is calibrated by experiments. For example, the typical value for silicon wafer is 0.015, which is related to the fracture energy release rate. represents fracture toughness; Indicates wafer thickness; represents the maximum residual tensile stress; represents the normalized reference stress, which is a material-related constant for silicon wafers. s ref =0.7 s y , s y is the yield strength;

[0066] In this step, a cutting depth model based on the logarithmic decay of fracture toughness and stress boundary control is established. The hyperbolic tangent function dynamically compresses the cutting depth under high residual stress conditions to a safe range, suppressing edge cracking caused by stress concentration release from the source. The function automatically reduces the cutting depth of low-toughness materials, prevents disorderly crack expansion, and reduces the residual rate of rubber wire.

[0067] Step S220: After the stress relief stage, the cutting depth corresponding to the material separation is calculated based on the geometric characteristics of the wafer and the mechanical characteristics of the material. The goal of the separation stage is to accurately separate the wafer into individual chips along the cutting lanes while ensuring the quality of the cutting edge and reducing the residual glue wire to ensure that the material separation can be completed efficiently and accurately during this stage. The specific calculation formula for the cutting depth in the separation stage is as follows:

[0068] ;

[0069] in, Indicates the cutting depth during the separation phase; Indicates wafer thickness; represents the surface compensation coefficient; Indicates surface roughness; represents the fracture extension coefficient; It represents the toughness-stiffness coupling term, which indicates that high-toughness materials or low-stiffness materials require deeper cutting to ensure complete fracture extension; represents fracture toughness; represents the elastic modulus;

[0070] In this step, the surface roughness, fracture extension coefficient, and toughness-stiffness coupling terms are integrated to achieve control over the cutting edge quality and rubber wire residue. The δ·Ra term actively increases the compensatory cutting amount for high-roughness surfaces to eliminate uncut residual fibers caused by microscopic pits. Combined with the high-toughness material properties characterized by fracture toughness, the cutting depth is ensured to completely separate the wafers while avoiding excessive penetration. The elastic modulus and fracture toughness are directly linked in the formula, effectively solving the process problems of ultra-thin wafers that are easily deformed due to low stiffness and easily torn due to high toughness, thereby improving the flatness of the cutting edge and the yield of chip separation.

[0071] In some embodiments of the present invention, the construction of a dicing tool library requires the pre-entry of multiple tool parameters, including tool type, tool physical properties, applicable wafer materials, historical process performance, etc., to form a structured and searchable tool database; specifically, the tool types include diamond saw blades, laser cutting heads, etc.; the tool physical properties include blade particle size, wheel shape, blade angle, tool material toughness, etc.; the historical process performance includes the cutting effect and glue wire residue of the tool on different wafers and at different dicing stages; applicable wafer materials include silicon, gallium arsenide and silicon carbide, etc.

[0072] In the actual application of the dicing tool library, the tool selection strategy is as follows:

[0073] During the stress relief phase, the goal is to slowly and evenly release stress within the wafer to avoid excessive cutting force causing new stress concentration or damage. The tool requirements are moderate cutting force, a stable cutting process, and the ability to gently act on the wafer. Based on this goal and combined with wafer characteristic data, if the wafer is thin and the residual stress is high, tools with small blade particle size, blunt blade edge (to reduce cutting impact), and good material toughness (to avoid chipping and the impact of stress release) are prioritized. For example, for a 30-micron thick silicon wafer with high residual stress, a diamond saw blade with a particle size of 30-50 microns and a blade angle of 60-80 degrees is selected from the tool library, which provides gentler stress release during cutting. An algorithm is used to convert the gentle stress release requirement into tool parameter constraints, such as the cutting force threshold and tool wear rate range. The tool library is then traversed to select the tool that meets the wafer characteristic adaptation and matches the cutting force and stress relief requirements as the optimal tool for the stress relief phase.

[0074] In the separation stage, the target requirement is to accurately separate the wafer materials, with high cutting edge quality and reduced adhesive residue. The tool needs to have high cutting precision, controllable cutting force and the ability to ensure the flatness of the cutting surface. Based on this target requirement, according to the wafer geometric characteristics and material mechanical properties, if the wafer cutting path is narrow and the material is brittle, select tools with high cutter wheel precision and sharp blade shape that fits the cutting path. For example, for silicon carbide wafers with a cutting path width of 20 microns, select a laser cutting tool with a cutter wheel width tolerance of ±1 micron and a blade sharpness of nanometer level to ensure cutting accuracy. At this stage, the requirements for precise separation and low adhesive residue are broken down into indicators such as cutting accuracy and edge quality, and converted into tool parameter requirements, such as cutter wheel size tolerance and cutting thermal control capability. The tool library is searched for tools that meet the wafer characteristics and can achieve the separation goal, and they are determined as the optimal tools for the separation stage.

[0075] In this embodiment, the phased target requirements, wafer characteristics and tool performance are dynamically coupled through a structured database to effectively solve the problem of residual adhesive wire in ultra-thin wafer cutting. In order to address the core contradiction in the stress relief stage, namely the contradiction between excessive cutting causing new stress and insufficient release leading to subsequent cracking, a mapping mechanism between wafer residual stress and tool parameters is established to enable tool selection to be driven by physical models instead of experience. For example, for 30-micron high-stress silicon wafers, the algorithm automatically locks on a diamond saw blade with a fine particle size (30-50μm) and a blunt edge (60-80°), and uses the physical property of the blunt edge to disperse stress, reduce the stress release rate, and block the chain reaction of adhesive wire generation caused by microcracks. During the separation stage, a dual constraint mechanism of cutting accuracy and thermal management is established. For narrow cutting conditions of brittle materials such as silicon carbide, the rigid requirements of nano-scale sharp cutting edges and ±1μm cutter wheel tolerance directly eliminate microscopic burrs; and the thermal conductivity constraint of the thermal management coating tool reduces the material melt adhesion rate by conducting cutting heat; quantitative mapping of tool performance and wafer characteristics is achieved, reducing the residual size of the glue wire on the cutting surface and improving product yield.

[0076] In some embodiments of the present invention, in order to effectively solve the problem of residual adhesive wire, it is necessary not only to make the best selection of the tool, but also to accurately determine the dicing process parameters based on the characteristics of the selected tool and the characteristics of the wafer; because different tools have different cutting performance and characteristics, and the wafer itself has unique geometric properties and material mechanical properties; only by reasonably matching the tool parameters with the wafer characteristics and determining the appropriate dicing process parameters can the residual adhesive wire be minimized to the greatest extent, the cutting edge quality can be improved, and the stability and efficiency of the cutting process can be guaranteed.

[0077] Specifically, the dicing process parameters include spindle speed, dicing blade height, cutting speed, etc.; among them, the spindle speed affects the cutting heat generation and tool cutting frequency. If the speed is too high, it is easy to cause local overheating of the wafer and melting of the material to produce glue wire; if the speed is too low, the cutting force is large, which can easily cause the wafer to crack; the dicing blade height determines the depth of the tool's penetration into the wafer, which is related to the cutting depth requirements in the stress relief and separation stages. If it is too high, it will over-cut, and if it is too low, it will not meet the stage process goals; the cutting speed affects the cutting efficiency and the stress release rhythm. If the speed is too fast, it is easy to cause stress concentration, and if it is too slow, it will affect production capacity and may increase heat accumulation due to long-term friction.

[0078] More specifically, during the stress relief phase, in order to meet the requirements of smoothly releasing stress and avoiding damage during the stress relief phase, the process parameters need to help the tool act gently on the wafer. Combining the tool parameters of the optimal tool with the wafer characteristics, the stress relief effect under different parameter combinations is verified through simulation or experiments. For example, for a 30-micron-thick silicon wafer with high residual stress, if the tool particle size is small and the toughness is good, the spindle speed can be appropriately reduced to reduce cutting heat, and the dicing knife height can be controlled to the cutting depth during the stress relief phase, so as to gradually release the stress at a stable cutting speed. The cutting heat threshold and stress release uniformity index are set, and a multi-objective optimization function is constructed to solve the combination of spindle speed, knife height, and cutting speed that allows sufficient stress release without excessive damage, and determine the optimal parameters for the stress relief phase.

[0079] During the separation stage, the requirements of precise separation and low adhesive residue need to be met, and the process parameters need to ensure cutting accuracy and edge quality. Based on the tool parameters of the optimal tool and the wafer characteristics, the influence of the parameters on the cutting edge cracking and adhesive wire generation is analyzed. For example, when using high-precision tools for silicon carbide wafers with narrow cutting paths, the spindle speed needs to be increased to ensure cutting efficiency, the dicing knife needs to be accurately controlled to match the cutting depth during the separation stage, and the cutting speed needs to be adjusted to separate the materials in an orderly manner. With the cutting edge cracking size and adhesive wire density as constraints, combined with tool life and production capacity requirements, the spindle speed, knife height, and cutting speed are optimized to determine the adaptation parameters for the separation stage.

[0080] In this embodiment, by analyzing the interaction between the tool and wafer characteristics, the process parameters are dynamically adjusted to break the limitations of the existing fixed process parameters; reasonable parameters in the stress relief stage can release stress smoothly and reduce the cause of glue wire from the source; adaptive parameters in the separation stage can improve cutting accuracy and quality and reduce the generation of glue wire during the cutting process; the process parameters in each stage are coordinated with the tool and wafer characteristics, effectively improving the glue wire residue problem and improving the ultra-thin wafer dicing yield and product reliability.

[0081] Certain steps in the above method embodiments may be equivalently replaced with other possible steps. Alternatively, certain steps in the method embodiments may be optional and may be deleted in certain usage scenarios. Alternatively, other possible steps may be added to the method embodiments. Furthermore, the various method embodiments may be implemented separately or in combination.

[0082] like Figure 2 As shown, the present invention also provides a process parameter determination system for improving ultra-thin wafer scribing tape, which specifically includes the following modules:

[0083] Wafer characteristic analysis module, used to analyze the characteristics of ultra-thin wafers to be diced and obtain wafer characteristic data;

[0084] a scribing stage division module, configured to input the wafer characteristic data into a wafer scribing analysis model to obtain at least two scribing stages;

[0085] A tool selection module is used to select the optimal tool for each scribing stage by using the target requirements and the wafer characteristic data as mapping conditions and screening the tool library in advance;

[0086] The process parameter optimization module is used to consider the interaction between the tool parameters corresponding to the optimal tool and the wafer characteristic data to determine the optimal dicing process parameters corresponding to the dicing stage.

[0087] In this embodiment, wafer characteristic data is dynamically acquired through the wafer characteristic analysis module, overcoming the limitations of traditional fixed parameter processes and achieving personalized adaptation to different wafers; secondly, the dicing stage division module divides the cutting process into a stress relief stage and a separation stage, accurately identifying the special needs of ultra-thin wafer cutting, and avoiding the defect of traditional processes that regard dicing as a single process; the tool selection module relies on a pre-built tool library and a mapping condition screening mechanism to match the optimal tool for different stage characteristics, especially using tools with smaller diamond particles to effectively reduce the risk of adhesive wire; the process parameter optimization module realizes dynamic optimization combination of key parameters such as spindle speed, knife height, and cutting speed through multi-parameter interaction analysis, solves the problem of cutting heat accumulation caused by the solidification of traditional process parameters, can reduce adhesive wire residue, improve cutting accuracy and yield, and extend tool life.

[0088] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the foregoing embodiments. The foregoing embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for determining process parameters for improving ultra-thin wafer scribing tape, characterized in that: include: Perform characteristic analysis on ultra-thin wafers to be diced to obtain wafer characteristic data; Inputting the wafer characteristic data into a wafer scribing analysis model to obtain at least two scribing stages; The scribing stage includes at least a stress relief stage and a separation stage; For each dicing stage, the corresponding target requirements and the wafer characteristic data are used as mapping conditions, and a pre-built dicing tool library is screened to obtain the optimal tool corresponding to the dicing stage; Considering the interaction between the tool parameters corresponding to the optimal tool and the wafer characteristic data, determining the optimal scribing process parameters corresponding to the scribing stage; the scribing process parameters include at least the spindle speed, the scribing blade height, and the cutting speed; During the stress relief phase, the stress relief effects of different parameter combinations were experimentally verified, combining the optimal tool parameters with wafer characteristics. The cutting thermal threshold and stress relief uniformity index were set, and a multi-objective optimization function was constructed to determine the optimal dicing process parameters for the stress relief phase, including the spindle speed, dicing blade height, and cutting speed, that resulted in sufficient stress relief without excessive damage. During the separation stage, based on the tool parameters and wafer characteristics of the optimal tool, the influence of the parameters on the cutting edge cracking and rubber wire generation is analyzed. With the cutting edge cracking size and rubber wire density as constraints, combined with the tool life and production capacity requirements, the spindle speed, dicing blade height and cutting speed are optimized as the optimal dicing process parameters for the separation stage.

2. The process parameter determination method for improving ultra-thin wafer scribing tape according to claim 1, characterized in that: The wafer characteristic data includes at least one of geometric characteristic parameters, material mechanical characteristic parameters, internal stress state parameters and surface quality characteristic parameters.

3. The process parameter determination method for improving ultra-thin wafer scribing tape according to claim 2, characterized in that: The geometric characteristic parameters include at least one of wafer thickness, warpage, scribe line width and edge flatness.

4. The process parameter determination method for improving ultra-thin wafer scribing tape according to claim 3, characterized in that: The material mechanical characteristic parameters include at least one of silicon substrate hardness, elastic modulus, fracture toughness and thermal conductivity.

5. The process parameter determination method for improving ultra-thin wafer scribing tape according to claim 4, characterized in that: The internal stress state parameter includes at least one of residual stress distribution, thermal stress coefficient, and stress gradient.

6. The process parameter determination method for improving ultra-thin wafer scribing tape according to claim 2, characterized in that: The wafer scribing analysis model calculates the cutting depth corresponding to the wafer in the stress relief stage according to the internal stress state parameters and material mechanical property parameters of the wafer. The calculation formula is: ； in, Indicates the cutting depth during the stress relief stage, which is used to release residual stress rather than complete separation; Represents the material constitutive coefficient, which is calibrated by experiments; represents fracture toughness; Indicates wafer thickness; represents the maximum residual tensile stress; σ ref represents the normalized reference stress, and σ is the material-related constant for silicon wafers. ref =0.7σ y ,σ y is the yield strength.

7. The process parameter determination method for improving ultra-thin wafer scribing tape according to claim 6, characterized in that: The wafer scribing analysis model calculates the cutting depth corresponding to the separation stage based on the geometric characteristic parameters and the material mechanical characteristic parameters. The calculation formula is: ； in, Indicates the cutting depth during the separation phase; Indicates wafer thickness; represents the surface compensation coefficient; Indicates surface roughness; represents the fracture extension coefficient; represents fracture toughness; Represents the elastic modulus.

8. A process parameter determination system for improving ultra-thin wafer scribing tape, wherein the system is applied to the process parameter determination method for improving ultra-thin wafer scribing tape as claimed in claim 1, characterized in that: include: Wafer characteristic analysis module, used to analyze the characteristics of ultra-thin wafers to be diced and obtain wafer characteristic data; a scribing stage division module, configured to input the wafer characteristic data into a wafer scribing analysis model to obtain at least two scribing stages; A tool selection module is used to select the optimal tool for each scribing stage by using the target requirements and the wafer characteristic data as mapping conditions and screening the tool library in advance; The process parameter optimization module is used to consider the interaction between the tool parameters corresponding to the optimal tool and the wafer characteristic data to determine the optimal dicing process parameters corresponding to the dicing stage.

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