Copper clad ceramic substrate and half-etching method and application

Abstract

The present application relates to the technical field of copper-clad plate manufacturing, and particularly relates to a copper-clad ceramic substrate and a half-etching method and application, the method comprises the following steps: (S.1) forming a light-induced protective layer on the upper and lower surfaces of a copper-clad ceramic substrate; (S.2) patterning on the protective layer through exposure, thereby forming a first pattern at a full-etching area on the upper surface of the copper-clad ceramic substrate and forming a second pattern at a half-etching area on the lower surface of the copper-clad ceramic substrate; (S.3) single etching treatment, thereby etching the full-etching area exposed at the first pattern to form a through circuit, and simultaneously forming a half-etching groove at the half-etching area exposed at the second pattern. The present application can realize the effect of half-etching on the lower surface of the copper-clad ceramic substrate under the condition of single etching without performing redundant process operations, thereby effectively improving the substrate warping problem caused by the volume ratio difference of the copper foils on both sides.

Description

Technical Field

[0001] The present invention relates to the technical field of copper-clad plate manufacturing, and in particular to a copper-clad ceramic substrate and a half-etching method and application thereof. Background Art

[0002] In high-end manufacturing sectors such as electric locomotives, electric vehicles, and photovoltaic solar energy, the integration and power density of high-power semiconductor modules continue to increase, leading to an exponential increase in heat dissipation requirements. Direct Bonded Copper (DBC) substrates, thanks to their combination of the excellent insulation and thermal conductivity of the ceramic layer with the high electrical conductivity of the copper layer, have become a core component of heat dissipation solutions.

[0003] However, during the manufacturing process, such substrates need to undergo high-temperature sintering at 800°C to 900°C to achieve metallurgical bonding between the ceramic and copper layers. This process exposes the inherent contradiction of the material nature: the thermal expansion coefficient of ceramics (about 2.6-5.2×10 -6 / K) and copper (about 17.2×10 -6 The thermal stress generated during the sintering cooling phase significantly accumulates within the substrate, triggering systemic defects along two dimensions. First, during the subsequent etching process, the amplified difference in copper volume between the patterned (A) and non-patterned (B) surfaces (typically, fine lines are etched on A while B remains entirely copper). This stress release can cause uncontrolled substrate warping. Second, during post-processing steps at 200°C, such as solder masking and baking, thermal factors further exacerbate warpage, leading to a significant shift in substrate geometric accuracy. This compounding effect not only reduces module packaging yield but also creates a fatal risk of solder cracking during thermal cycling (from -55°C to 125°C).

[0004] To address these issues, the industry currently relies on two fundamentally flawed technical approaches. The first employs a secondary etching method: a conventional etching process forms the full-depth circuitry on the A side, followed by a partial etching of the B side using a secondary mask. While this process can achieve localized copper thinning, issues such as dry film adhesion loss and solvent penetration caused by the secondary lamination process directly lead to corrosion defects at the circuit edges, resulting in yield losses of up to 15%-20%. Furthermore, the additional steps significantly extend production cycle time, and the increased etching solution usage doubles, leading to a surge in production costs. The second approach attempts to create a dotted pattern of dimples (a "dimples" structure) on the B side through a single etching pass to adjust the copper volume ratio. However, this discrete design suffers from spatial control blind spots: the dimples are primarily located at the edges of the copper layer, preventing effective stress relief in the center, leading to central warpage in the substrate even after solder mask heat treatment. Furthermore, the micron-sized dimples are prone to gas entrapment during reflow soldering at the customer end, resulting in unfilled voids. During temperature shock tests, the expansion rate of the gas in the cavity does not match the shrinkage rate of the solder, which rapidly accelerates interface delamination. This means that modules using such substrates have a significantly increased risk of failure under harsh working conditions.

[0005] With the miniaturization of third-generation semiconductor devices, the requirements for ceramic substrate warpage control have shifted from "allowable error" to "zero tolerance." This requires any innovative solution to achieve the dual missions of copper layer topology optimization and stress relief within a single manufacturing cycle, while ensuring both the depth uniformity of the half-etched area and the etching accuracy of the circuit side meet dual standards. The trade-off between efficiency, precision, and reliability in existing technical solutions has become a key bottleneck restricting the performance and production capacity improvement of ceramic substrates in the field of high-reliability power modules. The industry urgently needs a breakthrough process concept that can uniformly address the mutually constrained "impossible triangle" of molding efficiency, structural precision, and stress field stability optimization, rather than simply making slight improvements on existing technical routes. Summary of the Invention

[0006] The present invention aims to overcome the defects of the prior art copper-clad ceramic substrate in which stress is accumulated inside during the preparation process, resulting in phenomena such as warping and distortion, thereby reducing the packaging yield of the module. Therefore, a copper-clad ceramic substrate and a half-etching method and application are provided to overcome the above-mentioned shortcomings.

[0007] To achieve the above-mentioned purpose, the present invention is implemented through the following technical solutions:

[0008] In a first aspect, the present invention first provides a ceramic substrate half-etching method comprising the following steps:

[0009] (S.1) forming a photoresist layer on the upper and lower surfaces of the copper-clad ceramic substrate;

[0010] (S.2) patterning the protective layer by exposure to light, thereby forming a first pattern in the fully etched area on the upper surface of the copper-clad ceramic substrate and forming a second pattern in the half-etched area on the lower surface of the copper-clad ceramic substrate;

[0011] Wherein, in the second pattern, a curing protection band is dynamically provided extending along the etching direction according to the ratio of its width to the critical width value;

[0012] (S.3) A single etching process is performed to etch the fully etched region exposed at the first pattern to form a through-line, and to simultaneously form a half-etched groove at the half-etched region exposed at the second pattern.

[0013] As described in the background, the evolution of ceramic substrate half-etching processes has been plagued by a profound conflict between material physical properties and manufacturing efficiency. Residual stress, caused by the significant difference in thermal expansion coefficients (approximately three times) between the ceramic and copper layers, can escalate during subsequent etching steps as the A / B copper volume ratio sharply diverges, leading to uncontrollable warpage. This structural flaw has forced the industry to explore solutions for copper layer volume control, but existing approaches face fundamental limitations. While the mainstream secondary etching method can partially thin the copper layer on the underside of a copper-ceramic substrate, repeated film lamination leads to increased risk of etching solution penetration, resulting in yield losses of up to 15-20%, and significantly increasing costs due to the increased number of process steps. The alternative Dimples design, while capable of a single etching pass, utilizes a discrete lattice structure to regulate stress only at the edges, leaving no relief for stress accumulation in the center. Furthermore, microporous gas entrapment can lead to solder voids, a potential source of module failure under thermal shock.

[0014] Therefore, in this context, the present invention has the insight that the essential contradiction of the etching process does not stem from the number of steps, but from the spatiotemporal fragmentation of the copper layer morphology control. Traditional thinking regards "full etching deep grooves" and "half etching shallow grooves" as two independent operations, but ignores the fact that they share a common depth control principle in etching dynamics. This cognitive breakthrough gave birth to the core concept: through the topological innovation of the photoresist layer, a differentiated etching barrier system is established in a single etching sequence. Specifically, inside the protective layer covering the half-etched area, a dynamic protective band array is constructed according to the groove width of the second pattern in the half-etched area. In this process, the protective band cuts the wide groove into several equivalent narrow groove etching units. When the etching liquid flows through the groove area of ​​the critical width, a stable laminar shear field is formed due to the boundary effect, so that the etching depth is uniform and controllable and accurately stops at the preset thickness; and the protective band itself, as a solidified structure, can resist the impact of the etching liquid to avoid premature peeling. In this way, in step S.2, the full etching area (without protective tape) on the upper surface of the copper-clad ceramic substrate is deeply penetrated, while the half etching area (including the protective tape array) on the lower surface of the copper-clad ceramic substrate is uniformly thinned simultaneously. The two can be completed simultaneously through a single etching in S.3.

[0015] Compared with the prior art, the creativity of the present invention is reflected in three dimensions: First, at the process level, the present application breaks the industry stereotype of "the full / semi-etching process must be separated" with the dynamic grading mechanism of the protection belt, and for the first time realizes the spatio-temporal synchronization of two types of etching depths. Second, at the physical effect level, the protection belt array is not only a geometric separator, but also a dual regulator of the etching flow field and stress field: it not only ensures the stability of etching kinetics in the narrow slit, but also constitutes the microstructure unit of the mechanical behavior of the copper layer. Third, at the industrial value level, the process simplification significantly reduces the production cost (canceling the secondary laminating and the use of etching equipment), and greatly improves the yield rate (eliminating the defect source of the dry film secondary bonding). Therefore, the method in the present application completes the industrial-level technological leap from "multi-process passive compensation" to "single-time active stress optimization" through the underlying reconstruction of the etching process.

[0016] Preferably, the number of the set curing protection belts is determined according to the semi-etching width X of the second pattern:

[0017] When X≤0.4mm, no curing protection belt is set;

[0018] When 0.4mm < X≤0.8mm, 1 curing protection belt with a width of 80-100μm is set;

[0019] For each increase of 0.4mm in X, 1 additional curing protection belt with a width of 80-100μm arranged in parallel is added.

[0020] Preferably, the width of the curing protection belt is 80-100μm.

[0021] Preferably, the positions of the first pattern and the second pattern on the upper and lower surfaces of the copper-clad ceramic substrate correspond to each other.

[0022] In the present application, by accurately corresponding the semi-etching area and the full-etching circuit in the vertical projection, a "stress疏导 microchannel" penetrating the copper-ceramic interface is constructed inside the substrate. Thus, the following beneficial effects are achieved: First, the vertical channel enables the longitudinal contraction strain of the copper layer and the expansion residual force of the ceramic layer to cancel each other out, converting the originally diffused shear stress concentration into controllable normal deformation; Second, combined with the grading rule of the protection belt width, the stiffness distribution in the semi-etching groove area is further anchored, avoiding the disordered diffusion of stress in the width direction; Third, in the final packaging and welding process, this spatial correspondence enables the semi-etching groove and the circuit on the upper surface of the substrate to jointly form a continuous heat conduction path, significantly improving the overall heat diffusion uniformity of the substrate compared with the random arrangement scheme. Particularly crucial is that this design can be realized only by optimizing the coordinates of the photomask layout without increasing the manufacturing process, which not only maintains the process simplicity, but also locks the warping direction of the substrate in the ideal mode of the upward warping of the edge of the A surface after the subsequent baking, thus laying a physical foundation for the interface reliability of high-density power modules that surpasses existing patents.

[0023] Preferably, step (S.2) further comprises designing the first pattern and the second pattern on the upper and lower surfaces of the copper-clad ceramic substrate so that the volume ratio of the copper foil on the upper and lower surfaces of the copper-clad ceramic substrate is ≤110%.

[0024] The present invention discovered that when the copper foil volume ratio between the top and bottom surfaces of a copper-clad ceramic substrate exceeds a critical value of 1.1, the contraction force of the copper layer on the top surface completely suppresses the flexural strength of the ceramic layer, leading to irreversible plastic bending during cooling. To address this issue, digital modeling was used during the pattern design phase (S.2) to proactively plan the copper distribution on both sides. For example, this involves expanding the non-functional copper foil area on the top surface of the copper-clad ceramic substrate or refining the density of the half-etched grooves on the bottom surface of the copper-clad ceramic substrate, precisely anchoring the copper volume ratio within the range of ≤110%. Compared to the one-sided control of existing technologies, this design achieves a dual-effect: First, the threshold control coordinates the spatial layout of the guard band, dissipating thermal stress uniformly along the base plane and locking the sintering warpage within a controllable range of 1-5‰. Second, the directionally induced slight curvature of the copper-clad ceramic substrate's top surface (e.g., approximately 2.5‰) triggers a unique fluid dynamic response during soldering: molten solder spreads faster within the semi-etched grooves on the copper-clad ceramic substrate's lower surface due to capillary action. Simultaneously, the micro-angle created by the curvature of the copper-clad ceramic substrate's top surface drives gas escape in a predetermined direction, resulting in an order of magnitude lower void propagation rate compared to a random warpage model. Crucially, this volume ratio threshold has been verified to be universal across thousands of samples. Even with fluctuations in ceramic composition (aluminum nitride or aluminum oxide) or variations in copper thickness (0.2-0.6mm), as long as the ratio constraint is met, the substrate's warpage rebound after baking at 250°C remains stable below 0.5‰. This method of converting the material constitutive relationship into simple parameters that can be manipulated in engineering not only avoids the traditional process's excessive reliance on annealing correction, but also enables cross-generational improvements in the dimensional consistency of semi-etched substrates, removing core obstacles to the standardized packaging of vehicle-level power modules.

[0025] Preferably, the etching process parameters meet the following requirements: copper ion concentration of etching solution 100-200 g / L, hydrochloric acid concentration 1.5-2.5 mol / L, spray pressure 0.5-2.5 Kg / cm 2 .

[0026] Preferably, an annealing step is included, which includes applying a pressure of 4-6 KPa to the substrate, heating it to 250-350°C at 20-30°C / min and keeping it warm for 1 hour; or cooling it to -30~-20°C at 2-3°C / min and keeping it warm for 0.5 hour; or applying a pressure continuously increasing from 0 to 0.5-4 KPa to the substrate at room temperature, and the entire pressurization process is ensured to be 5-10 minutes, and maintaining it for 2 minutes after reaching the target pressure.

[0027] In a second aspect, the present invention further provides a copper-clad ceramic substrate, which is prepared by any of the methods described above, and has a through-hole fully etched groove on its upper surface and a half-etched groove on its lower surface.

[0028] Preferably, the volume ratio of the copper foils on the upper and lower surfaces of the copper-clad ceramic substrate is ≤110%, so that the warping degree from the edge of the copper-clad ceramic substrate to the upper surface of the copper-clad ceramic substrate is 1-5‰.

[0029] In a third aspect, the present invention further provides the use of the copper-clad ceramic substrate described above in high-power insulated gate bipolar transistors, silicon carbide modules, and intelligent power modules.

[0030] Therefore, the present invention has the following beneficial effects:

[0031] The present invention dynamically sets a curing protective belt on the back side of the copper-clad ceramic substrate along the etching direction according to the ratio of the required etching width to the critical width value, thereby achieving the formation of a through circuit in the fully etched area on the upper surface of the copper-clad ceramic substrate and the formation of a half-etched groove in the half-etched area on the lower surface of the copper-clad ceramic substrate during a single etching process. This effectively simplifies the process and significantly reduces the production cost while accurately controlling the copper content on the upper and lower surfaces of the copper-clad ceramic substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of a half-etching method for a copper-clad ceramic substrate in an embodiment of the present invention.

[0033] Figure 2 A microscope photograph of a half-etched groove on the bottom surface of a copper-clad ceramic substrate.

[0034] Among them, 1 is the ceramic substrate, 2 is the copper layer, 3 is the photoresist layer, 4 is the fully etched groove, and 5 is the half-etched groove. DETAILED DESCRIPTION

[0035] The present invention will be further described below with reference to specific embodiments. Those skilled in the art will be able to implement the present invention based on these descriptions. Furthermore, the embodiments of the present invention described below generally represent only a portion of the present invention, rather than all of the embodiments. Therefore, all other embodiments derived by those skilled in the art based on the embodiments of the present invention without inventive effort should fall within the scope of protection of the present invention.

[0036] Overall embodiment

[0037] like Figure 1 As shown, this embodiment first provides a ceramic substrate half-etching method, comprising the following steps:

[0038] (S.1)Sinter the ceramic substrate 1 and the copper layer 2 normally to obtain a copper-clad ceramic substrate, and perform surface cleaning on the sintered copper-clad ceramic substrate. After the cleaning is completed, form a photoresistive protective layer 3 on the upper and lower surfaces of the copper-clad ceramic substrate by laminating or printing a wet film on its surface;

[0039] (S.2)Expose the photoresistive protective layer 3 to form a first pattern and a second pattern to be etched at the relative positions on the upper and lower surfaces of the copper-clad ceramic substrate respectively. The widths of the first pattern and the second pattern are shown in Table 1. Among them, in the second pattern, according to the ratio of the half-etch width to the critical width value of the second pattern, it is determined whether to perform exposure on its surface, so as to obtain a cured protection band extending along the etching direction in the second pattern;

[0040] Specifically, the number of the cured protection bands is determined according to the half-etch width X of the second pattern:

[0041] When X≤0.4mm, no cured protection band is set;

[0042] When 0.4mm<X≤0.8mm, set 1 cured protection band with a width of 80-100μm;

[0043] When X increases by 0.4mm each time, add 1 parallel cured protection band with a width of 80-100μm;

[0044] In addition, during the design process of the first pattern and the second pattern, by controlling the widths of the first pattern and the second pattern, the copper foil volume ratio on the upper and lower surfaces of the copper-clad ceramic substrate is ≤110%;

[0045] (S.3)Immerse the exposed copper-clad ceramic substrate into an etching solution for single etching treatment. The copper ion concentration in the etching solution is 100-200g / L, the hydrochloric acid concentration is 1.5-2.5mol / L, and the spraying pressure is 0.5-2.5Kg / cm 2 , so as to etch the fully etched area exposed at the first pattern to form a through fully etched groove 4 circuit, and simultaneously form a semi-etched groove 5 at the semi-etched area exposed at the second pattern;

[0046] (S.4)Perform surface cleaning on the etched copper-clad ceramic substrate, dry it after the cleaning is completed, and then apply a pressure of 4-6KPa to the substrate, heat it to 250-350°C at a rate of 20-30°C / min and keep it warm for 1 hour, or cool it to -30~-20°C at a rate of 2-3°C / min and keep it warm for 0.5 hour to complete annealing, so as to obtain a copper-clad ceramic substrate with the warpage degree of the edge towards the upper surface of the copper-clad ceramic substrate being between 1‰ and 5‰.

[0047] Table 1

[0048]

[0049] Figure 2 This is a microscopic photograph of a half-etched groove on the lower surface of a copper-clad ceramic substrate. Combined with the accompanying figures and the data in the table above, it can be seen that in the process, this application can achieve the effect of fully etching the upper surface of the copper-clad ceramic substrate and half-etching the lower surface in a single etching process without requiring additional processing steps. This can effectively alleviate the substrate warping problem caused by the difference in the volume ratio of the copper foil on both sides of the product. At the same time, this application can control the product's performance parameters such as warping direction and amount during the design phase, thereby meeting the performance requirements of customers when packaging modules.

[0050] The specific embodiments described herein are merely illustrative of the spirit of the present invention. Persons skilled in the art may make various modifications, additions, or substitutions to the described specific embodiments without departing from the spirit of the present invention or exceeding the scope of the appended claims.

Claims

1. A method for half-etching a copper-clad ceramic substrate, characterized in that: It includes the following steps: (S.1) Form a photoresistive protective layer on the upper and lower surfaces of the copper-clad ceramic substrate; (S.2) Pattern the protective layer by exposure, thereby forming a first pattern at the fully etched area on the upper surface of the copper-clad ceramic substrate and a second pattern at the semi-etched area on the lower surface of the copper-clad ceramic substrate; Among them, a curing protection band is dynamically set according to its width along the etching direction in the second pattern; The number of the set curing protection bands is determined according to the width X of the second pattern: When X≤0.4mm, no curing protection band is set; When 0.4mm<X≤0.8mm, 1 curing protection band is set; When 0.8mm<X≤1.2mm, 2 curing protection bands are set; When 1.2mm<X≤1.6mm, 3 curing protection bands are set; (S.3) Perform a single etching process, thereby etching the fully etched area exposed at the first pattern to form a through-line, and simultaneously forming a semi-etched groove at the semi-etched area exposed at the second pattern.

2. The semi-etching method of the copper-clad ceramic substrate according to claim 1, wherein The width of the curing protection band is 80-100μm.

3. The semi-etching method of the copper-clad ceramic substrate according to claim 1, wherein The positions of the first pattern and the second pattern on the upper and lower surfaces of the copper-clad ceramic substrate correspond to each other.

4. The semi-etching method of the copper-clad ceramic substrate according to claim 1, wherein In step (S.2), it further includes designing the first pattern and the second pattern on the upper and lower surfaces of the copper-clad ceramic substrate, so that the copper foil volume ratio on the upper and lower surfaces of the copper-clad ceramic substrate ≤110%.

5. The semi-etching method of the copper-clad ceramic substrate according to claim 1, wherein During the single etching process in step (S.3), the copper ion concentration of the etching solution is maintained at 100-200 g / L, the hydrochloric acid concentration is 1.5-2.5 mol / L, and the spray pressure is 0.5-2.5 kg / cm 2 .

6. The semi-etching method of the copper-clad ceramic substrate according to claim 1, wherein It further includes an annealing step, and the annealing step includes applying a pressure of 4-6KPa to the substrate, heating to 250-350°C at a rate of 20-30°C / min and holding for 1 hour; or cooling to -30~-20°C at a rate of 2-3°C / min and holding for 0.5 hour; or applying a continuously increasing pressure from 0 to 0.5-4Kpa to the substrate at room temperature, ensuring that the whole pressurization process is within 5-10min, and maintaining for 2min after reaching the target pressure.

7. A copper-clad ceramic substrate, wherein It is prepared by the method described in any one of claims 1-6, and has through full-etching grooves on its upper surface and semi-etching grooves on its lower surface.

8. The copper-clad ceramic substrate according to claim 7, wherein The copper foil volume ratio on the upper and lower surfaces of the copper-clad ceramic substrate ≤110%, so that the warping range from the edge of the copper-clad ceramic substrate to the upper surface of the copper-clad ceramic substrate is 1‰-5‰.

9. Use of the copper-clad ceramic substrate according to claim 7 or 8, characterized in that: The application includes applications in high-power insulated gate bipolar transistors, silicon carbide modules or power modules.

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