A power supply noise compensation circuit and CMOS image sensor

Abstract

The application discloses a power supply noise compensation circuit and a CMOS image sensor, relates to the technical field of noise compensation of image sensors, and solves the problems that the existing compensation circuit cannot adapt to single-end input comparators and the application scene is limited. The scheme points are as follows: the circuit comprises a pixel circuit, a pixel power supply noise adjusting circuit, a digital-to-analog conversion circuit, a constant current source and a comparator; the input end of the pixel circuit is connected with a pixel power supply, the output end is connected with the ground through the constant current source, and the output end outputs a pixel signal with power supply noise; the input end of the pixel power supply noise adjusting circuit is connected with the input end of the pixel circuit or the input end of the digital-to-analog conversion circuit, and the output end outputs compensation noise; the compensation noise is converted into a slope signal with compensation noise through the digital-to-analog conversion circuit; the pixel signal and the slope signal are connected with the comparator; the built-in switch of the pixel power supply noise adjusting circuit realizes low-frequency compensation, high-frequency compensation and phase inversion, can be connected with double-end / single-end comparators, and can offset the pixel power supply noise.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of noise compensation of image sensors, more particularly, it relates to a power supply noise compensation circuit and a CMOS image sensor. BACKGROUND

[0002] In the design of CMOS image sensor (CIS) integrated circuits, noise suppression is always a big challenge for design engineers. Due to the dynamic changes of various signals in the circuit, the power supply voltage will appear jitter phenomenon, and then introduce additional noise components. This noise will be transmitted to the pixel (Pixel) output end through the conduction path between modules, and finally have a negative impact on the imaging quality. These noises mainly come from the action of pixel units and the existence of various parasitic capacitances in the circuit, and their characteristics are difficult to accurately quantify, so it is also difficult to offset by compensation means.

[0003] The existing compensation technology is to introduce a noise of the same size as the pixel noise at one end of the differential pair comparator, and use the common mode rejection characteristic of the differential pair to offset the pixel noise. But this compensation circuit is not suitable for single-ended input comparator (i.e. the slope signal and the pixel signal are input on the same side), and the application scenario is limited.

[0004] Therefore, the present application provides a power supply noise compensation circuit and a CMOS image sensor to solve the above problems. SUMMARY

[0005] The purpose of the present application is to provide a power supply noise compensation circuit and a CMOS image sensor to solve the problem that the existing compensation circuit cannot adapt to single-ended input comparator and the application scenario is limited. The present application introduces pixel power supply noise through the circuit, adjusts the gain and phase of the power supply noise to obtain compensation noise, and based on the superposition of compensation noise and pixel power supply noise, the pixel power supply noise is offset. Further, for single-ended input comparator, the phase is flipped by the pixel power supply noise adjustment circuit, and in the case of constant gain, the phase is flipped by 180° to realize noise compensation when input on the same side. For double-ended input comparator, the built-in switch in the pixel power supply noise adjustment circuit is adjusted, the phase is not flipped by 180°, the common mode rejection characteristic of the double-ended input comparator is used to offset the noise, and the noise compensation when input on different sides is realized. In addition, the circuit structure of the present application can also compensate the noise of the module monomer, and can be widely applied to different application scenarios.

[0006] The application provides a power supply noise compensation circuit, which comprises a pixel circuit, a pixel power supply noise adjustment circuit, a digital-to-analog conversion circuit, a constant current source and a comparator; the input end of the pixel circuit is connected with a pixel power supply, the output end is connected with the ground through the constant current source, and the output end outputs a pixel signal PIX_OUT with power supply noise; the input end of the pixel power supply noise adjustment circuit is connected with the input end of the pixel circuit or the input end of the digital-to-analog conversion circuit, and the output end outputs compensation noise; the compensation noise is converted into a ramp signal RAMP with compensation noise through the digital-to-analog conversion circuit; the pixel signal PIX_OUT and the ramp signal RAMP are both connected with the comparator through a capacitor, and noise compensation is realized at the input end or the output end of the comparator; wherein the pixel power supply noise adjustment circuit realizes low-frequency compensation, high-frequency compensation and phase inversion or realizes low-frequency compensation and high-frequency compensation on the input signal through built-in switches.

[0007] In a possible implementation, the input end of the pixel power supply noise adjustment circuit is connected with the input end of the pixel circuit, and the power supply noise is connected.

[0008] In a possible implementation, when the comparator adopts double-ended input, the pixel power supply noise adjustment circuit realizes low-frequency compensation and high-frequency compensation on the connected power supply noise, and outputs compensation noise with the same gain and phase as the power supply noise; when the comparator adopts single-ended input, the pixel power supply noise adjustment circuit realizes low-frequency compensation, high-frequency compensation and phase inversion on the connected power supply noise, and outputs compensation noise with the same gain and opposite phase as the power supply noise.

[0009] In a possible implementation, the pixel power supply noise adjustment circuit comprises a low-frequency gain and phase adjustment circuit and a high-frequency gain and phase adjustment circuit in parallel; the low-frequency gain and phase adjustment circuit comprises a bias circuit, a low-frequency coupling capacitor, a capacitor, a plurality of built-in switches and a plurality of transistors, and realizes low-frequency compensation and phase inversion by adjusting the on-off of the plurality of built-in switches; the high-frequency gain and phase adjustment circuit comprises a bias circuit, a high-frequency coupling capacitor, a capacitor, a plurality of built-in switches, a plurality of transistors and a high-pass filter circuit, and realizes high-frequency compensation and phase inversion by adjusting the on-off of the plurality of built-in switches.

[0010] In a possible implementation, the low-frequency gain and phase adjustment circuit comprises: a bias circuit, a low-frequency coupling capacitor C_LPF, a capacitor C1, N-channel transistors MN0, MN1, P-channel transistors MP0, MP1, MP2, MP3, MP4, built-in switches S1, S2, S3, S4, resistors Rda, R1; the gate of the transistor MP0 is connected to the bias circuit, the source is connected to the power supply, and the drain is connected to the drain of the transistor MN0; the gate of the transistor MN0 is connected to the bias circuit, and the gate is also connected to the input signal through the low-frequency coupling capacitor C_LPF, and the source is grounded through the resistor R1; one end of the capacitor C1 is connected to the power supply, and the other end is connected to the drain of the transistor MP0; the source of the transistor MP1 is connected to the power supply, the gate is connected to one end of the built-in switch S1, the other end of the built-in switch S1 is connected to the drain of the transistor MP0, the other end of the built-in switch S1 is also connected to the gate of the transistor MN3 through the built-in switch S2, and the drain of the transistor MP1 is connected to the source of the transistor MN0; the source of the transistor MP2 is connected to the power supply, the gate is connected to the gate of the transistor MP1, and the drain is connected to the drain of the transistor MP3; the source of the transistor MP3 is connected to the power supply, the gate is connected to the drain through the built-in switch S3, the drain of the transistor MP3 and the drain of the transistor MP2 are connected, and then connected to the drain of the transistor MP1 through the built-in switch S4, also connected to the drain of the transistor MN1, the gate of the transistor MN1 is connected to the bias circuit through the built-in switch S5, and the source of the transistor MN1 is grounded; the source of the transistor MP4 is connected to the power supply, the gate is connected to the gate of the transistor MP3, and the drain is grounded through the resistor Rda, and the drain serves as the output of the low-frequency gain and phase adjustment circuit.

[0011] In a possible implementation, the high-frequency gain and phase adjustment circuit comprises: a bias circuit, a high-frequency coupling capacitor C_HPF, a capacitor C2, N-channel transistors MN0', MN1', P-channel transistors MP0', MP1', MP2', MP3', MP4', built-in switches S1', S2', S3', S4', a high-pass filter circuit composed of a resistor R3 and a capacitor C3, resistors Rda and R2; the gate of the transistor MP0' is connected to the bias circuit, the source is connected to a power supply, and the drain is connected to the drain of the transistor MN0'; the gate of the transistor MN0' is connected to the bias circuit, and the gate is also connected to an input signal through the high-frequency coupling capacitor C_HPF, and the source is grounded through the resistor R2; one end of the capacitor C2 is connected to the power supply, and the other end is connected to the drain of the transistor MP0'; the source of the transistor MP1 is connected to the power supply, the gate is connected to one end of the built-in switch S1', the other end of the built-in switch S1' is connected to the drain of the transistor MP0', the other end of the built-in switch S1' is also connected to the gate of the transistor MN3' through the built-in switch S2', and the drain of the transistor MP1' is connected to the source of the transistor MN0'; the source of the transistor MP2' is connected to the power supply, the gate is connected to the gate of the transistor MP1', and the drain is connected to the drain of the transistor MP3'; the source of the transistor MP3' is connected to the power supply, the gate is connected to the drain through the built-in switch S3', the drain of the transistor MP3' and the drain of the transistor MP2' are connected to the drain of the transistor MP1' through the built-in switch S4', and are also connected to the drain of the transistor MN1'; the gate of the transistor MN1' is connected to the bias circuit through the built-in switch S5', and the source is grounded; the source of the transistor MP4' is connected to the power supply, the gate is connected to the gate of the transistor MP3', the drain is grounded through the resistor R3, the drain is also connected to one end of the capacitor C3, the other end of the capacitor C3 is grounded through the resistor Rda, and the other end of the capacitor C3 is used as an output of the high-frequency gain and phase adjustment circuit.

[0012] In a possible implementation, when the built-in switches S1, S3, S1', S3' are adjusted to be open and S2, S4, S2', S4' are adjusted to be closed, the pixel power supply noise adjustment circuit performs low-frequency compensation and high-frequency compensation on the input signal; when the built-in switches S1, S3, S1', S3' are adjusted to be closed and S2, S4, S2', S4' are adjusted to be open, the pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation, and phase inversion on the input signal.

[0013] In a possible implementation, the input end of the pixel power supply noise adjustment circuit is connected to the input end of the digital-to-analog conversion circuit, and the module unit noise is input.

[0014] In a possible implementation, the pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation, and phase inversion on the input module unit noise, and outputs compensation noise with the same gain and opposite phase as the module unit noise.

[0015] The application also provides a CMOS image sensor employing the power supply noise compensation circuit.

[0016] Compared with the prior art, the application has the following beneficial effects: the built-in switch of the pixel power supply noise adjustment circuit can realize low-frequency compensation, high-frequency compensation and phase inversion, can be flexibly connected with a double-ended comparator or a single-ended comparator, and realizes compensation for the pixel power supply noise; in addition, by changing the connection, the module single noise can also be compensated, and the application has a wide application scenario. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and constitute a part of this application, illustrate embodiments of the application and are used to explain the principle of the application. In the drawings:

[0018] Figure 1 a schematic diagram of the power supply noise compensation circuit provided by the embodiment of the application;

[0019] Figure 2 a schematic diagram of the pixel power supply noise adjustment circuit provided by the embodiment of the application for low-frequency compensation and high-frequency compensation of an input signal;

[0020] Figure 3 a schematic diagram of the pixel power supply noise adjustment circuit provided by the embodiment of the application for phase inversion of an input signal;

[0021] Figure 4 a working principle diagram of the power supply noise compensation when the double-ended input is provided by the embodiment of the application;

[0022] Figure 5 a working principle diagram of the power supply noise compensation when the single-ended input is provided by the embodiment of the application;

[0023] Figure 6 a circuit diagram of the low-frequency gain phase adjustment circuit and the high-frequency gain phase adjustment circuit provided by the embodiment of the application;

[0024] Figure 7 a schematic diagram of the pixel power supply noise adjustment circuit provided by the embodiment of the application for low-frequency compensation when the double-ended input is provided;

[0025] Figure 8 an effect diagram of the low-frequency compensation provided by the embodiment of the application;

[0026] Figure 9 a schematic diagram of the pixel power supply noise adjustment circuit provided by the embodiment of the application for high-frequency compensation when the double-ended input is provided;

[0027] Figure 10 an effect diagram of the high-frequency compensation provided by the embodiment of the application;

[0028] Figure 11 An effect diagram of low frequency compensation and high frequency compensation superposition provided for the embodiment of the present application;

[0029] Figure 12 A schematic diagram of low frequency compensation, high frequency compensation, and phase flip of a pixel power supply noise adjustment circuit provided for the embodiment of the present application when a single-ended input is used;

[0030] Figure 13 A working principle diagram of module single-body noise compensation provided for the embodiment of the present application. DETAILED DESCRIPTION

[0031] Hereinafter, the term "include" or "may include" used in various embodiments of the present application indicates the existence of the applied function, operation, or element and does not limit one or more additions of the function, operation, or element. Also, as used in various embodiments of the present application, the terms "include", "have", and their conjugates merely indicate the presence of the mentioned features, numbers, steps, operations, elements, components, or combinations thereof, and should not be construed as excluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0032] It should be noted that if a description connects one constituent element to another constituent element or is connected to another constituent element, the first constituent element can be directly connected to the second constituent element, and a third constituent element can be "connected" between the first constituent element and the second constituent element. In contrast, when one constituent element is "directly connected" to another constituent element or is "directly connected" to another constituent element, it can be understood that there is no third constituent element between the first constituent element and the second constituent element.

[0033] The terms used in various embodiments of the present application are used only for the purpose of describing particular embodiments and are not intended to limit various embodiments of the present application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly dictates otherwise. Unless otherwise defined, all terms used herein (including technical terms and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present application belong. The terms (such as terms defined in a generally used dictionary) will be interpreted to have the same meaning as the contextual meaning in the relevant technical field and will not be interpreted to have an idealized or overly formal meaning, unless clearly defined in various embodiments of the present application.

[0034] In order to make the purpose, technical solutions and advantages of the present application clearer, further detailed description of the present application will be given below in conjunction with the embodiments and drawings, the illustrative embodiments and their descriptions of the present application are only used to explain the present application, and do not limit the present application.

[0035] Please refer to Figure 1 as shown, Figure 1 The schematic diagram of the power supply noise compensation circuit provided by the embodiment of the present application. The power supply noise compensation circuit comprises: a pixel circuit (AMP in the figure represents a pixel circuit comprising an amplifier, and SEL represents a pixel circuit comprising a selection function), a pixel power supply noise adjusting circuit, a digital-to-analog conversion circuit, a constant current source and a comparator; the input end of the pixel circuit is connected to the pixel power supply, the output end is connected to the ground through the constant current source, and the output end outputs a pixel signal PIX_OUT with power supply noise; the input end of the pixel power supply noise adjusting circuit is connected to the input end of the pixel circuit or the input end of the digital-to-analog conversion circuit, and the output end outputs compensation noise, which is converted into a ramp signal RAMP with compensation noise by the digital-to-analog conversion circuit; the pixel signal PIX_OUT and the ramp signal RAMP are both connected to the comparator through a capacitor, and noise compensation is realized at the input end or the output end of the comparator; wherein the pixel power supply noise adjusting circuit performs low-frequency compensation, high-frequency compensation and phase inversion on the input signal, or performs low-frequency compensation and high-frequency compensation on the input signal through the built-in switch.

[0036] Specifically, the power supply noise compensation circuit is composed of a pixel circuit, a pixel power supply noise adjusting circuit, a digital-to-analog conversion circuit, a constant current source and a comparator. The input end of the pixel power supply noise adjusting circuit can be connected to the input end of the pixel circuit and the input end of the digital-to-analog conversion circuit through external switches K1 and K2 respectively, and the power supply noise or the module single noise is compensated through the gating switch K1 or K2. As Figure 1 shown, for power supply noise compensation, the power supply noise in the pixel power supply is output to the PIX_OUT side through the pixel circuit, and is output to the RAMP side through the pixel power supply noise adjusting circuit and the digital-to-analog conversion circuit, and the PIX_OUT side and the RAMP side input a double-ended comparator or a single-ended comparator, realizing power supply noise compensation. For module single noise compensation, the single noise of the digital-to-analog conversion circuit is output through the pixel power supply noise adjusting circuit, and is opposite to the single noise of itself to offset, realizing module single noise compensation.

[0037] The principle behind this application is that for power supply noise compensation, the noise on both the PIX_OUT and RAMP sides originates from the pixel power supply, representing the same source. However, due to different circuits, the gain and phase deviate. This deviation can be adjusted using a pixel power supply noise adjustment circuit. This circuit then utilizes the common-mode signal suppression characteristics of a two-ended comparator (differential amplifier) ​​to offset most of the noise on the pixel power supply. Alternatively, a single-ended comparator can be used to perform inverse phase cancellation before the signal is input to the comparator. For module unit noise compensation, the pixel power supply noise adjustment circuit directly adjusts the same source noise from the module unit and performs inverse phase cancellation with the module unit noise, eliminating most of the noise on the module unit.

[0038] When compensating for power supply noise (using a single-ended comparator) or module noise, the pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation, and phase flipping on the input homologous noise, obtaining a compensated noise with equal gain and opposite phase to the homologous noise, which is then offset at the output.

[0039] See Figure 2 As shown, Figure 2 This is a schematic diagram of the pixel power supply noise adjustment circuit provided in an embodiment of the present application performing low-frequency compensation and high-frequency compensation on the input signal. In the figure, the horizontal axis is frequency, the vertical axis is gain, the dotted line is the gain of the PIX_OUT side noise, and the solid line is the gain of the RAMP side noise. As shown in the left part of the figure, before adjustment, the low-frequency gain and high-frequency gain of the RAMP side noise are different from the gain of the PIX_OUT side noise, and the effect of cancellation is not achieved; as shown in the right part of the figure, after the low-frequency compensation and high-frequency compensation of the pixel power supply noise adjustment circuit are adjusted, the gain of the RAMP side noise is the same as the gain of the PIX_OUT side noise.

[0040] See Figure 3 As shown, Figure 3 Schematic diagram of the pixel power supply noise adjustment circuit provided in an embodiment of the present application performing a phase flip on the input signal. In the figure, the horizontal axis is time, the vertical axis is gain, the solid line is the phase of the PIX_OUT side noise, and the dotted line is the phase of the RAMP side noise. As shown in the left part of the figure, the phase of the RAMP side noise is consistent with the phase of the PIX_OUT side noise before adjustment; as shown in the right part of the figure, after the phase flip adjustment of the pixel power supply noise adjustment circuit, the phase of the RAMP side noise differs by 180° from the phase of the PIX_OUT side noise, and can be directly superimposed and offset.

[0041] In this way, when compensating for power supply noise (using a single-ended comparator) or module noise, the noise on the RAMP side and the noise on the PIX_OUT side have the same gain but opposite phase. After superposition, the noise on the RAMP side and the noise on the PIX_OUT side cancel each other out, thereby achieving the purpose of noise reduction.

[0042] Similarly, when compensating for power supply noise (using a two-ended comparator), the pixel power supply noise adjustment circuit performs low-frequency and high-frequency compensation on the input homologous noise to obtain a compensated noise with equal gain and the same phase as the homologous noise, and then uses the common-mode rejection characteristics of the two-ended comparator to offset it.

[0043] The improvement of this application lies in that the built-in switch based on the pixel power supply noise adjustment circuit can realize low-frequency compensation, high-frequency compensation, and phase flipping, and can be flexibly connected to a double-ended comparator or a single-ended comparator to achieve compensation for pixel power supply noise; in addition, by changing the connection, the module monomer noise can also be compensated, which has a wide range of application scenarios.

[0044] In a possible implementation, an input terminal of the pixel power supply noise adjustment circuit is connected to an input terminal of the pixel circuit and receives power supply noise.

[0045] Furthermore, when the comparator adopts a dual-ended input, the pixel power supply noise adjustment circuit performs low-frequency compensation and high-frequency compensation on the connected power supply noise, and outputs compensation noise with the same gain and phase as the power supply noise; when the comparator adopts a single-ended input, the pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation and phase flipping on the connected power supply noise, and outputs compensation noise with the same gain and opposite phase as the power supply noise.

[0046] Specifically, see Figure 4 As shown, Figure 4 The working principle diagram of the power supply noise compensation for dual-end input provided in the embodiment of the present application. It mainly uses the characteristic of the dual-end comparator (differential amplifier) ​​that can suppress common-mode signals to offset the noise on the pixel power supply. The noise of the pixel power supply flows through the pixel circuit to the PIX_OUT side of the comparator, and the other path flows through the digital-to-analog conversion circuit to the RAMP side. Because the two noise paths pass through different paths, the phase and gain are different when they reach the input end of the comparator, and the cancellation effect is not achieved. Therefore, it is necessary to add a pixel power supply noise adjustment circuit to adjust the phase and gain of the noise on the RAMP side to be the same as the phase and gain of the noise on the PIX_OUT side, and then achieve the noise cancellation effect through the comparator. That is, the pixel power supply noise adjustment circuit needs to perform low-frequency compensation and high-frequency compensation for the connected power supply noise.

[0047] See Figure 5 As shown, Figure 5The working principle diagram of the power supply noise compensation of the single-ended input is provided for the embodiments of the present application. Since the RAMP and the PIX OUT are input on the same side, in addition to the same gain of the noise on the RAMP side and the noise on the PIX OUT side, the phase of the noise on the RAMP side needs to be flipped by 180°, so as to realize the cancellation of the noise. That is, the pixel power supply noise adjustment circuit needs to perform low-frequency compensation, high-frequency compensation and phase flipping on the input power supply noise.

[0048] In a possible implementation, the pixel power supply noise adjustment circuit comprises a low-frequency gain phase adjustment circuit and a high-frequency gain phase adjustment circuit in parallel; the low-frequency gain phase adjustment circuit comprises a bias circuit, a low-frequency coupling capacitor, a capacitor, a plurality of built-in switches and a plurality of transistors, and the low-frequency compensation and the phase flipping are realized by adjusting the on-off of the plurality of built-in switches; the high-frequency gain phase adjustment circuit comprises a bias circuit, a high-frequency coupling capacitor, a capacitor, a plurality of built-in switches, a plurality of transistors and a high-pass filter circuit, and the high-frequency compensation and the phase flipping are realized by adjusting the on-off of the plurality of built-in switches.

[0049] Specifically, the bias circuit is used to provide a reference voltage for turning on the transistors, the low-frequency / high-frequency coupling capacitor is used to couple the input signal (noise signal) into the circuit, the capacitor is used to adjust the inflection point of the low-frequency / high-frequency compensation, the plurality of built-in switches are used to control the conduction direction of the circuit, the plurality of transistors are used to realize the low-frequency compensation, the high-frequency compensation and the phase flipping in cooperation with the built-in switches, and the high-pass filter circuit is used to filter out the low-frequency part and output the high-frequency part.

[0050] Further, please refer to Figure 6 , and Figure 6The circuit diagram of the low-frequency gain phase adjusting circuit and the high-frequency gain phase adjusting circuit provided by the embodiment of the present application is shown in the following. The low-frequency gain phase adjusting circuit comprises a bias circuit, a low-frequency coupling capacitor C_LPF, a capacitor C1, N-channel transistors MN0 and MN1, P-channel transistors MP0, MP1, MP2, MP3, MP4, built-in switches S1, S2, S3 and S4, resistors Rda and R1. The gate of the transistor MP0 is connected to the bias circuit, the source is connected to a power supply, and the drain is connected to the drain of the transistor MN0. The gate of the transistor MN0 is connected to the bias circuit, and the gate is also connected to an input signal through the low-frequency coupling capacitor C_LPF, and the source is connected to the ground through the resistor R1. One end of the capacitor C1 is connected to the power supply, and the other end is connected to the drain of the transistor MP0. The source of the transistor MP1 is connected to the power supply, and the gate is connected to one end of the built-in switch S1. The other end of the built-in switch S1 is connected to the drain of the transistor MP0, and the other end of the built-in switch S1 is also connected to the gate of the transistor MN3 through the built-in switch S2. The drain of the transistor MP1 is connected to the source of the transistor MN0. The source of the transistor MP2 is connected to the power supply, the gate is connected to the gate of the transistor MP1, and the drain is connected to the drain of the transistor MP3. The source of the transistor MP3 is connected to the power supply, and the gate is connected to the drain through the built-in switch S3. The drain of the transistor MP3 and the drain of the transistor MP2 are connected to the drain of the transistor MP1 through the built-in switch S4, and are also connected to the drain of the transistor MN1. The gate of the transistor MN1 is connected to the bias circuit through the built-in switch S5, and the source of the transistor MN1 is connected to the ground. The source of the transistor MP4 is connected to the power supply, the gate is connected to the gate of the transistor MP3, and the drain is connected to the ground through the resistor Rda. The drain is used as the output of the low-frequency gain phase adjusting circuit.

[0051] Further, still referring to Figure 6As shown, the high-frequency gain and phase adjustment circuit includes: a bias circuit, a high-frequency coupling capacitor C_HPF, a capacitor C2, N-channel transistors MN0', MN1', P-channel transistors MP0', MP1', MP2', MP3', MP4', built-in switches S1', S2', S3', S4', a high-pass filter circuit composed of a resistor R3 and a capacitor C3, and resistors Rda and R2; the gate of the transistor MP0' is connected to the bias circuit, the source is connected to the power supply, and the drain is connected to the drain of the transistor MN0'. The gate of the transistor MN0' is connected to the bias circuit, the gate is also connected to the input signal through the high-frequency coupling capacitor C_HPF, and the source is grounded through the resistor R2; one end of the capacitor C2 is connected to the power supply, and the other end is connected to the drain of the transistor MP0'; the source of the transistor MP1 is connected to the power supply, and the gate is connected to one end of the built-in switch S1', the other end of the built-in switch S1' is connected to the drain of the transistor MP0', and the other end of the built-in switch S1' is connected to the drain of the transistor MP0'. One end is also connected to the gate of transistor MN3' via a built-in switch S2', and the drain of transistor MP1' is connected to the source of transistor MN0'; the source of transistor MP2' is connected to the power supply, the gate is connected to the gate of transistor MP1', and the drain is connected to the drain of transistor MP3'; the source of transistor MP3' is connected to the power supply, the gate is connected to the drain via a built-in switch S3', the drain of transistor MP3' is connected to the drain of transistor MP1 via a built-in switch S4', and is also connected to the drain of transistor MN1'. The gate of transistor MN1' is connected to the bias circuit via a built-in switch S5', and the source of transistor MN1' is grounded; the source of transistor MP4' is connected to the power supply, the gate is connected to the gate of transistor MP3', and the drain is grounded via a resistor R3. The drain is also connected to one end of capacitor C3, the other end of capacitor C3 is grounded via a resistor Rda, and the other end of capacitor C3 serves as the output of the high-frequency gain and phase adjustment circuit.

[0052] Furthermore, when the built-in switches S1, S3, S1', and S3' are opened and S2, S4, S2', and S4' are closed, the pixel power supply noise adjustment circuit performs low-frequency compensation and high-frequency compensation on the input signal; when the built-in switches S1, S3, S1', and S3' are closed and S2, S4, S2', and S4' are opened, the pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation, and phase flipping on the input signal.

[0053] Specifically, when using Figure 4 When the dual-end input comparator shown performs power supply noise compensation, the pixel power supply noise adjustment circuit needs to perform low-frequency compensation and high-frequency compensation on the input signal so that the phase and gain of the noise on the RAMP side are the same as the phase and gain of the noise on the PIX_OUT side.

[0054] See Figure 7 As shown, Figure 7The schematic diagram of the pixel power noise adjusting circuit provided by the embodiment of the present application for low frequency compensation is shown in the figure. In the figure, switches S1, S3 and S5 are in the open state, switches S2 and S4 are in the closed state, and transistors MN1, MP1 and MP2 are in the off state. The figure also shows the flow direction and phase change of the input signal.

[0055] In the low frequency gain phase adjusting circuit, the output path of the input signal is: the input signal passes through the capacitor C_LPF to the gate of MN0 (the phase is unchanged), then flows to the source of MN0 (the phase is unchanged), then flows to the gate of MP3 (the phase changes by 180°), and finally flows through the drain of MP4 and is output (the phase changes by 180°). After passing through the above path, the output signal OUT has the same phase and gain as the input signal (the power noise).

[0056] At this time, the low frequency gain of the output signal OUT is:

[0057] In the formula, Gain_LPF is the low frequency gain of the output signal; Vnoise is the voltage of the input signal; R1 is the resistance R1; g MP4 MP4 is the transconductance of the transistor MP4; g MP3 MP3 is the transconductance of the transistor MP3; and Rda is the output resistance of the digital-to-analog conversion circuit. The current passes through Rda to form a current path, and the resistance value of Rda affects the gain of the pixel power noise adjusting circuit.

[0058] From the derived low frequency gain, it can be seen that if the size of the low frequency gain is to be adjusted, only the number of transistors MP4 and MP3 in parallel needs to be adjusted. In theory, the more the number is, the larger the adjustable range is, and appropriate proportions can be selected according to the actual noise size to reduce the cost. Please refer to the figure shown in Figure 8 , Figure 8 The effect diagram of the low frequency compensation provided by the embodiment of the present application is shown in the figure. In the figure, the horizontal axis represents the frequency, the vertical axis represents the gain, the solid line represents the gain before low frequency compensation, and the dashed line represents the achievable gain range after low frequency compensation.

[0059] Please refer to the figure shown in Figure 9 , Figure 9 The schematic diagram of the pixel power noise adjusting circuit provided by the embodiment of the present application for high frequency compensation is shown in the figure. In the figure, switches S1', S3' and S5' are in the open state, switches S2' and S4' are in the closed state, and transistors MN1', MP1' and MP2' are in the off state. The figure also shows the flow direction and phase change of the input signal. The circuit structure of the high frequency gain phase adjusting circuit is the same as that of the low frequency gain phase adjusting circuit, except that a low-pass high-pass filter circuit is added to the output.

[0060] ​The gain of the output signal OUT is related to the resistance and capacitance properties of the high-pass filter circuit. Assuming that a high-pass filter circuit of fHz is used, the high-frequency gain of the output signal OUT is:

[0061] Gain_HPF_f=20 ,

[0062] Where, Gain_HPF_f: high-frequency gain of the output signal; Vnoise: voltage of the input signal; R2: resistor R2; g MP4’ : Transconductance of transistor MP4'; g MP3’ : transconductance of transistor MP3'; Rda: output resistance of the digital-to-analog converter circuit; R3: resistor R3; Z c3 : Capacitive reactance of capacitor C3. f : frequency of alternating current; c : capacitance value of the capacitor; j : The phase characteristic of the capacitor, that is, the current leads the voltage by 90 degrees.

[0063] It should be noted that although the gain of the high-frequency part at any frequency can be calculated using the formula, the high-frequency gain calculated at this time is the high-frequency gain when the default low-frequency gain is 0. In actual applications, the gain of the high-frequency part will often change with the change of the low-frequency gain, and the adjustment range will change. The reason is that the gain of the high-frequency part is superimposed on the low-frequency gain. When the low-frequency gain is smaller, the adjustable range of the high-frequency part is larger, and vice versa, the adjustable range of the high-frequency part is smaller. Therefore, when adjusting the gain of the high-frequency part, the gain adjustment amount for each step is usually not calculated. Instead, the appropriate high-frequency gain is adjusted according to the actual noise amount.

[0064] See Figure 10 As shown, Figure 10 This is a diagram showing the effect of high-frequency compensation provided by an embodiment of the present application. In the figure, the horizontal axis represents frequency, the vertical axis represents gain, the solid line represents gain before high-frequency compensation, and the dotted line represents the gain range achievable after high-frequency compensation.

[0065] See Figure 11 As shown, Figure 11 This is a diagram showing the effect of superimposing low-frequency compensation and high-frequency compensation according to an embodiment of the present application. When the gain and phase of the compensation noise output by the pixel power supply noise adjustment circuit match the gain and phase of the noise on the PIX_OUT side, the noise is canceled out after passing through the two-terminal comparator.

[0066] When using Figure 5The single-ended input comparator shown performs power supply noise compensation. The pixel power supply noise adjustment circuit needs to perform low frequency compensation, high frequency compensation and phase reversal on the input signal, so that the gain of the RAMP side noise is the same as that of the PIX_OUT side noise and the phase is opposite.

[0067] Please refer to Figure 12 shown, Figure 12 The single-ended input pixel power supply noise adjustment circuit provided in the embodiment of the present application performs low frequency compensation, high frequency compensation and phase reversal. In the figure, switches S2, S4, S2' and S4' are in an open state, and switches S1, S3, S5, S1', S3' and S5' are in a closed state. The figure also shows the flow direction and phase change of the input signal.

[0068] At this time, the low frequency gain of the output signal OUT is Gain_LPF=20log( );

[0069] In the formula, Gain_LPF: low frequency gain of the output signal; Vnoise: voltage of the input signal; R1: resistance R1; g MP2 : transconductance of transistor MP2; g MP1 : transconductance of transistor MP1; g MP4 : transconductance of transistor MP4; g MP3 : transconductance of transistor MP3; Rda: output resistance of the digital-to-analog conversion circuit.

[0070] Assuming that a high-pass filter circuit with fHz is used here, the high frequency gain of the output signal OUT is:

[0071] Gain_HPF_f=20 ,

[0072] In the formula, Gain_HPF_f: high frequency gain of the output signal; Vnoise: voltage of the input signal; R2: resistance R2; g MP2’ : transconductance of transistor MP2'; g MP1’ : transconductance of transistor MP1'; g MP4’ : transconductance of transistor MP4'; g MP3’ : transconductance of transistor MP3'; Rda: output resistance of the digital-to-analog conversion circuit; R3: resistance R3; Z c3 : capacitive reactance of capacitor C3. f : frequency of alternating current; c : capacitance value of capacitor; j : phase characteristic of capacitor, i.e. current leading voltage by 90 degrees.

[0073] Taking the low-frequency gain and phase adjustment circuit as an example, the output path of the input signal is: MN0's gate → MN0's source (phase flipped 180°) → MP2's gate → MP2's source (phase flipped 180°) → MP4's gate → MP4's source (phase flipped 180°). After this path, the output signal OUT has a 180° phase flip compared to the input signal.

[0074] At this point, when using a single-ended input comparator for power supply noise compensation, the pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation, and phase flipping on the input signal, ensuring that the RAMP-side noise and the PIX_OUT-side noise have the same gain and opposite phases. The RAMP-side noise and the PIX_OUT-side noise cancel each other out at the comparator input, making the comparator input cleaner.

[0075] In a possible implementation, an input end of the pixel power supply noise adjustment circuit is connected to an input end of the digital-to-analog conversion circuit and receives module unit noise.

[0076] Furthermore, the pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation and phase flipping on the connected module monomer noise, and outputs compensation noise with the same gain and opposite phase as the module monomer noise.

[0077] Specifically, see Figure 13 As shown, Figure 13 This diagram illustrates the working principle of module noise compensation provided by an embodiment of the present application. By introducing the module noise to be compensated (the power supply noise of the digital-to-analog conversion circuit in the figure) into the pixel power supply noise adjustment circuit, low-frequency compensation, high-frequency compensation, and phase inversion are performed to obtain compensation noise with equal gain and opposite phase. The compensation noise and module noise are directly canceled out at the output. This demonstrates that, in addition to compensating for pixel power supply noise, the present application can also compensate for module noise.

[0078] In addition, the embodiment of the present application also provides a CMOS image sensor, which adopts Figure 1 The power supply noise compensation circuit shown in the figure can effectively reduce pixel power supply noise and improve imaging effects.

[0079] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A power supply noise compensation circuit, characterized in that: include: Pixel circuit, pixel power supply noise adjustment circuit, digital-to-analog conversion circuit, constant current source and comparator; The input end of the pixel circuit is connected to the pixel power supply, the output end is grounded through the constant current source, and the output end outputs a pixel signal PIX_OUT with power supply noise; The input end of the pixel power supply noise adjustment circuit is connected to the input end of the pixel circuit or the input end of the digital-to-analog conversion circuit, and the output end outputs compensation noise, and the compensation noise is converted into a ramp signal RAMP with compensation noise by the digital-to-analog conversion circuit; The pixel signal PIX_OUT and the ramp signal RAMP are connected to the comparator to implement noise compensation at the input or output of the comparator; The pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation and phase reversal on the input signal through a built-in switch, or performs low-frequency compensation and high-frequency compensation on the input signal.

2. The power supply noise compensation circuit according to claim 1, characterized in that: The input end of the pixel power supply noise adjustment circuit is connected to the input end of the pixel circuit and receives power supply noise.

3. The power supply noise compensation circuit according to claim 2, characterized in that: When the comparator adopts a double-ended input, the pixel power supply noise adjustment circuit performs low-frequency compensation and high-frequency compensation on the input power supply noise, and outputs compensation noise with the same gain and phase as the power supply noise; When the comparator adopts a single-ended input, the pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation and phase flipping on the input power supply noise, and outputs compensation noise with the same gain and opposite phase as the power supply noise.

4. The power supply noise compensation circuit according to claim 1, wherein: The pixel power supply noise adjustment circuit includes: A low-frequency gain and phase adjustment circuit and a high-frequency gain and phase adjustment circuit connected in parallel; The low-frequency gain and phase adjustment circuit includes: a bias circuit, a low-frequency coupling capacitor, a capacitor, a plurality of built-in switches and a plurality of transistors, and realizes low-frequency compensation and phase reversal by adjusting the on and off of the plurality of built-in switches; The high-frequency gain phase adjustment circuit includes: a bias circuit, a high-frequency coupling capacitor, a capacitor, multiple built-in switches, multiple transistors and a high-pass filter circuit, and achieves high-frequency compensation and phase reversal by adjusting the on-off of multiple built-in switches.

5. The power supply noise compensation circuit according to claim 4, characterized in that: The low-frequency gain phase adjustment circuit comprises: Bias circuit, low-frequency coupling capacitor C_LPF, capacitor C1, N-channel transistors MN0, MN1, P-channel transistors MP0, MP1, MP2, MP3, MP4, built-in switches S1, S2, S3, S4, resistors Rda, R1; The gate of the transistor MP0 is connected to the bias circuit, the source is connected to the power supply, the drain is connected to the drain of the transistor MN0, the gate of the transistor MN0 is connected to the bias circuit, the gate is also connected to the input signal through the low-frequency coupling capacitor C_LPF, and the source is grounded through the resistor R1; One end of the capacitor C1 is connected to the power supply, and the other end is connected to the drain of the transistor MP0; The source of the transistor MP1 is connected to the power supply, the gate is connected to one end of the built-in switch S1, the other end of the built-in switch S1 is connected to the drain of the transistor MP0, the other end of the built-in switch S1 is also connected to the gate of the transistor MN3 via the built-in switch S2, and the drain of the transistor MP1 is connected to the source of the transistor MN0; The source of the transistor MP2 is connected to the power supply, the gate is connected to the gate of the transistor MP1, and the drain is connected to the drain of the transistor MP3; The source of transistor MP3 is connected to the power supply, and the gate is connected to the drain via a built-in switch S3. The drain of transistor MP3 is connected to the drain of transistor MP2 and then to the drain of transistor MP1 via a built-in switch S4. The drain of transistor MN1 is also connected. The gate of transistor MN1 is connected to the bias circuit via a built-in switch S5. The source of transistor MN1 is grounded. The source of the transistor MP4 is connected to the power supply, the gate is connected to the gate of the transistor MP3, the drain is grounded via the resistor Rda, and the drain serves as the output of the low-frequency gain phase adjustment circuit.

6. The power supply noise compensation circuit according to claim 5, characterized in that: The high-frequency gain phase adjustment circuit comprises: A bias circuit, a high-frequency coupling capacitor C_HPF, a capacitor C2, N-channel transistors MN0', MN1', P-channel transistors MP0', MP1', MP2', MP3', MP4', built-in switches S1', S2', S3', S4', a high-pass filter circuit consisting of a resistor R3 and a capacitor C3, and resistors Rda and R2; The gate of the transistor MP0' is connected to the bias circuit, the source is connected to the power supply, the drain is connected to the drain of the transistor MN0', the gate of the transistor MN0' is connected to the bias circuit, the gate is also connected to the input signal through the high-frequency coupling capacitor C_HPF, and the source is grounded through the resistor R2; One end of the capacitor C2 is connected to the power supply, and the other end is connected to the drain of the transistor MP0'; The source of the transistor MP1 is connected to the power supply, the gate is connected to one end of the built-in switch S1', the other end of the built-in switch S1' is connected to the drain of the transistor MP0', the other end of the built-in switch S1' is also connected to the gate of the transistor MN3' via the built-in switch S2', and the drain of the transistor MP1' is connected to the source of the transistor MN0'; The source of the transistor MP2' is connected to the power supply, the gate is connected to the gate of the transistor MP1', and the drain is connected to the drain of the transistor MP3'; The source of transistor MP3' is connected to the power supply, and the gate is connected to the drain via a built-in switch S3'. The drain of transistor MP3' is connected to the drain of transistor MP2' and then to the drain of transistor MP1 via a built-in switch S4'. The drain of transistor MN1' is also connected to the drain of transistor MN1'. The gate of transistor MN1' is connected to the bias circuit via a built-in switch S5'. The source of transistor MN1' is grounded. The source of transistor MP4' is connected to the power supply, the gate is connected to the gate of transistor MP3', the drain is grounded through resistor R3, and the drain is also connected to one end of capacitor C3. The other end of capacitor C3 is grounded through resistor Rda. The other end of capacitor C3 serves as the output of the high-frequency gain phase adjustment circuit.

7. The power supply noise compensation circuit according to claim 6, characterized in that: When the built-in switches S1, S3, S1', and S3' are opened and S2, S4, S2', and S4' are closed, the pixel power supply noise adjustment circuit performs low-frequency compensation and high-frequency compensation on the input signal; when the built-in switches S1, S3, S1', and S3' are closed and S2, S4, S2', and S4' are opened, the pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation, and phase flipping on the input signal.

8. The power supply noise compensation circuit according to claim 1, characterized in that: The input end of the pixel power supply noise adjustment circuit is connected to the input end of the digital-to-analog conversion circuit and is connected to the module monomer noise.

9. The power supply noise compensation circuit according to claim 8, characterized in that: The pixel power supply noise adjustment circuit performs low-frequency compensation, high-frequency compensation and phase flipping on the connected module monomer noise, and outputs compensation noise with the same gain and opposite phase as the module monomer noise.

10. A CMOS image sensor, characterized in that: It adopts a power supply noise compensation circuit as described in any one of claims 1-9.

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