Waveform data storage method, waveform data reading method, system and electronic device

Abstract

The present application relates to a waveform data storage method, a waveform data reading method, a system, and an electronic device. The method includes: a logic processing module receives waveform data sent by an upper-level module; the waveform data is the original waveform data of testing at least one valid pin, which is cyclically split and sent according to a preset first bit number, and the upper-level module sends waveform data corresponding to one valid pin each time; the logic processing module stores the received waveform data in a storage unit in sequence; waveform data sent at the same time is stored in the same row, and waveform data sent at different times is stored in different rows; the logic processing module receives at least one first linked list sent by the upper-level module and stores it in a storage unit; each first linked list records the first starting address and first ending address of at least a portion of the waveform data in the storage unit, and the first starting address and first ending address are used to read the corresponding waveform data from the storage unit. The above method can improve testing efficiency.

Description

Technical Field

[0001] The present application relates to the field of digital testing technology, and in particular to a waveform data storage method, a waveform data reading method, a system, and an electronic device. Background Art

[0002] In digital testing scenarios, pin testing is often involved. Typically, there are a large number of pins, and corresponding waveform data (pattern data) is pre-set for each pin. This waveform data is the test data or test vector used to test the corresponding pin.

[0003] Traditionally, when executing a test task, waveform data for all pins is stored in a memory cell, such as DDR (Double Data Rate SDRAM). Due to the large number of pins, storing waveform data for all pins in the memory cell results in a lengthy write operation, thus affecting test efficiency. Summary of the Invention

[0004] Based on this, it is necessary to provide a waveform data storage method, waveform data reading method, system, electronic device, computer-readable storage medium and computer program product that can improve test efficiency in response to the above technical problems.

[0005] In a first aspect, the present application provides a waveform data storage method, the method comprising: a logic processing module receiving waveform data sent down by an upper-layer module; the waveform data is the original waveform data for testing a valid pin that is cyclically split and sent down by the upper-layer module according to a preset first bit number, wherein the valid pin is the pin to be tested in the current test task, there is at least one valid pin, and the upper-layer module sends down waveform data corresponding to one valid pin each time; the logic processing module stores the received waveform data in a storage unit in sequence; wherein the waveform data sent down at the same time are stored in the same row, and the waveform data sent down at different times are stored in different rows; the logic processing module receives at least one first linked list sent down by the upper-layer module, and stores at least one first linked list in the storage unit; wherein each first linked list records a first starting address and a first ending address of at least a part of the waveform data in the storage unit; the first starting address and the first ending address are used to read the corresponding waveform data from the storage unit.

[0006] In one embodiment, the waveform data includes waveform data shared by at least two valid pins; the shared waveform data is not repeatedly transmitted. Before the logic processing module receives the waveform data transmitted by the upper-level module, the method further includes: the logic processing module receives a group identifier transmitted by the upper-level module, the group identifier being used to indicate at least two valid pins that share the same waveform data; after receiving the shared waveform data, the method further includes: the logic processing module copying the shared waveform data according to the number of valid pins indicated by the group identifier. The logic processing module sequentially stores the received waveform data in a storage unit, including: the logic processing module sequentially storing the waveform data transmitted by the upper-level module and the copied waveform data in the storage unit according to the corresponding valid pins.

[0007] In one embodiment, the method also includes: the logic processing module receives the first starting address and the first total number of rows sent by the upper module; the first starting address is the starting address of the waveform data stored in the storage unit, and the first total number of rows is the total number of rows of the waveform data stored in the storage unit; the logic processing module stores the received waveform data in the storage unit in sequence, including: the logic processing module stores the received waveform data in the storage unit in sequence according to the first starting address and the first total number of rows.

[0008] In one embodiment, a current test task includes at least one test item; in at least one first linked list received by a logic processing module, each first linked list corresponding to the same test item forms a linked list group; the linked list group is sent to the logic processing module in batches according to a preset second number of bits; and storing at least one first linked list in a storage unit includes: the logic processing module stores the first linked lists sent at the same time in the same row in the storage unit, and stores the first linked lists sent at different times in different rows in the storage unit.

[0009] In one embodiment, the method further includes: the logic processing module receives microinstruction data sent by the upper-level module; the microinstruction data is data formed by the upper-level module combining multiple microinstructions in an execution order and satisfying a preset second number of bits; the logic processing module stores the received microinstruction data in a storage unit; the logic processing module receives at least one second linked list sent by the upper-level module, and stores at least one second linked list in the storage unit, wherein each second linked list records a second starting address and a second ending address of a portion of the microinstruction data in the storage unit, and the second starting address and the second ending address are used to read the corresponding microinstruction data from the storage unit.

[0010] In one embodiment, each microinstruction includes a cycle identifier, an operation code, waveform setting data, and an operand of a test cycle; wherein the operation code is used to specify the operation to be performed; and the operation codes and / or waveform setting data in the microinstructions of adjacent test cycles are different.

[0011] In one embodiment, one test item corresponds to one second linked list; the microinstruction data indicated by the second linked list corresponding to each test item includes a plurality of microinstructions related to the test item.

[0012] In the second aspect, the present application also provides a waveform data reading method, which includes: a logic processing module receives a test start instruction issued by an upper-level module; wherein the test start instruction includes a first target linked list address; the logic processing module obtains a first target linked list indicated by the first target linked list address from a storage unit, wherein the first target linked list is one or more of the first linked lists stored in the storage unit; the first linked list is used to record a first starting address and a first ending address of at least a part of the waveform data in the storage unit; the waveform data of the valid pins is stored in the storage unit, and the waveform data stored in the same row corresponds to the same valid pin, and the waveform data of different valid pins are stored in different rows; the logic processing module reads the corresponding target waveform data from the storage unit according to the first starting address and the first ending address in the first target linked list; the logic processing module executes the test according to the target waveform data.

[0013] In one embodiment, the test start instruction also includes a second target linked list address; the method also includes: the logic processing module obtains the second target linked list indicated by the second target linked list address from the storage unit; wherein the second target linked list is one or more of the second linked lists stored in the storage unit; the second linked list is used to record the second starting address and the second ending address of the microinstruction data stored in the storage unit; according to the second starting address and the second ending address in the second target linked list, the corresponding target microinstruction data is read from the storage unit; the logic processing module executes the test according to the target waveform data, including: the logic processing module executes the test according to the target waveform data and the target microinstruction data.

[0014] In one embodiment, the logic processing module performs a test based on the target waveform data and the target microinstruction data, including: for each line of waveform data corresponding to each valid pin in the target waveform data, the logic processing module splits each line of waveform data multiple times and stores it in the first first-in-first-out queue corresponding to the valid pin; the logic processing module reads the sub-waveform data corresponding to the same target test cycle of each valid pin from the first first-in-first-out queue corresponding to each valid pin according to a preset third bit number, and vectorizes the sub-waveform data corresponding to each valid pin to obtain a waveform test vector; the logic processing module splits multiple microinstructions in the read target microinstruction data, and stores the split single microinstructions in the second first-in-first-out queue in sequence; the logic processing module reads the microinstruction carrying the cycle identifier of the target test cycle from the second first-in-first-out queue, discards the cycle identifier in the read microinstruction, and reorganizes it in vector form to generate a microinstruction vector; and performs a test based on the waveform test vector and the microinstruction vector.

[0015] In a third aspect, the present application also provides another waveform data storage method, which includes: the upper-level module sends the original waveform data of multiple valid pins targeted by the current test task to the logic processing module in multiple rounds according to a preset first bit number, so that the logic processing module stores the sent waveform data in sequence in the storage unit; wherein, in each round, the upper-level module sends the waveform data of each valid pin in sequence according to a preset first bit number based on the preset order between the multiple valid pins; the upper-level module sends the waveform data corresponding to one valid pin each time; the waveform data sent at the same time are stored in the same row in the storage unit, and the waveform data sent at different times are stored in different rows in the storage unit; the upper-level module generates at least one first linked list and sends each first linked list to the logic processing module; each first linked list is used to record the first starting address and the first ending address of at least a part of the waveform data in the storage unit; the upper-level module obtains the first linked list addresses corresponding to each first linked list returned by the logic processing module, and records the correspondence between each first linked list address and each test item in the current test task; In response to the test trigger operation for the target test item in the current test task, the first target linked list address corresponding to the target test item is obtained based on the corresponding relationship, and a test start instruction carrying the first target linked list address is generated and issued, so that the logic processing module obtains the corresponding target waveform data based on the first target linked list address to perform the test.

[0016] In one embodiment, the upper-layer module splits and sends the original waveform data of multiple valid pins targeted by the current test task to the logic processing module in a cyclic manner according to a preset first bit number, including: the upper-layer module sends the original waveform data of multiple valid pins to the logic processing module in a cyclic manner according to a preset first bit number for multiple rounds until the original waveform data of multiple valid pins are sent; in each round, the upper-layer module sends the waveform data of each valid pin in sequence according to a preset first bit number based on a preset order between the multiple valid pins.

[0017] In one embodiment, each first linked list is sent to the logic processing module, including: for each test item in the current test task, the upper-level module groups the first linked lists corresponding to the test item into a group to form a linked list group, and sends the linked list group in batches according to a preset second number of bits.

[0018] In one embodiment, the method also includes: the upper-level module parses the microinstruction configuration data to obtain the operation code and waveform setting data corresponding to each test cycle; for any test cycle, if the operation code and / or waveform setting data corresponding to the test cycle changes compared with the previous test cycle, the upper-level module generates a microinstruction based on the cycle identifier of the test cycle, the operation code and waveform setting data corresponding to the test cycle, and the operand corresponding to the test cycle; the upper-level module combines the multiple generated microinstructions in an execution order to form microinstruction data that meets the second bit number and sends it to the logic processing module.

[0019] In a fourth aspect, the present application further provides a waveform data storage system, which includes an upper layer module, a communication board and a digital board; the digital board includes a logic processing module and a storage unit;

[0020] The upper layer module is used to cyclically split the original waveform data of the valid test pin according to the preset first bit number and send it to the communication board; wherein the valid pin is the pin to be tested in the current test task, there is at least one valid pin, and the upper layer module sends the waveform data corresponding to one valid pin each time;

[0021] The communication board is used to convert the format of the waveform data sent each time, and send the converted waveform data that is adapted to the format supported by the digital board to the logic processing module in the digital board;

[0022] A logic processing module, configured to sequentially store the received waveform data in a storage unit; wherein waveform data sent at the same time are stored in the same row, and waveform data sent at different times are stored in different rows;

[0023] The upper layer module is further used to send at least one first linked list to the communication board; wherein each first linked list records a first starting address and a first ending address of at least a portion of the waveform data in the storage unit, and the first starting address and the first ending address are used to read the corresponding waveform data from the storage unit;

[0024] The communication board is further used to transparently transmit the at least one first linked list sent to the logic processing module;

[0025] The logic processing module is further configured to store at least one first linked list in the storage unit.

[0026] In a fifth aspect, the present application provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps in the method mentioned in the first aspect when executing the computer program.

[0027] In a sixth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the method mentioned in the first aspect when the computer program is executed by a processor.

[0028] In a seventh aspect, the present application provides a computer program product, comprising a computer program, which implements the steps of the method mentioned in the first aspect when executed by a processor.

[0029] In the aforementioned waveform data storage and reading method, system, electronic device, storage medium, and computer program product, the upper-level module only needs to transmit waveform data for the pins to be tested in the current test task—the active pins. Specifically, the original waveform data used to test the active pins is cyclically split and transmitted according to a preset first bit number, with waveform data corresponding to one active pin being transmitted each time. The logic processing module stores waveform data transmitted at the same time in the same row, and waveform data transmitted at different times in different rows. In this way, each row in the storage unit stores waveform data for only one active pin, and different active pins are stored in different rows, thus achieving column-based storage of waveform data based on pins. The logic processing module also stores at least one first linked list in the storage unit, each of which records the first starting address and first ending address of a portion of waveform data in the storage unit. This allows for convenient access to waveform data for active pins during subsequent testing phases based on the first starting address and first ending address in the first linked list. By combining this new column-based storage method with a linked list, while meeting test requirements, it is possible to specifically store only the waveform data of valid pins in the storage unit without storing the waveform data of all pins, which greatly reduces the write operation of the storage unit and improves test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic flow chart of a waveform data storage method according to an embodiment;

[0031] Figure 2 is a schematic diagram of storing waveform data by column in one embodiment;

[0032] Figure 3 A schematic diagram of the principle of waveform data storage in one embodiment;

[0033] Figure 4 A schematic diagram showing the principle of a microinstruction data storage method according to one embodiment;

[0034] Figure 5 1 is a flow chart of a waveform data reading method according to an embodiment;

[0035] Figure 6 Schematic diagram of the principle of a waveform data reading method in one embodiment;

[0036] Figure 7 A schematic flow chart of a waveform data storage method according to another embodiment;

[0037] Figure 8 FIG. 1 is a diagram showing the internal structure of an electronic device in one embodiment. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0039] In traditional methods, the logic processing module stores the pattern data for all pins by row. That is, a row of memory cells stores the pattern data for each pin within the same test cycle. However, during a test, only some pins may need to be tested, and the untested pins are considered invalid. Since storing the pattern data for invalid pins also involves a write operation to the memory cells, this affects test efficiency. Furthermore, storing the pattern data for invalid pins wastes storage space, reducing the data storage depth of valid pins (i.e., the available storage space for valid pins is relatively reduced), and the corresponding maximum supported cycle is also reduced.

[0040] The embodiments of this application address the aforementioned issues with traditional methods by proposing a novel storage method or structure. Specifically, this method stores pattern data for valid pins on a column-by-column basis (i.e., on a pin-by-pin basis), rather than storing pattern data for all pins, thereby improving testing efficiency. Furthermore, a corresponding novel data retrieval method is proposed for this novel storage method, as described below.

[0041] In one embodiment, Figure 1 As shown, a waveform data storage method is provided, which is described by taking the application of the method to a logic processing module as an example. The method includes the following steps:

[0042] S102, the logic processing module receives the waveform data sent by the upper module; the waveform data is the original waveform data for testing the valid pins split and sent by the upper module according to the preset first bit number, and the upper module sends the waveform data corresponding to one valid pin each time.

[0043] Among them, the valid pins are the pins that need to be tested in the current test task, and there is at least one valid pin.

[0044] The upper-layer module may include a host computer and / or a driver. For example, the host computer may be a PC (Personal Computer), a workstation, or an ARM processor, and the logic processing module may be an ASIC (Application-Specific Integrated Circuit) or an FPGA (Field-Programmable Gate Array).

[0045] Specifically, users can configure a waveform file (pattern file) based on the upper-level module. This waveform file includes the original pattern data of the configured valid pins. The upper-level module obtains the original pattern data of multiple valid pins configured by the user for the current test task and sends the pattern data in units of pins, that is, sending the pattern data of one valid pin at a time. The size of each sent pattern data conforms to the first number of bits (part of the original pattern data of the valid pin). In this way, the logic processing module receives partial pattern data for the same valid pin each time.

[0046] The first number of bits may be 640 bits or other values, which is determined by the number of bits supported by a single row in the storage unit.

[0047] In some examples, the upper-layer module may send the original pattern data of multiple valid pins to the logic processing module in multiple rounds according to a preset first number of bits until the original pattern data of the multiple valid pins is sent. In each round, the upper-layer module sends the pattern data of each valid pin in sequence according to the preset first number of bits based on a preset order among the multiple valid pins.

[0048] For example, if the first bit number is 640 bits, and there are three valid pins: Pin1, Pin3, and Pin9, in the first round of delivery, the 640-bit pattern data for Pin1, the 640-bit pattern data for Pin3, and the 640-bit pattern data for Pin9 are delivered in the order of Pin1->Pin3->Pin9, completing one round of delivery. Then, in the second round of delivery, the new 640-bit pattern data is delivered starting with Pin1, in the order of Pin1->Pin3->Pin9. This completes multiple rounds of delivery.

[0049] like Figure 2 As shown, on the side of the logic processing module, the storage method corresponding to the sending method is: storing Pin1 waveform data, Pin3 waveform data and Pin9 waveform data in sequence. After one round of storage, continue to store the next round of Pin1 waveform data, Pin3 waveform data and Pin9 waveform data in sequence in the order of Pin1->Pin3->Pin9. And so on, until all the waveform data sent is stored. For example, assuming that the total number of rows to be stored is 1000 rows, then all the waveform data written in the storage unit will be stored. The total number of rows to be stored can be determined based on the total number of bits to be stored and the number of bits supported by each row in the storage unit.

[0050] S104 , the logic processing module stores the received waveform data in the storage unit in sequence; wherein, the waveform data sent at the same time are stored in the same row, and the waveform data sent at different times are stored in different rows.

[0051] The storage unit may be DDR (Double Data Rate), SSD (Solid State Drive), Flash (flash memory), BlockRAM (Block Random Access Memory), etc.

[0052] Specifically, the logic processing module can store the received pattern data in the storage unit in the order in which it was issued. It should be understood that since each time the pattern data for a valid pin is issued, a row in the storage unit stores the pattern data for the same valid pin, and pattern data for different valid pins is stored in different rows in the storage unit. In this way, the pattern data for valid pins is stored by column.

[0053] In some examples, each time a pattern data is sent down from an upper-layer module, it is sent down to the logic processing module on the digital interface card (DIO) via the communication interface card (CTI). The communication interface card converts the pattern data sent down from the upper-layer module to a format compatible with the bus format and then sends the converted pattern data, now compatible with the format supported by the digital interface card, to the logic processing module on the digital interface card.

[0054] like Figure 3 As shown in the figure, the upper-layer module sequentially transmits 640 bits of waveform data for each of the 32 valid pins. The communication board performs a 4-bit to 3-bit conversion operation, converting the single 640-bit waveform data into 480 bits for transmission. The FPGA in the digital board stores the 480-bit waveform data by column in the storage unit. That is, each row stores the 480-bit waveform data for a valid pin, sequentially storing the waveform data from Pin 0 to Pin 31. After completing one round of storage, the next round of 480-bit waveform data from Pin 0 to Pin 31 is stored, starting with Pin 0, until all the transmitted waveform data is stored.

[0055] In some embodiments, the logic processing module receives the first first address and the first total number of rows sent by the upper layer module. In the embodiment of the present application, step S104 includes: the logic processing module sequentially stores the received pattern data in the storage unit according to the first first address and the first total number of rows.

[0056] The first starting address is the starting address of the pattern data stored in the storage unit, and the first total number of rows is the total number of rows of pattern data to be stored in the storage unit. In each embodiment of the present application, the total number of rows of data such as pattern data, microinstruction data, and linked list data can also be referred to as the total length of the data.

[0057] Specifically, the storage unit is pre-allocated with storage area 1, which is used to store pattern data for all valid pins. The upper-level module can pre-acquire the first starting address (i.e., the first address in storage area 1) and the first total number of rows corresponding to the pattern data and send them to the logic processing module. The logic processing module can locate the starting location of the pattern data in the storage unit based on the first starting address and then sequentially store the received pattern data until the number of rows stored reaches the first total number of rows, indicating that the pattern data is completely stored.

[0058] S106, the logic processing module receives at least one first linked list sent down by the upper-level module, and stores at least one first linked list in the storage unit; wherein, each first linked list records the first starting address and the first ending address of at least a part of the waveform data in the storage unit, and the first starting address and the first ending address are used to read the corresponding waveform data from the storage unit.

[0059] Specifically, the upper-level module can generate at least one first linked list (i.e., a waveform data linked list) based on the transmitted pattern data and send it to the logic processing module for storage. When a test is initiated for the current test task, the logic processing module can retrieve the pattern data of the valid pins to be tested based on the first starting address and first ending address in the first linked list and execute the test.

[0060] In some embodiments, as shown in Table 1, the first linked list includes fields such as the start address, the end address, the flag of the last linked list, the number of valid pins, the flag of the valid pins, and the pin order.

[0061] The starting address (i.e., the first starting address) is the address at which pattern data begins to be stored in the storage unit, and the ending address (i.e., the first ending address) is the address at which pattern data ends to be stored in the storage unit. The last linked list flag (Last_flag) is used to identify the last linked list in the linked list group (the last linked list). If a first linked list is the last linked list, the value of Last_flag is set to 1. The valid pin flag is used to identify valid pins. Assuming there are 32 pins, if a first linked list is used to record the starting and ending addresses of the pattern data after storage for Pins 1, 3, and 9, the "valid pin flag" field occupies 32 bits, with each bit corresponding to a pin. The bits corresponding to Pins 1, 3, and 9 can be set to 1, while the bits corresponding to other pins can be set to 0. In Table 1, the "Number of valid pins" field corresponds to [7:0], indicating that this field occupies 8 bits. In this example, the number of valid pins is 3. Pin sequence, used to indicate the order of pins when sending Pattern data.

[0062] It should be understood that the first linked list may have fewer or more fields than those shown in Table 1. For example, it may also include other fields such as first offset information (see description below), code pattern, etc., which is not limited to this.

[0063] Table 1

[0064]

[0065] In some embodiments, the pattern file includes multiple sub-files, each sub-file includes pattern data of a portion of valid Pins, and the pattern data in all sub-files constitute the complete original pattern data of all valid Pins. For each sub-file, the upper-level module can obtain the first starting address and the first ending address of the pattern data stored in the sub-file, and generate the first linked list corresponding to the sub-file based on the first starting address and the first ending address. Exemplarily, the upper-level module can also generate the first linked list corresponding to the sub-file based on the first starting address and the first ending address, as well as the first offset information. The first offset information is used to indicate the end bit of the last row of actual pattern data recorded in the first linked list.

[0066] In some examples, the upper-level module can calculate the first starting address and first ending address corresponding to the pattern data in each sub-file in the storage unit based on the first starting address, the amount of pattern data sent at a single time, and the order in which the pattern data of the configured valid pins are sent.

[0067] In other examples, after storing the pattern data, the logic processing module can return the first storage address of each stored pattern data to the upper module. The upper module can determine the first starting address and the first ending address based on the first storage addresses corresponding to the pattern data in the same subfile.

[0068] In some embodiments, the current test task includes at least one test item; in at least one first linked list received by the logic processing module, each first linked list corresponding to the same test item forms a linked list group; the linked list group is sent to the logic processing module in batches according to a preset second number of bits.

[0069] It should be understood that each test item in the current test task has corresponding pattern data (for example, each test item has one or more corresponding subfiles, each of which contains its corresponding pattern data). Each test item has at least one corresponding first linked list, and the first linked list corresponding to each test item is used to record the first starting address and first ending address of the pattern data corresponding to the test item.

[0070] For each test item, the upper-layer module may group the first linked lists corresponding to the test item into a linked list group. For example, the end bit of the last first linked list in the linked list group is assigned a value of 1. The upper-layer module may distribute the data in the linked list group (i.e., a group of continuous data) to the logic processing module in batches according to a preset second bit number. The logic processing module stores the first linked lists distributed at the same time in the same row in the storage unit, and stores the first linked lists distributed at different times in different rows in the storage unit.

[0071] For example, the second number of bits may be 480 bits, that is, 480 bits of linked list data in the linked list group are sent each time. One test item may correspond to multiple rows of 480 bits of linked list data.

[0072] It should be understood that the total amount of data in the linked list group corresponding to a test item may not be an integer multiple of 480 bits. Therefore, if the last row (i.e., the last row sent) contains less than 480 bits, the upper-layer module can pad the remaining bits with zeros to reach 480 bits before sending it again. The upper-layer module can also record the second offset information, which indicates the remainder, that is, the end bit of the actual first linked list data in the last row.

[0073] In some examples, a storage area 2 is pre-divided in the storage unit, i.e., all first linked lists are independently stored in storage area 2. The upper-layer module can pre-acquire the second starting address of the first linked list stored in storage area 2 and the second total number of rows to be stored in the first linked list, and send them to the logic processing module. The logic processing module can locate the starting location of storage of the first linked list in the storage unit based on the second starting address, thereby sequentially storing the received first linked list until the number of rows stored reaches the second total number of rows.

[0074] In some embodiments, the logic processing module can return the storage address of the first linked list to the upper-level module, recorded as the first linked list address. The upper-level module can record the correspondence between each first linked list address and each test item in the current test task. The first linked list indicated by the first linked list address corresponding to each test item is used to record the first starting address and first ending address of the pattern data corresponding to the test item.

[0075] When a test trigger operation is received for a target test item, the upper-level module can respond to the test trigger operation, obtain the first linked list address corresponding to the target test item based on the above-mentioned recorded correspondence, generate and issue a test start instruction carrying the first linked list address, so that the logic processing module obtains the corresponding target Pattern data based on the carried first linked list address to perform the test.

[0076] In the above method, the upper module only needs to send down a part of the waveform data of the valid pin in multiple cycles. The logic processing module can store the waveform data based on the pins in columns, and store at least one first linked list in the storage unit, and each first linked list records the first starting address and the first ending address of a part of the waveform data in the storage unit. In this way, when it is necessary to obtain the waveform data of the valid pins in the subsequent test stage, the corresponding waveform data can be conveniently obtained based on the first starting address and the first ending address in the first linked list. By combining the new column-based storage method and the linked list, while meeting the test requirements, it is possible to specifically store only the waveform data of the valid pins in the storage unit, which greatly reduces the write operation of the storage unit and thus improves the test efficiency. Secondly, there is no need to store the waveform data of all pins, which greatly saves the space occupied by the storage unit, so that there is more space to store the waveform data of the valid pins.

[0077] In some embodiments, the waveform data sent down by the upper module includes waveform data shared by at least two valid pins; the shared waveform data is not sent down repeatedly.

[0078] Specifically, before sending waveform data, the upper-level module will identify whether the waveform data is shared by multiple valid pins. If so, it will generate a group identifier (Group ID) corresponding to the waveform data and send it to the logic processing module. The group identifier is used to indicate at least two valid pins that share the waveform data.

[0079] After receiving the shared waveform data, the logic processing module can copy the shared waveform data corresponding to the group identifier according to the number of valid pins indicated by the group identifier. The logic processing module stores the waveform data sent by the upper module and the copied waveform data in the storage unit in sequence according to the corresponding valid pins.

[0080] For example, the number of waveform data sent and the number of copied waveform data are equal to the number of valid pins indicated by the group identifier. For example, if the group identifier indicates three valid pins, indicating that these three valid pins share waveform data 1, then two copies of waveform data 1 can be copied. Thus, including the sent waveform data, there are three copies of waveform data 1 in total. Then, the three copies of waveform data 1 can be stored in the DDR in order according to the corresponding valid pins.

[0081] The above solution does not need to repeatedly send the shared waveform data, and thus does not need to repeatedly write the data into the storage unit, thereby improving efficiency.

[0082] In some embodiments, the method further includes: the logic processing module receives microinstruction data sent by the upper-level module; the microinstruction data is data formed by the upper-level module combining multiple microinstructions in an execution order and meeting a preset second number of bits; the logic processing module stores the received microinstruction data in a storage unit.

[0083] It should be understood that the waveform file configured by the user also includes microinstruction configuration data (ie, configuration data related to microinstructions). The upper-level module can parse the microinstruction configuration data to generate multiple microinstructions corresponding to the current test task.

[0084] In some embodiments, each microinstruction includes a cycle identifier of a test cycle, an operation code, waveform setting data, and an operand; the operation codes and / or waveform setting data in microinstructions of adjacent test cycles are different.

[0085] Specifically, the upper-level module can parse the microinstruction configuration data to obtain the operation code (OpCode) and waveform setting data (WaveFormSet) corresponding to each test cycle. Furthermore, the upper-level module parses the operation code and waveform setting data to generate microinstructions.

[0086] The opcode specifies the operation to be performed (e.g., a microinstruction). The opcode can indicate a normal microinstruction (Normal) or a special microinstruction (Non-Normal). Normal microinstructions represent pattern data that continues to drive the next test cycle and do not require any other special processing. Special microinstructions are microinstructions with special functions. For example, special microinstructions may include Loop, Endloop, Repeat, Scan, Trig, and Match.

[0087] It should be understood that waveform data (pattern data) is used to tell the test equipment the values ​​to be driven, the expected values, and the timing rules to be used. Waveform setup data is used to define the specific time points at which these values ​​are driven under the timing rules used.

[0088] For any test cycle, if the opcode and / or waveform setting data corresponding to that test cycle changes compared to the previous test cycle, this indicates a change in the microinstruction. Therefore, the upper-level module can generate a microinstruction based on the cycle identifier, opcode, waveform setting data, and operand corresponding to the current test cycle. This avoids repeated generation of the same microinstruction, avoids redundancy, and reduces data computation and storage requirements.

[0089] For example, if the microinstructions of the first nine test cycles are all Normal and the waveform setting data WaveFormSet is the same, then the first nine test cycles use one microinstruction. If a special microinstruction appears in the 10th test cycle (that is, the microinstruction changes from Normal to special microinstruction) or WaveFormSet changes, a new microinstruction is generated, that is, the cycle identifier of the 10th test cycle (vector number = 10), special microinstruction, WaveFormSet and operand generate a new microinstruction.

[0090] After generating the microinstructions, the upper layer module may combine the generated microinstructions in an execution order and send microinstruction data that meets the second bit number to the logic processing module each time. The logic processing module stores the received microinstruction data in a storage unit.

[0091] Take the second bit number as 480 bits as an example, Figure 4 As shown, the upper module parses the opcode and waveform setting data to generate microinstructions. Each microinstruction is 96 bits, so every 5 microinstructions can be combined in the execution order to form 480 bits of microinstruction data for distribution. The communication board transmits the 480 bits of microinstruction data to the digital board in the bus format. The FPGA in the digital board stores the 480 bits of microinstruction data in the memory in sequence. Specifically, each row in the memory stores 480 bits of microinstruction data consisting of 5 microinstructions. For example, Figure 4 In the example, microinstruction n-4 to microinstruction n are 5 microinstructions, forming 480 bits of microinstruction data, which are stored in one row.

[0092] If the microinstruction data in the last row is less than 480 bits, the remaining bits of the last row can be padded with 0s to make up 480 bits of data, and the third offset information is recorded. The third offset information is used to indicate the remainder so as to determine the non-0-padded, substantial microinstruction data from the 480 bits of microinstruction data after the last row is padded with 0s.

[0093] In some embodiments, a storage area 3 is pre-divided in the storage unit, i.e., all microinstruction data is independently stored in storage area 3. The upper-level module can pre-acquire the third first address at which the microinstruction data is stored in storage area 3, as well as the third total number of rows in which the microinstruction data is to be stored, and send these to the logic processing module. Thus, the logic processing module can locate the starting location of storage of the microinstruction data in the storage unit based on the third first address, and sequentially store the received microinstruction data in the storage unit until the number of rows stored reaches the third total number of rows.

[0094] In some embodiments, the upper-level module can generate at least one second linked list (i.e., a microinstruction linked list). Each second linked list records the second starting address and the second ending address of at least a portion of the microinstruction data in the storage unit, and generates the second linked list based on the second starting address and the second ending address. The second starting address and the second ending address are used to read the corresponding microinstruction data from the storage unit. For example, when the microinstruction data in the last row is less than 480 bits, the upper-level module generates the second linked list based on the third offset information, the second starting address, and the second ending address corresponding to the microinstruction data in the last row.

[0095] In some embodiments, each test item in the current test task corresponds to only one second linked list; the microinstruction data indicated by the second linked list corresponding to each test item includes multiple microinstructions related to the test item. The upper-level module can assemble a second linked list based on the second starting address and second ending address of the microinstruction data corresponding to the same test item and send it to the logic processing module for storage.

[0096] In some examples, the upper-level module can calculate the second starting address and the second ending address of the microinstruction data storage corresponding to each test item based on the second first address, the amount of microinstruction data sent in a single time, and the configured sending order of the microinstruction data. In other examples, after storing the microinstruction data, the logic processing module returns the second storage address of the microinstruction data stored each time to the upper-level module. The upper-level module can determine the second starting address and the second ending address of the microinstruction data storage corresponding to each test item based on the second storage addresses corresponding to the microinstruction data stored multiple times corresponding to the same test item.

[0097] The upper-layer module can send the generated second linked list to the logic processing module for storage. For example, the upper-layer module can sequentially send multiple second linked lists according to the second number of bits (e.g., 480 bits). If the last sent second linked list data does not reach the second number of bits, zeros are added and corresponding fourth offset information is recorded. The fourth offset information is used to indicate the end bit of the actual second linked list data sent last.

[0098] In some embodiments, a storage area 4 is pre-divided in the storage unit, i.e., all second linked lists are independently stored in storage area 4. The upper-layer module can pre-acquire the fourth starting address of the second linked list stored in storage area 4 and the fourth total number of rows to be stored in the second linked list, and send them to the logic processing module. The logic processing module can locate the starting location of storage of the second linked list in the storage unit based on the fourth starting address, and thus sequentially store the received second linked lists until the number of rows stored reaches the fourth total number of rows.

[0099] like Figure 5 As shown, in one embodiment, another waveform data storage method is provided, which is implemented through interaction between an upper layer module and a logic processing module, and specifically includes the following steps:

[0100] (1) The upper-layer module parses the configured waveform file, which includes data of multiple business boards. The data of each business board includes the waveform data and microinstruction configuration data corresponding to the business board.

[0101] It should be understood that the digital board includes multiple service boards (FEs), and the waveform data corresponding to each service board are all waveform data of valid pins.

[0102] (2) Determine whether the data of all business boards have been preloaded.

[0103] If yes, then the process ends. If no, the current service board is determined from the unloaded service boards, and the data corresponding to the current service board is preloaded. In the embodiment of the present application, steps (2), (3.5), (4.7), (5.7) and (6) are all performed by the upper layer module.

[0104] The preloading process for the data corresponding to the current service board mainly includes waveform data preloading, microinstruction preloading, and linked list preloading. These three preloading processes can be processed in parallel. The waveform data preloading includes steps (3.1) to (3.5), the microinstruction preloading includes steps (4.1) to (4.7), and the linked list preloading includes steps (5.1) to (5.5).

[0105] (3.1) The upper layer module sends the first address and the first total number of rows of the waveform data corresponding to the current business board stored in the memory.

[0106] (3.2) The upper-layer module sends the waveform data of multiple valid pins in the waveform data corresponding to the current business board in multiple rounds in sequence, sending 640 bits of waveform data of a valid pin each time.

[0107] (3.3) The communication board will perform a 4-bit to 3-bit operation, converting the 640-bit waveform data into 480-bit waveform data and sending it down.

[0108] (3.4) Based on the first address of the memory, the FPGA writes the received 480-bit waveform data into the memory in sequence.

[0109] (3.5) Determine whether all waveform data corresponding to the current business card has been preloaded based on the first total number of rows. If so, execute step (6); if not, return to step (3.2) to continue processing the remaining unloaded waveform data of the current business card.

[0110] (4.1) The upper-level module parses the operation code and waveform setting data corresponding to each test cycle from the microinstruction configuration data.

[0111] (4.2) If the opcode and / or waveform setting data corresponding to the current test cycle changes compared to the previous test cycle, the upper-level module generates a microinstruction based on the cycle identifier of the current test cycle, the opcode, waveform setting data, and operands corresponding to the current test cycle.

[0112] (4.3) The upper-level module sends the third address and the third total number of rows of microinstructions stored in the memory.

[0113] (4.4) The upper module sends microinstruction data in 480-bit units. If the last microinstruction data sent is less than 480 bits, it is padded with 0.

[0114] (4.5) The communication board sends 480-bit microinstruction data according to the communication protocol.

[0115] (4.6) Based on the third address of the memory, the FPGA writes the received 480-bit microinstruction data into the memory in sequence.

[0116] (4.7) Based on the third total number of rows, determine whether all microinstruction data corresponding to the current business card has been preloaded. If so, execute step (6). If not, return to step (4.4) to continue processing the remaining unloaded microinstruction data of the current business card.

[0117] (5.1) The upper-level module generates a target linked list; the target linked list is the first linked list corresponding to the waveform data or the second linked list corresponding to the microinstructions.

[0118] (5.2) When the target linked list is the first linked list, the upper-level module forms a linked list group with all target linked lists corresponding to the current test item; the end bit of the last target linked list is 1.

[0119] In the case where the target linked list is the second linked list, the current test item corresponds to one target linked list, and step (5.2) may not be executed.

[0120] (5.3) The upper module sends the target first address and the total number of target rows stored in the target linked list in the memory.

[0121] It should be understood that when the target linked list is the first linked list, the target first address is the second first address and the target total number of rows is the second total number of rows. When the target linked list is the second linked list, the target first address is the fourth first address and the target total number of rows is the fourth total number of rows.

[0122] (5.4) The upper-layer module sends down the linked list data in 480-bit units. If the last linked list data sent down is less than 480 bits, it is padded with 0.

[0123] When the target linked list is the first linked list, the linked list group is sent in units of 480 bits, and the first linked list data is sent each time; when the target linked list is the second linked list, the target linked list is sent in units of 480 bits, and the second linked list data is sent each time.

[0124] (5.5) The communication board sends 480-bit linked list data according to the communication protocol.

[0125] (5.6) Based on the target first address of the memory, the FPGA writes the received 480-bit linked list data into the memory in sequence.

[0126] (5.7) Based on the target total number of rows, determine whether all linked list data corresponding to the current business card has been preloaded. If so, execute step (6). If not, return to step (5.4) to continue processing the remaining unloaded linked list data of the current business card.

[0127] (6) Determine whether all data corresponding to the current business board have been preloaded.

[0128] If yes, return to step (2). If no, return to execute the unfinished processing in waveform data preloading, microinstruction preloading, and linked list preloading.

[0129] like Figure 6 As shown, in some embodiments, a waveform data reading method is provided, which is applied to a logic processing module and specifically includes the following steps:

[0130] S602: The logic processing module receives a test start instruction sent by an upper-layer module; wherein the test start instruction includes the address of the first target linked list.

[0131] S604, the logic processing module obtains the first target linked list indicated by the first target linked list address from the storage unit, wherein the first target linked list is one or more of the first linked lists stored in the storage unit; the first linked list is used to record the first starting address and the first ending address of the waveform data stored in the storage unit; what is stored in the storage unit is the waveform data of the valid pin, the waveform data stored in the same row corresponds to the same valid pin, and the waveform data of different valid pins are stored in different rows.

[0132] The test start instruction may be an instruction for starting a test for a target test item in a current test task. The first target linked list may be a first linked list stored in the storage unit and corresponding to the target test item.

[0133] In some examples, the first target linked list address may be all first linked list addresses corresponding to the target test item. The logic processing unit retrieves the corresponding first target linked list from the storage unit according to each first target linked list address, that is, obtains all first target linked lists corresponding to the target test item.

[0134] In other examples, the first target linked list address may be the first first linked list address among multiple first linked list addresses corresponding to the target test item. The test start instruction also carries the first linked list length, which is used to represent the number of first target linked lists corresponding to the target test item. Assuming that target test item 1 corresponds to 5 first linked list addresses, the first target linked list address is the first first linked list address among these 5 first linked list addresses, and the first linked list length is 5. The logic processing unit can then sequentially obtain the first target linked lists starting from the first target linked list address until the length or number of the obtained first target linked lists reaches the first linked list length (such as when 5 linked lists are obtained continuously), and then stop to obtain all the first target linked lists corresponding to the target test item.

[0135] S606: The logic processing module reads the corresponding target waveform data from the storage unit according to the first start address and the first end address in the first target linked list.

[0136] The logic processing module can start reading the stored waveform data from the first starting address until it reaches the first ending address. The waveform data read between the first starting address and the first ending address is the target waveform data, which is the waveform data required to perform the test on the target test item.

[0137] S608: The logic processing module performs a test according to the target waveform data.

[0138] The above method, when waveform data is stored in columns, can be combined with the first linked list to quickly and accurately read target waveform data to perform testing, thereby improving test efficiency.

[0139] In some embodiments, the test initiation instruction further includes a second target linked list address. In this embodiment, the method further includes: the logic processing module obtaining a second target linked list indicated by the second target linked list address from a storage unit; wherein the second target linked list is one or more second linked lists stored in the storage unit; the second linked list is used to record the second starting address and the second ending address of the microinstruction data stored in the storage unit; and reading the corresponding target microinstruction data from the storage unit according to the second starting address and the second ending address in the second target linked list.

[0140] The second target linked list address is a second linked list address corresponding to the target test item targeted by the test start instruction. The second target linked list refers to a second linked list stored in the storage unit and corresponding to the target test item.

[0141] In some examples, the target test item may correspond to a second target linked list, and thus, the target test item may correspond to a second linked list address, namely, the second target linked list address.

[0142] In other examples, the target test item may also correspond to multiple second target linked lists, and thus the target test item may correspond to multiple second linked list addresses.

[0143] In this case, the second target linked list address can be all second linked list addresses corresponding to the target test item. For example, target test item 1 corresponds to three second linked list addresses, and these three second linked list addresses are all second target linked list addresses. The logic processing unit retrieves all second target linked lists corresponding to the target test item from the storage unit based on each second target linked list address.

[0144] The second target linked list address may also be the first second linked list address among the multiple second linked list addresses corresponding to the target test item. The test start instruction may also carry a second linked list length, which is used to represent the number of second target linked lists corresponding to the target test item. Assume that target test item 1 corresponds to 3 second linked list addresses, the second target linked list address is the first second linked list address, and the test start instruction also carries a second linked list length of 3. In this case, the logic processing unit may sequentially obtain the second target linked lists starting from the second target linked list address until the length or number of the obtained second target linked lists reaches the second linked list length (i.e., 3 linked lists are obtained continuously), and then stop to obtain all the second target linked lists corresponding to the target test item.

[0145] The logic processing module reads corresponding target microinstruction data from the storage unit according to the second starting address and the second ending address in the second target linked list. The logic processing module may start reading the stored microinstruction data from the second starting address and stop reading the stored microinstruction data until the second ending address is reached. The microinstruction data between the second starting address and the second ending address is the target microinstruction data, which is the microinstruction data required to execute the test for the target test item.

[0146] In this embodiment, step S608 includes: the logic processing module executing a test based on the target waveform data and the target microinstruction data. It should be understood that the target waveform data may include waveform data for multiple test cycles, and the target microinstructions may include microinstructions for multiple test cycles. Therefore, for each test cycle, the logic processing module may combine the waveform data and microinstructions corresponding to the same test cycle to execute the test within that test cycle.

[0147] In some embodiments, the logic processing module performs tests based on the target waveform data and the target microinstruction data, including: for each row of waveform data corresponding to each valid pin in the target waveform data, the logic processing module splits each row of waveform data multiple times and stores it in the first first-in-first-out queue corresponding to the valid pin; the logic processing module reads the sub-waveform data corresponding to the same target test cycle of each valid pin from the first first-in-first-out queue corresponding to each valid pin according to a preset third bit number, and vectorizes the sub-waveform data corresponding to each valid pin to obtain a waveform test vector; the logic processing module splits multiple microinstructions in the read target microinstruction data, and stores the split single microinstructions in the second first-in-first-out queue in sequence; the logic processing module reads the microinstruction carrying the cycle identifier of the target test cycle from the second first-in-first-out queue, discards the cycle identifier in the read microinstruction, and reorganizes it in vector form to generate a microinstruction vector; and performs tests based on the waveform test vector and the microinstruction vector.

[0148] It should be understood that Pattern has multiple modes (referred to as pattern modes), for example, 3 bits indicating a pattern code (i.e., one pattern data), 6 bits indicating a pattern code, or 12 bits indicating a pattern code. Therefore, the specific size of the third bit is determined by the pattern mode and is not limited thereto. For example, the third bit can be 6 bits or 12 bits.

[0149] like Figure 7 As shown, the logic processing module can read the first linked list from the storage system (ie, the storage unit) according to the first linked list address and write it into the corresponding first-in-first-out queue FIFO (eg, Figure 7 The queue-waveform data linked list), and read the second linked list from the storage system according to the second linked list address, and write it into the corresponding first-in-first-out queue (such as Figure 7 Then, using a state machine that controls the linked list, target waveform data is read from the storage system based on the first linked list in the queue-waveform data linked list, and target microinstruction data is read from the storage system based on the second linked list in the queue-microinstruction linked list.

[0150] Since the microinstruction data and the waveform data for each pin occupy one row in the storage unit (e.g., 480 bits), direct storage would consume storage resources. Therefore, the waveform data for each pin in the target waveform data can be split, and the split sub-waveform data can be sequentially stored in a first first-in-first-out queue with a smaller bit width (e.g., a bit width of 60 bits). The target microinstruction data can also be split into individual microinstructions, and the split individual microinstructions can be sequentially stored in a second first-in-first-out queue with an even smaller bit width (e.g., a bit width of 96 bits).

[0151] In some embodiments, taking a storage system in which 480 bits are stored in one row as an example, the logic processing module may split each row of waveform data into multiple parts and store them in the corresponding first FIFO queue according to the following process:

[0152] (1-1) The logic processing module can store the target waveform data into the third first-in-first-out queue (such as Figure 7 in the queue-waveform data).

[0153] like Figure 7 As shown, there are 32 valid pins (Pin0 to Pin31). The queue-waveform data has a bit width of 480 bits. One row of waveform data contains 480 bits of waveform data corresponding to one pin, that is, the pattern data for that pin under 160 cycles (test cycles), with one cycle corresponding to 3 bits of pattern data. It should be understood that if there are 1000 rows of target waveform data, the queue-waveform data depth is 1K.

[0154] (1-2) The logic processing module can read 480-bit waveform data from the third first-in-first-out queue in sequence, and send it to the 480-bit register corresponding to the valid Pin according to the valid Pin flag corresponding to the read waveform data.

[0155] See Figure 7 The Pin0 register is the 480-bit register corresponding to Pin0, and can also be expressed as Pin0_reg[479:0]. The Pin31 register is the 480-bit register corresponding to Pin31, and can be expressed as Pin31_reg[479:0]. All 32 valid pins have corresponding 480-bit registers.

[0156] (1-3) Each valid pin corresponding to the 480-bit register is shifted and the read 480-bit waveform data is stored in the first FIFO queue corresponding to the valid pin in 8 steps. Figure 7 Pin0-queue ~ Pin31-queue are the first-in-first-out queues with a bit width of 60 bits corresponding to Pin0 ~ Pin1.

[0157] For example, if the number of valid pins is greater than 8, the interval between the first 480-bit waveform data and the next 480-bit waveform data received by the 480-bit register corresponding to each pin is greater than 8 clock cycles clk, thereby ensuring that the shift is completed without conflict.

[0158] If the number of valid pins is less than 8, in the process of reading waveform data from the third first-in-first-out queue, the control waits for 8 clock cycles clk after reading the waveform data of a valid pin once, and then reads the waveform data of the next valid pin to ensure that each 480-bit register has time to store the read waveform data into the corresponding 60-bit first-in-first-out queue.

[0159] In some embodiments, the logic processing module may split the target microinstruction data into multiple parts and store them in the second FIFO queue according to the following process:

[0160] (2-1) The logic processing module can store the target microinstruction data into the fourth first-in-first-out queue (such as Figure 7 In the queue - micro instruction data). Figure 7 As shown, the bit width of the queue-microinstruction data is also 480 bits. A row of microinstruction data includes 5 microinstructions, that is, microinstructions under 5 cycles, and each microinstruction is 96 bits.

[0161] (2-2) The logic processing module can sequentially read 480-bit microinstruction data from the fourth first-in-first-out queue and send it to the 480-bit register corresponding to the microinstruction. Figure 7 The microinstruction-register in the register is the 480-bit register corresponding to the microinstruction.

[0162] (2-3) The 480-bit register corresponding to the microinstruction is shifted and stores the read 480it microinstruction data into the second first-in-first-out queue corresponding to the microinstruction in 5 times. Figure 7 The microinstruction queue in is the second first-in-first-out queue, which stores 96-bit microinstructions each time.

[0163] Taking the third bit number as 6 bits as an example, the waveform data corresponding to each valid Pin is split multiple times and stored in the corresponding first FIFO queue (such as Figure 7 After the Pin0-queue to Pin31-queue in the test cycle, the 60-bit waveform data corresponding to each valid Pin can be obtained from the first FIFO queue corresponding to each valid Pin. Then, 6-bit sub-waveform data is read from the 60-bit waveform data corresponding to each valid Pin. These sub-waveform data correspond to the same target test cycle. Therefore, the logic processing module can vectorize the sub-waveform data corresponding to each valid pin to obtain a waveform test vector. Figure 7 As shown, Pin31[5:0]...Pin1[5:0] Pin0[5:0] is a vector reorganization of the 6-bit sub-waveform data of each Pin from Pin0 to Pin31 to obtain a 192-bit waveform test vector.

[0164] After the microinstruction data is split multiple times and stored in the corresponding second first-in-first-out queue, the logic processing module can perform vector continuous processing to continuously read the microinstructions carrying the cycle identifier of the target test cycle from the second first-in-first-out queue. Furthermore, the cycle identifier can be discarded. For example, for a 96-bit microinstruction, a 40-bit cycle identifier can be discarded, so that 56 bits are taken for each test cycle, that is, only 56 bits of substantial data are transmitted downward, and then the data after discarding the cycle identifier is reassembled in vector form to generate a microinstruction vector (i.e. Figure 7 In this way, the 192-bit waveform test vector and the 56-bit microinstruction vector can be sent to the microinstruction module to perform the test.

[0165] It should be understood that the entire process is continuous, so it is necessary to ensure that each clock domain generates a waveform test vector and a microinstruction vector without interruption.

[0166] Although the steps in the flowcharts of the above embodiments are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Moreover, at least a portion of the steps in the flowcharts of the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but may be executed at different times. The order of execution of these steps or stages is not necessarily sequential, but may be executed in rotation or alternation with other steps or at least a portion of steps or stages in other steps.

[0167] In one embodiment, an electronic device is provided. The electronic device may be a logic processing module or an upper layer module. The internal structure diagram thereof may be as follows: Figure 8 As shown. The electronic device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and a storage unit memory. The non-volatile storage medium stores an operating system and a computer program. The storage unit memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The input / output interface of the electronic device is used to exchange information between the processor and an external device. The communication interface of the electronic device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a waveform data storage method or a waveform data reading method is implemented.

[0168] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application and does not constitute a limitation on the electronic device. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0169] In some embodiments, a waveform data storage system is provided, including an upper-layer module, a communication board and a digital board. The digital board includes a logic processing module and a storage unit. The steps in the waveform data storage method and the waveform data reading method in the embodiments of the present application can be implemented through the interaction of the above modules.

[0170] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in each embodiment of the present application are implemented.

[0171] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in each embodiment of the present application when executed by a processor.

[0172] Those skilled in the art will appreciate that all or part of the processes in the above-described embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described embodiments. Any reference to a memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory.

[0173] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0174] The above embodiments merely illustrate several implementation methods and are not to be construed as limiting the scope of the present invention. Those skilled in the art will appreciate that variations and modifications may be made without departing from the scope of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A waveform data storage method, characterized in that: The method comprises: The logic processing module receives waveform data sent down by the upper-layer module; the waveform data is generated by the upper-layer module cyclically splitting the original waveform data for testing valid pins according to a preset first number of bits, wherein the valid pin is a pin to be tested in the current test task, there is at least one valid pin, and the upper-layer module sends the waveform data corresponding to one valid pin at a time; The logic processing module stores the received waveform data in a storage unit in sequence; wherein the waveform data sent at the same time are stored in the same row, and the waveform data sent at different times are stored in different rows; The logic processing module receives at least one first linked list sent down by the upper-level module and stores the at least one first linked list in the storage unit; wherein each of the first linked lists records the first starting address and the first ending address of at least a part of the waveform data in the storage unit, and the first starting address and the first ending address are used to read the corresponding waveform data from the storage unit.

2. The method according to claim 1, characterized in that The waveform data includes waveform data shared by at least two valid pins; the shared waveform data is not repeatedly sent; Before the logic processing module receives the waveform data sent by the upper module, the method further includes: The logic processing module receives a group identifier sent by an upper layer module; the group identifier is used to indicate at least two valid pins that share the same waveform data; After receiving the shared waveform data, the method further includes: The logic processing module copies the shared waveform data according to the number of valid pins indicated by the group identifier; The logic processing module sequentially stores the received waveform data in a storage unit, including: The logic processing module stores the waveform data sent by the upper module and the copied waveform data in the storage unit in sequence according to the corresponding valid pins.

3. The method according to claim 1, characterized in that Before the logic processing module sequentially stores the received waveform data in the storage unit, the method further includes: The logic processing module receives the first first address and the first total number of rows sent by the upper module; the first first address is the first address of the waveform data stored in the storage unit, and the first total number of rows is the total number of rows of the waveform data stored in the storage unit; The logic processing module sequentially stores the received waveform data in a storage unit, including: The logic processing module stores the received waveform data in sequence in the storage unit according to the first starting address and the first total number of rows.

4. The method according to claim 1, wherein The current test task includes at least one test item; in the at least one first linked list received by the logic processing module, each of the first linked lists corresponding to the same test item forms a linked list group; The linked list group is sent to the logic processing module in batches according to a preset second number of bits; Storing the at least one first linked list in the storage unit includes: The logic processing module stores the first linked lists delivered at the same time in the same row in the storage unit, and stores the first linked lists delivered at different times in different rows in the storage unit.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: The logic processing module receives the microinstruction data sent by the upper module; the microinstruction data is formed by the upper module combining multiple microinstructions in an execution order and meeting a preset second number of bits; The logic processing module stores the received microinstruction data in the storage unit; The logic processing module receives at least one second linked list sent down by the upper-level module, and stores the at least one second linked list in the storage unit, wherein each of the second linked lists records a second starting address and a second ending address of at least a portion of the microinstruction data in the storage unit, and the second starting address and the second ending address are used to read the corresponding microinstruction data from the storage unit.

6. The method according to claim 5, characterized in that Each of the microinstructions includes a test cycle identifier, an operation code, waveform setting data, and an operand; wherein the operation code is used to specify the operation to be performed; the operation codes and / or the waveform setting data in the microinstructions of adjacent test cycles are different.

7. The method according to claim 5, characterized in that One test item in the current test task corresponds to one second linked list; the microinstruction data indicated by the second linked list corresponding to each test item includes a plurality of microinstructions related to the test item.

8. A method for reading waveform data, characterized in that: The method comprises: The logic processing module receives a test start instruction sent by the upper module; wherein the test start instruction includes the first target linked list address; The logic processing module obtains a first target linked list indicated by the first target linked list address from a storage unit, wherein the first target linked list is one or more first linked lists stored in the storage unit; the first linked list is used to record a first start address and a first end address of at least a portion of the waveform data in the storage unit; the waveform data of valid pins is stored in the storage unit, the waveform data stored in the same row corresponds to the same valid pin, and the waveform data of different valid pins are stored in different rows; The logic processing module reads the corresponding target waveform data from the storage unit according to the first starting address and the first ending address in the first target linked list; The logic processing module performs a test according to the target waveform data.

9. The method according to claim 8, characterized in that The test start instruction also includes a second target linked list address; Before the logic processing module performs a test according to the target waveform data, the method further includes: The logic processing module obtains a second target linked list indicated by the second target linked list address from the storage unit; wherein the second target linked list is one or more second linked lists stored in the storage unit; the second linked list is used to record the second starting address and the second ending address of the microinstruction data stored in the storage unit; Reading corresponding target microinstruction data from the storage unit according to the second starting address and the second ending address in the second target linked list; The logic processing module performs a test according to the target waveform data, including: The logic processing module performs a test according to the target waveform data and the target microinstruction data.

10. The method according to claim 9, characterized in that The logic processing module performs a test according to the target waveform data and the target microinstruction data, including: For each row of waveform data corresponding to each valid pin in the target waveform data, the logic processing module splits each row of waveform data into multiple times and stores the splits into a first first-in-first-out queue corresponding to the valid pin; The logic processing module reads, according to a preset third number of bits, the sub-waveform data of each valid pin corresponding to the same target test cycle from the first first-in-first-out queue corresponding to each valid pin, and performs vector recombination on the sub-waveform data corresponding to each valid pin to obtain a waveform test vector; The logic processing module splits the plurality of microinstructions in the read target microinstruction data, and sequentially stores the split individual microinstructions into a second first-in-first-out queue; The logic processing module reads the microinstruction carrying the cycle identifier of the target test cycle from the second FIFO queue, discards the cycle identifier in the read microinstruction, and reassembles the microinstruction in a vector form to generate a microinstruction vector; Testing is performed according to the waveform test vector and the microinstruction vector.

11. A waveform data storage method, characterized in that: The method comprises: The upper layer module sends the original waveform data of multiple valid pins targeted by the current test task to the logic processing module in multiple rounds according to a preset first bit number, so that the logic processing module sequentially stores the sent waveform data in the storage unit; wherein the waveform data corresponding to one valid pin is sent each time; the waveform data sent at the same time are stored in the same row, and the waveform data sent at different times are stored in different rows; The upper layer module generates at least one first linked list and sends each of the first linked lists to the logic processing module; each of the first linked lists is used to record a first starting address and a first ending address of at least a portion of the waveform data in the storage unit; The upper layer module obtains the first linked list addresses respectively corresponding to the first linked lists returned by the logic processing module, and records the corresponding relationship between the first linked list addresses and the test items in the current test task; In response to a test trigger operation for the target test item in the current test task, the first target linked list address corresponding to the target test item is obtained based on the corresponding relationship, and a test start instruction carrying the first target linked list address is generated and issued, so that the logic processing module obtains the corresponding target waveform data based on the first target linked list address to perform the test.

12. The method according to claim 11, characterized in that The sending each of the first linked lists to the logic processing module includes: For each test item in the current test task, the upper layer module groups the first linked lists corresponding to the test items into a group to form a linked list group, and sends the linked list group in batches according to a preset second number of bits.

13. The method according to claim 11 or 12, characterized in that The method further comprises: The upper layer module parses the microinstruction configuration data to obtain the operation code and waveform setting data corresponding to each test cycle; For any test cycle, if the operation code and / or waveform setting data corresponding to the test cycle changes compared to the previous test cycle, the upper-layer module generates a microinstruction according to the cycle identifier of the test cycle, the operation code and waveform setting data corresponding to the test cycle, and the operand corresponding to the test cycle; The upper layer module combines the generated multiple microinstructions in an execution order to form microinstruction data that meets the second bit number and sends the microinstruction data to the logic processing module.

14. A waveform data storage system, characterized in that: The system includes an upper layer module, a communication board and a digital board; the digital board includes a logic processing module and a storage unit; The upper layer module is used to cyclically split the original waveform data of testing at least one valid pin according to a preset first number of bits and send it to the communication board; Sending the waveform data corresponding to one valid pin each time; The communication board is used to convert the waveform data sent each time into a suitable format and then send it to the logic processing module; The logic processing module is used to sequentially store the received waveform data in the storage unit; The waveform data sent at the same time are stored in the same row, and the waveform data sent at different times are stored in different rows; The upper layer module is further configured to send at least one first linked list to the communication board; each of the first linked lists records a first starting address and a first ending address of at least a portion of the waveform data in the storage unit; The communication board is further configured to transparently transmit the at least one first linked list sent to the logic processing module; The logic processing module is further configured to store the at least one first linked list in the storage unit.

15. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7, 8 to 10, or 11 to 13 are implemented.

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