Scalar processors, high-performance processors, and electronic devices

Abstract

The application provides a scalar processor, a high-performance processor and an electronic device, the scalar processor comprising: a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit; wherein the synchronization unit is configured to synchronize the scalar processor and a vector processor. The scalar processor provided by the application synchronizes the scalar processor and the vector processor through the synchronization unit, thereby efficiently executing instructions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to a scalar processor, a high-performance processor and an electronic device. BACKGROUND

[0002] The scalar processor is a kind of computer processor, opposite to vector processor.

[0003] The scalar processor can process all scalar calculations and bit operations, and provides effective support for control and DSP (Digital Signal Processor) oriented operations. SUMMARY

[0004] In order to solve one of the above technical defects, the present application provides a scalar processor, a high-performance processor and an electronic device.

[0005] In a first aspect, the present application provides a scalar processor, comprising: a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0006] The fetch unit is configured to fetch instructions and dispatch the instructions.

[0007] The register renaming unit is configured to receive the instructions dispatched by the fetch unit and perform register renaming.

[0008] The operation reservation stack unit is configured to serve as a launch queue of the scalar operation unit.

[0009] The memory reservation stack unit is configured to serve as a launch queue of the memory access unit.

[0010] The scalar operation unit is configured to receive the instructions and data sent by the operation reservation stack unit, perform operations on the data based on the instructions, and write the operation results back to the register renaming unit.

[0011] The memory access unit is configured to receive the instructions and data sent by the memory reservation stack unit, register information, read and write the data based on the instructions and the register information.

[0012] The program control unit is configured to receive the instructions and data from the register renaming unit, process the data based on the instructions, and output the processing results.

[0013] The synchronization unit is configured to synchronize the scalar processor with the vector processor.

[0014] The pipeline control unit is configured to generate a pause signal of a pipeline and / or generate a start and stop signal of the scalar processor.

[0015] Optionally, the scalar processor further comprises: an instruction cache and a data store;

[0016] a fetch unit for generating a fetch request address, outputting the fetch request address to the instruction cache for instruction fetching, receiving instructions from the instruction cache and storing them in the data store; sequentially reading qualified instructions from the data store every cycle, decoding and checking the read instructions, and sequentially dispatching the checked instructions.

[0017] Optionally, the scalar processor further comprises: a special vector register, a status flag register;

[0018] a register renaming unit for receiving and storing the dispatched instructions from the fetch unit, renaming the special vector register, decoding the instructions, and generating a pipeline stall signal; receiving and writing back data from one or more of the scalar operation unit, the memory access unit, the program control unit, the synchronization unit, the special vector register, the condition register, and the flag register; and sending the instructions to one or more of the operation reservation stack unit, the memory reservation stack unit, the program control unit, and the synchronization unit;

[0019] The condition register is located in the register renaming unit.

[0020] The instructions of the scalar operation unit and the memory access unit support reading and writing operations of the condition register;

[0021] The instructions of the synchronization unit support reading operations of the condition register;

[0022] The jump and function call instructions of the program control unit support reading operations of the condition register;

[0023] When an instruction enters the condition register, if there is an unexecuted instruction in the condition register, the pipeline stalls.

[0024] Optionally, the register renaming unit comprises: one or more physical registers and one or more logical registers.

[0025] Any physical register is one of the following: a scalar physical register, a vector physical register, a condition register, and a flag register.

[0026] Any logical register is one of the following: a scalar logical register and a vector logical register.

[0027] The mapping relationship between the logical registers and the physical registers is maintained by a register mapping table; initially, all the mapping physical registers corresponding to the table entries with the logical register indexes in the register mapping table are all 0; when the instruction is executed or when an interrupt occurs, the logical register allocated for the related physical register is determined, and the mapping of the table entry corresponding to the allocated logical register index in the register mapping table is updated to the identifier of the related physical register;

[0028] The mapping relationship between the vector logical registers and the vector physical registers is maintained by a special vector register mapping table; initially, all the mapping vector physical registers corresponding to the table entries with the vector logical register indexes in the special vector register mapping table are all 0; when the instruction is executed, the vector logical register allocated for the related vector physical register is determined, and the mapping of the table entry corresponding to the allocated vector logical register index in the special vector register mapping table is updated to the identifier of the related vector physical register.

[0029] Optionally, an operation reservation stack unit is configured to receive the instruction, dispatch and renaming information from the register renaming unit and push into a queue; and pop the ready instruction to the scalar operation unit for execution.

[0030] The operation reservation stack unit is further configured to decode the input instruction and store the instruction type information.

[0031] Optionally, a storage reservation stack unit is configured to receive the instruction and the register renaming information from the register renaming unit and push into a queue.

[0032] The storage reservation stack unit is further configured to send a read request to the register renaming unit when the instruction address register is ready and save the read address operand.

[0033] The register renaming unit is further configured to calculate the address and decode the address after the instruction obtains the address, and save the decoding information.

[0034] The register renaming unit is further configured to detect any instruction with a ready source register and completed address decoding, and then transmit the instruction to the memory unit for execution.

[0035] Optionally, the scalar processor performs conditional execution decoding on the preset bit of the instruction, and if the condition is met, outputs a valid instruction, otherwise outputs an empty instruction.

[0036] If there is a read-write related operation on the condition register, the pipeline is blocked, and the read operation is performed after the write operation on the condition register is completed; wherein, the read-write of the condition register does not have a bypass.

[0037] Optionally, the synchronization unit is connected to the pipeline control unit, the register renaming unit, the program control unit and the vector processor.

[0038] The instruction of the synchronization unit is from the register renaming unit, and the reading and writing of the data of the synchronization unit are both interacted with the register renaming unit.

[0039] The synchronization unit is configured to receive the pause signal sent by the pipeline control unit, and send the execution stage pause signal generated when communicating with the vector processor to the pipeline control unit, so as to generate the execution pause signal of the scalar processor.

[0040] The synchronization unit is configured to generate the instruction and send the instruction to the program control unit.

[0041] In a second aspect of the present application, a high-performance processor is provided, comprising the scalar processor and the vector processor as described in the first aspect.

[0042] In a third aspect of the present application, an electronic device is provided, comprising the high-performance processor as described in the second aspect, or comprising one or more processor clusters, wherein each processor cluster comprises a plurality of high-performance processors as described in the second aspect.

[0043] The present application provides a scalar processor, a high-performance processor and an electronic device. The scalar processor comprises a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit. The synchronization unit is configured to synchronize the scalar processor and the vector processor. The scalar processor provided by the present application synchronizes the scalar processor and the vector processor through the synchronization unit, and thus efficiently executes instructions. BRIEF DESCRIPTION OF DRAWINGS

[0044] The accompanying drawings, which are included to provide a further understanding of the present application and constitute a part of this application, illustrate embodiments of the present application and explain the present application together with the description. In the drawings:

[0045] Figure 1 A schematic diagram of a scalar processor according to an embodiment of the present application is shown in FIG. 2.

[0046] Figure 2 A schematic diagram of a synchronization unit according to an embodiment of the present application is shown in FIG. 3.

[0047] Figure 3 A schematic diagram of a high-performance processor according to an embodiment of the present application is shown in FIG. 4.

[0048] Figure 4A schematic diagram of an architecture of a vector processor provided in an embodiment of the present application is shown in FIG. 1.

[0049] Figure 5 A schematic diagram of a structure of a vector operation unit provided in an embodiment of the present application is shown in FIG. 2.

[0050] Figure 6 A schematic diagram of an architecture of another vector processor provided in an embodiment of the present application is shown in FIG. 3. DETAILED DESCRIPTION

[0051] In order to make the technical solutions and advantages in the embodiments of the present application clearer, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0052] In the process of implementing the present application, the inventors found that a scalar processor is a kind of computer processor, which is opposite to a vector processor. The scalar processor can process all scalar calculations and bit operations, and provides effective support for control and DSP (Digital Signal Processor)-oriented operations.

[0053] In view of the above problems, a scalar processor, a high-performance processor and an electronic device are provided in an embodiment of the present application. The scalar processor comprises a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit. The synchronization unit is configured to synchronize the scalar processor and the vector processor. The scalar processor provided in the present application synchronizes the scalar processor and the vector processor through the synchronization unit, and thus executes instructions efficiently.

[0054] Referring to Figure 1 The scalar processor provided in the present embodiment comprises a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit.

[0055] In addition, the scalar processor can further comprise one or more other units, such as one or more other functional modules, one or more instruction caches, one or more data storages, one or more special vector registers, one or more status flag registers, etc.

[0056] 1. Fetch unit

[0057] The instruction fetch unit is configured to fetch instructions and dispatch the instructions.

[0058] In particular, the instruction fetch unit is configured to generate an instruction fetch request address, output the instruction fetch request address to the instruction cache to fetch instructions, and receive the instructions from the instruction cache and store the instructions in the data store. In each cycle, one or more instructions are sequentially read from the data store, decoded and checked, and the checked instructions are sequentially dispatched.

[0059] For example, the instruction fetch unit generates an instruction fetch request address, outputs the instruction fetch request address to the instruction cache to fetch instructions, and receives the instructions from the instruction cache and stores the instructions in the data store. In each cycle, one or more instructions are sequentially read from the data store, decoded and checked, and the checked instructions are sequentially dispatched. Each time, at most one program control unit instruction, one synchronization unit instruction, one or more scalar operation unit instructions, and one or more memory access unit instructions are dispatched.

[0060] 2. Register renaming unit

[0061] The register renaming unit is configured to receive the instructions dispatched by the instruction fetch unit and perform register renaming.

[0062] In particular, the register renaming unit is configured to receive the instructions dispatched by the instruction fetch unit and store the instructions, perform special vector register renaming, perform instruction condition decoding, and generate a pipeline stall signal. The register renaming unit is also configured to receive data from one or more of the scalar operation unit, the memory access unit, the program control unit, the synchronization unit, the special vector register, the condition register, and the status flag register and write the data back to the corresponding registers. The register renaming unit is further configured to send the instructions to one or more of the operation reservation stack unit, the memory reservation stack unit, the program control unit, and the synchronization unit.

[0063] For example, the register renaming unit is configured to receive the instructions dispatched by the instruction fetch unit and perform register renaming, special vector register renaming, instruction condition decoding, and pipeline stall signal generation. The register renaming unit is also configured to receive data from the write back registers of the execution units (such as the scalar operation unit, the memory access unit, the program control unit, and the synchronization unit), the special vector register, the condition register, and the status flag register and write the data back to the corresponding registers.

[0064] The scalar processor supports out-of-order write back, has high execution efficiency, and distributes the instructions to the operation reservation stack unit, the memory reservation stack unit, the program control unit, or the synchronization unit.

[0065] The register renaming unit has a bandwidth of 6 bits, and multiple (such as 4) input instructions can be active at the same time.

[0066] The condition register can be multiple and located in the register renaming unit.

[0067] The instruction of the scalar operation unit and the memory access unit supports the operation of reading and writing the condition register.

[0068] The instruction of the synchronization unit supports the operation of reading the condition register.

[0069] The jump and function call instruction of the program control unit supports the operation of reading the condition register.

[0070] When the instruction enters the condition register, if the condition register has an unexecuted instruction, the pipeline is blocked.

[0071] That is, the condition register does not perform the renaming, and triggers the dispatch blocking to wait when the read-write correlation occurs. The condition register read-write rules are as follows:

[0072] ● Read rule:

[0073] (1) All instructions of the scalar operation unit, the memory access unit, and the synchronization unit support the conditional execution, and need to read the value of the condition register.

[0074] (2) The scalar operation unit also supports the read condition register instruction operation.

[0075] (3) The jump and function call instruction of the program control unit supports the read condition register operation.

[0076] ● Write rule:

[0077] (1) The scalar operation unit supports the write condition register instruction.

[0078] (2) The scalar operation unit logic class instruction and the comparison class instruction support the write condition register option.

[0079] When the actual execution of the write condition register instruction issued in front is not yet executed, and the instruction of reading or writing the same condition register enters, the pipeline is blocked, a condition execution blocking signal is generated, and the previous condition register is written.

[0080] In addition, the register renaming unit includes one or more physical registers and one or more logical registers.

[0081] Any physical register is one of the following: a scalar physical register, a vector physical register, a condition register, and a flag register.

[0082] Any logical register is one of the following: a scalar logical register and a vector logical register.

[0083] For example, the register renaming unit contains one or more physical registers, for example, a plurality of 512-bit wide special vector registers, a plurality of condition registers, and a state flag register.

[0084] Among them, the special vector register is renamed, the condition register, and the state flag register are not renamed.

[0085] The number of logical registers is multiple, such as multiple logical registers being scalar logical registers and multiple vector logical registers.

[0086] In addition, the mapping relationship between the logical register and the physical register is maintained by the register mapping table. The mapping relationship between the vector logical register and the vector physical register is maintained by the special vector register mapping table.

[0087] 1) Register mapping table

[0088] Initially, the mapping physical registers of the table entries corresponding to all logical register indexes in the register mapping table are all 0. When the instruction is executed, or when the interrupt comes, the logical register allocated to the related physical register is determined, and the mapping of the table entry corresponding to the allocated logical register index in the register mapping table is updated to the identifier of the related physical register.

[0089] For example, the depth of the register mapping table is 32, the width is 6 bits, and the mapping relationship between all logical registers and all physical registers is saved. Initially, the mapping of the register mapping table is invalid, and the mapping physical registers of all table entries are all 0. When the physical register is allocated to the logical register for use, the table entry corresponding to the logical register index in the register mapping table is changed to the ID of the physical register.

[0090] It should be noted that the register mapping table is updated only when the instruction is actually executed. If the conditional execution instruction is not executed, the register mapping table will not be updated. In addition, the register mapping table will not be updated when the jump comes, but the interrupt return address must update the register mapping table when the interrupt comes, so as to ensure that the interrupt can return normally.

[0091] 2) Special vector register mapping table

[0092] Initially, the mapping vector physical registers of the table entries corresponding to all vector logical register indexes in the special vector register mapping table are all 0. When the instruction is executed, the vector logical register allocated to the related vector physical register is determined, and the mapping of the table entry corresponding to the allocated vector logical register index in the special vector register mapping table is updated to the identifier of the related vector physical register.

[0093] For example, the special vector register mapping table is 4 deep by 3 bits wide and holds the mapping of all vector logical registers to all vector physical registers. Initially, the special vector register mapping table is mapped to invalid and all the table entries are mapped to vector physical register 0. When a vector physical register is allocated to a vector logical register, the special vector register mapping table entry corresponding to the vector logical register index is changed to the ID of the vector physical register.

[0094] It should be noted that the special vector register mapping table is only updated when the instruction is actually executed. If the conditional execution instruction is not executed, the special vector register mapping table is not updated. Also, the special vector register mapping table is not updated when a jump occurs.

[0095] 3. Operation reservation stack unit

[0096] The operation reservation stack unit is the dispatch queue for the scalar operation units.

[0097] The operation reservation stack unit receives instructions, dispatch and renaming information from the register renaming unit and pushes the information into the queue. The operation reservation stack unit also pops ready instructions to the scalar operation units for execution.

[0098] The operation reservation stack unit also decodes the incoming instructions and stores the instruction type information.

[0099] That is, the operation reservation stack unit is the dispatch queue for the scalar operation units. The operation reservation stack unit receives instructions and related dispatch and renaming information from the register renaming unit and pushes the information into the queue. The operation reservation stack unit also pops ready instructions to the scalar operation units for execution. The operation reservation stack unit also decodes the incoming instructions and stores the instruction type information.

[0100] In implementation, the depth of the operation reservation stack unit can be flexibly adjusted. For example, the depth of the operation reservation stack unit is 8. Multiple scalar operation units share one operation reservation stack unit.

[0101] The instruction dispatch and receive rules of the operation reservation stack unit are as follows:

[0102] (1) The output of the register renaming unit enters the operation reservation stack unit.

[0103] (2) When there is any free scalar operation unit, it takes instructions and operands from the operation reservation stack unit for execution.

[0104] (3) The principle of taking instructions from the operation reservation stack unit for execution is to take executable instructions that can be sent from the operation reservation stack unit in the order from front to back for execution.

[0105] (4) Whether the instruction can be sent according to the values of all source registers or special vector registers or condition registers and status flag registers are ready to be determined.

[0106] (5) If there are multiple instructions to be sent, the oldest instruction is sent first according to the instruction order.

[0107] (6) If any scalar operation unit is blocked, it can no longer receive new instructions.

[0108] (7) If the instruction previously sent to any scalar operation unit is a division instruction, it cannot send a new division instruction until the division result is calculated and the calculation completion En signal is returned.

[0109] 4. Memory reservation stack unit

[0110] The memory reservation stack unit is the transmission queue of the memory access unit.

[0111] The memory reservation stack unit is used to receive instructions and register renaming information from the register renaming unit and push them into the queue.

[0112] The memory reservation stack unit is also used to send a read request to the register renaming unit when the instruction address register is ready, and save the read address operand.

[0113] The register renaming unit is also used to calculate the address and decode the address after the instruction gets the address, and save the decoding information.

[0114] The register renaming unit is also used to detect and transmit any instruction to the memory access unit for execution when the source register of the instruction is ready and the address decoding is complete.

[0115] In specific implementation, the depth of the memory reservation stack unit can be flexibly adjusted, such as the depth of the memory reservation stack unit being 16. Multiple memory access units share one memory reservation stack unit. The memory reservation stack unit is the transmission queue of the memory access unit. The memory reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the memory reservation stack unit is ready, a read request is sent to the register renaming unit and the read address operand is saved to the queue. After the instruction in the memory reservation stack unit gets the address, the address can be calculated and decoded, and the generated decoding information can be saved in the queue. When the source register of the instruction in the memory reservation stack unit is ready and the address decoding is complete, it can be transmitted to the memory access unit for execution, and a series of checks such as address type check, address comparison check and address forward check, etc. are required before transmission.

[0116] The rules for the memory reservation stack unit to send and receive instructions are as follows:

[0117] (1) The output of the register renaming unit enters the memory reservation stack unit.

[0118] (2) When the source operand of the address calculation is ready, the memory access address is calculated and saved in the memory reservation stack unit.

[0119] (3) Address-irrelevant instructions: can be sent out of order, the out-of-order rules are: read instruction after read instruction, read instruction after write instruction, write instruction after read instruction can be sent out of order, and write instruction after write instruction needs to be in order (cannot be sent to different memory access units at the same time), even if the write instruction after write instruction is address-irrelevant, it also needs to be in order.

[0120] (4) Address-dependent instructions: read instruction after write instruction, write instruction after read instruction, write instruction after write instruction, and read instruction after read instruction all need to be in order.

[0121] (5) Address-irrelevant but located in the same memory space as all instructions that have not been successfully sent (i.e., instructions on the way to the destination that have not been sent, including at the memory access unit level and at the memory access unit output level) can be sent out of order to the same memory access unit, but cannot be sent to two or more memory access units.

[0122] (6) Memory access instructions located in the same memory space but address-irrelevant can only be sent one at a time, and cannot be sent to two or more memory access units at the same time.

[0123] (7) Address-dependent judgment principle: whether the address is dependent or not is determined by whether it is located in different memory spaces or not, and whether it is dependent or not is determined by the data granularity when located in the same memory space.

[0124] 5. Scalar operation unit

[0125] In specific implementation, the scalar operation unit can be one or more.

[0126] If the scalar processor includes two scalar operation units, they are scalar operation unit 0 and scalar operation unit 1.

[0127] The scalar operation unit is used to receive the instructions and data sent by the operation reservation stack unit, perform operations on the data based on the instructions, and write the operation results back to the register renaming unit.

[0128] The scalar operation unit is the calculation unit of the scalar processor, and can perform various types of fixed-point and floating-point operations, such as addition and subtraction, multiplication, division, logical operation, comparison operation, and shifting. It receives the instructions and data sent by the operation reservation stack unit, performs operations, and writes the results back to the register heap unit of the register renaming unit or the special vector register heap unit.

[0129] The following exemplary provides several instruction examples, and in the specific implementation, it is not limited to the following instructions, and it is not limited whether to include all instructions.

[0130] The instruction of the execution stage of one level includes: fixed-point addition and subtraction, logic class instruction, shift class instruction, fixed-point comparison class instruction, read-write Flag instruction, fixed-point maximum and minimum instruction, ABS instruction, bit reverse order instruction, selection instruction, special vector register distribution instruction, read special vector register instruction, Byte reverse instruction, Merge instruction, immediate assignment instruction, FirstOne instruction, CRC instruction, floating-point classification instruction, floating-point partial domain, rounding instruction.

[0131] The instruction of the execution stage of three levels includes: fixed-point multiplication instruction, fixed-point conversion class instruction, bit screening instruction, Count instruction, floating-point addition and subtraction instruction.

[0132] The instruction supporting Bypass includes: selection instruction, fixed-point addition and subtraction instruction, shift class instruction, immediate assignment instruction, ABS instruction, logic class instruction, comparison class instruction, maximum and minimum instruction.

[0133] The execution period of the division instruction is uncertain, and the data of the divisor and the dividend is related. The instruction execution is completed to generate a DivEn instruction, indicating that the instruction execution is completed and the result is output to the register heap. During the execution of the division instruction, a new division instruction cannot be input, but other scalar calculation unit instructions can be input. The output port of the first stage pipeline is multiplexed when the output port of the first stage pipeline is not used by other scalar calculation unit instructions. The division outputs its result, and the DivEn identifier is output at the same time. The DivEn identifier is output to the operation reservation stack unit, indicating that the Div instruction can be continuously output to the current scalar operation unit.

[0134] 6, memory unit

[0135] In the specific implementation, the memory unit can be one or more.

[0136] If the scalar processor includes two memory units, they are memory unit 0 and memory unit 1.

[0137] The memory unit is used to receive the instruction and data and register information sent by the storage reservation stack unit, and read and write the data based on the instruction and register information.

[0138] The memory access unit is a functional module that executes memory access-related instructions in a scalar processor. The memory access unit receives instructions and data, as well as register-related information, from the memory-reserved stack. It executes the instructions accordingly, interacts with other units for data reading and writing, and writes data back to the register renaming unit for read and write instructions. This includes register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector-level read and write instructions. Vector granularities include 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing times.

[0139] In addition, the memory access unit is responsible for providing the number of instructions required by the FENCE, and the memory access unit interacts with the memory reservation stack unit to complete the data storage configuration.

[0140] 7. Program Control Unit

[0141] In practice, there is only one program control unit.

[0142] The program control unit receives instructions and data from the register renaming unit, processes the data based on the instructions, and outputs the processing results.

[0143] The program control unit is a functional module that executes instructions related to the execution order of the scalar processor's control program. The program control unit receives instructions and data from the register renaming unit, processes the data accordingly, and outputs the processing results to other modules of the scalar processor. Different instructions have different processing time cycles.

[0144] The program control unit is responsible for controlling the direction of program execution (such as stopping, interrupting, jumping, and function calling), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetching operation of the instruction cache, as well as the FENCE operation; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information, etc.

[0145] 8. Synchronization Unit

[0146] In practice, there is only one synchronization unit.

[0147] The synchronization unit is used for synchronizing the scalar processor and the vector processor.

[0148] like Figure 2 As shown, the synchronization unit establishes communication connections with the pipeline control unit, register renaming unit, program control unit, and vector processor.

[0149] The instructions for the synchronization unit come from the register renaming unit, and the reading and writing of data in the synchronization unit are all done in interaction with the register renaming unit.

[0150] The synchronization unit is configured to receive the pause signal sent by the pipeline control unit, send an execution stage pause signal generated when communicating with the vector processor to the pipeline control unit, so as to generate an execution pause signal of the scalar processor.

[0151] The synchronization unit is configured to generate an instruction and send the instruction to the program control unit.

[0152] That is, the synchronization unit is a unit for synchronizing the scalar processor and the vector processor, which receives an instruction and data sent by the register renaming unit, reads data from the vector processor and writes back to the register file, reads data from the register file unit or the special vector register file unit and sends the data to the functional module of the vector processor, is responsible for starting and state querying of the vector processor, such as querying reading and writing of the read-write FIFO (First Input First Output) in the vector program control unit of the vector processor, configuration of the register file, reading or writing of the scalar register, state querying of the register file, reading of the FIFO depth, reading of the start vector processor instruction counter, and providing the program control unit with synchronization unit instruction information.

[0153] The synchronization unit interacts with the pipeline control unit, the register renaming unit and the program control unit inside the scalar processor, and interacts with the vector processor, the scalar processor and the vector processor transmission queue module. The synchronization unit instruction comes from the register renaming unit, and the reading and writing of data are interacted with the register renaming unit. The blocking signal from the pipeline control unit is received, and the execution stage blocking signal of the synchronization unit itself is generated when communicating with the vector processor, and is sent to the pipeline control unit, which is used to generate the execution stage signal acting on the entire scalar processor. The synchronization unit generates an instruction to be executed in the next cycle, and sends the instruction to the program control unit, which is used for the instruction of the counter of the program control unit. The synchronization unit interacts with the vector processor, including but not limited to: configuring the register file with special vector registers or registers, reading and writing the scalar register, querying the write state of the register file. The scalar processor interacts with the scalar processor and the vector processor transmission queue module, including but not limited to: starting the vector processor, querying the state of the vector processor, reading and writing the FIFO data in the instruction fetch unit of the vector processor, reading the FIFO depth, and reading the start vector processor instruction counter.

[0154] Therefore, in the specific implementation, the synchronization unit can have the following functions (it should be noted that the following functions are only examples, and there can be other functions, and the embodiments and subsequent embodiments do not limit the specific functions of the synchronization unit) :

[0155] Start vector processor function, used to start the vector processor, including immediate start and register start, the pipeline waits until the start is successful, or the result of success or failure is written back to the destination register.

[0156] Query vector processor execution status function, supporting optional item B.

[0157] Read-write FIFO function, the FIFO is located in the instruction fetch unit of the vector processor, for example, the FIFO bit width is 32 bits, the read-write FIFO waits until success, or the result of success or failure of the read-write FIFO is written back to the register.

[0158] Write register file stack function, including special vector register write or register write.

[0159] Read-write scalar register function, including immediate index or register index read-write.

[0160] Query register file stack write-back status function, for example, to wait until all write register file stacks are completed, or the result of whether the write register file stack is completed is returned to the register.

[0161] When the relevant operation is not completed, a synchronization unit's own blocking signal is generated, which blocks the waiting, and the signal is sent to the pipeline control unit to generate a pipeline blocking signal.

[0162] A FIFO (for example, a 32-bit deep FIFO) can also be added between the scalar processor and the vector processor to store the start vector processor request, and the read-write FIFO previously located in the vector processor is moved to the scalar processor and vector processor transmission queue module. The scalar processor and vector processor transmission queue module unit implements the start vector processor, the query vector processor execution status, the read-write FIFO function, the read FIFO depth function, the read start vector processor instruction counter function, the start vector processor can be started successfully under the condition that the start vector processor FIFO is not full, the query vector processor execution status passes, and the vector processor state is stopped under the condition that the vector processor is executed and the start vector processor FIFO is empty.

[0163] 9. Pipeline control unit

[0164] Pipeline control unit, used to generate the pause signal of the pipeline and / or generate the start and stop signal of the scalar processor.

[0165] The pipeline control unit is the flow control unit of the scalar processor, and is connected with each unit inside the scalar processor, responsible for generating the blocking signal of the pipeline, for example, the blocking in the normal working mode and the blocking in the debugging mode.

[0166] The pipeline control unit also communicates with the communication and synchronization unit to generate a signal for starting and stopping the scalar processor.

[0167] In addition, the scalar processor can also perform conditional execution decoding in actual application. For example, when the scalar processor performs conditional execution decoding, the scalar processor performs execution condition judgment on the preset bits of the instruction, and outputs a valid instruction if the condition is met, or outputs a null instruction otherwise. The null instruction represents a null instruction or an invalid instruction.

[0168] If there is a read-write related operation on the condition register, pipeline blocking is triggered, and the read operation is performed after the write operation on the condition register is completed. The condition register read-write operation does not have a bypass.

[0169] Taking the condition register as two, condition register 0 and condition register 1, and the preset bits as [29:28] bits as an example, when the scalar processor performs conditional execution decoding, the scalar processor performs execution condition judgment on the input instruction based on the [29:28] bits of the instruction set encoding, and outputs a valid instruction if the condition is met, or outputs a null instruction otherwise.

[0170] The [29:28] bits are 00, indicating that the condition register 0 is executed, the [29:28] bits are 01, indicating that the condition register 1 is executed, the [29:28] bits are 10, indicating that the condition register 0 is executed, and the [29:28] bits are 11, indicating unconditional execution. If the condition is not met, the instruction is invalid, and a null instruction is output.

[0171] If there is a read-write related operation on the condition register, pipeline blocking is triggered, and the read operation is performed after the write operation on the condition register is completed. The condition register read-write operation does not have a bypass.

[0172] The embodiment provides a scalar processor, which comprises a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit. The synchronization unit is used for synchronization between the scalar processor and a vector processor. The scalar processor realizes synchronization between the scalar processor and the vector processor through the synchronization unit, and thus efficiently executes instructions.

[0173] Based on the same inventive concept of the scalar processor, the embodiment provides a high-performance processor, which comprises a scalar processor and a vector processor.

[0174] The connection relationship between the scalar processor and the vector processor can be as shown in Figure 3

[0175] ​The scalar processor and the vector processor share a data store. The vector processor can only access the data store and can only be executed by the scalar processor. That is, the vector processor can only access the data store and can only be executed by the scalar processor.

[0176] A connection is established between the scalar processor and the vector processor. For example, the scalar processor and the vector processor are connected through a dedicated instruction channel.

[0177] In addition, the high-performance processor can further include two registers, one register corresponding to the scalar processor and the other register corresponding to the vector processor. The vector processor can read and write its corresponding register, and the scalar processor can read and write the register corresponding to the vector processor in addition to reading and writing its corresponding register.

[0178] The scalar processor can read and write the register of the vector processor.

[0179] The scalar processor is connected to a global memory.

[0180] The scalar processor can be

[0181] The scalar processor can be Figure 1 The scalar processor can be

[0182] That is, the scalar processor includes a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0183] The fetch unit is configured to fetch instructions and dispatch the instructions.

[0184] The register renaming unit is configured to receive the instructions dispatched by the fetch unit and perform register renaming.

[0185] The operation reservation stack unit is a firing queue of the scalar operation unit.

[0186] The memory reservation stack unit is a firing queue of the memory access unit.

[0187] The scalar operation unit is configured to receive the instructions and data sent by the operation reservation stack unit, perform operations on the data based on the instructions, and write the operation results back to the register renaming unit.

[0188] The memory access unit is configured to receive the instructions and data sent by the memory reservation stack unit, register information, read and write the data based on the instructions and the register information.

[0189] The program control unit is configured to receive the instructions and data from the register renaming unit, process the data based on the instructions, and output the processing results.

[0190] a synchronization unit for synchronizing the scalar processor with the vector processor.

[0191] a pipeline control unit for generating a stall signal of the pipeline and / or generating a start and stop signal of the scalar processor.

[0192] Optionally, the scalar processor further comprises an instruction cache and a data store.

[0193] a fetch unit for generating a fetch request address, outputting the fetch request address to the instruction cache for instruction fetch, receiving the instruction from the instruction cache and storing the instruction in the data store, sequentially reading the qualified instruction from the data store in each cycle, decoding and checking the read instruction, and sequentially dispatching the checked instruction.

[0194] Optionally, the scalar processor further comprises a special vector register and a status flag register.

[0195] a register renaming unit for receiving and storing the dispatched instruction from the fetch unit, renaming the special vector register, decoding the instruction condition, and generating a pipeline stall signal, receiving and writing back data from one or more of the scalar operation unit, the memory access unit, the program control unit, the synchronization unit, the special vector register, the condition register, and the flag register, and sending the instruction to one or more of the operation reservation stack unit, the memory reservation stack unit, the program control unit, and the synchronization unit.

[0196] The condition register is located in the register renaming unit.

[0197] The instruction of the scalar operation unit and the memory access unit supports the operation of reading and writing the condition register.

[0198] The instruction of the synchronization unit supports the operation of reading the condition register.

[0199] The jump and function call instruction of the program control unit supports the operation of reading the condition register.

[0200] When the instruction enters the condition register, if there is an unexecuted instruction in the condition register, the pipeline is stalled.

[0201] Optionally, the register renaming unit comprises one or more physical registers and one or more logical registers.

[0202] Any physical register is one of the following: a scalar physical register, a vector physical register, a condition register, and a flag register.

[0203] Any logical register is one of the following: a scalar logical register and a vector logical register.

[0204] The mapping relationship between the logical registers and the physical registers is maintained by a register mapping table. Initially, the mapping physical registers corresponding to the table entries with all logical register indexes in the register mapping table are all 0. When an instruction is executed or an interrupt occurs, the mapping of the table entry corresponding to the allocated logical register index in the register mapping table is updated to the identifier of the relevant physical register after the logical register allocated for the relevant physical register is determined.

[0205] The mapping relationship between the vector logical registers and the vector physical registers is maintained by a special vector register mapping table. Initially, the mapping vector physical registers corresponding to the table entries with all vector logical register indexes in the special vector register mapping table are all 0. When an instruction is executed, the mapping of the table entry corresponding to the allocated vector logical register index in the special vector register mapping table is updated to the identifier of the relevant vector physical register after the vector logical register allocated for the relevant vector physical register is determined.

[0206] Optionally, an operation reservation stack unit is configured to receive the instruction, dispatch and renaming information from the register renaming unit and push into a queue. The ready instruction is popped out to the scalar operation unit for execution.

[0207] The operation reservation stack unit is also configured to decode the input instruction and store the instruction type information.

[0208] Optionally, a storage reservation stack unit is configured to receive the instruction and register renaming information from the register renaming unit and push into a queue.

[0209] The storage reservation stack unit is also configured to send a read request to the register renaming unit when the instruction address register is ready and save the read address operand.

[0210] The register renaming unit is also configured to calculate the address and decode the address after the instruction obtains the address, and save the decoding information.

[0211] The register renaming unit is also configured to detect and then transmit any instruction whose source register is ready and the address decoding is completed to the memory unit for execution.

[0212] Optionally, the scalar processor performs the execution condition judgment on the preset bit of the instruction when performing the conditional execution decoding, and outputs a valid instruction if the condition is met, or outputs an empty instruction otherwise.

[0213] If there is a read-write related operation on the condition register, the pipeline is blocked and the read operation is performed after the write operation on the condition register is completed. The read-write operation on the condition register does not have a bypass.

[0214] Optionally, the synchronization unit is communicatively coupled to the pipeline control unit, the register renaming unit, the program control unit, and the vector processor.

[0215] The instruction of the synchronization unit is from the register renaming unit, and the reading and writing of the data of the synchronization unit are both with the register renaming unit.

[0216] The synchronization unit is configured to receive the pause signal sent by the pipeline control unit, and send the execution stage pause signal generated when communicating with the vector processor to the pipeline control unit, so as to generate the execution pause signal of the scalar processor.

[0217] The synchronization unit is configured to generate instructions and transmit the instructions to the program control unit.

[0218] (II) Vector processor

[0219] Referring to Figure 4 The vector processor comprises a vector program control unit, a plurality of functional units, a register file stack, and a scalar register.

[0220] In addition, the vector processor further comprises private vector registers of the vector interleaving unit and private vector registers of the vector access unit.

[0221] 1. Vector program control unit

[0222] The vector program control unit is configured to fetch instructions and emit instructions.

[0223] That is, the vector program control unit is configured to fetch instructions, determine whether to execute the instructions, and emit the instructions to the functional units based on the determination result.

[0224] The vector program control unit is further configured to control the jump of the instructions.

[0225] The vector program control unit has scalar computing capability.

[0226] The vector program control unit interacts with the scalar register.

[0227] In a specific implementation, the vector program control unit is an instruction fetch and emission unit, which fetches instructions from a cache according to a PC value, emits the instructions to the functional units according to a wait value (configured by a wait instruction) after determining whether to execute the instructions, controls the jump of the instructions, and has partial scalar computing capability.

[0228] In addition, the vector program control unit is further configured to receive a start command sent by another operation processor, and start the vector processor. The vector processor returns an indication signal indicating whether the vector processor is ended to the other operation processor.

[0229] Taking other processing processors as scalar processors as an example, the vector program control unit receives the start command issued by the synchronization unit of the scalar processor, starts the vector processor to execute, and also returns an indication signal to the synchronization unit whether the vector processor execution has ended.

[0230] 2. Functional Units

[0231] Functional units are used to perform functional processing according to instructions.

[0232] For example, a functional unit receives instructions from a vector program control unit, processes the data accordingly, and outputs the processing results at the address specified in the instructions.

[0233] The functional units include: one or more vector operation units, one or more vector interleaving units, and one or more vector access units.

[0234] 1) Vector operation unit

[0235] Any vector operation unit is used to perform vector operations according to instructions.

[0236] like Figure 5 As shown, any vector operation unit includes: a floating-point multiply-add subunit, a floating-point multiply-accumulate subunit, a floating-point arithmetic subunit, a tensor multiplication subunit, and an intermediate result register.

[0237] The floating-point multiply-accumulate subunit and the floating-point arithmetic subunit share one issue slot. Therefore, a maximum of 8 instructions from the vector operation unit can be issued per cycle.

[0238] The floating-point multiplication-accumulation subunit and the tensor multiplication subunit share a single launch slot.

[0239] The floating-point multiply-accumulate subunit is a functional unit that executes instructions related to floating-point multiply-accumulate operations. For example, instructions related to floating-point multiply-accumulate operations include integer and floating-point vector multiplication and accumulation, multiplication, addition, tensor calculation, etc.

[0240] Each vector operation unit has its own intermediate result register.

[0241] One floating-point multiply-accumulate subunit, one floating-point multiply-accumulate subunit, one tensor multiplication subunit, and one floating-point arithmetic subunit share an intermediate result register.

[0242] (1) Floating-point multiply-accumulate and floating-point multiply-accumulate subunits, which can perform integer and floating-point vector multiplication, multiply-accumulate, and other operations. Supported types include, but are not limited to, int32, fp32, and fp64.

[0243] (2) The floating-point arithmetic operator unit can perform integer and floating-point vector arithmetic operations, such as comparison, addition, subtraction, bit operation, etc. The supported types include but are not limited to int8, uint8, int16, uint16, int32, uint32, bool, fp16, bf16, fp32, tf32, fp64.

[0244] (3) The tensor multiplication subunit can perform tensor multiplication, multiply-accumulate, etc. The supported types include but are not limited to int8, bf16, fp16, tf32.

[0245] 2) Vector interleaving unit

[0246] Any vector interleaving unit is used for interleaving and logical processing of data according to instructions.

[0247] The vector interleaving unit is a control and data processing unit in the vector processor, responsible for interleaving data, supporting logic and partial fixed-point calculation, and also supporting a large number of customized instructions, including table lookup, transverse calculation, sparse matrix calculation, precision conversion, FIFO (First Input First Output), etc. Data broadcast, extraction, internal interleaving, etc. instructions are executed.

[0248] Each vector interleaving unit has a set of private vector registers, so the private vector registers of the vector interleaving unit correspond to the vector interleaving unit one by one.

[0249] 3) Vector access unit

[0250] Any vector access unit is used for multi-mode memory access, address calculation, and scalar calculation according to instructions.

[0251] The vector access unit is a memory access unit in the vector processor, mainly responsible for reading instructions / writing instructions and various scalar calculations.

[0252] Among them, the reading / writing instructions support multiple memory access modes, such as row mode, column mode / discrete mode / extended mode / accumulation mode.

[0253] At the same time, multiple parameter configurations are supported, and the maximum reading / writing instruction data bit width can reach 1024 bits. Address calculation, loading / storage, etc. instructions are executed.

[0254] All vector access units share a set of private vector registers, so the private vector registers of the vector access unit are shared by multiple vector access units.

[0255] 3, Register file stack

[0256] The register file stack is used to return data after reading and writing requests. The data is rearranged before being returned. The register file stack interacts with the functional units for reading and writing. The data in the register file stack is used to configure the configuration registers of the vector program control unit.

[0257] The register file stack is a general vector register stack, which is the main storage unit in the vector processor. It is responsible for receiving reading and writing requests and returning data. In some functions, the data can be rearranged before being returned to the request module.

[0258] The register file stack interacts with the functional units (such as floating-point multiply-add operation subunits, floating-point arithmetic operation subunits, floating-point multiply-accumulate operation subunits, and tensor multiplication subunits) in the vector processor for reading and writing. Meanwhile, the data in the register file stack is used to configure the instruction fetch unit configuration registers.

[0259] The register file stack is also used to write data to other arithmetic processors. It receives state information from other arithmetic processors to query whether the data writing is complete.

[0260] Taking a scalar processor as an example, the synchronization unit of the scalar processor can write data to the register file stack. The register file stack can also receive state information from the synchronization unit of the scalar processor to query whether the data writing is complete.

[0261] The depth of the register file stack is configurable.

[0262] Figure 6 A schematic diagram of a vector processor with four vector operation subunits, four vector interleaving subunits, and four vector access subunits is shown.

[0263] The vector processor provided in the embodiment supports a VLIW (Very Long Instruction Word) instruction set. Each VLIW can consist of one or more instructions, and each instruction corresponds to a functional unit.

[0264] In addition, the vector processor and other arithmetic processors are provided with a read FIFO unit and a write FIFO unit.

[0265] The vector program control unit and other arithmetic processors perform reading operations on the read FIFO unit and writing operations on the write FIFO unit.

[0266] The other arithmetic processors perform reading operations or writing operations on the vector registers.

[0267] The scalar processor and the vector processor are provided with read and write FIFO units for transmitting data, and the scalar processor and the vector program control unit can perform read or write operation on the read and write FIFO.

[0268] Meanwhile, the synchronization unit of the scalar processor can perform read or write operation on the scalar register of the vector processor.

[0269] The scalar processor in the high-performance processor comprises a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit. The synchronization unit is configured to synchronize the scalar processor and the vector processor. The high-performance processor synchronizes the scalar processor and the vector processor through the synchronization unit, thereby efficiently executing instructions.

[0270] Based on the same inventive concept of the scalar processor, the electronic device comprises the high-performance processor or one or more processor clusters, wherein each processor cluster comprises a plurality of high-performance processors.

[0271] The heterogeneous multi-core processor can be as shown in Figure 3 The implementation details of the heterogeneous multi-core processor can also be as shown in the embodiment shown in Figure 3 The implementation details of the heterogeneous multi-core processor can also be as shown in the embodiment shown in

[0272] For example, the high-performance processor comprises a scalar processor and a vector processor.

[0273] The scalar processor can be as shown in Figure 1 The scalar processor can be as shown in

[0274] The scalar processor comprises a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit.

[0275] The fetch unit is configured to fetch instructions and dispatch the instructions.

[0276] The register renaming unit is configured to receive the instructions dispatched by the fetch unit and perform register renaming.

[0277] The operation reservation stack unit is a firing queue of the scalar operation unit.

[0278] The memory reservation stack unit is a firing queue of the memory access unit.

[0279] The scalar operation unit receives the instruction and data sent by the operation reservation stack unit, and performs operation on the data based on the instruction, and writes the operation result back to the register renaming unit.

[0280] The memory access unit receives the instruction and data, and register information sent by the memory reservation stack unit, and performs read and write on the data based on the instruction and register information.

[0281] The program control unit receives the instruction and data from the register renaming unit, processes the data based on the instruction, and outputs the processing result.

[0282] The synchronization unit is used for synchronization between the scalar processor and the vector processor.

[0283] The pipeline control unit is used for generating a pause signal of the pipeline and / or generating a start and stop signal of the scalar processor.

[0284] Optionally, the scalar processor further comprises an instruction cache and a data storage.

[0285] The instruction fetch unit generates an instruction fetch request address, outputs the instruction fetch request address to the instruction cache for instruction fetch, receives the instruction from the instruction cache, and stores the instruction in the data storage. In each cycle, the instruction fetch unit sequentially reads the qualified instruction from the data storage, decodes and checks the read instruction, and sequentially dispatches the checked instruction.

[0286] Optionally, the scalar processor further comprises a special vector register and a status flag register.

[0287] The register renaming unit receives and stores the instruction dispatched by the instruction fetch unit, renames the special vector register, decodes the instruction condition, and generates a pipeline stall signal. The register renaming unit receives and writes back the data from one or more of the scalar operation unit, the memory access unit, the program control unit, the synchronization unit, the special vector register, the condition register, and the flag register. The register renaming unit sends the instruction to one or more of the operation reservation stack unit, the memory reservation stack unit, the program control unit, and the synchronization unit.

[0288] The condition register is located in the register renaming unit.

[0289] The instruction of the scalar operation unit and the memory access unit supports the operation of reading and writing the condition register.

[0290] The instruction of the synchronization unit supports the operation of reading the condition register.

[0291] The jump and function call instruction of the program control unit supports the operation of reading the condition register.

[0292] When the instruction enters the condition register, if there is an unexecuted instruction in the condition register, the pipeline is stalled.

[0293] Optionally, the register renaming unit comprises one or more physical registers and one or more logical registers.

[0294] Any physical register is one of the following: a scalar physical register, a vector physical register, a condition register, a flag register.

[0295] Any logical register is one of the following: a scalar logical register, a vector logical register.

[0296] The mapping relationship between the logical registers and the physical registers is maintained by a register mapping table. Initially, all the mapping physical registers corresponding to the table entries of the logical register indexes in the register mapping table are all 0. When an instruction is executed or an interrupt occurs, the logical register allocated to the relevant physical register is determined, and the mapping of the table entry corresponding to the allocated logical register index in the register mapping table is updated to the identifier of the relevant physical register.

[0297] The mapping relationship between the vector logical registers and the vector physical registers is maintained by a special vector register mapping table. Initially, all the mapping vector physical registers corresponding to the table entries of the vector logical register indexes in the special vector register mapping table are all 0. When an instruction is executed, the vector logical register allocated to the relevant vector physical register is determined, and the mapping of the table entry corresponding to the allocated vector logical register index in the special vector register mapping table is updated to the identifier of the relevant vector physical register.

[0298] Optionally, the operation reservation stack unit is configured to receive instructions, dispatch and renaming information from the register renaming unit, and push into a queue. The ready instructions are popped out to the scalar operation unit for execution.

[0299] The operation reservation stack unit is also configured to decode the input instructions and store instruction type information.

[0300] Optionally, the storage reservation stack unit is configured to receive instructions and register renaming information from the register renaming unit, and push into a queue.

[0301] The storage reservation stack unit is also configured to send a read request to the register renaming unit when an instruction address register is ready, and save the read address operand.

[0302] The register renaming unit is also configured to calculate an address and decode the address when the instruction obtains the address, and save the decoding information.

[0303] The register renaming unit is also configured to detect when any instruction has a ready source register and the address decoding is completed, and then transmit the instruction to the memory unit for execution.

[0304] Optionally, the scalar processor performs execution condition judgment on the preset bit of the instruction when performing conditional execution decoding, and outputs a valid instruction if the condition is met, or outputs a null instruction otherwise.

[0305] If there is a read-write related operation on the condition register, pipeline blocking is triggered, and the read operation is performed after the write operation on the condition register is completed. The read-write of the condition register does not have a bypass.

[0306] Optionally, the synchronization unit is in communication connection with the pipeline control unit, the register renaming unit, the program control unit, and the vector processor.

[0307] The instruction of the synchronization unit comes from the register renaming unit, and the read-write of the data of the synchronization unit is all interactive with the register renaming unit.

[0308] The synchronization unit is configured to receive a pause signal sent by the pipeline control unit, and send an execution stage pause signal generated when communicating with the vector processor to the pipeline control unit, so as to generate an execution pause signal of the scalar processor.

[0309] The synchronization unit is configured to generate an instruction and transmit the instruction to the program control unit.

[0310] The embodiment provides an electronic device, and the scalar processor in the electronic device comprises: an instruction fetching unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory accessing unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit; the synchronization unit is configured to synchronize the scalar processor and the vector processor. The electronic device synchronizes the scalar processor and the vector processor through the synchronization unit, and thus efficiently executes instructions.

[0311] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program codes. The solutions in the embodiments of the present application can be implemented in various computer languages, such as object-oriented programming languages Java and interpreted scripting language JavaScript.

[0312] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0313] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 means for functionally implementing the steps listed in the flowchart block or blocks.

[0314] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks ​ means for functionally implementing the steps listed in the flowchart block or blocks.

[0315] While the preferred embodiments of the application have been described, additional variations and modifications can be employed by those skilled in the art. Therefore, the appended claims intend to cover all such modifications and variations as fall within the true spirit and scope of the application.

[0316] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A scalar processor, characterized in that, The scalar processor includes: an instruction fetch unit, a register renaming unit, an arithmetic reserved stack unit, a memory reserved stack unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit. The instruction fetching unit is used to fetch instructions and dispatch instructions; The register renaming unit is used to receive instructions and register renaming dispatched by the instruction fetch unit; The operation reserve stack unit is the issue queue of the scalar operation unit; The storage reservation stack unit is the issue queue of the memory access unit; The scalar arithmetic unit is used to receive instructions and data sent by the arithmetic storage stack unit, perform arithmetic on the data based on the instructions, and write the arithmetic result back to the register renaming unit. The memory access unit is used to receive instructions, data, and register information sent by the memory retention stack unit, and to read and write the data based on the instructions and register information. The program control unit is used to receive instructions and data from the register renaming unit, process the data based on the instructions, and output the processing result. The synchronization unit is used for synchronizing the scalar processor and the vector processor; the synchronization unit establishes a communication connection with the pipeline control unit, the register renaming unit, the program control unit, and the vector processor. The instructions of the synchronization unit come from the register renaming unit, and the reading and writing of data in the synchronization unit are all done in interaction with the register renaming unit. The synchronization unit is used to receive the pause signal sent by the pipeline control unit, and send the execution-level pause signal generated when communicating with the vector processor to the pipeline control unit so as to generate the execution pause signal of the scalar processor. The synchronization unit is used to generate instructions and transmit them to the program control unit; The pipeline control unit is used to generate a pipeline pause signal and / or generate start and stop signals for the scalar processor.

2. The scalar processor according to claim 1, characterized in that, The scalar processor further includes: an instruction cache and data storage; The instruction fetch unit is configured to generate an instruction fetch request address, output the instruction fetch request address to the instruction cache for instruction fetching, receive instructions from the instruction cache, and store them in the data storage; in each cycle, it sequentially reads instructions that meet the conditions from the data storage, decodes and performs relevant checks on the read instructions, and then sequentially dispatches the checked instructions.

3. The scalar processor according to claim 1, characterized in that, The scalar processor also includes: a special vector register and a status flag register; The register renaming unit is used to receive and store instructions dispatched by the instruction fetch unit, rename special vector registers, conditionally decode instructions, and generate pipeline congestion signals; receive data from one or more of the scalar arithmetic unit, memory access unit, program control unit, synchronization unit, special vector register, condition register, and flag register and write it back; and send instructions to one or more of the arithmetic reserved stack unit, storage reserved stack unit, program control unit, and synchronization unit. The condition register is located in the register renaming unit; The instructions of the scalar arithmetic unit and the memory access unit support reading and writing the condition register; The instructions of the synchronization unit support reading the condition register; The jump and function call instructions of the program control unit support reading the condition register; When an instruction enters the condition register, the pipeline will be blocked if there are unexecuted instructions in the condition register.

4. The scalar processor according to claim 3, characterized in that, The register renaming unit includes: one or more physical registers and one or more logical registers; Among them, any physical register can be one of the following: scalar physical register, vector physical register, condition register, or flag register; Any logic register can be one of the following: scalar logic register or vector logic register; The mapping relationship between logical registers and physical registers is maintained by a register mapping table. Initially, the mapped physical registers of all entries corresponding to logical register indices in the register mapping table are all 0. When an instruction is executed or an interrupt occurs, the logical register allocated to the relevant physical register is determined, and the mapping of the entries corresponding to the allocated logical register indices in the register mapping table is updated to the identifier of the relevant physical register. The mapping relationship between vector logic registers and vector physical registers is maintained by a special vector register mapping table. Initially, the mapped vector physical registers of all entries corresponding to the vector logic register indices in the special vector register mapping table are all 0. When an instruction is executed, the vector logic register allocated to the relevant vector physical register is determined, and the mapping of the entries corresponding to the allocated vector logic register indices in the special vector register mapping table is updated to the identifier of the relevant vector physical register.

5. The scalar processor according to claim 1, characterized in that, The operation retention stack unit is used to receive instructions, dispatch and renaming information from the register renaming unit and push them into the queue; pop ready instructions to the scalar operation unit for execution; The operation storage stack unit is also used to decode the input instructions and store instruction type information.

6. The scalar processor according to claim 1, characterized in that, The storage retention stack unit is used to receive instructions and register renaming information from the register renaming unit and push them into the queue. The storage retention stack unit is also used to send a read request to the register renaming unit when the instruction address register is ready, and save the read address operand; The register renaming unit is also used to calculate the address, decode the address, and save the decoding information after the address is obtained by the instruction. The register renaming unit is also used to detect and send any instruction to the memory access unit for execution when the source register of any instruction is ready and the address decoding is completed.

7. The scalar processor according to claim 1, characterized in that, When performing conditional execution decoding, the scalar processor checks the execution conditions of the preset bits of the instruction. If the conditions are met, it outputs a valid instruction; otherwise, it outputs an empty instruction. If there are read / write related operations in the condition register, pipeline blocking is triggered, and the read operation will only be performed after the condition register write operation is completed; there is no bypass for condition register read / write.

8. A high-performance processor, characterized in that, include: The scalar processor and vector processor according to any one of claims 1-7.

9. An electronic device, characterized in that, include: The high-performance processor of claim 8; or, comprising one or more processor clusters, wherein each processor cluster includes a plurality of the high-performance processors of claim 8.

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