Memory access dependency prediction method and system for processor and storage medium

Abstract

The invention is suitable for the technical field of processors, and particularly relates to a memory access dependency prediction method and system for a processor and a storage medium. The memory access dependency prediction system comprises a loading and storage dependency predictor used for predicting whether address dependency exists in a loading instruction and a storage instruction; the loading and storage dependency predictor comprises a loading instruction reordering cache, a storage instruction reordering cache, an index generator, a loading and storage dependency historical record table and a storage execution record table; the storage execution record table is used for recording a storage instruction reordering cache index value and a reordering cache age value of the storage instruction. Compared with the prior art, the method has the advantages that the address dependency prediction accuracy and efficiency of the loading instruction and the storage instruction are higher, and the performance of the processor is better.

Description

Technical Field

[0001] The present invention is applicable to the field of processor technology, and in particular relates to a memory access dependency prediction method, system, and storage medium for a processor. Background Art

[0002] There are many dependencies between different instructions in a program. Dependencies mean that the execution of one instruction depends on the result of another instruction. They can be divided into the following categories: (1) Data dependency, the correlation between the operands of instructions; (2) Address dependency, which indicates the correlation between the memory access addresses of the instructions (load instructions and store instructions) that access the memory; (3) Control dependency, the dependency caused by branch instructions; (4) Structural dependency, which is caused by insufficient hardware resources. In modern high-performance processors, the out-of-order execution and sequential submission strategies advocate "relieving" or "solving" the dependencies between instructions to improve instruction parallelism while ensuring that the processor can implement precise exceptions.

[0003] Compared to common instructions (such as arithmetic instructions), memory access instructions need to consider address dependencies in addition to data dependencies. There are three strategies for inferring address dependencies: (1) Conservative type, that is, when the load instruction load0 performs address dependency check, if there is an older store instruction store0 whose memory access address is not ready, it is always considered that there is an address dependency between the load instruction load0 and the store instruction store0, so the load instruction load0 will always access the memory after the store instruction store0.

[0004] (2) Aggressive type, that is, when the load instruction load0 performs address dependency check, if there is an older storage instruction store0 whose memory access address is not ready, it is always considered that there is no address dependency between the load instruction load0 and the storage instruction store0. If at this time there is no address dependency between the load instruction load0 and the older storage instruction storeX, the load instruction load0 may access the memory before the storage instruction store0.

[0005] (3) Prediction type: that is, to establish a predictor for address dependency between load instructions and store instructions. When the load instruction load0 performs an address dependency check, if there is an older store instruction store0 whose access address is not ready, the predictor is used to determine whether there is an address dependency between the load instruction load0 and the store instruction store0.

[0006] However, in the address dependency speculation process, the conservative strategy has the advantage of simple processing, but it will increase unnecessary waiting time for the load instruction to access memory when there is actually no address dependency between the load instruction and the store instruction.

[0007] The advantage of the aggressive strategy is its simplicity. However, it can sometimes be too aggressive and lead to misjudgment of the address dependencies between load and store instructions. This causes the load instruction to retrieve incorrect data from memory, ultimately necessitating a pipeline flush and re-fetching and executing instructions starting with the load instruction.

[0008] The predictive strategy is a compromise between the conservative strategy and the aggressive strategy. It consumes some hardware resources but provides more accurate address dependency prediction, thereby improving processor performance.

[0009] Therefore, there is an urgent need for a new memory access dependency prediction method, system and storage medium for a processor to solve the above technical problems. Summary of the Invention

[0010] The present invention provides a memory access dependency prediction method, system and storage medium for a processor, aiming to improve the accuracy and efficiency of address dependency prediction for load instructions and store instructions, thereby improving the performance of the processor.

[0011] In a first aspect, the present invention provides a memory access dependency prediction system for a processor, the memory access dependency prediction system comprising: a load and store dependency predictor, configured to predict whether the load instruction and the store instruction have an address dependency; The load and store dependency predictor includes a load instruction reorder cache, a store instruction reorder cache, an index generator, a load and store dependency history record table, and a store execution record table; The load instruction reordering cache is used to store the load instructions; The storage instruction reordering cache is used to store the storage instruction; The index generator is configured to process the program counter of the load instruction or the program counter of the store instruction to obtain a load table entry index or a store table entry index of the load and store dependency history table; and store the load table entry index into a corresponding table entry of the load instruction reorder cache or store the store table entry index into a corresponding table entry of the store instruction reorder cache; The load and store dependency history record table is used to record the dependency relationship between the load instruction and the store instruction; The storage execution record table is used to record the storage instruction reorder cache index value and the reorder cache age value of the storage instruction.

[0012] Preferably, the load and store dependency history table includes a request arbiter, a plurality of static storage modules, a plurality of in-row table entry selectors, and a port output selector; The request arbitrator is used to arbitrate the read and write requests of the load instruction and the store instruction to the static storage module according to a preset priority; The static storage module is used to store the index value of the storage execution record table; The in-row entry selector is used to select a single static storage entry in the static storage module and send it to the port output selector; The port output selector is used to select a final entry from the received multiple static storage entries for output.

[0013] Preferably, the storage instruction reordering cache is also used to read the execution record table entry index of the corresponding storage execution record table from the load and store dependency history record table according to the storage table entry index, and store the storage instruction reordering cache index value and the reordering cache age value corresponding to the storage instruction into the storage execution record table according to the execution record table entry index.

[0014] Preferably, the load instruction reordering cache is further used to read the execution record table entry index of the corresponding storage execution record table from the load and store dependency history record table according to the load table entry index, and read the reordering cache age value and the storage instruction reordering cache index value of the corresponding table entry in the storage execution record table according to the execution record table entry index; compare and predict the reordering cache age value with the load instruction to obtain a prediction result, and write the prediction result and the storage instruction reordering cache index value into the table entry corresponding to the load instruction reordering cache.

[0015] Preferably, when the load instruction and the store instruction are executed out of order, an address dependency check is performed based on the address information of the load instruction to determine whether there is a store instruction that precedes the current load instruction and is not ready in the program sequence; if so, determining whether the load instruction has an address dependency with the store instruction based on the prediction result; If the prediction result is that there is a store-after-load mark, the current load instruction enters a dormant state until the store instruction corresponding to the store instruction reordering cache index value wakes up the current load instruction, and the current load instruction re-initiates memory access and performs a write-back operation.

[0016] Preferably, when the load instruction and the store instruction are executed out of order, an address dependency check is performed based on the address information of the store instruction to determine whether the memory access address of the store instruction overlaps with the memory access address of the load instruction: if so, the store instruction reordering cache writes the store instruction reordering cache index value corresponding to the store instruction into the table entry corresponding to the load instruction in the load instruction reordering cache, and marks a store-after-load violation; When the load instruction performs an address check, if it meets the commit condition and is marked with the store-after-load violation, the load instruction reordering cache updates the entry of the load and store dependency history table according to the load table entry index and the store instruction reordering cache index value.

[0017] Preferably, the memory access dependency prediction system further includes a performance monitoring module; The performance monitoring module is used to count the total prediction times and prediction error times of the load and store dependency predictor; when the ratio between the total prediction times and the prediction error times reaches a preset ratio, all table entries in the load and store dependency predictor are cleared.

[0018] In a second aspect, the present invention further provides a memory access dependency prediction method for a processor, the memory access dependency prediction method being based on the memory access dependency prediction system for a processor as described in any one of the above embodiments, the memory access dependency prediction method comprising the following steps: S1. The index generator processes the program counter of the storage instruction to obtain a storage entry index of the load and store dependency history table; and stores the storage entry index into a corresponding entry of the storage instruction reorder cache; S2. Reading an execution record entry index of the corresponding storage execution record table from the load and store dependency history table according to the storage entry index, and storing a storage instruction reorder cache index value and a reorder cache age value of the storage instruction into a corresponding entry in the storage execution record table according to the execution record entry index; S3, the index generator processes the program counter of the load instruction to obtain a load table entry index of the load and store dependency history table; and stores the load table entry index into a corresponding table entry of the load instruction reordering cache; S4, the load instruction reads a corresponding execution record table entry index from the load and store dependency history table according to the load table entry index; reads the reorder cache age value and the store instruction reorder cache index value of the corresponding table entry in the store execution record table according to the execution record table entry index; and compares and predicts the reorder cache age value with the load instruction to obtain a prediction result; S5. When the load instruction and the store instruction are executed out of order, perform an address dependency check based on the address information of the load instruction to determine whether there is a store instruction that precedes the load instruction and is not ready in the program sequence; if so, determine whether the load instruction has an address dependency with the store instruction based on the prediction result; If the prediction result is that there is a store-after-load tag, the load instruction enters a dormant state until the store instruction corresponding to the store instruction reordering cache index value wakes up the load instruction, and the load instruction re-initiates memory access and performs a write-back operation.

[0019] In a third aspect, the present invention also provides a computer device comprising: a memory, a processor, and a memory access dependency prediction program for the processor stored in the memory and executable on the processor, wherein the processor implements the steps of the memory access dependency prediction method for the processor as described in any one of the above embodiments when executing the memory access dependency prediction program for the processor.

[0020] In a fourth aspect, the present invention also provides a computer-readable storage medium, on which a memory access dependency prediction program for a processor is stored. When the memory access dependency prediction program for a processor is executed by the processor, the steps in the memory access dependency prediction method for a processor as described in any one of the above embodiments are implemented.

[0021] Compared to the prior art, the present invention uses a load and store dependency predictor to store, record, and predict load and store instructions. When performing address dependency checks on load instructions, the load and store dependency predictor's prediction results can be used to determine whether there is an address dependency between the load and store instructions. This effectively predicts address dependencies for memory access instructions, reducing unnecessary memory access waits and the occurrence of load-after-store (LAW) violations. Furthermore, the present invention's load and store dependency history table utilizes banked static memory modules rather than register files, saving physical implementation area and reducing read / write port conflicts, making it suitable for high-frequency processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings: Figure 1 1 is a schematic structural diagram of a memory access dependency prediction system for a processor provided by an embodiment of the present invention; Figure 2 1 is a schematic diagram of some fields of a table entry of the load instruction reordering cache for a memory access dependency prediction system for a processor provided by an embodiment of the present invention; Figure 3 1 is a schematic diagram of some fields of an entry of the storage instruction reordering cache of the memory access dependency prediction system for a processor provided by an embodiment of the present invention; Figure 4 1 is a schematic diagram of the structure of a load and store dependency history record table for a memory access dependency prediction system for a processor provided by an embodiment of the present invention; Figure 5 1 is a schematic structural diagram of a static storage module for a processor memory access dependency prediction system provided by an embodiment of the present invention; Figure 6 1 is a schematic diagram of some fields of an entry in a load and store dependency history record table of a memory access dependency prediction system for a processor provided by an embodiment of the present invention; Figure 7 1 is a schematic structural diagram of a storage execution record table for a memory access dependency prediction system for a processor provided by an embodiment of the present invention; Figure 8 1 is a schematic structural diagram of an index generator for a memory access dependency prediction system for a processor provided by an embodiment of the present invention; Figure 9 This is a flowchart of a method for predicting memory access dependencies of a processor provided by an embodiment of the present invention; Figure 10 It is a structural diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0024] Example 1 Please refer to Figure 1 The present invention provides a memory access dependency prediction system 100 for a processor, wherein the memory access dependency prediction system includes a load and store dependency predictor 2 .

[0025] The load and store dependency predictor 2 is used to predict whether the load instruction and the store instruction have address dependencies, and can perform processing such as prediction, update, and clearing of the load instruction / store instruction.

[0026] The load and store dependency predictor 2 includes a load instruction reorder buffer 21 (Load Instruction Reorder Buffer, LOB), a store instruction reorder buffer 22 (Store Instruction Reorder Buffer, SOB), an index generator 23, a load and store dependency history table 24 (Load-Store Dependency History Table, LSDHT) and a store execution profile table 25 (Store Execution Profile Table, SPT).

[0027] The load instruction reordering cache 21 is used to store the load instructions in program order. It uses a first-in-first-out (FIFO) queue to load the issued but uncompleted load instructions to ensure that they submit the results in program order to maintain the correctness of memory operations. The relevant fields in the table entries of the load instruction reordering cache 21 can be referred to Figure 2 , which includes the valid flag bit, the load table entry index (load and store dependency history table index value), the store instruction reorder cache index value, and the prediction result (store-after-load prediction flag).

[0028] The storage instruction reordering cache 22 is used to store the storage instructions in the order of the program. It uses a first-in-first-out queue to manage the issued storage instructions, track their addresses, data and execution status, and ensure that the storage operation updates the memory in the order of the program. The relevant fields in the table of the storage instruction reordering cache 22 can be referred to Figure 3 , which includes a valid flag bit and a storage table entry index.

[0029] Specifically, in practical applications, the load instruction reorder cache 21 and the store instruction reorder cache 22 belong to the data load and store unit (LSU). Load instructions and store instructions can be executed out of order through the LSU. The LSU also includes structures such as a data cache, a page table cache, and an interface with an external storage subsystem.

[0030] The load and store dependency history record table 24 is used to record the dependency relationship between the load instruction and the store instruction, thereby providing a reference for dependency prediction of the current instruction and optimizing pipeline execution efficiency.

[0031] In the embodiment of the present invention, please refer to Figure 4 , Figure 4 This is a structural diagram of a load and store dependency history table 24 for a memory access dependency prediction system for a processor provided by an embodiment of the present invention; the load and store dependency history table 24 includes a request arbitrator 241, multiple static storage modules 242 (Static Random Access Memory, SRAM), multiple in-row table entry selectors 243 and a port output selector 244.

[0032] The request arbiter 241 is configured to arbitrate read and write requests from the load instructions and the store instructions to the static storage module 242 according to a preset priority. For example, when multiple load instructions / store instructions simultaneously require reading and writing to the static storage module 242, these requests are arbitrated according to a certain priority, ensuring that a static storage module 242 is accessed at most once in the same clock cycle.

[0033] The static storage module 242 is used to store the index value of the storage execution record table 25. b Each SRAM block has 2 h Each line stores 2 w There are 24 entries in the load and store dependency history table, please refer to Figure 5-6 , Figure 5 2 is a schematic structural diagram of a static storage module 242 for a processor memory access dependency prediction system provided by an embodiment of the present invention. Figure 6 Figure 2 is a schematic diagram of a portion of the fields in a load and store dependency history table 24 entry for a memory access dependency prediction system for a processor according to an embodiment of the present invention. The entries in the load and store dependency history table 24 stored in a single static storage module 242 include a 1-bit valid bit, an m-bit saturation counter, and an n-bit index value to the storage execution record table 25.

[0034] The row entry selector 243 is used to select a single static storage entry in the static storage module 242 and send it to the port output selector 244. For example, when a row is read from a static storage module 242, the 2 w Select a single entry from the entries.

[0035] The port output selector 244 is used to select the final table entry from the received multiple static storage table entries for output. b The final entry is selected from the single entries selected by the static storage modules 242 .

[0036] The storage execution record table 25 is used to record the storage instruction reorder cache index value and reorder cache age value of the storage instruction, assisting in handling storage conflicts and ensuring that storage operations are completed in the correct order. Figure 7 , Figure 7 2 is a schematic structural diagram of a storage execution record table 25 for a memory access dependency prediction system for a processor provided by an embodiment of the present invention, which includes a valid bit, a storage instruction reordering cache index value, and a reordering cache age value.

[0037] The index generator 23 is used to process the program counter of the load instruction or the program counter of the store instruction to obtain the load table entry index or the store table entry index of the load and store dependency history table 24; and store the load table entry index into the corresponding table entry of the load instruction reordering cache 21 or store the store table entry index into the corresponding table entry of the store instruction reordering cache 22, so as to quickly query the relevant records in the dependency history or cache. Please refer to Figure 8 , Figure 8 The following is a schematic diagram of the structure of an index generator 23 for a processor memory dependency prediction system provided by an embodiment of the present invention. It processes (e.g., performs a hash operation on) the 32-bit program counter (PC) of the load / store instruction to generate the load entry index / store entry index for the load and store dependency history table 24. The b bit is used for the static storage module 242 index, the h bit is used for the row index within the static storage module 242, and the w bit is used for the entry index within the row of the static storage module 242. Furthermore, the n-bit execution record entry index for the storage execution record table 25 is also generated by the index generator 23.

[0038] In an embodiment of the present invention, the storage instruction reorder cache 22 is further used to read the execution record table entry index of the corresponding storage execution record table 25 from the load and store dependency history table 24 according to the storage table entry index, and store the storage instruction reorder cache index value and the reorder cache age value corresponding to the storage instruction into the storage execution record table 25 according to the execution record table entry index.

[0039] In an embodiment of the present invention, the load instruction reordering cache 21 is further used to read the execution record table entry index of the corresponding storage execution record table 25 from the load and store dependency history table 24 according to the load table entry index, and read the reordering cache age value and the storage instruction reordering cache index value of the corresponding table entry in the storage execution record table 25 according to the execution record table entry index; compare and predict the reordering cache age value with the load instruction to obtain a prediction result, and write the prediction result and the storage instruction reordering cache index value into the corresponding table entry of the load instruction reordering cache 21.

[0040] In an embodiment of the present invention, when the load instruction and the store instruction are executed out of order, an address dependency check is performed based on the address information of the load instruction to determine whether a store instruction prior to the current load instruction is not ready in the program sequence; if so, determining whether the load instruction has an address dependency with the store instruction based on the prediction result; If the prediction result indicates the presence of a load-after-store (LAW) flag, the current load instruction enters a dormant state until the store instruction corresponding to the store instruction reordering cache index wakes it up. The current load instruction then re-initiates a memory access and performs a write-back operation, thus avoiding pipeline flushes caused by LAW violations.

[0041] In an embodiment of the present invention, when the load instruction and the store instruction are executed out of order, an address dependency check is performed based on the address information of the store instruction to determine whether the memory access address of the store instruction overlaps with the memory access address of the load instruction (address overlap refers to a situation where the memory address ranges involved in two or more memory access operations (such as load instructions / store instructions) partially or completely overlap). If so, the store instruction reordering cache 22 writes the store instruction reordering cache index value corresponding to the store instruction into the entry corresponding to the load instruction in the load instruction reordering cache 21, and marks a store-after-load violation. When the load instruction performs an address check, if it meets the commit condition and is marked with the store-after-load violation, the load instruction reorder cache 21 updates the entry of the load and store dependency history table 24 according to the load table entry index and the store instruction reorder cache index value.

[0042] Specifically, during the out-of-order execution process, including store instruction a and load instruction b, the address information of load instruction b is first sent to the data load and store processing unit (LSU). During the address dependency check, it is found that the memory access address of the older (earlier in the program order) store instruction a is not ready, and no valid prediction information is stored in the table entry of the load instruction reordering cache 21 (because the table entry index of its load and store dependency history table 24 does not index to a valid table entry). Therefore, it is speculated that there is no store-after-load (LAW) violation for store instruction a, and the memory access is continued and the load result is written back.

[0043] When the address of storage instruction a is then sent to the data load and store processing unit (LSU), it is found during the address dependency check that its memory access address overlaps with the memory access address of load instruction b, that is, a store-after-load (LAW) violation occurs at this time. Storage instruction a stores its own storage instruction reordering cache index value (sob_idx) into the entry of the load and store dependency history table 24 corresponding to load instruction b.

[0044] When load instruction b detects that it meets the commit condition and a store LAW violation has occurred, it reads the load entry index (ld_idx) stored in its load and store dependency history table 24 entry and deindexes it based on the store instruction reorder cache index value (sob_idx) recorded in its load instruction reorder cache 21 entry to obtain the store entry index (st_idx) recorded in the load instruction reorder cache 21 entry. Then, based on the load entry index (ld_idx) and the store entry index (st_idx), the corresponding two entries in load and store dependency history table 24 are read in sequence in two consecutive beats, the corresponding valid update counter values ​​are incremented, the valid bits are modified (in another alternative embodiment, they can be set to always be equal to the value of the highest bit of the valid update counter), and the PC of load instruction b is used by index generator 23 to generate an execution record entry index (spt_idx) for updating the store execution record table 25. The three are combined to form the new entry value of load and store dependency history table 24. The two generated new entry values ​​are sequentially stored in the two entries of the load and store dependency history table 24 indexed by the load entry index (ld_idx) and the store entry index (st_idx). Thus, the update process of the load and store dependency history table 24 is completed.

[0045] When the storage instruction a is submitted from the load instruction reordering cache 21, the load table entry index (ld_idx) stored in the table entry corresponding to the load instruction reordering cache 21 is used to read the corresponding load and store dependency history record table 24 again, and the storage execution record table 25 is indexed according to the execution record table entry index (spt_idx) recorded in the table entry of the load and store dependency history record table 24. If the storage instruction reordering cache index value (sob_idx) and the reordering cache age value (rob_ptr) of the read table entry of the storage execution record table 25 are respectively equal to the table entry index storage instruction reordering cache index value (sob_idx) and the reordering cache age value (rob_ptr) of the load instruction reordering cache 21 of the storage instruction a, then the table entry of the storage execution record table 25 is set to invalid.

[0046] In the embodiment of the present invention, the memory access dependency prediction system 100 further includes a performance monitoring module 1; The performance monitoring module 1 is used to count the total prediction times and prediction error times of the load and store dependency predictor 2 (a prediction error refers to when a storage instruction is renamed or when a load instruction address is checked and no address dependency is found); when the ratio between the total prediction times and the prediction error times reaches a preset ratio, all table entries in the load and store dependency predictor 2 are cleared.

[0047] Compared to the prior art, the present invention uses a load and store dependency predictor to store, record, and predict load and store instructions. When performing address dependency checks on load instructions, the load and store dependency predictor's prediction results can be used to determine whether there is an address dependency between the load and store instructions. This effectively predicts address dependencies for memory access instructions, reducing unnecessary memory access waits and the occurrence of load-after-store (LAW) violations. Furthermore, the present invention's load and store dependency history table utilizes banked static memory modules rather than register files, saving physical implementation area and reducing read / write port conflicts, making it suitable for high-frequency processors.

[0048] Example 2 Please refer to Figure 9 The present invention provides a memory access dependency prediction method for a processor. The memory access dependency prediction method is based on the memory access dependency prediction system 100 for a processor as described in the first embodiment. The memory access dependency prediction method includes the following steps: S1. The index generator 23 processes the program counter of the store instruction to obtain the store entry index (st_idx) of the load and store dependency history table 24; and stores the store entry index (st_idx) into the corresponding entry of the store instruction reorder cache 22; S2. Reading the execution record entry index of the corresponding store execution record table 25 from the load and store dependency history table 24 according to the store entry index (st_idx), and storing the store instruction reorder cache index value (sob_idx) and reorder cache age value (rob_ptr) of the store instruction into the corresponding entry of the store execution record table 25 according to the execution record entry index; S3, the index generator 23 processes the program counter of the load instruction to obtain the load table entry index (ld_idx) of the load and store dependency history table 24; and stores the load table entry index (ld_idx) into the corresponding table entry of the load instruction reorder cache 21; S4, the load instruction reads the corresponding execution record table entry index from the load and store dependency history table 24 according to the load table entry index (ld_idx); reads the reorder cache age value (rob_ptr) and the store instruction reorder cache index value (sob_idx) of the corresponding entry in the store execution record table 25 according to the execution record table entry index; compares and predicts the reorder cache age value (rob_ptr) with the load instruction to obtain a prediction result; S5. When the load instruction and the store instruction are executed out of order, perform an address dependency check based on the address information of the load instruction to determine whether there is a store instruction that precedes the load instruction and is not ready in the program sequence; if so, determine whether the load instruction has an address dependency with the store instruction based on the prediction result; If the prediction result is that there is a store-after-load tag, the load instruction enters a dormant state until the store instruction corresponding to the store instruction reordering cache index value (sob_idx) wakes up the load instruction, and the load instruction re-initiates memory access and performs a write-back operation.

[0049] In an embodiment of the present invention, an update process of the load and store dependency predictor 2 is also included. During the out-of-order execution process, including a store instruction a and a load instruction b, the address information of the load instruction b is first sent to the data load and store processing unit (LSU). When the address dependency check is performed, it is found that the memory access address of the older (earlier in the program order) store instruction a is not ready, and no valid prediction information is stored in the table entry of the load instruction reordering cache 21 (because the table entry index of its load and store dependency history record table 24 does not index to a valid table entry). Therefore, it is speculated that there is no store-after-load (LAW) violation for the store instruction a, and the memory access is continued and the load result is written back.

[0050] When the address of storage instruction a is then sent to the data load and store processing unit (LSU), it is found during the address dependency check that its memory access address overlaps with the memory access address of load instruction b, that is, a store-after-load (LAW) violation occurs at this time. Storage instruction a stores its own storage instruction reordering cache index value (sob_idx) into the entry of the load and store dependency history table 24 corresponding to load instruction b.

[0051] When load instruction b detects that it meets the commit condition and a store LAW violation has occurred, it reads the load entry index (ld_idx) stored in its load and store dependency history table 24 entry and deindexes it based on the store instruction reorder cache index value (sob_idx) recorded in its load instruction reorder cache 21 entry to obtain the store entry index (st_idx) recorded in the load instruction reorder cache 21 entry. Then, based on the load entry index (ld_idx) and the store entry index (st_idx), the corresponding two entries in load and store dependency history table 24 are read in sequence in two consecutive beats, the corresponding valid update counter values ​​are incremented, the valid bits are modified (in an alternative embodiment, they can be always equal to the value of the highest bit of the valid update counter), and the PC of load instruction b is used by index generator 23 to generate an execution record entry index (spt_idx) for updating the store execution record table 25. The three are combined to form the new entry value of load and store dependency history table 24. The two generated new entry values ​​are sequentially stored in the two entries of the load and store dependency history table 24 indexed by the load entry index (ld_idx) and the store entry index (st_idx). Thus, the update process of the load and store dependency history table 24 is completed.

[0052] When the storage instruction a is submitted from the load instruction reordering cache 21, the load table entry index (ld_idx) stored in the table entry corresponding to the load instruction reordering cache 21 is used to read the corresponding load and store dependency history record table 24 again, and the storage execution record table 25 is indexed according to the execution record table entry index (spt_idx) recorded in the table entry of the load and store dependency history record table 24. If the storage instruction reordering cache index value (sob_idx) and the reordering cache age value (rob_ptr) of the read table entry of the storage execution record table 25 are respectively equal to the table entry index storage instruction reordering cache index value (sob_idx) and the reordering cache age value (rob_ptr) of the load instruction reordering cache 21 of the storage instruction a, then the table entry of the storage execution record table 25 is set to invalid.

[0053] In an embodiment of the present invention, statistics are collected on the total number of predictions and the number of prediction errors (a prediction error refers to a situation where no address dependency is found when a storage instruction is renamed or when a load instruction address is checked) of the load and store dependency predictor 2; when the ratio between the total number of predictions and the number of prediction errors reaches a preset ratio, all table entries in the load and store dependency predictor 2 are cleared.

[0054] The memory access dependency prediction method for a processor is based on the memory access dependency prediction system 100 for a processor in the above embodiment, and can achieve the same technical effect. Please refer to the description in the above embodiment and will not be repeated here.

[0055] Example 3 The embodiment of the present invention also provides a computer device, please refer to Figure 10 , Figure 10 3 is a structural diagram of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a memory access dependency prediction program for the processor stored in the memory 302 and executable on the processor 301.

[0056] The processor 301 calls the memory access dependency prediction program for the processor stored in the memory 302 and executes the steps of the memory access dependency prediction method for the processor provided in the embodiment of the present invention. Figure 9 , specifically including the following steps: S1. The index generator 23 processes the program counter of the store instruction to obtain the store entry index (st_idx) of the load and store dependency history table 24; and stores the store entry index (st_idx) into the corresponding entry of the store instruction reorder cache 22; S2. Reading the execution record entry index of the corresponding store execution record table 25 from the load and store dependency history table 24 according to the store entry index (st_idx), and storing the store instruction reorder cache index value (sob_idx) and reorder cache age value (rob_ptr) of the store instruction into the corresponding entry of the store execution record table 25 according to the execution record entry index; S3, the index generator 23 processes the program counter of the load instruction to obtain the load table entry index (ld_idx) of the load and store dependency history table 24; and stores the load table entry index (ld_idx) into the corresponding table entry of the load instruction reorder cache 21; S4, the load instruction reads the corresponding execution record table entry index from the load and store dependency history table 24 according to the load table entry index (ld_idx); reads the reorder cache age value (rob_ptr) and the store instruction reorder cache index value (sob_idx) of the corresponding entry in the store execution record table 25 according to the execution record table entry index; compares and predicts the reorder cache age value (rob_ptr) with the load instruction to obtain a prediction result; S5. When the load instruction and the store instruction are executed out of order, perform an address dependency check based on the address information of the load instruction to determine whether there is a store instruction that precedes the load instruction and is not ready in the program sequence; if so, determine whether the load instruction has an address dependency with the store instruction based on the prediction result; If the prediction result is that there is a store-after-load tag, the load instruction enters a dormant state until the store instruction corresponding to the store instruction reordering cache index value (sob_idx) wakes up the load instruction, and the load instruction re-initiates memory access and performs a write-back operation.

[0057] In an embodiment of the present invention, an update process of the load and store dependency predictor 2 is also included. During the out-of-order execution process, including a store instruction a and a load instruction b, the address information of the load instruction b is first sent to the data load and store processing unit (LSU). When the address dependency check is performed, it is found that the memory access address of the older (earlier in the program order) store instruction a is not ready, and no valid prediction information is stored in the table entry of the load instruction reordering cache 21 (because the table entry index of its load and store dependency history record table 24 does not index to a valid table entry). Therefore, it is speculated that there is no store-after-load (LAW) violation for the store instruction a, and the memory access is continued and the load result is written back.

[0058] When the address of storage instruction a is then sent to the data load and store processing unit (LSU), it is found during the address dependency check that its memory access address overlaps with the memory access address of load instruction b, that is, a store-after-load (LAW) violation occurs at this time. Storage instruction a stores its own storage instruction reordering cache index value (sob_idx) into the entry of the load and store dependency history table 24 corresponding to load instruction b.

[0059] When load instruction b detects that it meets the commit condition and a store LAW violation has occurred, it reads the load entry index (ld_idx) stored in its load and store dependency history table 24 entry and deindexes it based on the store instruction reorder cache index value (sob_idx) recorded in its load instruction reorder cache 21 entry to obtain the store entry index (st_idx) recorded in the load instruction reorder cache 21 entry. Then, based on the load entry index (ld_idx) and the store entry index (st_idx), the corresponding two entries in load and store dependency history table 24 are read in sequence in two consecutive beats, the corresponding valid update counter values ​​are incremented, the valid bits are modified (in an alternative embodiment, they can be always equal to the value of the highest bit of the valid update counter), and the PC of load instruction b is used by index generator 23 to generate an execution record entry index (spt_idx) for updating the store execution record table 25. The three are combined to form the new entry value of load and store dependency history table 24. The two generated new entry values ​​are sequentially stored in the two entries of the load and store dependency history table 24 indexed by the load entry index (ld_idx) and the store entry index (st_idx). Thus, the update process of the load and store dependency history table 24 is completed.

[0060] When the storage instruction a is submitted from the load instruction reordering cache 21, the load table entry index (ld_idx) stored in the table entry corresponding to the load instruction reordering cache 21 is used to read the corresponding load and store dependency history record table 24 again, and the storage execution record table 25 is indexed according to the execution record table entry index (spt_idx) recorded in the table entry of the load and store dependency history record table 24. If the storage instruction reordering cache index value (sob_idx) and the reordering cache age value (rob_ptr) of the read table entry of the storage execution record table 25 are respectively equal to the table entry index storage instruction reordering cache index value (sob_idx) and the reordering cache age value (rob_ptr) of the load instruction reordering cache 21 of the storage instruction a, then the table entry of the storage execution record table 25 is set to invalid.

[0061] In an embodiment of the present invention, statistics are collected on the total number of predictions and the number of prediction errors (a prediction error refers to a situation where no address dependency is found when a storage instruction is renamed or when a load instruction address is checked) of the load and store dependency predictor 2; when the ratio between the total number of predictions and the number of prediction errors reaches a preset ratio, all table entries in the load and store dependency predictor 2 are cleared.

[0062] The computer device 300 provided in an embodiment of the present invention can implement the steps in the memory access dependency prediction method for a processor in the above embodiment, and can achieve the same technical effects. Please refer to the description in the above embodiment and will not be repeated here.

[0063] Example 4 An embodiment of the present invention also provides a computer-readable storage medium, on which a memory access dependency prediction program for a processor is stored. When the memory access dependency prediction program for a processor is executed by the processor, the various processes and steps in the memory access dependency prediction method for a processor provided by an embodiment of the present invention are implemented, and the same technical effects can be achieved. To avoid repetition, they will not be described here.

[0064] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0065] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0066] Through the above description of the embodiments, those skilled in the art will clearly understand that the methods of the above embodiments can be implemented using software plus the necessary general-purpose hardware platform. Of course, hardware can also be used, but in many cases the former is the more preferred implementation method. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, or optical disk) and includes a number of instructions for enabling a terminal (such as a mobile phone, computer, server, air conditioner, or network device) to execute the methods described in the various embodiments of the present invention.

[0067] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A memory access dependency prediction system for a processor, characterized in that: The memory access dependency prediction system includes: Load and store dependency predictors, used to predict whether load and store instructions have address dependencies; The load and store dependency predictor includes a load instruction reorder cache, a store instruction reorder cache, an index generator, a load and store dependency history record table, and a store execution record table; The load instruction reordering cache is used to store the load instructions; The storage instruction reordering cache is used to store the storage instruction; The index generator is configured to process the program counter of the load instruction or the program counter of the store instruction to obtain a load table entry index or a store table entry index of the load and store dependency history table; and store the load table entry index into a corresponding table entry of the load instruction reorder cache or store the store table entry index into a corresponding table entry of the store instruction reorder cache; The load and store dependency history record table is used to record the dependency relationship between the load instruction and the store instruction; The storage execution record table is used to record the storage instruction reorder cache index value and the reorder cache age value of the storage instruction.

2. The memory access dependency prediction system for a processor according to claim 1, wherein: The load and store dependency history table includes a request arbiter, a plurality of static storage modules, a plurality of in-row table entry selectors, and a port output selector; The request arbitrator is used to arbitrate the read and write requests of the load instruction and the store instruction to the static storage module according to a preset priority; The static storage module is used to store the index value of the storage execution record table; The in-row entry selector is used to select a single static storage entry in the static storage module and send it to the port output selector; The port output selector is used to select a final entry from the received multiple static storage entries for output.

3. The memory access dependency prediction system for a processor according to claim 1, wherein: The storage instruction reordering cache is also used to read the execution record table entry index of the corresponding storage execution record table from the load and store dependency history table according to the storage table entry index, and store the storage instruction reordering cache index value and the reordering cache age value corresponding to the storage instruction into the storage execution record table according to the execution record table entry index.

4. The memory access dependency prediction system for a processor according to claim 3, wherein: The load instruction reorder cache is further configured to read, from the load and store dependency history table, an execution record entry index of the corresponding storage execution record table according to the load entry index, and read, according to the execution record entry index, the reorder cache age value and the storage instruction reorder cache index value of the corresponding entry in the storage execution record table; A prediction result is obtained by comparing the reorder cache age value with the load instruction, and the prediction result and the store instruction reorder cache index value are written into a table entry corresponding to the load instruction reorder cache.

5. The memory access dependency prediction system for a processor according to claim 4, wherein: When the load instruction and the store instruction are executed out of order, an address dependency check is performed based on the address information of the load instruction to determine whether a store instruction prior to the current load instruction is not ready in the program sequence; if so, determining whether the load instruction has an address dependency with the store instruction based on the prediction result; If the prediction result is that there is a store-after-load mark, the current load instruction enters a dormant state until the store instruction corresponding to the store instruction reordering cache index value wakes up the current load instruction, and the current load instruction re-initiates memory access and performs a write-back operation.

6. The memory access dependency prediction system for a processor according to claim 4, wherein: When the load instruction and the store instruction are executed out of order, an address dependency check is performed based on the address information of the store instruction to determine whether a memory access address of the store instruction overlaps with a memory access address of the load instruction: if so, the store instruction reordering cache writes the store instruction reordering cache index value corresponding to the store instruction into a table entry corresponding to the load instruction in the load instruction reordering cache, and marks a store-after-load violation; When the load instruction performs an address check, if it meets the commit condition and is marked with the store-after-load violation, the load instruction reordering cache updates the entry of the load and store dependency history table according to the load table entry index and the store instruction reordering cache index value.

7. The memory access dependency prediction system for a processor according to claim 1, wherein: The memory access dependency prediction system further includes a performance monitoring module; The performance monitoring module is used to count the total prediction times and prediction error times of the load and store dependency predictor; when the ratio between the total prediction times and the prediction error times reaches a preset ratio, all table entries in the load and store dependency predictor are cleared.

8. A memory access dependency prediction method for a processor, characterized in that: The memory access dependency prediction method is based on the memory access dependency prediction system for a processor according to claims 1 to 7, and the memory access dependency prediction method comprises the following steps: S1. The index generator processes the program counter of the storage instruction to obtain a storage entry index of the load and store dependency history table; and stores the storage entry index into a corresponding entry of the storage instruction reorder cache; S2. Reading an execution record entry index of the corresponding storage execution record table from the load and store dependency history table according to the storage entry index, and storing a storage instruction reorder cache index value and a reorder cache age value of the storage instruction into a corresponding entry in the storage execution record table according to the execution record entry index; S3, the index generator processes the program counter of the load instruction to obtain a load table entry index of the load and store dependency history table; and stores the load table entry index into a corresponding table entry of the load instruction reordering cache; S4, the load instruction reads a corresponding execution record table entry index from the load and store dependency history table according to the load table entry index; reads the reorder cache age value and the store instruction reorder cache index value of the corresponding table entry in the store execution record table according to the execution record table entry index; and compares and predicts the reorder cache age value with the load instruction to obtain a prediction result; S5. When the load instruction and the store instruction are executed out of order, perform an address dependency check based on the address information of the load instruction to determine whether there is a store instruction that precedes the load instruction and is not ready in the program sequence; if so, determine whether the load instruction has an address dependency with the store instruction based on the prediction result; If the prediction result is that there is a store-after-load tag, the load instruction enters a dormant state until the store instruction corresponding to the store instruction reordering cache index value wakes up the load instruction, and the load instruction re-initiates memory access and performs a write-back operation.

9. A computer device, characterized in that: include: A memory, a processor, and a memory access dependency prediction program for the processor stored in the memory and executable on the processor, wherein the processor implements the steps of the memory access dependency prediction method for the processor as described in claim 8 when executing the memory access dependency prediction program for the processor.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a memory access dependency prediction program for a processor, and when the memory access dependency prediction program for a processor is executed by the processor, the steps in the memory access dependency prediction method for a processor as described in claim 8 are implemented.

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