Driving circuit and electronic device

Abstract

The invention relates to a driving circuit and an electronic device. The driving circuit includes: a stage including: a first transistor connected to a first terminal receiving a start signal and connected to a first node; a second transistor connected between the first node and a second node; an inverter connected between a third terminal receiving a second voltage and the second terminal, the inverter configured to control a voltage of the third node to a voltage of a voltage level obtained by inverting a voltage level of the first node or a voltage level of the second node; a pull-down transistor including a gate connected to the second node; a pull-up transistor including a gate connected to the third node; and a reset circuit configured to reset the second node or the third node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority benefit of Korean Patent Application Nos. 10-2024-0026260 and 10-2024-0105708 filed on February 23, 2024, and August 7, 2024, respectively, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a driving circuit, and more particularly, to a driving circuit capable of outputting a gate signal, and a display device and an electronic device including the driving circuit. Background Art

[0004] Currently, display devices are thin and lightweight electronic visual display devices commonly used in various devices such as televisions, computer monitors, smartphones and tablet computers. Unlike the older cathode ray tube (CRT) displays that are bulky and rely on an electron beam to illuminate a fluorescent screen, flat panel displays (FPDs) use modern technology that enables compact form factors and high image quality. Examples of FPDs include liquid crystal displays (LCDs), organic light emitting diode (OLED) displays and micro-light emitting diode (MicroLED) displays.

[0005] A display device may include a pixel region comprising a plurality of pixels, a gate drive circuit, a data drive circuit, and a controller. The gate drive circuit includes a stage connected to a gate line, and the stage supplies a gate signal via a gate line connected to the stage in response to a signal from the controller. Each stage includes several transistors. However, if one of the multiple internal nodes of the stage remains at a low level for an extended period, stress-related issues may result for a particular transistor in the stage. Stress-related issues may include threshold voltage shift, increased leakage current, or reduced drive current, which may together reduce the lifespan and performance of the display device and increase power consumption. Summary of the Invention

[0006] One or more embodiments include a driving circuit capable of stably outputting a gate signal at low power, and a display device and an electronic device including the driving circuit.

[0007] According to an embodiment, a drive circuit includes multiple stages. Each of the multiple stages includes first to seventh transistors. The first transistor is connected to a first terminal that receives a start signal and is connected to a first node. The first transistor includes a gate connected to a clock terminal that receives a clock signal. The second transistor is connected between the first node and the second node and includes a gate connected to a second terminal that receives a first voltage. The third transistor is connected between a third terminal that receives a second voltage higher than the first voltage and a third node. The third transistor includes a gate connected to the first node. The fourth transistor is connected between the third node and the second terminal and includes a gate connected to the second node. The fifth transistor is connected between the output terminal and the second terminal and includes a gate connected to the second node. The sixth transistor is connected between the third terminal and the output terminal and includes a gate connected to the third node. The seventh transistor is connected between the third node and the second terminal and includes a gate connected to a reset terminal.

[0008] In an embodiment, from the time when the first voltage and the second voltage are input to the time when the clock signal is input, a reset signal of the gate-on voltage can be input to the reset terminal of each of the multiple stages, and multiple voltages of multiple third nodes of the multiple stages can be simultaneously reset to the first voltage.

[0009] In an embodiment, for a specific period before the time when the first voltage and the second voltage are input, a voltage of 0 volts (V) can be input to the first terminal, the second terminal, the third terminal and the reset terminal of each of the multiple stages, and the multiple voltages of the multiple third nodes of the multiple stages can be discharged to 0V at the same time.

[0010] In an embodiment, when a start signal is input after the time when a clock signal is input, output signals can be output sequentially from multiple output terminals of multiple stages, and from the time when the clock signal is input, a reset signal of the gate cut-off voltage can be input to the reset terminal of each of the multiple stages.

[0011] In an embodiment, the third transistor may be a P-channel transistor, and the fourth transistor may be an N-channel transistor.

[0012] In an embodiment, the fourth transistor may be an N-channel transistor, and the first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the seventh transistor may be P-channel transistors.

[0013] In an embodiment, each of the plurality of stages may further include: a first capacitor connected between the second node and the output terminal; and a second capacitor connected between the third terminal and the third node.

[0014] In an embodiment, each of the plurality of stages may further include an eighth transistor connected between the third terminal and the first node and including a gate connected to the reset terminal, wherein the seventh transistor and the eighth transistor are N-channel transistors.

[0015] In an embodiment, each of the multiple stages may further include: an eighth transistor connected between the third terminal and the first node and including a gate connected to the second reset terminal, wherein the seventh transistor is a P-channel transistor and the eighth transistor is an N-channel transistor, wherein the timing of the first reset signal input to the reset terminal connected to the seventh transistor being the gate-on voltage and the timing of the second reset signal input to the second reset terminal connected to the eighth transistor being the gate-on voltage are the same.

[0016] According to an embodiment, a drive circuit includes multiple stages. Each of the multiple stages includes first to eighth transistors. The first transistor is connected to a first terminal that receives a start signal and is connected to a first node. The first transistor includes a gate connected to a clock terminal that receives a clock signal. The second transistor is connected between the first node and the second node and includes a gate connected to a second terminal that receives a first voltage. The third transistor is connected between a third terminal that receives a second voltage higher than the first voltage and a third node. The third transistor includes a gate connected to the first node. The fourth transistor is connected between the third node and the second terminal and includes a gate connected to the second node. The fifth transistor is connected between the output terminal and the second terminal and includes a gate connected to the second node. The sixth transistor is connected between the third terminal and the output terminal and includes a gate connected to the third node. The seventh transistor is connected between the third node and a fourth terminal that receives a third voltage lower than the first voltage. The seventh transistor includes a gate connected to a reset terminal. The eighth transistor is connected between the third terminal and the first node and includes a gate connected to the reset terminal.

[0017] In an embodiment, the seventh transistor and the eighth transistor may be N-channel transistors.

[0018] In an embodiment, from the time when the first voltage, the second voltage, and the third voltage are input to the time when the clock signal is input, a reset signal of the gate-on voltage can be input to the reset terminal of each of the multiple stages, and multiple voltages of multiple third nodes of the multiple stages can be simultaneously reset to the first voltage.

[0019] In an embodiment, for a specific period before the time when the first voltage, the second voltage and the third voltage are input, a voltage of 0V can be input to the first terminal, the second terminal, the third terminal and the reset terminal of each of the multiple stages, and the multiple voltages of the multiple third nodes of the multiple stages can be discharged to 0V at the same time.

[0020] In an embodiment, when a start signal is input after the time when a clock signal is input, output signals can be output sequentially from multiple output terminals of multiple stages, and from the time when the clock signal is input, a reset signal of the gate cut-off voltage can be input to the reset terminal of each of the multiple stages.

[0021] In an embodiment, the third transistor may be a P-channel transistor, and the fourth transistor may be an N-channel transistor.

[0022] In an embodiment, each of the plurality of stages may further include: a first capacitor connected between the second node and the output terminal; and a second capacitor connected between the third terminal and the third node.

[0023] According to an embodiment, an electronic device includes a controller, a power supply circuit, and a driver circuit. The controller is configured to output multiple clock signals. The power supply circuit is configured to output multiple voltages. The driver circuit is configured to output a gate signal based on the multiple clock signals and the multiple voltages. The driver circuit includes multiple stages. Each of the multiple stages includes a first transistor, a second transistor, an inverter, a pull-down transistor, a pull-up transistor, and a reset transistor. The first transistor is connected to a first terminal that receives a start signal and to a first node, and includes a gate connected to a clock terminal that receives one of the multiple clock signals. The second transistor is connected between the first node and the second node and includes a gate connected to a second terminal that receives a first voltage among the multiple voltages. The inverter is connected between a third terminal that receives a second voltage among the multiple voltages and the second terminal. The inverter is configured to control the voltage of the third node to a voltage level obtained by inverting the voltage level of the first node or the second node. The pull-down transistor is connected between the output terminal and the second terminal and includes a gate connected to the second node. The pull-up transistor is connected between the third terminal and the output terminal and includes a gate connected to the third node. The reset circuit is configured to reset the second node or the third node.

[0024] In an embodiment, the reset circuit may include a third transistor connected between the third node and the second terminal and including a gate connected to the reset terminal.

[0025] The reset circuit may include: a third transistor connected between the third node and the second terminal and including a gate connected to the reset terminal; and a fourth transistor connected between the third terminal and the first node and including a gate connected to the reset terminal, wherein the third transistor and the fourth transistor are N-channel transistors.

[0026] In an embodiment, the reset circuit may include: a third transistor connected between a third node and a fourth terminal receiving a third voltage among a plurality of voltages, the third transistor including a gate connected to the reset terminal; and a fourth transistor connected between the third terminal and the first node and including a gate connected to the reset terminal, wherein the third transistor and the fourth transistor are N-channel transistors.

[0027] In an embodiment, the reset circuit may include: a third transistor connected between the third node and the second terminal and including a gate connected to the first reset terminal; and a fourth transistor connected between the third terminal and the first node and including a gate connected to the second reset terminal, wherein the third transistor is a P-channel transistor and the fourth transistor is an N-channel transistor, wherein a timing at which a first reset signal input to the first reset terminal connected to the third transistor is a gate-on voltage and a timing at which a second reset signal input to the second reset terminal connected to the fourth transistor is a gate-on voltage are the same.

[0028] According to an embodiment, an electronic device includes: a controller configured to receive a conduction operation signal from a processor and output a reset signal based on the conduction operation signal; and a driver circuit including a stage configured to receive the reset signal and reset a control node. The stage includes a first transistor, a second transistor, an inverter, a pull-down transistor, a pull-up transistor, and a reset transistor. The first transistor is connected to a first terminal that receives a start signal and to a first node, and includes a gate connected to a clock terminal that receives a clock signal. The second transistor is connected between the first node and a second node and includes a gate connected to a second terminal that receives a first voltage. The inverter is connected between a third terminal that receives a second voltage and a second terminal. The inverter is configured to control the voltage of the control node to a voltage level obtained by inverting the voltage level of the first node or the voltage level of the second node. The pull-down transistor is connected between an output terminal and a second terminal and includes a gate connected to the second node. The pull-up transistor is connected between the third terminal and the output terminal and includes a gate connected to the control node. The reset transistor is connected between the control node and a second terminal and includes a gate connected to a reset terminal that receives the reset signal.

[0029] In an embodiment, the stage may further include a second reset transistor connected between the third terminal and the first node and including a gate connected to the reset terminal, wherein the reset transistor and the second reset transistor are N-channel transistors.

[0030] In an embodiment, the stage may further include: a second reset transistor connected between the third terminal and the first node and including a gate connected to the second reset terminal, wherein the reset transistor is a P-channel transistor and the second reset transistor is an N-channel transistor, wherein the controller is further configured to control the timing at which the reset signal input to the reset terminal connected to the reset transistor is a gate-on voltage and the timing at which the second reset signal input to the second reset terminal connected to the second reset transistor is a gate-on voltage to be the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of certain embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a diagram schematically showing a driving circuit according to an embodiment;

[0033] Figure 2 is a diagram schematically showing input / output signals of a driving circuit according to an embodiment;

[0034] Figure 3 and Figure 4 is a diagram showing the embodiment of the present invention. Figure 1 a diagram of any one of a plurality of stages in a driver circuit;

[0035] Figure 5 and Figure 6 is a timing diagram for describing the operation of a stage according to an embodiment;

[0036] Figure 7 and Figure 8 is a diagram showing the embodiment of the present invention. Figure 1 a diagram of any one of a plurality of stages in a driver circuit;

[0037] Figure 9 is a timing diagram for describing the operation of a stage according to an embodiment;

[0038] Figure 10 and Figure 11 is a diagram showing the embodiment of the present invention. Figure 1 a diagram of any one of a plurality of stages in a driver circuit;

[0039] Figure 12 and Figure 13 is a diagram showing the embodiment of the present invention. Figure 1 a diagram of any one of a plurality of stages in a driver circuit;

[0040] Figure 14 is a diagram schematically showing a display device according to an embodiment; and

[0041] Figure 15、 Figure 16A 、 Figure 16B 、 Figure 17A and Figure 17B is a perspective view schematically showing a display device according to an embodiment. DETAILED DESCRIPTION

[0042] The embodiment of embodiment example will now be shown in detail with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements from time to time. In this regard, the present embodiment can have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following only describes the embodiment with reference to the accompanying drawings to explain the various aspects of this specification. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. Throughout the disclosure, the expression "at least one of a, b and c (kind / person)" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or their variants.

[0043] Although the present disclosure allows for various changes and many embodiments, specific embodiments will be shown in the drawings and described in the detailed description. The effects and features of the present disclosure and methods for achieving them will be explained with reference to the embodiments described in detail below with reference to the drawings. However, the present disclosure is not limited to the following embodiments and may be implemented in various forms.

[0044] Although terms such as "first" and "second" may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0045] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0046] When X and Y are directly or indirectly connected to each other, it can include the case where X and Y are physically connected to each other, the case where X and Y are functionally connected to each other, and the case where X and Y are electrically connected to each other. When X and Y are indirectly connected, it can include the case where X and Y are indirectly connected with other elements between X and Y. Here, X and Y can be elements (e.g., equipment, devices, circuits, wiring, electrodes, terminals, films, layers, and regions). Therefore, the connection relationship is not limited to a specific connection relationship (e.g., the connection relationship shown in the drawings or detailed description), and can include other connection relationships in addition to the connection relationship shown in the drawings or detailed description.

[0047] In the following embodiments, when X and Y are connected to each other, it may mean that X and Y are electrically connected to each other. When X and Y are electrically connected to each other, it may include a case where X and Y are directly connected to each other and / or a case where X and Y are indirectly connected to each other with other components between X and Y. When X and Y are indirectly connected, it may include a case where one or more elements (e.g., switches, transistors, capacitors, inductors, resistors, or diodes) that enable electrical connection between X and Y are connected between X and Y.

[0048] In the following embodiments, the term "on" used in association with the state of the device may refer to a state in which the device is activated, and the term "off" may refer to a state in which the device is disabled. The term "on" used in association with a signal received by the device may refer to a signal for activating the device, and the term "off" may refer to a signal for disabling the device. The device may be activated by a high level voltage or a low level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low level voltage, and an N-channel transistor (N-type transistor) is activated by a high level voltage. Therefore, it should be understood that the "on" voltages for P-channel transistors and N-channel transistors have opposite (low and high) voltage levels. Hereinafter, the voltage for activating (turning on) the transistor is referred to as the gate-on voltage, and the voltage for disabling (turning off) the transistor is referred to as the gate-off voltage.

[0049] Embodiments of the present disclosure relate to a driver circuit for a display device, the driver circuit including a reset circuit in at least one stage to address issues such as stress on transistors. The reset circuit is designed to initialize internal nodes to predefined voltage levels, thereby reducing the stress caused by long-term low-level signals at these nodes and ensuring reliable operation under abnormal power-on / power-off sequences. In addition, the inclusion of specific auxiliary transistors helps to disperse stress and further alleviate long-term degradation. By managing voltage conversion and optimizing transistor usage, the reset circuit helps to achieve stable gate signal output with low power consumption. In addition, the reset circuit alleviates issues such as leakage current, threshold voltage shift and potential failures caused by accumulated stress, especially during extended or low-frequency operation.

[0050] Figure 1 is a diagram schematically showing a driving circuit according to an embodiment. Figure 2 is a diagram schematically showing input / output signals of a driving circuit according to an embodiment.

[0051] Reference Figure 1The driving circuit DRV according to the embodiment includes a plurality of stages (eg, a plurality of stages ST1 to STn). The plurality of stages (eg, a plurality of stages ST1 to STn) can sequentially output a plurality of output signals (eg, a plurality of output signals OUT[1], ..., OUT[k-4] (see Figure 2 ), OUT[k-3], OUT[k-2], OUT[k-1], OUT[k], ..., and OUT[n]) are output to signal lines. For example, the output signal can be output to an output line such as a gate line of a display panel. Wherein n is a positive integer and k is a positive integer less than or equal to n.

[0052] Each of the plurality of stages (e.g., a plurality of stages ST1 to STn) may be connected to one or more signal lines. The plurality of signal lines may include at least one input line and at least one output line. The at least one input line may include at least one clock line 13 and at least one voltage line (e.g., a first voltage line 11, a second voltage line 12, an external start signal line 14, and a reset signal line 15), wherein the at least one clock line 13 is used to input at least one clock signal to each of the plurality of stages (e.g., a plurality of stages ST1 to STn), and the at least one voltage line is used to input at least one voltage signal. At least one output signal OUT (see Figure 3 ) can be output to at least one output line (e.g., a gate line).

[0053] Each of the multiple stages (e.g., multiple stages ST1 to STn) may include multiple terminals to which multiple signals are input and / or output. A terminal may refer to one end of a signal line. The multiple signals may include a clock signal and a voltage signal. The multiple terminals may include an input terminal IN, a first voltage input terminal V1, a second voltage input terminal V2, a clock terminal CK, an output terminal GOUT, and a reset terminal RS.

[0054] A plurality of stages (eg, a plurality of stages ST1 to STn) may be started in response to a start signal STV (see Figure 3 ) respectively output output signals (e.g., multiple output signals OUT[1], ..., OUT[k-3], OUT[k-2], OUT[k-1], OUT[k], ..., and OUT[n]). For example, the n-th stage STn can output the n-th output signal OUT[n] to the n-th signal line. The start signal STV can be an external start signal FLM for controlling the timing of the first output signal OUT[1] and can be input to the first stage ST1.

[0055] The start signal STV may be input (supplied) to the input terminal IN. The start signal may be an external start signal FLM or an output signal output from a previous stage (hereinafter, referred to as a "previous output signal"). The external start signal FLM may be input as the start signal STV to the input terminal IN of the first stage ST1, and the previous output signal may be input as the start signal STV to the input terminal IN of each of the second stage ST2 to the nth stage STn. The previous stage may be a stage positioned at least one stage before the current stage. Figure 1 In the preceding stage, the previous stage is a stage positioned immediately before the current stage. For example, the k-3th output signal OUT[k-3] output from the k-3th stage STk-3 can be input to the input terminal IN of the k-2th stage STk-2 as the start signal STV.

[0056] Clock signal CLK (see, for example, Figure 3 ) can be input to the clock terminal CK. The clock signal CLK may include a first clock signal CLK1 and a second clock signal CLK2. The first clock signal CLK1 or the second clock signal CLK2 can be input to the clock terminal CK. In an embodiment, the first clock signal CLK1 is input to the clock terminal CK of the odd-numbered stage (for example, the first stage ST1, the k-3 stage STk-3, etc.) and the second clock signal CLK2 can be input to the clock terminal CK of the even-numbered stage (for example, the k-2 stage STk-2, etc.). In an embodiment, the second clock signal CLK2 is input to the clock terminal CK of the odd-numbered stage and the first clock signal CLK1 is input to the clock terminal CK of the even-numbered stage. In an embodiment, the clock signals CLK1 and CLK2 are square wave signals that alternate between a high level voltage and a low level voltage. These signals control the timing of the transistor operations within the stage of the driver circuit. The second clock signal CLK2 can be phase shifted relative to the first clock signal CLK1. For example, the second clock signal CLK2 may have the same waveform as the first clock signal CLK1 but be delayed by a certain interval (eg, half a cycle).

[0057] The first voltage VGH may be input to the first voltage input terminal V1, and the second voltage VGL may be input to the second voltage input terminal V2. The second voltage VGL may have a lower voltage level than the first voltage VGH.

[0058] like Figure 2As shown in , the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals in which a high level voltage and a low level voltage are repeated. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 can be square wave signals in which a first voltage VGH and a second voltage VGL are repeated. The first clock signal CLK1 and the second clock signal CLK2 can have the same waveform and can be phase-shifted signals. For example, the second clock signal CLK2 can have the same waveform as the first clock signal CLK1, and the second clock signal CLK2 can be input with its phase shifted (delayed) by a specific interval. The second clock signal CLK2 can be shifted half (1 / 2) cycle relative to the first clock signal CLK1. In the first clock signal CLK1 and the second clock signal CLK2, the duration during which the high level voltage is maintained for one cycle can be the same as the duration during which the low level voltage is maintained for one cycle.

[0059] The output signal can be output from the output terminal GOUT. Figure 2 As shown in , the output signals (e.g., multiple output signals OUT[1], ..., OUT[k-3], OUT[k-2], OUT[k-1], OUT[k], ..., and OUT[n]) outputted from the output terminals GOUT of the plurality of stages (e.g., multiple stages ST1 to STn) can be sequentially shifted by a specific interval. In an embodiment, the plurality of stages (e.g., multiple stages ST1 to STn) can be shifted by 1 / 2 cycle and sequentially output high-level output signals (e.g., multiple output signals OUT[1], ..., OUT[k-3], OUT[k-2], OUT[k-1], OUT[k], ..., and OUT[n]). In an embodiment, the high-level voltage and the low-level voltage of the output signal can be a first voltage VGH and a second voltage VGL, respectively. In an embodiment, the plurality of stages (e.g., multiple stages ST1 to STn) can sequentially output high-level output signals, and the output signal of each stage is delayed by half a clock cycle relative to the previous stage.

[0060] Figure 3 and Figure 4 is a diagram showing the embodiment of the present invention. Figure 1 A diagram of any one of the multiple stages in a driving circuit. Figure 5 and Figure 6 is a timing diagram for describing the operation of the stages according to the embodiment.

[0061] Reference Figure 3In an embodiment, stage ST includes a control circuit 131, an output circuit 135, and a reset circuit 137a. Each of the control circuit 131, the output circuit 135, and the reset circuit 137a may include at least one transistor. The at least one transistor may include an N-channel transistor and / or a P-channel transistor. For example, the fourth transistor T4 may be an N-channel transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-channel transistors.

[0062] The P-channel transistor may be a P-channel silicon transistor. The silicon transistor may include a silicon semiconductor, and the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the silicon transistor may be a low-temperature polycrystalline silicon (LTPS) thin film transistor.

[0063] The N-channel transistor may be an N-channel oxide transistor. The oxide transistor may include an oxide semiconductor, and the oxide semiconductor may include a zinc oxide (Zn)-based material such as zinc oxide, indium zinc oxide (In-Zn), or gallium indium zinc oxide (Ga-In-Zn). In some embodiments, the oxide semiconductor may be an indium gallium zinc oxide (IGZO) semiconductor. In some embodiments, the oxide semiconductor may be an indium tin gallium zinc oxide (ITGZO) semiconductor. For example, the oxide transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor.

[0064] The gate-on voltage of the P-channel transistor may be a low-level voltage, and the gate-off voltage of the P-channel transistor may be a high-level voltage. The gate-on voltage of the N-channel transistor may be a high-level voltage, and the gate-off voltage of the N-channel transistor may be a low-level voltage.

[0065] The control circuit 131 may control the voltages of the first node A, the second node Q, and the third node QB in response to a signal input to the input terminal IN. For example, the control circuit 131 may control the voltages of the first node A, the second node Q, and the third node QB in response to a start signal STV (eg, an external start signal FLM (see Figure 1 ) or a previous output signal) to control the voltages of the first node A, the second node Q, and the third node QB. The control circuit 131 may include first to fourth transistors T1 to T4.

[0066] The first transistor T1 may be connected between the input terminal IN and the first node A. The gate of the first transistor T1 may be connected to the clock terminal CK. When the clock signal CLK input to the clock terminal CK is at a low level, the first transistor T1 may be turned on, allowing the first transistor T1 to transmit the start signal from the input terminal IN to the first node A. The clock signal CLK may be the first clock signal CLK1 or the second clock signal CLK2.

[0067] In an embodiment, the first clock signal CLK1 is input to the clock terminal CK of the odd-numbered stages ST, and the second clock signal CLK2 is input to the clock terminal CK of the even-numbered stages ST. In an embodiment, the second clock signal CLK2 is input to the clock terminal CK of the odd-numbered stages ST, and the first clock signal CLK1 is input to the clock terminal CK of the even-numbered stages ST.

[0068] The second transistor T2 can be connected between the first node A and the second node Q. The gate of the second transistor T2 can be connected to the second voltage input terminal V2. The second transistor T2 can be turned on by the second voltage VGL input to the second voltage input terminal V2, enabling the second transistor T2 to transmit the start signal received from the first transistor T1 to the second node Q. In an embodiment, when the stage ST is receiving power, the second transistor T2 is always in the on state. In a stage where the second transistor T2 is omitted and the first transistor T1 is provided alone, the stress on the first transistor T1 may increase due to the long-term low level of the second node Q or the long-term low level of the first node A. Because the second transistor T2 is provided, the first and second transistors T1 and T2 can share the stress caused by the long-term low level of the second node Q or the long-term low level of the first node A, thereby reducing the stress on the first transistor T1. This stress reduction can reduce or prevent threshold voltage shift and leakage current and increase transistor life. In addition, when the first transistor T1 is turned off, the second transistor T2 can prevent the line voltage drop between the input terminal IN and the first node A. Preventing line voltage drops can maintain signal integrity, ensuring that subsequent stages receive the correct voltage levels and avoiding potential interruptions in the sequential operation of the gate driver circuit. Without the second transistor T2, the first transistor T1 would handle the transmission of the signal and face stress due to the prolonged low-level voltage at the first node A or the second node Q. The second transistor T2 shares this stress with the first transistor T1. In addition, when the first transistor T1 is turned off, the second transistor T2 ensures that the voltage at the first node A remains stable, preventing undesirable voltage drops. In addition, the second transistor T2 can facilitate smooth transmission of the start signal STV to the second node Q by operating in series (tandem) with the first transistor T1.

[0069] The third transistor T3 may be connected between the first voltage input terminal V1 and the third node QB. The gate of the third transistor T3 may be connected to the first node A. When the start signal transmitted to the first node A is at a low level, the third transistor T3 may be turned on, allowing the third transistor T3 to transmit the first voltage VGH from the first voltage input terminal V1 to the third node QB. Due to the third transistor T3, the voltage of the third node QB may be a voltage level obtained by inverting the voltage level of the first node A.

[0070] The fourth transistor T4 may be connected between the third node QB and the second voltage input terminal V2. The gate of the fourth transistor T4 may be connected to the second node Q. When the start signal transmitted to the second node Q is at a high level, the fourth transistor T4 may be turned on, allowing the fourth transistor T4 to transmit the second voltage VGL from the second voltage input terminal V2 to the third node QB. Due to the fourth transistor T4, the voltage of the third node QB may be a voltage level obtained by inverting the voltage level of the second node Q.

[0071] The third transistor T3 and the fourth transistor T4 can control the voltage level of the third node QB according to the voltage level of the first node A or the voltage level of the second node Q, and thus can be used as an inverter or a level shifter. In an embodiment, the third transistor T3 and the fourth transistor T4 are connected to form an inverter or are replaced by an inverter.

[0072] The output circuit 135 may be connected between the first voltage input terminal V1 and the second voltage input terminal V2. The output circuit 135 may output an output signal OUT of a high voltage or a low voltage depending on the voltage level of the second node Q and the voltage level of the third node QB. The output circuit 135 may include a fifth transistor T5 and a sixth transistor T6. The output circuit 135 may also include a first capacitor C1 and a second capacitor C2.

[0073] The fifth transistor T5 may be connected between the output terminal GOUT and the second voltage input terminal V2. The gate of the fifth transistor T5 may be connected to the second node Q. The fifth transistor T5 may be a pull-down transistor that transmits a low-level voltage to the output terminal GOUT. When the second node Q is at a low level, the fifth transistor T5 may be turned on, allowing the fifth transistor T5 to transmit the second voltage VGL, a low-level voltage, from the second voltage input terminal V2 to the output terminal GOUT.

[0074] The sixth transistor T6 may be connected between the first voltage input terminal V1 and the output terminal GOUT. The gate of the sixth transistor T6 may be connected to the third node QB. The sixth transistor T6 may be a pull-up transistor that transmits a high-level voltage to the output terminal GOUT. When the third node QB is at a low level, the sixth transistor T6 may be turned on, allowing the sixth transistor T6 to output the first voltage VGH, which is a high-level voltage, from the first voltage input terminal V1 to the output terminal GOUT.

[0075] The first capacitor C1 may be connected between the output terminal GOUT and the second node Q. The second capacitor C2 may be connected between the first voltage input terminal V1 and the third node QB. The first capacitor C1 may maintain the voltage of the second node Q, and the second capacitor C2 may maintain the voltage of the third node QB.

[0076] The reset circuit 137a can reset the third node QB. The reset circuit 137a can include a seventh transistor T7. The seventh transistor T7 can reset the third node QB based on a reset signal ESR input to the reset terminal RS. The seventh transistor T7 can be connected between the third node QB and the second voltage input terminal V2, and the gate of the seventh transistor T7 can be connected to the reset terminal RS. When the reset signal ESR is applied to the reset terminal RS at a low level, the seventh transistor T7 can be turned on and can reset (initialize) the third node QB to the second voltage VGL.

[0077] In an embodiment, the reset signal ESR is input at a low level to the first to n-th stages ST1 to STn in a specific interval (e.g., a reset interval). For example, after a device including the stages is powered on and before the device operates and / or when an operation error occurs in the device, the low-level reset signal ESR may be input to initialize the voltage of the third node QB (reset the voltage of the third node QB).

[0078] In an embodiment, Figure 4 As shown in FIG, the first transistor T1 to the seventh transistor T7 of the stage ST are dual-gate transistors each including a back gate. Each of the first transistor T1 to the seventh transistor T7 may include a first gate as a top gate (gate) positioned above the semiconductor and a second gate as a bottom gate (back gate) positioned below the semiconductor. The back gate of each of the first transistor T1 to the seventh transistor T7 may be connected to its own gate. For example, the back gate of the first transistor T1 may be connected to the top gate of the first transistor T1.

[0079] Will refer to Figure 5 and Figure 6 describe Figure 4 and Figure 5 The operation of the stages shown in .

[0080] Reference Figure 5The first interval PP1 (e.g., the first period) and the second interval PP2 (e.g., the second period) are intervals (e.g., periods) before the output signal OUT is output. The third interval PP3 (e.g., the third period) is an interval in which the output signal OUT is output. The first interval PP1, the second interval PP2, and the third interval PP3 can be distinguished based on the voltage levels of the input signals input to the plurality of stages (e.g., the plurality of stages ST1 to STn). The input signals may include a first voltage VGH, a second voltage VGL, an external start signal FLM, a reset signal ESR, and a clock signal CLK.

[0081] The first section PP1 is a section in which the voltage of the input signal is set to ground (voltage of 0 V). The first section PP1 may be a section from a first time t1 to a second time t2.

[0082] Starting from the first time t1, in the first interval PP1, a voltage of 0V may be applied to the first voltage line 11, the second voltage line 12, the clock line 13, and the reset signal line 15 connected to the plurality of stages (e.g., the plurality of stages ST1 to STn). A voltage of 0V may be input to the external start signal line 14 connected to the first stage ST1 from among the plurality of stages (e.g., the plurality of stages ST1 to STn). In an embodiment, referring to Figure 14 , the voltage of 0V is provided by the power supply circuit 170 or the controller 190.

[0083] As an input signal of a voltage of 0V is input to the plurality of stages (e.g., the plurality of stages ST1 to STn), in the first interval PP1, a voltage VQ_M of the second node Q of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) may be charged to a voltage higher than the low-level voltage VQ_L, and a voltage VQB_M of the third node QB may be discharged to a voltage lower than the high-level voltage VQB_H. In an embodiment, in the first interval PP1, a voltage VQB_M of the third node QB of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) may be 0V.

[0084] In the first interval PP1, the voltage OUT_M of the output signal OUT of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) may be a voltage at a level higher than the level of the low-level voltage OUT_L. For example, in the first interval PP1, the voltage OUT_M of the output signal OUT of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) may be 0 V.

[0085] The second interval PP2 may be a reset interval in which the third node QB of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) is fully discharged. The second interval PP2 may span from a second time t2 to a third time t3, during which a square wave clock signal CLK is applied. The second time t2 may be a power-on time. The power-on time may be a time during which the first voltage VGH and the second voltage VGL are applied.

[0086] Starting from the second time t2, in the second interval PP2, the high-level first voltage VGH and the low-level second voltage VGL may be input to the plurality of stages (e.g., the plurality of stages ST1 to STn). In this case, the external start signal FLM input to the first stage ST1 may be a high-level voltage FLM_H, the reset signal ESR input to the plurality of stages (e.g., the plurality of stages ST1 to STn) may be a low-level voltage ESR_L, and the clock signal CLK may be a low-level voltage CLK_L. In an embodiment, the high-level voltage FLM_H of the external start signal FLM may be the first voltage VGH, and the low-level voltage FLM_L of the external start signal FLM may be the second voltage VGL. The low-level voltage ESR_L of the reset signal ESR and the low-level voltage CLK_L of the clock signal CLK may be the second voltage VGL.

[0087] The seventh transistor T7 of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) can be turned on by the reset signal ESR of the low-level voltage ESR_L, allowing the second voltage VGL to be transmitted to the third node QB. Therefore, in the second interval PP2, the voltage VQB of the third node QB of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) can be discharged to the second voltage VGL. The sixth transistor T6, whose gate is connected to the third node QB, can be turned on, allowing the first voltage VGH to be transmitted to the output terminal GOUT. Therefore, the plurality of stages (e.g., the plurality of stages ST1 to STn) can simultaneously output the output signal OUT of the high-level voltage OUT_H.

[0088] The first transistor T1 of each of the plurality of stages (eg, the plurality of stages ST1 to STn) may be turned on by the clock signal CLK of the low level voltage CLK_L, allowing the start signal STV (see Figure 3 and Figure 4) is transmitted to the first node A and the second node Q. The start signal STV may be an external start signal FLM of a high-level voltage FLM_H and a previous output signal of a high-level voltage OUT_H (e.g., an output signal OUT[1] of the first stage input to the second stage). Therefore, in the second interval PP2, the voltage of the first node A and the voltage VQ of the second node Q of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) may be a high-level voltage VQ_H. The fifth transistor T5, whose gate is connected to the second node Q, may be turned off.

[0089] Starting from the third time t3, the square wave clock signal CLK may be input to the plurality of stages (e.g., the plurality of stages ST1 to STn). After a certain delay from the third time t3, at the fourth time t4, the external start signal FLM of the high level voltage FLM_H may be input to the first stage ST1. Starting from the fourth time t4, the plurality of stages (e.g., the plurality of stages ST1 to STn) may sequentially output the output signal OUT.

[0090] Starting from the third time t3, in the third interval PP3, the clock signal CLK, in which the high-level voltage CLK_H and the low-level voltage CLK_L alternate with each other, may be input to multiple stages (e.g., multiple stages ST1 to STn). Starting from the third time t3, in the third interval PP3, the reset signal ESR of the high-level voltage ESR_H may be input to the multiple stages (e.g., multiple stages ST1 to STn). In an embodiment, the high-level voltage ESR_H of the reset signal ESR and the high-level voltage CLK_H of the clock signal CLK may be the first voltage VGH. In the third interval PP3, the first voltage VGH and the second voltage VGL may be input to the multiple stages (e.g., multiple stages ST1 to STn). The seventh transistor T7 of each of the multiple stages (e.g., multiple stages ST1 to STn) may be turned off by the reset signal ESR of the high-level voltage ESR_H. That is, when the multiple stages (e.g., multiple stages ST1 to STn) operate to output the output signal OUT of the high-level voltage OUT_H, the seventh transistor T7 may be turned off.

[0091] At the fourth time t4, the start signal FLM of the high level voltage FLM_H may be input to the first stage ST1, and multiple stages (e.g., multiple stages ST1 to STn) may operate to sequentially output output signals (e.g., OUT[1] to OUT[n]) of the high level voltage OUT_H.

[0092] From the third time t3 to the fourth time t4, the voltage VQ of the second node Q of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) may be a low-level voltage VQ_L, and the voltage VQB of the third node QB may be a high-level voltage VQB_H. From the third time t3 to the fourth time t4, the output signal OUT of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) may be a low-level voltage OUT_L.

[0093] Starting from the fourth time t4, the voltage VQ of the second node Q of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) may sequentially change from the low-level voltage VQ_L to the high-level voltage VQ_H, and the voltage VQB of the third node QB may sequentially change from the high-level voltage VQB_H to the low-level voltage VQB_L. Starting from the fourth time t4, the output signal OUT of the plurality of stages (e.g., the plurality of stages ST1 to STn) may sequentially change from the low-level voltage OUT_L to the high-level voltage OUT_H.

[0094] In an embodiment, when the first clock signal CLK1 is input to the odd-numbered stages and the second clock signal CLK2 is input to the even-numbered stages, the output signal OUT of the odd-numbered stages may change from the low-level voltage OUT_L to the high-level voltage OUT_H in synchronization with the low-level voltage CLK_L of the first clock signal CLK1, and the output signal OUT of the even-numbered stages may change from the low-level voltage OUT_L to the high-level voltage OUT_H in synchronization with the low-level voltage CLK_L of the second clock signal CLK2.

[0095] In the following, reference will be made to Figure 6 describe Figure 3 and Figure 4 1 to 4. Operation of one stage ST from among a plurality of stages (eg, a plurality of stages ST1 to STn) after a fourth time t4 is shown in FIG. The stage ST may be an odd-numbered stage or an even-numbered stage.

[0096] exist Figure 6 , the clock signal CLK, the previous output signal OUT', the voltage VQ of the second node Q, the voltage VQB of the third node QB, and the output signal OUT are shown. The clock signal CLK may be the first clock signal CLK1 or the second clock signal CLK2.

[0097] The previous output signal OUT′ of a high level may be input to the input terminal IN, and in the first subinterval P1 , the clock signal CLK of a low level may be input to the clock terminal CK.

[0098] The first transistor T1 can be turned on by the low-level clock signal CLK. The second transistor T2 can be in a conductive state due to the low-level second voltage VGL. Since the first transistor T1 and the second transistor T2 are turned on, the high-level previous output signal OUT' can be transmitted to the first node A and the second node Q of the stage ST, and the fifth transistor T5 can be turned off. The third transistor T3 whose gate is connected to the first node A can be turned off, and the fourth transistor T4 whose gate is connected to the second node Q can be turned on, and the voltage of the third node QB can be the low-level second voltage VGL. The sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, the high-level output signal OUT can be output from the output terminal GOUT of the stage ST.

[0099] In the second sub-interval P2 , a high-level clock signal CLK may be input to the clock terminal CK.

[0100] The first transistor T1 can be turned off by the high-level clock signal CLK. Due to the low-level second voltage VGL, the second transistor T2 can be in the on state. Because the first node A and the second node Q maintain a high-level voltage in the first subinterval P1 due to the first capacitor C1, the fifth transistor T5 can remain in the off state. The fourth transistor T4, whose gate is connected to the second node Q, can be turned on, and the low-level second voltage VGL can be transmitted to the third node QB. The sixth transistor T6, whose gate is connected to the third node QB, can be turned on, and the high-level first voltage VGH can be transmitted to the output terminal GOUT. Therefore, the high-level output signal OUT can be output from the output terminal GOUT of the stage ST.

[0101] The operation of stage ST in the third sub-interval P3 and the fifth sub-interval P5 is the same as the operation of stage ST in the first sub-interval P1, and the operation of stage ST in the fourth sub-interval P4 and the sixth sub-interval P6 is the same as the operation of stage ST in the second sub-interval P2, and therefore their description will be omitted.

[0102] In the seventh sub-interval P7 , the low-level clock signal CLK may be input to the clock terminal CK.

[0103] The first transistor T1 can be turned on by the low-level clock signal CLK. Due to the low-level second voltage VGL, the second transistor T2 can be in a conductive state. Since the first transistor T1 and the second transistor T2 are turned on, the low-level previous output signal OUT' can be transmitted to the first node A and the second node Q of the stage ST, and the fifth transistor T5 can be turned on. The low-level second voltage VGL is transmitted to the output terminal GOUT through the turned-on fifth transistor T5. Therefore, the low-level output signal OUT can be output from the output terminal GOUT of the stage ST.

[0104] The fourth transistor T4 whose gate is connected to the second node Q may be turned off, the third transistor T3 whose gate is connected to the first node A may be turned on, and the voltage of the third node QB may be the high-level first voltage VGH. The sixth transistor T6 whose gate is connected to the third node QB may be turned off.

[0105] Figure 7 and Figure 8 is a diagram showing the embodiment of the present invention. Figure 1 A diagram of any one of the multiple stages in a driving circuit. Figure 9 It is a timing diagram for describing the operation of the level according to the embodiment. Figures 3 to 6 Describes the differences in configuration and operation.

[0106] Reference Figure 7 The stage ST may include a control circuit 131, an output circuit 135, and a reset circuit 137b. Each of the control circuit 131, the output circuit 135, and the reset circuit 137b may include at least one transistor. The at least one transistor may include an N-channel transistor and / or a P-channel transistor. For example, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 may be N-channel transistors, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 may be P-channel transistors.

[0107] In an embodiment, Figure 8 As shown in FIG, the first transistor T1 to the eighth transistor T8 of the stage ST are dual-gate transistors each further including a back gate. Each of the first transistor T1 to the eighth transistor T8 may include a first gate as a top gate (gate) positioned above the semiconductor and a second gate as a bottom gate (back gate) positioned below the semiconductor. The back gate of each of the first transistor T1 to the eighth transistor T8 may be connected to its own top gate.

[0108] Except for the configuration of reset circuit 137b Figure 3 and Figure 4 In addition to the different configuration of the reset circuit 137a of the stage ST, Figure 7 and Figure 8 Each of the stages shown in ST is Figure 3 and Figure 4 The same as the ST level.

[0109] The reset circuit 137b can reset the second node Q and the third node QB. The reset circuit 137b may include a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 and the eighth transistor T8 may be N-channel oxide transistors. When the seventh transistor T7 and the eighth transistor T8 are N-channel transistors, the risk of leakage during low-frequency driving can be reduced, and the threshold voltage shift margin can be increased compared to the case where the seventh transistor T7 and the eighth transistor T8 are P-channel transistors. For example, when the seventh transistor T7 and the eighth transistor T8 are P-channel transistors, the threshold voltage is approximately -1.42V and the threshold voltage shift margin is approximately Δ0.9V, while when the seventh transistor T7 and the eighth transistor T8 are N-channel transistors, the threshold voltage is approximately -1.04V and the threshold voltage shift margin is approximately Δ1.28V.

[0110] The seventh transistor T7 may be connected between the third node QB and the second voltage input terminal V2, and a gate of the seventh transistor T7 may be connected to the reset terminal RS. When the reset signal ESR is applied to the reset terminal RS at a high level, the seventh transistor T7 may be turned on and may reset the voltage of the third node QB to the second voltage VGL.

[0111] The eighth transistor T8 may be connected between the first voltage input terminal V1 and the first node A, and a gate of the eighth transistor T8 may be connected to the reset terminal RS. When the reset signal ESR is applied to the reset terminal RS at a high level, the eighth transistor T8 may be turned on and may reset the voltage of the first node A and the voltage of the second node Q to the first voltage VGH.

[0112] Reference Figure 9 , starting from the first time t1 , in the first interval PP1 , a voltage of 0V may be input to the reset signal line 15 connected to the plurality of stages (eg, the plurality of stages ST1 to STn).

[0113] Starting from the second time t2, in the second interval PP2, the reset signal ESR input to the reset signal line 15 connected to the plurality of stages (eg, the plurality of stages ST1 to STn) may be a high level voltage ESR_H. The high level voltage ESR_H of the reset signal ESR may be the first voltage VGH.

[0114] The seventh transistor T7 and the eighth transistor T8 of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) can be turned on by the reset signal ESR of the high-level voltage ESR_H, the second voltage VGL can be transmitted to the third node QB, and the first voltage VGH can be transmitted to the first node A and the second node Q. Therefore, the voltage VQB of the third node QB of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) can be discharged to the second voltage VGL, and the voltages of the first node A and the second node Q can be charged to the first voltage VGH. The fifth transistor T5 whose gate is connected to the second node Q can be turned off, the sixth transistor T6 whose gate is connected to the third node QB can be turned on, and the first voltage VGH can be transmitted to the output terminal GOUT. Therefore, the output signal OUT of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) can be the high-level voltage OUT_H.

[0115] Starting from the third time t3, the reset signal ESR of the low level voltage ESR_L may be input to the plurality of stages (e.g., the plurality of stages ST1 to STn). In an embodiment, the low level voltage ESR_L of the reset signal ESR may be the second voltage VGL. The seventh transistor T7 and the eighth transistor T8 of each of the plurality of stages (e.g., the plurality of stages ST1 to STn) may be turned off by the reset signal ESR of the low level voltage ESR_L. That is, when the plurality of stages (e.g., the plurality of stages ST1 to STn) operate to output the output signal OUT of the high level voltage OUT_H, the seventh transistor T7 and the eighth transistor T8 may be turned off.

[0116] Figure 10 and Figure 11 is a diagram showing the embodiment of the present invention. Figure 1 A diagram of any one of the multiple stages in the driver circuit. Figure 7 and Figure 8 The reset circuit 137b is configured such that the seventh transistor T7 of the reset circuit 137c is connected to the third voltage line for inputting the third voltage VGL2. Figure 10 and Figure 11 Each of the stages shown in ST is Figure 7 and Figure 8 The same as the ST level.

[0117] The reset circuit 137c may include a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 and the eighth transistor T8 may be N-channel oxide transistors.

[0118] The seventh transistor T7 may be connected between the third node QB and the third voltage input terminal V3, and the gate of the seventh transistor T7 may be connected to the reset terminal RS. The third voltage input terminal V3 may be one end of a third voltage line. When a reset signal ESR is applied to the reset terminal RS at a high level, the seventh transistor T7 may be turned on and may reset the voltage of the third node QB to a third voltage VGL2. In an embodiment, the third voltage VGL2 is a voltage lower than the second voltage VGL.

[0119] The eighth transistor T8 may be connected between the first voltage input terminal V1 and the first node A, and a gate of the eighth transistor T8 may be connected to the reset terminal RS. When the reset signal ESR is applied to the reset terminal RS at a high level, the eighth transistor T8 may be turned on and may reset the voltage of the first node A and the voltage of the second node Q to the first voltage VGH.

[0120] Reference Figure 9 Starting from the first time t1, in the first interval PP1, a voltage of 0V may be input to the third voltage line connected to the plurality of stages (e.g., the plurality of stages ST1 to STn). Starting from the second time t2, a third voltage VGL2 may be input to the third voltage line connected to the plurality of stages (e.g., the plurality of stages ST1 to STn).

[0121] Figure 12 and Figure 13 is a diagram showing the embodiment of the present invention. Figure 1 A diagram of any one of the multiple stages in the driver circuit. Figure 3 and Figure 4 The reset circuit 137a of the stage ST includes an eighth transistor T8 in addition to the reset circuit 137d. Figure 12 and Figure 13 Each of the stages shown in ST is Figure 3 and Figure 4 The same as the ST level.

[0122] The reset circuit 137d may include a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 may be a P-channel silicon transistor, and the eighth transistor T8 may be an N-channel oxide transistor. For example, the reset circuit 137d may include complementary transistors.

[0123] The seventh transistor T7 may be connected between the third node QB and the second voltage input terminal V2, and a gate of the seventh transistor T7 may be connected to the first reset terminal RS1. When the first reset signal ESR1 is applied to the first reset terminal RS1 at a low level, the seventh transistor T7 may be turned on and may reset the voltage of the third node QB to the second voltage VGL.

[0124] The eighth transistor T8 may be connected between the first voltage input terminal V1 and the first node A, and a gate of the eighth transistor T8 may be connected to the second reset terminal RS2. When the second reset signal ESR2 is applied to the second reset terminal RS2 at a high level, the eighth transistor T8 may be turned on and may reset the voltage of the first node A and the voltage of the second node Q to the first voltage VGH.

[0125] In an embodiment, the timing at which the low-level first reset signal ESR1 is input to the gate of the seventh transistor T7 and the timing at which the high-level second reset signal ESR2 is input to the gate of the eighth transistor T8 are the same. That is, the seventh transistor T7 and the eighth transistor T8 can be turned on at the same time, so that the third node QB and the second node Q are reset at the same time. The controller 190 (see Figure 14 ) can supply reset signals ESR1 and ESR2.

[0126] The voltage change of the first reset signal ESR1 over time is related to Figure 5 and the voltage change of the second reset signal ESR2 over time is the same as that shown in Figure 9 Same as shown in .

[0127] Figure 14 is a diagram schematically showing a display device according to an embodiment.

[0128] The display device 10 is a device for displaying moving images or still images and can visually provide information to a user. The display device 10 according to the embodiment can be a display device such as an organic light emitting display device, an inorganic light emitting display device (or an inorganic electroluminescent (EL) display device), or a quantum dot light emitting display device.

[0129] Reference Figure 14 The display device 10 according to the embodiment may include a display panel 110. The display panel 110 may include a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel, but the type of the display panel 110 is not limited thereto. The display panel 110 may be a rigid type or a flexible type that can be rolled or folded.

[0130] A plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX connected to the plurality of gate lines GL and the plurality of data lines DL may be positioned on the display panel 110. An area where the plurality of pixels PX are positioned may correspond to a display area where an image is displayed.

[0131] The plurality of pixels PX may be repeatedly arranged in a first direction (x direction or row direction) and a second direction (y direction or column direction). The plurality of pixels PX may be arranged in various forms (such as stripe arrangement, The plurality of pixels PX may be arranged in any of a plurality of patterns (e.g., a grid arrangement, a diamond arrangement, or a mosaic arrangement) to display an image. Each of the plurality of pixels PX may include an organic light emitting diode as a display element, and the organic light emitting diode may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. Each pixel PX may emit light, such as red light, green light, blue light, or white light, through an organic light emitting diode (OLED). Each pixel PX may be connected to a corresponding gate line from among a plurality of gate lines GL and a corresponding data line from among a plurality of data lines DL.

[0132] In an embodiment, the plurality of transistors included in the pixel circuit may be P-channel silicon transistors. In an embodiment, the plurality of transistors included in the pixel circuit may be N-channel oxide transistors. In an embodiment, some of the plurality of transistors included in the pixel circuit may be P-channel silicon transistors, and others may be N-channel oxide transistors.

[0133] Each of the plurality of gate lines GL may extend in the x-direction (row direction) and may be connected to a plurality of pixels PX positioned in the same row. Each of the plurality of gate lines GL may transmit a gate signal to the plurality of pixels PX in the same row. Each of the plurality of data lines DL may extend in the y-direction (column direction) and may be connected to the plurality of pixels PX positioned in the same column. Each of the plurality of data lines DL may transmit a data signal to each of the plurality of pixels PX in the same column in synchronization with the gate signal.

[0134] Various wires for transmitting electrical signals to be applied to the display area, external drive circuits electrically connected to pixel circuits, and pads to which a printed circuit board or a driver integrated circuit (IC) chip is attached may be located in a peripheral area (e.g., a non-display area) outside the display area of ​​the display panel 110. For example, a gate drive circuit 130, a data drive circuit 150, a power supply circuit 170, and a controller 190 may be provided in the peripheral area of ​​the display panel 110.

[0135] The gate drive circuit 130 may be connected to a plurality of gate lines GL, may generate a gate signal GS in response to a gate drive control signal GCS from the controller 190, and may sequentially supply the gate signal GS to the gate lines GL. The gate lines GL may be connected to the gates of the transistors included in the pixels PX, and the gate signal GS may be a gate control signal for controlling the on and off state of the transistors to which the gate lines are connected. The gate signal GS may include a gate-on voltage for turning on the transistors and a gate-off voltage for turning off the transistors. The gate drive circuit 130 may include a plurality of stages for sequentially generating and outputting the gate signal GS.

[0136] In an embodiment, the gate drive circuit 130 may be implemented as Figure 1 driving circuit DRV. For example, the gate signal GS output by the gate driving circuit 130 to each gate line GL may correspond to a high-level output signal OUT output to the output line by each of the plurality of stages (e.g., a plurality of stages ST1 to STn). Each of the plurality of stages (e.g., a plurality of stages ST1 to STn) may be connected to a gate line GL positioned in a corresponding row of the display panel 110. Each of the plurality of stages (e.g., a plurality of stages ST1 to STn) may generate a gate signal GS as an output signal OUT, and may output the gate signal GS to the gate line GL connected to each of the plurality of stages (e.g., a plurality of stages ST1 to STn). That is, each of the first stage ST1 to the nth stage STn may supply a high-level gate signal GS to the gate line GL provided in the corresponding row. In an embodiment, each of the first stage ST1 to the nth stage STn of the gate driving circuit 130 may be a reference Figures 3 to 13 Description of the Grade St.

[0137] The number of stages constituting the gate driving circuit 130 according to an embodiment may be changed in various ways according to the number of rows (horizontal lines) provided on the display panel 110 .

[0138] The data driving circuit 150 may be connected to a plurality of data lines DL and may supply data signals DATA to the data lines DL in response to data driving control signals DCS from the controller 190. The data signals DATA input to the data lines DL may be input to the pixels PX to which the gate signals are input. The data driving circuit 150 may convert input image data having grayscale levels input from the controller 190 into data signals DATA in the form of voltage or current.

[0139] The power supply circuit 170 can generate signals (voltage and current) required to drive the pixel PX in response to the power drive control signal PCS from the controller 190. The power supply circuit 170 can supply power to the components of the electronic device. The power supply circuit 170 can include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each of the multiple components of the electronic device.

[0140] When the display device 10 is an organic light-emitting display device, the power supply circuit 170 may generate a first power supply voltage ELVDD and a second power supply voltage ELVSS, and may supply the first power supply voltage ELVDD and the second power supply voltage ELVSS to the pixels PX. The first power supply voltage ELVDD may be a high-level voltage supplied to one terminal of a drive transistor connected to the first electrode (pixel electrode or anode) of the organic light-emitting diode of each pixel PX. The second power supply voltage ELVSS may be a low-level voltage supplied to the second electrode (counter electrode or cathode) of the organic light-emitting diode. The first power supply voltage ELVDD and the second power supply voltage ELVSS may be driving voltages for causing the plurality of pixels PX to emit light.

[0141] Also refer to Figures 9 to 13 The power supply circuit 170 may generate a first voltage VGH, a second voltage VGL, and a third voltage VGL2 and may supply the first voltage VGH, the second voltage VGL, and the third voltage VGL2 to the gate driving circuit 130 .

[0142] The controller 190 may generate a gate drive control signal GCS, a data drive control signal DCS, and a power drive control signal PCS based on externally input signals. The controller 190 may supply the gate drive control signal GCS to the gate drive circuit 130, the data drive control signal DCS to the data drive circuit 150, and the power drive control signal PCS to the power supply circuit 170.

[0143] In an embodiment, the gate drive control signal GCS may include a reset signal ESR, an external start signal FLM, and a plurality of clock signals (e.g., clock signals CLK1 and CLK2). Before the voltages such as the first voltage VGH, the second voltage VGL, and the third voltage VGL2 are stably operated by the power supply circuit 170, the reset signal ESR may be supplied to the gate drive circuit 130 by the controller 190, thereby enabling the display device to operate stably. The controller 190 may independently control the timing of outputting the first reset signal ESR1 and the second reset signal ESR2.

[0144] In an embodiment, the display device 10 may be connected to a processor of an electronic device. The processor may include an application processor AP. The controller 190 may receive a conduction operation signal from the application processor AP, such as a power-on signal PO and / or an operation flag signal FLAG. When the electronic device is powered on by a user or awakened from sleep mode, the controller 190 may receive the conduction operation signal from the application processor AP and generate and output a gate drive control signal GCS, a data drive control signal DCS, and a power drive control signal PCS based on the signal. The gate drive circuit 130 that receives the gate drive control signal GCS may operate according to the timing of the above-described embodiment.

[0145] Although Figure 14 The display device 10 is shown as including the power supply circuit 170 independently of the controller 190 , but the present disclosure is not limited thereto. In an embodiment, the power supply circuit 170 may be included in the controller 190 .

[0146] In an embodiment, the gate driving circuit 130, the data driving circuit 150, the power supply circuit 170, and the controller 190 may be mounted as driving chips on the display panel 110. The data driving circuit 150, the power supply circuit 170, and the controller 190 may be formed as separate integrated circuit chips, or may be formed as one integrated circuit chip and may be positioned on a flexible printed circuit board (FPCB) electrically connected to pads positioned on one side of the substrate constituting the display panel 110. In another embodiment, the data driving circuit 150, the power supply circuit 170, and the controller 190 may be positioned directly on the substrate in a chip-on-glass (COG) or chip-on-plastic (COP) manner.

[0147] In an embodiment, during the process of forming transistors constituting pixel circuits in the display area of ​​the substrate, a portion or all of the gate driver circuit 130 may be directly formed in the peripheral area of ​​the substrate. The gate driver circuit 130 may include an amorphous silicon thin film transistor (TFT) gate driver circuit (ASG), a low temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (OSG) built into the display panel 110.

[0148] Figures 15 to 17B is a perspective view schematically showing a display device according to an embodiment.

[0149] like Figure 15 As shown in , the display device 10 according to the embodiment may be rigid without flexibility and may be completely flat.

[0150] The display device 10 may include a display area DA that displays an image and a peripheral area PA outside the display area DA. The display area DA may be completely surrounded by the peripheral area PA. In a plan view, the display area DA may have a rectangular shape. In another embodiment, the display area DA may have a polygonal shape (e.g., a triangle, a pentagon, or a hexagon), a circular shape, an elliptical shape, or an irregular shape. The display area DA may have a shape with rounded corners.

[0151] In an embodiment, Figure 15 and Figure 16AAs shown in , the display device 10 may include a display area DA having a shape in which the length in the y direction is greater than the length in the x direction. Figure 17A As shown in , the display device 10 may include a display area DA having a shape in which a length in the x direction is greater than a length in the y direction. The z direction may be substantially perpendicular to a plane defined by the x and y directions.

[0152] like 16A to 17B As shown in , the display device 10 according to the embodiment can be folded or bent. In an embodiment, the display device 10 can be folded so that the display surfaces face each other. In another embodiment, the display device 10 can be folded so that the display surfaces face outward. The term "folding" means that the shape is not fixed, but can be changed from the original shape to another shape, and can include being folded, bent or curled along at least one specific line (i.e., a folding axis).

[0153] like Figure 16A and Figure 17A As shown in , the display area DA may include at least one flexible and foldable folding area. Figure 16B and Figure 17B As shown in FIG, the folding area FA can be folded along a folding axis FAX.

[0154] Each stage of the driving circuit according to the embodiment may include a reset circuit (eg, Figure 3 The reset circuit 137a, Figure 7 The reset circuit 137b, Figure 10 The reset circuit 137c and Figure 12 The reset circuit 137d) is used to reset the multiple stages simultaneously before the operation for outputting the output signal. Therefore, flickering due to abnormal power-on / power-off order (or sequence) can be prevented. Specifically, when the operation is performed quickly as shown in FIG. Figure 16A and Figure 17A When the flexible display device shown in is folded / unfolded, flickering caused by an abnormal power-on / power-off order (or sequence) can be prevented. For example, undesirable visual effects such as brief flickering of light on the display panel may occur.

[0155] The electronic device according to the embodiment may output various information under the control of the operating system through the display device 10. When the processor executes an application stored in the memory, the display device 10 may provide application information to the user through the display panel.

[0156] The display device 10 can be used not only as a display screen for a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, or an ultra-mobile PC (UMPC), but can also be used as any of a variety of products such as a television, a computer device, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. In addition, the display device 10 according to the embodiment can be used in a wearable device such as a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD). In addition, the display device 10 according to the embodiment can be used as a central information display (CID) positioned on a dashboard, a center console, or an instrument panel of a vehicle, an interior rearview mirror display that replaces a side mirror of a vehicle, or a display positioned on the back of a front seat for entertaining rear seat passengers of a vehicle.

[0157] The electronic device of the present disclosure may be any of a variety of devices. The electronic device may include at least one of a portable communication device (e.g., a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a household appliance. The electronic device according to the embodiment is not limited to the above devices.

[0158] According to the embodiment, a driving circuit capable of stably outputting a gate signal at low power and a display device including the same can be provided.

[0159] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope as defined by the appended claims.

Claims

1. A driving circuit comprising a plurality of stages, wherein: Each of the plurality of stages comprises: a first transistor connected to a first terminal receiving a start signal and connected to a first node, the first transistor including a gate connected to a clock terminal receiving a clock signal; a second transistor connected between the first node and the second node and including a gate connected to a second terminal receiving a first voltage; a third transistor connected between a third terminal receiving a second voltage higher than the first voltage and a third node, the third transistor including a gate connected to the first node; a fourth transistor connected between the third node and the second terminal and including a gate connected to the second node; a fifth transistor connected between the output terminal and the second terminal and including a gate connected to the second node; a sixth transistor connected between the third terminal and the output terminal and including a gate connected to the third node; and A seventh transistor is connected between the third node and the second terminal and includes a gate connected to a reset terminal.

2. The driving circuit according to claim 1, wherein: From the time when the first voltage and the second voltage are input to the time when the clock signal is input, a reset signal of the gate-on voltage is input to the reset terminal of each of the multiple stages, and the multiple voltages of the multiple third nodes of the multiple stages are simultaneously reset to the first voltage.

3. The driving circuit according to claim 2, wherein: For a specific period before the time when the first voltage and the second voltage are input, a voltage of 0 volts is input to the first terminal, the second terminal, the third terminal and the reset terminal of each of the multiple stages, and the multiple voltages of the multiple third nodes of the multiple stages are discharged to 0 volts at the same time.

4. The driving circuit according to claim 2, wherein: When the start signal is input after the time when the clock signal is input, output signals are sequentially output from the plurality of output terminals of the plurality of stages, and The reset signal of a gate-off voltage is input to the reset terminal of each of the plurality of stages from the time when the clock signal is input.

5. The driving circuit according to claim 1, wherein: The third transistor is a P-channel transistor, and The fourth transistor is an N-channel transistor. The driving circuit according to claim 1 , wherein: The fourth transistor is an N-channel transistor, and The first transistor, the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-channel transistors.

7. The driving circuit according to claim 1, wherein: Each of the plurality of stages further comprises: a first capacitor connected between the second node and the output terminal; and A second capacitor is connected between the third terminal and the third node.

8. The driving circuit according to claim 1, wherein: Each of the plurality of stages further includes an eighth transistor connected between the third terminal and the first node and including a gate connected to the reset terminal, Wherein, the seventh transistor and the eighth transistor are N-channel transistors.

9. The driving circuit according to claim 1, wherein: Each of the plurality of stages further includes an eighth transistor connected between the third terminal and the first node and including a gate connected to a second reset terminal, wherein the seventh transistor is a P-channel transistor and the eighth transistor is an N-channel transistor, The timing of the first reset signal input to the reset terminal connected to the seventh transistor being the gate-on voltage and the timing of the second reset signal input to the second reset terminal connected to the eighth transistor being the gate-on voltage are the same.

10. A driving circuit comprising a plurality of stages, wherein: Each of the plurality of stages comprises: a first transistor connected to a first terminal receiving a start signal and connected to a first node, the first transistor including a gate connected to a clock terminal receiving a clock signal; a second transistor connected between the first node and the second node and including a gate connected to a second terminal receiving a first voltage; a third transistor connected between a third terminal receiving a second voltage higher than the first voltage and a third node, the third transistor including a gate connected to the first node; a fourth transistor connected between the third node and the second terminal and including a gate connected to the second node; a fifth transistor connected between the output terminal and the second terminal and including a gate connected to the second node; a sixth transistor connected between the third terminal and the output terminal and including a gate connected to the third node; a seventh transistor connected between the third node and a fourth terminal receiving a third voltage lower than the first voltage, the seventh transistor including a gate connected to a reset terminal; and An eighth transistor is connected between the third terminal and the first node and includes a gate connected to the reset terminal.

11. The driving circuit according to claim 10, wherein: The seventh transistor and the eighth transistor are N-channel transistors.

12. The driving circuit according to claim 10, wherein: From the time when the first voltage, the second voltage and the third voltage are input to the time when the clock signal is input, a reset signal of the gate-on voltage is input to the reset terminal of each of the multiple stages, and the multiple voltages of the multiple third nodes of the multiple stages are simultaneously reset to the first voltage.

13. The driving circuit according to claim 12, wherein: For a specific period before the time when the first voltage, the second voltage and the third voltage are input, a voltage of 0 volts is input to the first terminal, the second terminal, the third terminal and the reset terminal of each of the multiple stages, and the multiple voltages of the multiple third nodes of the multiple stages are discharged to 0 volts at the same time.

14. The driving circuit according to claim 12, wherein: When the start signal is input after the time when the clock signal is input, output signals are sequentially output from the plurality of output terminals of the plurality of stages, and The reset signal of a gate-off voltage is input to the reset terminal of each of the plurality of stages from the time when the clock signal is input.

15. The driving circuit according to claim 10, wherein: The third transistor is a P-channel transistor, and The fourth transistor is an N-channel transistor.

16. The driving circuit according to claim 10, wherein: Each of the plurality of stages further comprises: a first capacitor connected between the second node and the output terminal; and A second capacitor is connected between the third terminal and the third node.

17. An electronic device, wherein: The electronic device comprises: a controller configured to output a plurality of clock signals; a power supply circuit configured to output a plurality of voltages; and a driving circuit configured to output a gate signal based on the plurality of clock signals and the plurality of voltages, The driving circuit includes a plurality of stages, wherein each of the plurality of stages includes: a first transistor connected to a first terminal receiving a start signal and to a first node, the first transistor including a gate connected to a clock terminal receiving one of the plurality of clock signals; a second transistor connected between the first node and the second node and including a gate connected to a second terminal receiving a first voltage among the plurality of voltages; an inverter connected between a third terminal receiving a second voltage among the plurality of voltages and the second terminal, the inverter configured to control a voltage of a third node to a voltage level obtained by inverting a voltage level of the first node or a voltage level of the second node; a pull-down transistor connected between the output terminal and the second terminal and including a gate connected to the second node; a pull-up transistor connected between the third terminal and the output terminal and including a gate connected to the third node; and The reset circuit is configured to reset the second node or the third node.

18. The electronic device according to claim 17, wherein: The reset circuit includes a third transistor connected between the third node and the second terminal and including a gate connected to a reset terminal.

19. The electronic device according to claim 17, wherein: The reset circuit comprises: a third transistor connected between the third node and the second terminal and including a gate connected to a reset terminal; and a fourth transistor connected between the third terminal and the first node and including a gate connected to the reset terminal, Wherein, the third transistor and the fourth transistor are N-channel transistors.

20. The electronic device according to claim 17, wherein The reset circuit comprises: a third transistor connected between the third node and a fourth terminal receiving a third voltage among the plurality of voltages, the third transistor including a gate connected to a reset terminal; and a fourth transistor connected between the third terminal and the first node and including a gate connected to the reset terminal, Wherein, the third transistor and the fourth transistor are N-channel transistors.

21. The electronic device according to claim 17, wherein The reset circuit comprises: a third transistor connected between the third node and the second terminal and including a gate connected to a first reset terminal; and a fourth transistor connected between the third terminal and the first node and including a gate connected to a second reset terminal, wherein the third transistor is a P-channel transistor, and the fourth transistor is an N-channel transistor, The timing of the first reset signal input to the first reset terminal connected to the third transistor being the gate-on voltage and the timing of the second reset signal input to the second reset terminal connected to the fourth transistor being the gate-on voltage are the same.

22. An electronic device, wherein: The electronic device comprises: a controller configured to receive a conduction operation signal from the processor and output a reset signal based on the conduction operation signal; and a driver circuit comprising a stage configured to receive the reset signal and reset a control node, Wherein, the stages include: a first transistor connected to a first terminal receiving a start signal and connected to a first node, the first transistor including a gate connected to a clock terminal receiving a clock signal; a second transistor connected between the first node and the second node and including a gate connected to a second terminal receiving a first voltage; an inverter connected between a third terminal receiving a second voltage and the second terminal, the inverter configured to control the voltage of the control node to a voltage level obtained by inverting the voltage level of the first node or the voltage level of the second node; a pull-down transistor connected between the output terminal and the second terminal and including a gate connected to the second node; a pull-up transistor connected between the third terminal and the output terminal and including a gate connected to the control node; and A reset transistor is connected between the control node and the second terminal and includes a gate connected to a reset terminal receiving the reset signal.

23. The electronic device according to claim 22, wherein: The stage further includes a second reset transistor connected between the third terminal and the first node and including a gate connected to the reset terminal, Wherein, the reset transistor and the second reset transistor are N-channel transistors.

24. The electronic device according to claim 22, wherein: The stage further includes a second reset transistor connected between the third terminal and the first node and including a gate connected to a second reset terminal, wherein the reset transistor is a P-channel transistor, and the second reset transistor is an N-channel transistor, The controller is further configured to control the timing of the reset signal input to the reset terminal connected to the reset transistor being the gate-on voltage and the timing of the second reset signal input to the second reset terminal connected to the second reset transistor being the gate-on voltage to be the same.

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