Package structure

Abstract

A package structure includes a light emitting epitaxial structure (2100), a light receiving structure (2200), a first conductive structure (2100P), a second conductive structure (2200N), and a third conductive structure (2400). The light-emitting epitaxial structure (2100) includes an upper distributed Bragg reflector (2100U), an active structure (2100A), and a lower distributed Bragg reflector (2100L) stacked in sequence. The light-receiving structure (2200) is located under the active structure (2100A) and contacts the light-emitting epitaxial structure (2100). A first conductive structure (2100P) contacts the upper distributed Bragg reflector (2100U) and extends to cover the lower surface (2200B) of the light receiving structure (2200), a second conductive structure (2200N) contacts the lower surface (2200B) of the light receiving structure (2200), and a third conductive structure (2400) contacts the upper surface (2100LT) of the lower distributed Bragg reflector (2100L) and extends to cover the lower surface (2200B) opposite to the upper surface (2100LT). Wherein the first conductive structure (2100P) is insulated from the second conductive structure (2200N), the first conductive structure (2100P) is insulated from the third conductive structure (2400), and the second conductive structure (2200N) is insulated from the third conductive structure (2400).

Description

Package structure Technical Field

[0001] The present application relates to a packaging structure, and in particular to a packaging structure for an optoelectronic device. Background Art

[0002] The Vertical Cavity Surface Emitting Laser (VCSEL) is a type of semiconductor laser element. Due to its epitaxial surface-emitting structure, and driven by market demand and the emergence of more applications in various IoT products, smart electronics, and intelligent sensing products, VCSEL components have gradually expanded from the network communication product market to a variety of smart products (for example, optical communication light source modules, proximity sensors in smart tablets and smart headsets, depth, distance, and 3D sensors, lidar sensors for advanced driver assistance systems, light sources or panels for micro-projection displays, eye trackers in interactive devices, and photonic integrated circuits).

[0003] In most of the aforementioned current applications, due to various product development and usage requirements (e.g., low cost, portability, miniaturization, high integration compatibility with other components, reliability in stringent automotive environments, long product lifespan, low power consumption, extended operating time, and high-frequency electrical drive operation), an increasing number of VCSEL devices are adopting flip-chip packaging technology to meet these requirements.

[0004] Summary of the Invention

[0005] In view of this, the present application provides packaging structures in different embodiments.

[0006] In some embodiments, a packaging structure is provided, comprising a light-emitting epitaxial structure, a light-receiving structure, a first conductive structure, a second conductive structure, and a third conductive structure. The light-emitting epitaxial structure includes an upper distributed Bragg reflector (DBR), an active structure, and a lower DBR stacked in sequence. The light-receiving structure is located below the active structure and contacts the light-emitting epitaxial structure. The first conductive structure contacts the upper DBR and extends to cover the lower surface of the light-receiving structure. The second conductive structure contacts the light-receiving structure on the lower surface. The third conductive structure contacts the upper surface of the lower DBR and extends to cover the lower surface relative to the upper surface. The first conductive structure is insulated from the second conductive structure, the first conductive structure is insulated from the third conductive structure, and the second conductive structure is insulated from the third conductive structure.

[0007] In some embodiments, the upper DBR includes a P-type semiconductor structure, and the lower DBR includes an N-type semiconductor structure.

[0008] In some embodiments, the first conductive structure is a P-electrode of a light-emitting epitaxial structure.

[0009] In some embodiments, the second conductive structure is an N-electrode of the light receiving structure.

[0010] In some embodiments, the third conductive structure is a common electrode of the light-emitting epitaxial structure and the light-receiving structure.

[0011] In some embodiments, the light receiving structure is integrally formed as part of the lower DBR.

[0012] In some embodiments, the encapsulation structure further includes a transparent base layer, which is bonded to the epitaxial light emitting structure via a first bonding layer, wherein the transparent base layer and the first bonding layer are transparent to light emitted from the epitaxial light emitting structure.

[0013] In some embodiments, the light receiving structure is bonded to the lower DBR via a second bonding layer.

[0014] In some embodiments, the second adhesive layer is conductive.

[0015] In some embodiments, the packaging structure further includes another DBR located under the light receiving structure.

[0016] In some embodiments, a method for singularizing an epitaxial wafer is provided, wherein the epitaxial wafer comprises a stacked semiconductor layer and a base layer, the stacked semiconductor layer being disposed on an upper surface of the base layer, wherein the base layer may be made of sapphire, glass, or a Group III-V compound. The method comprises a processing step, a cutting step, and a cleaving step. The processing step comprises: processing a portion of the base layer from the upper surface of the epitaxial wafer using a stealth dicing technique, thereby forming a processing region in the portion of the base layer, wherein the processing region comprises at least one row of fracture points extending substantially parallel to the lower surface of the epitaxial wafer, and the distance between the processing region and the upper surface of the epitaxial wafer does not exceed 60 microns. The dicing step comprises: dicing another portion of the base layer from the lower surface of the epitaxial wafer using a laser lift-off technique or a wheel dicing technique, thereby forming a scribe line in the other portion of the base layer, wherein the scribe line has a scribe width and a scribe depth, wherein the scribe width is less than 20 microns and the scribe depth is 30 microns. Splitting step: using a splitting technique on the scribe line to split the epitaxial wafer into a plurality of semiconductor lasers.

[0017] In some embodiments, a method for singulating an epitaxial wafer is provided, wherein the epitaxial wafer includes a semiconductor stacking layer and a base layer, the semiconductor stacking layer being located on an upper surface of the base layer, wherein the base layer can be made of sapphire, glass, or a III-V compound. The method includes: a cutting step and a splitting step. Cutting step: using laser lift-off technology or wheel knife cutting technology to cut a portion of the base layer from the lower surface of the epitaxial wafer, and forming a cutting path in the portion of the base layer, wherein the cutting path has a cutting width and a cutting depth, the cutting width is less than 10 microns, and the cutting depth does not exceed 90 microns. Splitting step: using a splitting technology on the cutting path to split the epitaxial wafer into multiple semiconductor lasers.

[0018] In some embodiments, the stealth cutting technology is achieved using a laser having a wavelength of 1064 nanometers.

[0019] In some embodiments, the III-V compound is GaAs, InP, or GaSb.

[0020] In some embodiments, a semiconductor laser is provided, comprising a base layer, an epitaxial structure located on the base layer, an insulating layer, a first electrode, and a second electrode. The epitaxial structure comprises an upper reflector, a lower reflector, and an active area located between the upper reflector and the lower reflector. The upper reflector, the active area, and the lower reflector are stacked on the base layer. The second electrode is on the epitaxial structure and electrically connected to the semiconductor layer of the upper reflector. The first electrode is on the base layer and electrically connected to the semiconductor layer of the upper reflector. The second electrode comprises at least one metal layer and a P-type contact layer, connected to the P-type semiconductor layer of the upper reflector, and the first electrode comprises at least one metal layer connected to the base layer and electrically connected to the N-type semiconductor layer of the lower reflector. The insulating layer is located between the epitaxial structure and the second electrode, and extends to the side of the epitaxial structure to prevent the second electrode from directly contacting the active area and the lower reflector. The side surface of the base layer has at least one row of cracking points.

[0021] In some embodiments, the semiconductor laser may be a vertical cavity surface emitting laser with a vertical chip structure or a flip chip vertical cavity surface emitting laser.

[0022] In some embodiments, a VCSEL chip is provided, comprising a base layer, an epitaxial structure located on the base layer, an insulating layer, a first electrode, and a second electrode. The epitaxial structure comprises an upper reflector, a lower reflector, and an active area located between the upper reflector and the lower reflector. The upper reflector, the active area, and the lower reflector are stacked on the base layer. The second electrode is on the epitaxial structure and electrically connected to the semiconductor layer of the upper reflector. The first electrode is on the base layer and electrically connected to the semiconductor layer of the upper reflector. The second electrode comprises at least one metal layer and a P-type contact layer, connected to the P-type semiconductor layer of the upper reflector 1, and the first electrode comprises at least one metal layer connected to the base layer and electrically connected to the N-type semiconductor layer of the lower reflector. The insulating layer is located between the epitaxial structure and the second electrode, and extends to the side of the epitaxial structure to prevent the second electrode from directly contacting the active area and the lower reflector.

[0023] In some embodiments, at least one region of the second electrode has at least one set of patterns for indicating the relative position of the VCSEL chip on an epitaxial wafer. In some embodiments, the at least one region is at least one side or at least one corner of the second electrode.

[0024] In some other embodiments, at least one region of the insulating layer has at least one set of patterns for indicating the relative position of the VCSEL chip on an epitaxial wafer. In some embodiments, the at least one region is at least one side or at least one corner of the insulating layer.

[0025] Furthermore, in some embodiments, at least two of a region of the insulating layer of the epitaxial structure and a region of the second electrode respectively have at least one set of patterns for indicating the relative position of the VCSEL chip on an epitaxial wafer in the horizontal and vertical directions.

[0026] In some embodiments, a semiconductor laser chip is provided, including a base layer and a semiconductor stack layer formed on the base layer, wherein the base layer has a stepped structure on a side opposite to the semiconductor stack layer.

[0027] In some embodiments, the photovoltaic unit package structure further includes an upper electrode and a lower electrode. The upper electrode is formed on the semiconductor stack of the VCSEL chip, and the lower electrode is formed on the bottom surface of the semiconductor stack of the VCSEL chip. The upper electrode is electrically connected to the first-type semiconductor layer of the semiconductor stack, and the lower electrode is electrically connected to the second-type semiconductor layer of the semiconductor stack through the base layer.

[0028] In some embodiments, a VSCEL chip is provided, comprising: a base layer, a semiconductor stack layer, a first electrode structure, a second electrode structure, and an insulating layer. The semiconductor stack layer is located on the base layer, and has a first surface, a second surface, and a side surface. The second surface is opposite to the first surface, and the side surface is located between the first and second surfaces. The semiconductor stack layer includes a first-type semiconductor layer, a second-type semiconductor layer, and an active layer. The active layer is located between the first-type semiconductor layer and the second-type semiconductor layer. The base layer is located on the side of the second-type semiconductor layer opposite to the first-type semiconductor layer. The base layer can be a growth substrate for the semiconductor stack layer, that is, the semiconductor stack layer is grown directly on the base layer. The base layer is conductive and has a bottom and a plateau portion extending from the bottom. The plateau portion has a plateau surface (connected to the second surface) and a plateau side surface, and the plateau side surface is connected to the plateau surface. The base layer has a bottom first surface, a bottom second surface, and a bottom side surface. The bottom first surface is connected to the plateau side surface, the bottom second surface is opposite to the bottom first surface, and the bottom side surface is located between the bottom first and second surfaces. The insulating layer is located on the first surface and extends through the side surface, the plateau surface, and the plateau side surface to the bottom first surface. The insulating layer has an opening, the opening is located on the first surface, and the first electrode structure is located in the opening and contacts the first-type semiconductor layer. The first electrode structure is further located on the first surface and extends through the side surface, the platform surface, and the platform side surface to the bottom first surface. The insulating layer further extends through the bottom first surface to the bottom side surface. The second-type semiconductor layer in the semiconductor stack layer also includes a platform portion and a lateral extension distributed on the platform surface, and the insulating layer and the first electrode structure are further located on the surface of the platform portion. The second electrode structure is located on the bottom second surface. Therefore, when the VSCEL chip is subsequently electrically bonded to the electrode pads on the carrier, the first electrode structure extends to the platform side, and the bonding area between the electrode structure on one side of the VSCEL chip and the bonding structure (e.g., solder paste) bonded to the carrier can be increased without increasing the size of the VSCEL chip. In this way, when the VSCEL chip is packaged, the chip size can be reduced while maintaining the spacing between the electrode pads on the carrier.

[0029] In some embodiments, a photoelectric module is provided, comprising a driver chip, a light emitting device, and a light receiving device, wherein the driver chip is electrically connected to the light emitting device and the light receiving device.

[0030] In one or more embodiments, the light emitting device includes at least one semiconductor light source, such as a semiconductor laser, such as a VCSEL structure.

[0031] In one or more embodiments, the light receiving device includes at least one semiconductor sensor, such as a single-photon avalanche diode (SPAD).

[0032] In some embodiments, the optoelectronic module further includes a lens assembly mounted on the region of the light receiving device.

[0033] In some embodiments, the optoelectronic module can be electrically connected to the circuit board via a ball grid array (BGA) structure. Specifically, in one embodiment, the optoelectronic module further includes a BGA structure located on the back side of the driver chip (on the side opposite the light-emitting device and the light-receiving device) for electrically connecting to the circuit board.

[0034] In some embodiments, an optoelectronic module is provided, comprising a driver chip, a light-emitting device, and passive components. The light-emitting device can be mounted directly on the driver chip, or mounted on a carrier board, which in turn is mounted on the driver chip. The driver chip provides an electrical signal, voltage, or current to drive the light-emitting device as a light source and is electrically connected to a printed circuit board via a ball grid array structure.

[0035] In some embodiments, a transmitting module is provided, which integrates a light emitting device, a passive component, a driver chip, and a carrier. The light emitting device, the passive component, and the driver chip are mounted on the carrier. The light emitting device, the passive component, and the driver chip can be mounted on the same side or different sides of the carrier. The carrier provides power distribution through multiple through-holes and multiple metal layers located between the components (including the driver chip, the light emitting device, and the passive component) and is electrically connected to the printed circuit board through a ball grid array structure. The driver chip provides an electrical signal, voltage, or current to drive the light emitting device as a light source.

[0036] In some embodiments, an underfill may be included between the driver chip and the carrier board, and the underfill covers the ball grid array structure.

[0037] In some embodiments, the optoelectronic module further includes a molding material and metal wires. The driver chip is electrically connected to the carrier board via the metal wires, and the molding material covers the driver chip and the metal wires.

[0038] In some embodiments, a light emitting device is provided, comprising: a semiconductor layer, a transparent base layer, a spacer layer, a first pattern layer, and a cover layer. The first pattern layer is formed on an upper surface of the spacer layer, and then the cover layer is formed on the first pattern layer.

[0039] In some embodiments, a light emitting device is provided, comprising: a semiconductor layer, a transparent base layer, a spacer layer, a first pattern layer, a second pattern layer, and a cover layer. The first pattern layer is formed on the spacer layer. The second pattern layer is formed between the transparent base layer and the spacer layer.

[0040] In some embodiments, a light emitting device is provided, comprising: a semiconductor layer, a transparent base layer, a spacer layer, a first pattern layer, a second pattern layer, a third pattern layer, and a cover layer. The first pattern layer is formed on the spacer layer. The second pattern layer is formed between the transparent base layer and the spacer layer. The third pattern layer is formed between the transparent base layer and the semiconductor layer.

[0041] In some embodiments, a light emitting device is provided, comprising: a semiconductor layer, a first transparent base layer, a first pattern layer, and a covering layer. The first transparent base layer is located on the semiconductor layer, the first pattern layer is formed on the upper surface of the first transparent base layer, and the covering layer is located on the first pattern layer.

[0042] In some embodiments, a light emitting device is provided, comprising a semiconductor layer, a first transparent base layer, a first pattern layer, a second pattern layer, and a cover layer. The first transparent base layer is located on the semiconductor layer, the second pattern layer is formed between the first transparent base layer and the semiconductor layer, the first pattern layer is formed on the upper surface of the first transparent base layer, and the cover layer is located on the first pattern layer.

[0043] In some embodiments, a light emitting device is provided, comprising a semiconductor layer, a first transparent base layer, a second transparent base layer, and a first pattern layer. The first transparent base layer is located on the semiconductor layer, the first pattern layer is formed between the two transparent base layers (the first transparent base layer and the second transparent base layer), and the adhesive layer may be further located on one side of the first pattern layer.

[0044] In some embodiments, the first pattern layer may be formed on the first transparent base layer or the second transparent base layer, and another adhesive layer may be further located between the first transparent base layer and the second transparent base layer.

[0045] In some embodiments, a light emitting device is provided, comprising a semiconductor layer, a first transparent base layer, an adhesive layer, a second transparent base layer, and a pattern layer. The first transparent base layer is located on the semiconductor layer, the second transparent base layer is bonded to the first transparent base layer using the adhesive layer, and the pattern layer is formed on the second transparent base layer.

[0046] In some embodiments, a light emitting device is provided, comprising a semiconductor layer, a first transparent base layer, an adhesive layer, a second transparent base layer, a pattern layer, and a third transparent base layer. The first transparent base layer is disposed on the semiconductor layer, the second transparent base layer is bonded to the first transparent base layer via the adhesive layer, the pattern layer is formed on the second transparent base layer, and the third transparent base layer covers the pattern layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1A is a schematic cross-sectional view illustrating a packaging structure of a photovoltaic unit according to an embodiment;

[0048] 1B is a schematic cross-sectional view illustrating a packaging structure of a photovoltaic unit according to an embodiment;

[0049] FIG1C is a schematic cross-sectional view illustrating a packaging structure of a light emitting sensor package according to an embodiment;

[0050] FIG1D is a schematic cross-sectional view illustrating a packaging structure of a light emitting sensor package according to an embodiment;

[0051] 2A is a schematic cross-sectional view illustrating a packaging structure of a photovoltaic unit according to an embodiment;

[0052] FIG2B is a schematic cross-sectional view illustrating a packaging structure of a light emitting sensor package according to an embodiment;

[0053] 3A is a schematic cross-sectional view illustrating a packaging structure of an optoelectronic device according to an embodiment;

[0054] 3B is a schematic cross-sectional view illustrating a packaging structure of an optoelectronic device according to an embodiment;

[0055] 3C is a schematic cross-sectional view illustrating a packaging structure of an optoelectronic device according to an embodiment;

[0056] 4A to 4D are top views illustrating packaging structures of optoelectronic devices according to some embodiments;

[0057] 5 is a schematic cross-sectional view illustrating a packaging structure of an optoelectronic device according to an embodiment;

[0058] FIG6 is a schematic diagram illustrating an application of a packaging structure of an optoelectronic device according to an embodiment;

[0059] 7A to 7K are schematic cross-sectional views illustrating multiple steps of a process for manufacturing a packaging structure of an optoelectronic device according to one embodiment;

[0060] FIG8A is a top view of a portion of a VCSEL wafer taken using an optical microscope;

[0061] FIG8B is a top view image of a portion of a VCSEL wafer taken using an optical microscope;

[0062] 9A and 9B are schematic diagrams illustrating a conventional VCSEL die singulation process using an ablation laser or a saw from the front side of a thinned VCSEL wafer;

[0063] 10A to 10C are schematic diagrams illustrating a process method for singulating a thinned VCSEL wafer to cut out a plurality of dies according to one embodiment;

[0064] 11A to 11D are schematic perspective views illustrating processing steps of a method for singulating an epitaxial wafer according to some embodiments;

[0065] 12A and 12B are schematic diagrams illustrating a process method for singulating a thinned VCSEL wafer to cut out a plurality of dies according to one embodiment;

[0066] FIG13A is a schematic cross-sectional view of a VCSEL chip according to an embodiment;

[0067] 13B and 13C are cross-sectional images of a VCSEL chip taken using an optical microscope;

[0068] FIG14A is a top view of a VCSEL chip according to an embodiment;

[0069] FIG14B is a schematic cross-sectional view showing a cross section taken along line 14B-14B' of FIG14A;

[0070] 15A to 15B are different schematic diagrams illustrating a VCSEL chip according to one or more embodiments;

[0071] 15C to 15D are top views illustrating a VCSEL chip according to one or more embodiments;

[0072] FIG16 is a top view of a VCSEL chip according to an embodiment;

[0073] 17A to 17F are schematic cross-sectional views illustrating multiple steps of a fabrication process for the VCSEL chip shown in FIG. 15B according to one embodiment;

[0074] 18A to 18G are schematic cross-sectional views illustrating multiple steps of a VCSEL chip fabrication process along line 16Z-16Z' in FIG. 16 according to one embodiment;

[0075] FIG19A is a schematic diagram illustrating the bottom / back surface of an epitaxial wafer of an optoelectronic device according to one embodiment;

[0076] FIG19B is a schematic cross-sectional view taken along line 19X-19X' of FIG19A;

[0077] 19C is a schematic cross-sectional view illustrating a semiconductor laser chip cut from the epitaxial wafer of the optoelectronic device shown in FIG. 19A according to one embodiment;

[0078] FIG19D is a schematic cross-sectional view illustrating the semiconductor laser chip of FIG19C being welded to a carrier;

[0079] FIG20 is a schematic cross-sectional view showing a VCSEL chip mounted on a carrier and soldered to electrode pads of the carrier;

[0080] FIG21 is a cross-sectional diagram illustrating an optoelectronic module that can be applied as a Time of Flight (ToF) module according to one embodiment;

[0081] FIG22 is a schematic cross-sectional view illustrating a transmitting module according to an embodiment;

[0082] FIG23A is a schematic cross-sectional view of a transmitting module according to an embodiment;

[0083] FIG23B is a schematic cross-sectional view of a transmitting module according to an embodiment;

[0084] FIG24A is a schematic cross-sectional view of a light emitting device according to an embodiment;

[0085] FIG24B is a schematic cross-sectional view of a light emitting device according to an embodiment;

[0086] FIG24C is a schematic cross-sectional view illustrating a light emitting device according to an embodiment;

[0087] FIG25A is a schematic cross-sectional view of a light emitting device according to an embodiment;

[0088] FIG25B is a schematic cross-sectional view of a light emitting device according to an embodiment;

[0089] FIG25C is a schematic cross-sectional view illustrating a light emitting device according to an embodiment;

[0090] FIG25D is a schematic cross-sectional view of a light emitting device according to an embodiment;

[0091] FIG25E is a schematic cross-sectional view of a light emitting device according to an embodiment;

[0092] FIG26 is a schematic cross-sectional view of a laser element according to an embodiment;

[0093] FIG27A is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment;

[0094] FIG27B is a bottom view of the laser element shown in FIG27A;

[0095] FIG27C is a top view of the laser element shown in FIG27A ;

[0096] FIG28 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment;

[0097] FIG29 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment;

[0098] 30A to 30E are schematic diagrams of a top perspective view, a bottom perspective view, and cross-sectional views of different cross sections of a semiconductor light-emitting device according to an embodiment, respectively, for illustrating the configuration of a light-emitting region and a common electrode structure of the semiconductor light-emitting device;

[0099] FIG31 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment;

[0100] FIG32A is a schematic top perspective view of a semiconductor light emitting device according to an embodiment. FIG32B and FIG32C are schematic cross-sectional views taken along line segments 32B-32B' and 32C-32C' in FIG32A, respectively.

[0101] FIG33 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment; and

[0102] FIG. 34 is a schematic cross-sectional view of a semiconductor laser device according to an embodiment.

[0103] [Description of Symbols] 2, 2', 2-1, 2-2, 2-1', 2-2', 5, 6: Photoelectric unit 2C, 2D, 2D': Light-emitting sensor package 3A, 3B, 3C, 4A, 4B, 4C, 4D: Photoelectric device 1100, 24015, 26001, 27010: Transparent base layer 1101, 1401: Integrated optical element 1101A, 1101B: Microlens 1200, 2500, 25050, 26002, 27040, 30901, 31901, 32901: Adhesive layer 1300, 19900, 20900, 23900: carrier board 1310: first corresponding pad 1320: second corresponding pad 1330: third corresponding pad 1400: housing 1401: integrated optical element 1401A, 1401B: optical element 2000, 1500, 1600: stacked structure 2000B, 2200B, 10000B, 27206B: lower surface 2000T, 2100UT, 2100LT, 5100UT, 10000T, 15020T, 16020, 24020T, 25021T, P271: top surface 2000V, 2100V: through-hole structure 2000VI, 2100VI: insulation structure 2100, 2100', 2100-1, 2100-2, 2100-1', 2100-2', 5100, 6100: light-emitting epitaxial structure 2100A, 2100A', 5100A: active structure 2100L, 2100L', 5100L: lower distributed Bragg reflector 2100L1, 2100 L2, 2210', 5100L1, 5100L2: distributed Bragg reflector structure 2100U, 2100U', 5100U: upper distributed Bragg reflector 2100e, 2200e, 2200e1, 2200e2, 2200e3, 2400e, 20900e: electrode pads 2100P, 2100P1, 2100P2, 2200N, 2200N1, 2200N2, 2200N3, 2400, 2401, 2402, 5100P, 5400, 6400, 7100P, 7200N, 7400: conductive structures 2125, 5125, 7125, 14104, 15104, 16104, 27205, 28125, 29225, 29325, 328251, 328252, 328253, 328254, 33225: current limiting layer 2125A, 5125A, 7125A, 14104A, 27205A, 28125A, 29225A, 33225A: Current conduction area 2125B, 5125B, 7125B, 14104B, 27205B, 28125B, 29225B, 33225B:Current limiting regions 2200, 2200', 2200-1, 2200-2: light receiving structures 5500, 7700: conductive base layer 7100: light-emitting epitaxial layers 7100A, 15020A, 16020A, 20010A, 26033, 33204, 34103: active layers 7100L, 15020L, 16020L, 20010L, 26035, 34102: second-type semiconductor layer 7100M1 , 7100M2, 7200M: high platform structure 7100R: ring electrode structure 7100U, 15020U, 16020U, 20010U, 26031, 34101: first type semiconductor layer 7200: light receiving layer 7409: electrode structure 7409E: extended electrode 7901A, 7902A, 20031, 29082A, 29082B, 29084A, 29084B, 32825A1, 32825A2, 32825A3, 32825A4, 33082A, 33082B: Opening 9000: VCSEL wafer 9000F: Front side 9100: Epitaxial layer 9200: Thinned wafer layer 9300: Bottom metal layer 9900, 10900, 12900: Ablation laser or cutting machine 10000, 11000A, 11000B, 11000C, 11000D, 12000, 19001: Epitaxial wafer 10010, 12010, 13010, 14010, 19100, 20040, 30010, 31010, 32010, 34040: base layer 10011: processing area 10012: rupture point 10013, 12013: cutting road 10020, 12020, 19020, 20010, 33200, 34010: semiconductor stack layer 10030, 12030: metal layer 11011A, 11011B, 11011C, 11011D: first processing area 11011A', 11011B', 11011C', 11011D': second processing area 11012A, 11012B, 11012C, 11012D: first rupture point 11012A', 11012B', 11012C', 11012D': second rupture point 13000, 14000, 15000, 16000, 20000: VCSEL chip 13020, 14020, 15020, 16020, 27020, 29020, 29030, 31720, 31730: epitaxial structure 13020A, 14020A: active area 13020L, 14020L: lower reflector 13020U, 14020U: upper reflector 13040, 27702: first electrode 13050, 27704: second electrode14030, 14050, 15030, 15050, 16030, 16050: electrode 13011: rupture point 15100, 16100, 33900: growth substrate 13030, 14040, 15040, 16040, 16060, 7901, 7902, 20030, 26036, 26340, 29090, 29082, 29084, 30090, 31090, 31782, 32090, 33082, 33090, 34030: Insulating layer 19000: Semiconductor laser chip 19001B: Back surface 19000B: Bottom surface 19000S: Step structure 19030: Upper electrode 19040: Lower electrode 20020, 28132: First electrode structure 20041: Bottom 20042: Mesa portion 20042A: Mesa surface 20042B: Mesa side surface 20041A: Bottom first surface 20041B: Bottom second surface 20041 C: bottom side 20012A, 20012B, 34102A, 34102B: platform portion 20050, 28134: second electrode structure 20011, 28110A: first surface 20012, 28110B: second surface 20013, 34013, 34042, E13, E14: side 21000: optoelectronic module 21010, 22010, 23010: driver chip 21011: lens group 21020, 22020, 23020, 24000A, 24000B, 24000C, 25000A, 25000B, 25000C, 25000D, 25000E: light emitting device 21030: SPAD 21040, 22040: BGA structure 22000, 23000: Transmitter module 22030, 23030: Passive component 23050: Metal wire 23060: Molding material 24010, 25010, 33202, 33206: Semiconductor layer 24020: Spacer layer 24031, 25031: First pattern layer 24040, 25040: Cover layer 24032, 25032: Second pattern layer 24033: Third pattern layer 25021: First transparent Base layer 25022: second transparent base layer 25030: pattern layer 25023: third transparent base layer 26000, 27000: laser element 26003: laser unit 26034: first channel 26010, 29421, 29422, 30421: conductive layer 26003S: light-emitting side 26030: positive conductive structure 26032: back conductive structure 26320: second channel 26032A, 26032B: detection electrodes 26032C, 26032D: conductive electrodes27032: First insulating layer 27034: First metal connection layer 27050: Second metal connection layer 27060: Second insulating layer 27060A: Side 27080: Third insulating layer 27101: Anti-reflective structure 27202, 28121, 30222: First semiconductor structure 27204, 28126: Active structure 27206, 28122: Second semiconductor structure 27206A: End surface 27322: First opening 27341a: First protrusion 27341b: Second protrusion 27342: Second opening 27344A, 27344B, 27344C, 27344D: marking structure 27602a: first opening 27602b: second opening 27602c: third opening 27602d: fourth opening 27603: fifth opening 27802: first hole 27804: second hole 27902: first pad structure 27904: second pad structure 27902A, 27904A, 29502, 29602, 29702, 29802, 30502A, 30702A: intermediate layer 2790 2B, 27904B, 29504, 29604, 29704, 29804, 30504A, 30704A: bonding layer 28000, 29000, 30000, 31000, 32000, 33000, 34000: semiconductor light emitting element 28110: substrate 28120: epitaxial stack 28123: intermediate layer 28124: third semiconductor structure 28127: fourth semiconductor structure 28132A: first portion 28132B: second portion 28140, 32840, 32850 A, 32850B, 32850C, 32850D, 33104: recessed structure 28160: optical element 29010, 33100: substrate 29020A, 29030A, 34011: surface 29040, 30040, 31040, 32040, 33040: metal connection layer 29040A, 33040A: connection layer opening 29050, 29060, 29070, 29080, 30050A, 30050B, 30060A, 30060B, 30070A, 30070B, 30080A, 30080B, 31750, 31760, 31770, 31780, 33105, 33106, 34020, 34050: Electrode structure 29090A, 29090B, 33090A, 34032: Insulation layer opening 29040B, 30040B: Spacer 29201, 29301, U33: Through hole 29220, 29320, 33220: Contact structure 29222, 29322: Semiconductor structure29224, 29324: active area 29226, 29326, 30226, 31726, 31736, 32826: platform structure 29420, 29520, 30420, 31242, 31342, 33420: electrode connection layer 29821: side 29822: upper part 29901: adhesive layer 30000A, 30000B, 30000C, 3 0000D: luminous area 30040a, 30040b: parts 31010A, 31010B: sides 31720B, 34041: surface 32825A: luminous holes 510, 511, 512, 520, 521, 522, 523, 524, 525, 526: patterns 620, 621, 622, 623, 624, 625, 626, 627: pattern structure A : Plane size C: Arrow C271: First boundary C272: Second boundary D10, D12: Cutting depth D019: Depth D271: First distance D272: Second distance G010, G012: Crack G019: Groove G27: Spacing G271: First spacing G272: Second spacing G273: Third spacing G274: Fourth spacing L1, L2: Line L019: Width L26: Laser Light ray LD: length direction Lf: focused light Lg: interference light Lo, Lo1, Lo2, Lo': coherent light Lr, Lr1, Lr2: reflected light O27: center position O14: light outlet P27,: columnar structure P272, PB33: side surface P291, P292, P293, P294, P30, P3011, P3012, P3013, P3014, P3015, P3016, P3021, P3022, P3023, P3024, P3031, P3032, P311, P312, P33: epitaxial columnar structure 28150, PL: protective layer S271: first side S272: second side W10, W12: cutting width W291, W292, W311, W312: width WD: width direction θ, θ': angle DETAILED DESCRIPTION

[0104] The following text illustrates the concepts of the present application using exemplary embodiments with reference to the accompanying drawings. Similar or identical components are denoted by the same reference numerals in the drawings and description. Furthermore, the drawings are drawn to facilitate understanding, and the thicknesses and shapes of the layers shown in the drawings are not necessarily true to scale or actual dimensions of the components. It should be noted that components not shown in the drawings or described in the specification may be of a form known to those skilled in the art.

[0105] The following description of various embodiments of the present invention is provided in conjunction with the accompanying drawings. These descriptions are intended to facilitate a clear understanding and should be considered as exemplary. The phrases "in one embodiment" and the like in this specification are not limited to specific or identical embodiments. Those skilled in the art will appreciate that various changes, combinations, or adjustments may be made to the various embodiments of the present invention without departing from the scope and spirit of the present invention.

[0106] The terms "first", "second", "third", etc. used in this specification are used to identify and describe the features of each corresponding embodiment, and do not necessarily have any order, hierarchy or before and after meaning (for example, spatial position, time sequence, step sequence, etc.).

[0107] As used in this specification, terms such as "upper," "lower," "left," "right," "front," "back," "lower," "higher," "top," or "bottom" are used to describe the spatial distribution relationship of one element relative to another element (or one structure relative to another structure) in the drawings. It will be understood that if the structures depicted in the drawings are turned upside down, the elements described as being on the "lower," "beneath," or "lower" side will become elements on the "upper," "above," or "higher" side.

[0108] FIG1A is a cross-sectional diagram illustrating a packaging structure of a photoelectric unit 2 according to an embodiment. The photoelectric unit 2 can be used as a self-mixing interferometry (SMI) sensing unit.

[0109] FIG1B is a schematic cross-sectional view illustrating a packaging structure of a photovoltaic unit 2 according to an embodiment, wherein the photovoltaic unit 2 shown in FIG1A is adhered to a transparent substrate 1100 .

[0110] 1C is a cross-sectional view illustrating a package structure of a light-emitting sensor package 2C according to an embodiment, which includes a plurality of optoelectronic units 2 as shown in FIG. 1A adhered to a transparent substrate 1100 . The light-emitting sensor package 2C can be used as a self-mixing interference sensing device.

[0111] 1D is a schematic cross-sectional view illustrating a package structure of a light emitting sensor package 2D according to an embodiment, which includes a plurality of optoelectronic units 2 as shown in FIG. 1A adhered to a transparent substrate 1100 . The light emitting sensor package 2D can be used as a self-mixing interference sensing device.

[0112] According to the embodiment shown in FIG1A , the photovoltaic unit 2 includes a light-emitting structure and a light-receiving structure. The photovoltaic unit 2 is a stacked structure 2000 comprising a semiconductor epitaxial structure, a conductive structure, and an insulating structure. The stacked structure 2000 has an upper surface 2000T and a lower surface 2000B opposite to the upper surface 2000T. In the embodiment shown in FIG1A , the stacked structure 2000 of the photovoltaic unit 2 can be formed by epitaxial growth.

[0113] In the embodiment shown in FIG1A , the stacked structure 2000 includes an epitaxial light-emitting structure 2100, which corresponds to the light-emitting structure of the optoelectronic unit 2. In this embodiment, the epitaxial light-emitting structure 2100 may be a vertical cavity surface-emitting laser (VCSEL), which may be a stacked epitaxial structure including an upper distributed Bragg reflector (DBR) 2100U, a lower DBR 2100L, and an active structure 2100A located between the upper and lower DBRs 2100U and 2100L.

[0114] In the embodiment shown in FIG1A , the conductive structure 2100P contacts the upper DBR 2100U at its upper surface 2100UT. The conductive structure 2100P then extends to cover a portion of the lower surface 2000B through a via structure 2100V formed within the stacked structure 2000. In this embodiment, an insulating structure 2100VI is formed between the conductive structure 2100P and the stacked structure 2000. The insulating structure 2100VI serves to electrically insulate the conductive structure 2100P from the upper DBR 2100U, and the active structure 2100A from the lower DBR 2100L.

[0115] 1A , the upper DBR 2100U comprises a P-type semiconductor structure, and the lower DBR 2100L comprises an N-type semiconductor layer structure. In this embodiment, the conductive structure 2100P serves as a P-electrode of the epitaxial light-emitting structure 2100 .

[0116] 1A , the light receiving structure 2200 is integrally formed as part of the lower DBR 2100L of the light emitting epitaxial structure 2100 (e.g., VCSEL). In other words, in this embodiment, the lower DBR 2100L includes a DBR structure 2100L1, a light receiving structure 2200, and a DBR structure 2100L2 stacked in sequence.

[0117] In the embodiment shown in FIG1A , the conductive structure 2200N contacts the light receiving structure 2200 at the lower surface 2200B of the light receiving structure 2200. In one embodiment, the light receiving structure 2200 may be a photodiode, such as an avalanche photodiode (APD) or a PIN photodiode. In the embodiment shown in FIG1A , the conductive structure 2200N serves as the N-electrode of the light receiving structure 2200.

[0118] In the embodiment shown in FIG1A , the conductive structure 2400 contacts the DBR structure 2100L1 at the upper surface 2100LT of the lower DBR 2100L. The conductive structure 2400 then extends to cover a portion of the lower surface 2000B through a via structure 2000V formed within the stacked structure 2000. In the embodiment shown in FIG1A , an insulating structure 2000VI is located within the via structure 2000V and extends to cover a portion of the lower surface 2000B. The insulating structure serves to electrically insulate the conductive structure 2400 from the lower DBR 2100L. In the embodiment shown in FIG1A , the conductive structure 2400 contacts the N-type semiconductor DBR structure 2100L1, while the N-type semiconductor lower DBR 2100L is connected to the upper portion of the light receiving structure 2200. Therefore, the conductive structure 2400 serves as a common electrode for the epitaxial light emitting structure 2100 and the light receiving structure 2200. In this embodiment, the conductive structure 2400 is simultaneously the N-electrode of the light-emitting epitaxial structure 2100 and the P-electrode of the light-receiving structure 2200 .

[0119] In one embodiment, referring to FIG. 1A , the epitaxial light-emitting structure 2100 may further include a current confinement layer 2125 located between the upper DBR 2100U and the active structure 2100A. The current confinement layer 2125 includes a current confinement region 2125B and a current conduction region 2125A. The current conduction region 2125A is surrounded and defined by the current confinement region 2125B. The active structure 2100A may be a single-layer or multi-layer structure. For example, the active structure 2100A may include at least one quantum well layer. Furthermore, the active structure 2100A may include at least one current confinement layer and / or at least one tunnel junction structure.

[0120] In one embodiment, referring to Figures 1A and 1B , a transparent base layer 1100 may be adhered to the top surface 2000T via an adhesive layer 1200. The transparent base layer 1100 and the adhesive layer 1200 are transparent to light emitted from the active structure 2100A of the epitaxial light-emitting structure 2100. In this embodiment, electrode pads 2400e, 2200e, and 2100e are each formed on the bottom surface 2000B. The electrode pad 2400e contacts the conductive structure 2400 for bonding to the second corresponding pad 1320 of the carrier 1300 (as shown in Figure 1B ). The electrode pad 2200e contacts the conductive structure 2200N for bonding to the first corresponding pad 1310 of the carrier 1300. The electrode pad 2100e contacts the conductive structure 2100P for bonding to the third corresponding pad 1330 of the carrier 1300. In the embodiment shown in FIG. 1A , the photoelectric unit 2 is driven to emit coherent light Lo to a first object, and then the reflected light Lr from the first object can be detected by the light receiving structure 2200 of the photoelectric unit 2 .

[0121] In one or more embodiments, referring to FIG. 1B as an example, the optoelectronic unit 2 can be coupled to a controller via a carrier 1300. The optoelectronic unit 2's light-emitting structure and the optoelectronic unit 2's light-receiving structure can then be individually enabled by the controller via the conductive structure 2100P or 2200N corresponding to their respective structures (light-emitting structure or light-receiving structure). Alternatively, the optoelectronic unit 2's light-emitting structure and the optoelectronic unit 2's light-receiving structure can be jointly enabled by the controller via a common electrode (conductive structure 2400) shared by the emitter and light-receiving structures.

[0122] FIG1C illustrates the package structure of a light-sensing package 2C according to one embodiment. The package includes multiple optoelectronic units 2 (photoelectric unit 2-1 and photoelectric unit 2-2) as shown in FIG1A , bonded to a transparent substrate 1100. The light-sensing package 2C can function as a self-mixing interferometry sensing device. In one or more embodiments, the multiple optoelectronic units 2 of the light-sensing package 2C can be arranged in an array.

[0123] In the embodiment shown in FIG1C , each stacked structure of the optoelectronic unit 2-1 and the optoelectronic unit 2-2 has a structure identical or similar to that of the optoelectronic unit 2. In the embodiment shown in FIG1C , the conductive structure 2100P1 of the optoelectronic unit 2-1 can be connected to the conductive structure 2100P2 of the optoelectronic unit 2-2 via an interconnect structure (not shown in FIG1C ). In other words, in this embodiment, the conductive structures 2100P1 and 2100P2 can be connected to form a common electrode (conductive structure 2100P) that serves as the common electrode of the optoelectronic units 2-1 and 2-2. For example, in the embodiment shown in FIG1C , the common electrode (conductive structure 2100P) is the common P-electrode of the optoelectronic units of the light-emitting sensing package 2C.

[0124] In the embodiment shown in FIG1C , the electrode pad 2200e1 of the conductive structure 2200N1 can be connected to the electrode pad 2200e2 of the conductive structure 2200N2 via a common pad (first corresponding pad 1310) on the carrier 1300 (not shown in FIG1C ). In other words, in this embodiment, the common pad (first corresponding pad 1310) on the carrier 1300 can serve as a common N-electrode electrically connected to the light receiving structure of the light-emitting sensor package 2C. In the embodiment shown in FIG1C , the electrode pad 2200e3 of the conductive structure 2200N3 can also be connected to the electrode pads 2200e1 and 2200e2 via the common pad (first corresponding pad 1310) on the carrier 1300.

[0125] In the embodiment shown in FIG1C , the conductive structure 2401 of the photoelectric unit 2-1 is separated from the conductive structure 2402 of the photoelectric unit 2-2. In other words, in this embodiment, the conductive structure 2401 and the conductive structure 2402 are substantially electrically isolated from each other. Therefore, each of the photoelectric units 2-1 and 2-2 can be driven / controlled separately. In the embodiment shown in FIG1C , the photoelectric unit 2-1 is driven to emit coherent light Lo1 toward a first object, and the reflected light Lr1 from the first object can be detected by the light receiving structure of the photoelectric unit 2-1. The photoelectric unit 2-2 is driven to emit coherent light Lo2 toward a second object, and the reflected light Lr2 from the second object can be detected by the light receiving structure of the photoelectric unit 2-2.

[0126] Specifically, in some embodiments, since the laser light is reflected from the object, it contains implicit state information of the object (such as the distance relative to the photoelectric unit, rotation speed, movement speed, acceleration, etc.). Therefore, the aforementioned information can be obtained by comparing the phase changes between the light of different lasers and performing conversion calculations.

[0127] FIG1D illustrates the package structure of a light-emitting sensor package 2D according to one embodiment. The package includes a plurality of optoelectronic units 2 (e.g., optoelectronic units 2-1 and 2-2) as shown in FIG1A , bonded to a transparent substrate 1100. The light-emitting sensor package 2D can function as a self-mixing interferometry sensing device. The stacked structures of the optoelectronic units 2 in the embodiment shown in FIG1D have the same or similar structure as the stacked structures of the optoelectronic units 2 in the embodiment shown in FIG1A .

[0128] Referring to FIG. 1D and FIG. 1C , the structure of light-emitting sensor package 2D is similar to that of light-emitting sensor package 2C. Conductive structures 2100P1 and 2100P2 can be connected to form a common electrode (conductive structure 2100P), which serves as the common electrode (e.g., common P electrode) of the optoelectronic unit. Furthermore, conductive structures 2401 and 2402 are substantially electrically isolated from each other. Therefore, each optoelectronic unit shown in FIG. 1D can be driven / controlled independently.

[0129] Specifically, in the embodiment shown in FIG1D , conductive structure 2200N1 and conductive structure 2200N2 are each covered by an insulating structure, and conductive structure 2200N1 and conductive structure 2200N2 are connected to conductive structure 2200N3 via an interconnect structure (not shown in FIG1D ). Therefore, conductive structure 2200N3 can serve as a common conductive structure that connects electrode pads 2200e3, which serve as a common electrode and electrically connect each of the light receiving structures 2200. In other words, in the embodiment shown in FIG1D , electrode pads 2200e3 can serve as a common N-electrode electrically connected to the light receiving structures 2200 of the light emitting sensor package 2D.

[0130] 1D , in one or more embodiments, the transparent substrate 1100 may include an integrated optical element 1101. In one or more embodiments, the integrated optical element 1101 may include multiple optical elements (e.g., microlenses 1101A and 1101B), with microlens 1101A corresponding to a photoelectric unit 2-1 below microlens 1101A, and microlens 1101B corresponding to a photoelectric unit 2-2 below microlens 1101B. In one or more embodiments, the center position (or optical axis) of microlens 1101A is offset from the center position of the current-conducting region in the photoelectric unit 2-1 below it, and / or the center position (or optical axis) of microlens 1101B is offset from the center position of the current-conducting region in the photoelectric unit 2-2 below it, but the present application is not limited thereto.

[0131] In some embodiments, the staggered arrangement of the optical element and the current conducting region of each semiconductor laser (i.e., the light output port corresponding to the semiconductor laser) can cause a shift in the light emitted by the semiconductor laser, thereby changing the field of illumination (FOI) of the optoelectronic device.

[0132] FIG2A is a cross-sectional diagram illustrating a packaging structure of a photoelectric unit 2 ′ according to an embodiment. The photoelectric unit 2 ′ can be used as a self-mixing interferometry (SMI) sensing unit.

[0133] 2A and 1A , the optoelectronic unit 2 ′ has a similar structure to the optoelectronic unit 2 . In the embodiment shown in FIG. 2A , the optoelectronic unit 2 ′ includes a light-emitting epitaxial structure 2100 ′ and a light-receiving structure 2200 ′, wherein the light-receiving structure 2200 ′ is located below the light-emitting epitaxial structure 2100 ′.

[0134] Specifically, unlike the embodiment shown in FIG1A (in which the light receiving structure 2200 is integrally formed as part of the lower DBR 2100L of the epitaxial light emitting structure 2100), in the embodiment shown in FIG2A , the optoelectronic unit 2′ further includes an adhesive layer 2500 positioned between the epitaxial light emitting structure 2100′ and the light receiving structure 2200′, and the upper surface of the light receiving structure 2200′ is largely adhered to the lower surface of the epitaxial light emitting structure 2100′ via the adhesive layer 2500. The adhesive layer 2500 is transparent to the coherent light Lo′ emitted from the active structure 2100A′ of the epitaxial light emitting structure 2100′.

[0135] In the embodiment shown in FIG2A , the epitaxial light-emitting structure 2100′ may be a VCSEL, which may be a stacked epitaxial structure including an upper DBR 2100U′, a lower DBR 2100L′, and an active structure 2100A′ located between the upper and lower DBRs 2100U′, 2100L′. In the embodiment shown in FIG2A , the upper DBR 2100U′ comprises a P-type semiconductor structure, and the lower DBR 2100L′ comprises an N-type semiconductor layer structure. Furthermore, a conductive structure 2100P (as shown in FIG2A ) serves as a P-electrode for the epitaxial light-emitting structure 2100′.

[0136] In the embodiment shown in FIG2A , the subsequent layer 2500 is conductive, allowing the conductive structure (shown in FIG2A ) to be electrically conductive with the lower DBR 2100L' of the epitaxial light-emitting structure 2100' and the light-receiving structure 2200'. Therefore, the conductive structure 2400 serves as a common electrode for the epitaxial light-emitting structure 2100' and the light-receiving structure 2200'. In the embodiment shown in FIG2A , the conductive structure 2400 serves as both the N-electrode of the epitaxial light-emitting structure 2100' and the P-electrode of the light-receiving structure 2200'.

[0137] In the embodiment shown in FIG2A , the light receiving structure 2200′ further includes a DBR structure 2210′ and a conductive structure 2200N (as shown in FIG2A ) contacting the light receiving structure 2200′ on the lower surface of the light receiving structure 2200′. In one embodiment, the light receiving structure 2200′ may be a photodiode, such as an avalanche photodiode or a PIN photodiode. In the embodiment shown in FIG2A , the conductive structure 2200N serves as the N electrode of the light receiving structure 2200′. In the embodiment shown in FIG2A , the light receiving structure 2200′ may be formed by a wafer fusion process.

[0138] FIG2B is a schematic cross-sectional view of the package structure of a light-sensing package 2D′ according to one embodiment. The package includes multiple optoelectronic units 2′ (photoelectric unit 2-1′ and photoelectric unit 2-2′) as shown in FIG2A , adhered to a transparent substrate 1100. The light-sensing package 2D′ can function as a self-mixing interferometry sensing device. In one or more embodiments, the multiple optoelectronic units 2′ of the light-sensing package 2D′ can be arranged in an array.

[0139] In the embodiment shown in FIG2B , the conductive structure 2100P1 of the optoelectronic unit 2-1′ can be connected to the conductive structure 2100P2 of the optoelectronic unit 2-2′ via an interconnect structure (not shown in FIG2B ). In other words, in this embodiment, the conductive structures 2100P1 and 2100P2 can be connected to form a common electrode (conductive structure 2100P) (as shown in FIG2B ), which serves as the common electrode of the optoelectronic units 2-1′ and 2-2′. For example, in the embodiment shown in FIG2B , the common electrode is the common P-electrode of the optoelectronic units of the light-emitting sensing package 2D′.

[0140] In the embodiment shown in FIG2B , the conductive structure 2401 of the photovoltaic unit 2-1′ is separated from the conductive structure 2402 of the photovoltaic unit 2-2′. In other words, in this embodiment, the conductive structure 2401 and the conductive structure 2402 are substantially electrically isolated from each other. Therefore, each photovoltaic unit 2-1′ and 2-2′ can be driven / controlled separately.

[0141] In the embodiment shown in FIG2B , conductive structures 2200N1 and 2200N2 can be connected to conductive structure 2200N3 via an internal interconnect structure (not shown in FIG2B ). Therefore, conductive structure 2200N3 can serve as a common conductive structure, connecting electrode pads 2200e3 that serve as a common electrode and electrically connect each of the light receiving structures 2200′. In other words, in the embodiment shown in FIG2B , electrode pads 2200e3 can serve as a common N-electrode electrically connected to the light receiving structures 2200′ of the light emitting sensor package 2D′.

[0142] Figure 3A is a schematic cross-sectional view of the packaging structure of an optoelectronic device 3A according to one embodiment. Referring to Figure 3A as an example, in one or more embodiments, optoelectronic device 3A further includes a housing 1400 covering a light-sensing package 2D'. It should be noted that light-sensing package 2D' can be replaced with any of the aforementioned light-sensing packages, but the present application is not limited thereto.

[0143] In one or more embodiments, taking the embodiment shown in FIG. 3A as an example, the housing 1400 may include multiple optical elements 1401A and 1401B. In one or more embodiments, taking the embodiment shown in FIG. 3A as an example, the optical elements 1401A and 1401B may have the same or different optical functions. In one embodiment, the optical elements 1401A and 1401B may be used to project light. In another embodiment, the optical elements 1401A and 1401B may be used to focus light. In other embodiments, the optical element 1401A may be used to project light, while the optical element 1401B may be used to focus light. In one embodiment, the optical elements 1401A and 1401B may be used to project light or focus light in different directions, or the optical elements 1401A and 1401B may be used to project light at different angles, thereby expanding the field of view of the optoelectronic device 3A.

[0144] In some embodiments, a space between the housing 1400 and the transparent substrate 1100 can be filled with normal air, an inert gas, nitrogen, or maintained in a vacuum, thereby providing media environments with varying refractive indices. In other embodiments, an optical element with a concave lens structure can be formed on the transparent substrate 1100 and then covered by the housing 1400, similarly providing focusing and / or collimating functions.

[0145] In some embodiments, such as the embodiment shown in FIG. 1D or FIG. 3A to FIG. 3C , the optical element may include a diffraction optical element (DOE) structure, a microlens array structure, a metasurface structure, a metalens structure, or a combination of the aforementioned optical element structures. The metasurface structure is a nanostructure having multiple periodic arrangements.

[0146] In one or more embodiments, taking the embodiment shown in FIG. 3A as an example, the carrier 1300 may be a ceramic substrate, a printed circuit board, etc.

[0147] FIG3B is a schematic cross-sectional view illustrating a package structure of an optoelectronic device 3B according to an embodiment. The optoelectronic device 3B can be used as a self-mixing interferometry sensing device with a baseline signal or a reference signal.

[0148] In the embodiment shown in FIG3B , conductive structure 2100P1 completely covers the upper surface of the left epitaxial light-emitting structure 2100-1, while conductive structure 2100P2 does not completely cover the upper surface of the right epitaxial light-emitting structure 2100-2. As a result, the right epitaxial light-emitting structure 2100-2 can emit light normally. Therefore, light emitted from the active structure of the left epitaxial light-emitting structure 2100-1 is blocked and reflected downward by conductive structure 2100P1. Therefore, the signal output by the left light-receiving structure 2200-1 can serve as a baseline / reference signal for the signal output by the right light-receiving structure 2200-2 for self-mixing interferometry sensing.

[0149] FIG3C is a schematic cross-sectional view illustrating the packaging structure of an optoelectronic device 3C according to one embodiment. The optoelectronic device 3C can function as a self-mixing interferometry sensing device. According to the embodiment shown in FIG3C , the optoelectronic device 3C includes a plurality of optoelectronic cells arranged in an array, wherein the light emitting structure of one or more optoelectronic cells may differ from the light emitting structure of the other optoelectronic cells.

[0150] In one or more embodiments, by arranging multiple optoelectronic units in an array, the optoelectronic device can provide a two-dimensionally distributed laser beam. When this two-dimensionally distributed laser beam strikes an object, the laser beams emitted by each optoelectronic unit, after reflection from the object, carry information about the distance between the object and the optoelectronic device, as well as the object's motion state. Furthermore, because the optoelectronic device strikes the object with a two-dimensionally distributed laser beam, each laser beam can strike different locations on the object, resulting in more accurate distance and motion state information, or the object's three-dimensional contour information.

[0151] 3C and 3B , the right epitaxial light emitting structure 2100 - 2 ′ shown in FIG. 3C has the same or similar structure as the right epitaxial light emitting structure 2100 - 2 shown in FIG. 3B . In the embodiment shown in FIG. 3C , the right epitaxial light emitting structure 2100 - 2 ′ includes a VCSEL structure.

[0152] Specifically, in the embodiment shown in FIG. 3C , the left epitaxial structure 2100 - 1 ′ may be different from the right epitaxial structure 2100 - 2 ′; in other words, in this embodiment, the left epitaxial structure 2100 ′ may include an LED structure or a resonant cavity light emitting diode (RCLED) structure.

[0153] In one or more embodiments, the electrode structures of the light-emitting structure and / or the electrode structures of the light-receiving structure of the aforementioned optoelectronic device (e.g., a self-mixing interferometry sensing device) can be jointly constructed as one or more common electrodes for being jointly driven / controlled (e.g., in a jointly driven / controlled mode). When the optoelectronic device (e.g., a self-mixing interferometry sensing device) is enabled in the jointly driven / controlled mode, activation signals used to enable different units of the optoelectronic device can be ignored.

[0154] Please refer to FIG. 4A to FIG. 4D , which are top views illustrating a packaging structure of an optoelectronic device according to some embodiments.

[0155] As shown in FIG4A , in some embodiments, an optoelectronic device 4A includes an array of 32 SMI sensing units 4 - 1 . Each SMI sensing unit 4 - 1 includes a light-emitting structure, for example, a VCSEL semiconductor laser. The spacing between the SMI sensing units 4 - 1 is 133 microns. The VCSEL semiconductor laser emits light at a wavelength of, for example, 940 nanometers. The aperture of the light-emitting port of the VCSEL semiconductor laser is 8 to 10 microns.

[0156] As shown in FIG. 4B , in some embodiments, the optoelectronic device 4B includes 32 SMI sensing units 4 - 2 forming an array, and the spacing between the SMI sensing units 4 - 2 is 166 micrometers.

[0157] As shown in FIG. 4C , in some embodiments, the optoelectronic device 4C includes 32 SMI sensing units 4 - 3 forming an array, and the spacing between the SMI sensing units 4 - 3 is 186 micrometers.

[0158] As shown in FIG. 4D , in some embodiments, the optoelectronic device 4D includes 32 SMI sensing units 4 - 4 forming an array, and the spacing between the SMI sensing units 4 - 4 is 300 microns.

[0159] As shown in Figures 4A to 4D, in some embodiments, the optoelectronic devices 4A, 4B, 4C, and 4D include multiple SMI sensing units 4-1, 4-2, 4-3, and 4-4 to form an array. The SMI sensing units 4-1, 4-2, 4-3, and 4-4 have light-emitting structures (for example, VCSEL semiconductor lasers), wherein the upper electrodes (for example, VCSEL-) of the VCSEL semiconductor lasers of each SMI sensing unit 4-1, 4-2, 4-3, and 4-4 are extended to external electrodes (represented by squares) through conductive wiring, and the lower electrodes (for example, VCSEL+) of the VCSEL semiconductor lasers are connected in common. Thus, the SMI sensing units of the optoelectronic devices 4A, 4B, 4C, and 4D can be addressably controlled or partitioned through the external electrodes.

[0160] FIG5 is a cross-sectional view of a package structure of an optoelectronic device according to an embodiment. Referring to FIG5 , in this embodiment, the optoelectronic unit 5 is a SMI sensor chip with a vertical chip structure.

[0161] The optoelectronic unit 5 includes a light emitting structure, a light receiving structure 5200 and a conductive base layer 5500 , and the optoelectronic unit 5 is a stacked structure 5000 including a semiconductor epitaxial structure and a conductive structure.

[0162] In this embodiment, a light-emitting epitaxial structure 5100 (corresponding to the light-emitting structure of the optoelectronic unit 5) is disposed on a conductive substrate 5500. The stacked structure includes the light-emitting epitaxial structure 5100, which corresponds to the light-emitting structure of the optoelectronic unit 5. In this embodiment, the light-emitting epitaxial structure 5100 can be a vertical cavity surface-emitting laser, which can be a stacked epitaxial structure including an upper DBR 5100U, a lower DBR 5100L, and an active structure 5100A located between the upper and lower DBRs 5100U and 5100L.

[0163] In the embodiment shown in FIG. 5 , the conductive structure 5100P contacts the upper DBR 5100U at the upper surface 5100UT of the upper DBR 5100U.

[0164] 5 , the light receiving structure 5200 is integrally formed as part of the lower DBR 5100L of the light emitting epitaxial structure 5100 (e.g., VCSEL). In other words, in this embodiment, the lower DBR 5100L includes a DBR structure 5100L1, a light receiving structure 5200, and a DBR structure 5100L2 stacked in sequence.

[0165] 5 , the upper DBR 5100U comprises a P-type semiconductor structure, and the lower DBR 5100L comprises an N-type semiconductor layer structure. In this embodiment, the conductive structure 5100P serves as a P-electrode of the epitaxial light-emitting structure 5100 .

[0166] In the embodiment shown in FIG5 , the conductive structure 5200N is located on a side of the conductive base layer 5500 opposite the light receiving structure 5200 and is electrically connected to the light receiving structure 5200 via the conductive base layer 5500. In one embodiment, the light receiving structure 5200 may be a photodiode, such as an avalanche photodiode or a PIN photodiode. In the embodiment shown in FIG5 , the conductive structure 5200N serves as the N electrode of the light receiving structure 5200.

[0167] In the embodiment shown in FIG5 , the conductive structure 5400 is connected to the upper portion of the light receiving structure 5200 and is electrically connected to the lower DBR 5100L through the light receiving structure 5200. Therefore, the conductive structure 5400 serves as a common electrode for the epitaxial light emitting structure 5100 and the light receiving structure 5200. In this embodiment, the conductive structure 5400 serves as both the N-electrode of the epitaxial light emitting structure 5100 and the P-electrode of the light receiving structure 5200.

[0168] In one embodiment, referring to FIG. 5 , the epitaxial light-emitting structure 5100 may further include a current confinement layer 5125 located between the upper DBR 5100U and the active structure 5100A. The current confinement layer 5125 includes a current confinement region 5125B and a current conduction region 5125A. The current conduction region 5125A is surrounded and defined by the current confinement region 5125B. The active structure 5100A may be a single-layer or multi-layer structure. For example, the active structure 5100A may include at least one quantum well layer. Furthermore, the active structure 5100A may include at least one current confinement layer and / or at least one tunneling junction structure.

[0169] In one embodiment, please refer to FIG. 6 , which is a schematic diagram illustrating an application of a packaging structure for an optoelectronic device according to one embodiment. In this embodiment, the structure of optoelectronic device 6 is similar to that of optoelectronic device 5 , with the primary difference being that, in this embodiment, the conductive structure 6400 is located on one side of the epitaxial light-emitting structure 6100 , as viewed in cross-section. In the embodiment shown in FIG. 5 , the conductive structure 5400 is located on both sides of the epitaxial light-emitting structure 5100 . In some embodiments, the conductive structure 5400 is ring-shaped. Furthermore, in the embodiment shown in FIG. 6 , the epitaxial light-emitting structure 6100 (corresponding to the light-emitting structure of optoelectronic unit 6 ) and the light-receiving structure 6200 are sequentially disposed on a conductive base layer 6500 . In this embodiment, the epitaxial light-emitting structure 6100 (corresponding to the light-emitting structure of optoelectronic unit 6 ) and the light-receiving structure 6200 are sequentially disposed on a conductive base layer 6500 . In this embodiment, the epitaxial light-emitting structure 6100 can be a vertical cavity surface-emitting laser (VCSEL), which can be a stacked epitaxial structure comprising an upper DBR 6100U, a lower DBR 6100L, and an active structure 6100A located between the upper and lower DBRs 6100U and 6100L. In the embodiment shown in FIG6 , a conductive structure 6100P is located on the upper surface 6100UT of the upper DBR 6100U and is electrically connected to the upper DBR 6100U. In the embodiment shown in FIG6 , the upper DBR 6100U comprises a P-type semiconductor structure, and the lower DBR 6100L comprises an N-type semiconductor layer structure. In this embodiment, the conductive structure 6100P serves as the P-electrode of the epitaxial light-emitting structure 6100. In the embodiment shown in FIG6 , a conductive structure 6200N is located on the side of the conductive base layer 6500 opposite the light receiving structure 6200 and is electrically connected to the light receiving structure 6200 through the conductive base layer 6500. In one embodiment, the light receiving structure 6200 may be a photodiode, such as an avalanche photodiode or a PIN photodiode. In the embodiment shown in FIG6 , the conductive structure 6200N serves as the N-electrode of the light receiving structure 6200. In the embodiment shown in FIG6 , the conductive structure 6400 is connected to the upper portion of the light receiving structure 6200 and electrically connected to the lower DBR 6100L through the light receiving structure 6200. Therefore, the conductive structure 6400 serves as a common electrode for the epitaxial light emitting structure 6100 and the light receiving structure 6200. In this embodiment, the conductive structure 6400 serves as both the N-electrode of the epitaxial light emitting structure 6100 and the P-electrode of the light receiving structure 6200.

[0170] FIG6 is a schematic diagram illustrating the packaging structure of an optoelectronic device for eye tracking according to some embodiments. The optoelectronic device 6 is an SMI sensing device, including at least one SMI sensing unit, which can be mounted, for example, on a head-mounted display. The optoelectronic device 6 can be used in conjunction with a micro-optical device (e.g., a microlens) for eye tracking. A light-emitting device (e.g., a VCSEL) in the SMI sensing unit emits coherent light Lo, which is focused and projected by the microlens into focused light Lf. The focused light Lf is then projected onto the eye and reflected by the eye. The reflected light Lr returns to the resonant cavity within the VCSEL in the SMI sensing unit and generates interference light Lg. A receiving device (e.g., an APD or PIN) in the SMI sensing unit detects changes in the interference light Lg and outputs the output. After calculation, the rotational (movement) offset or velocity of the measured eye can be determined.

[0171] According to one embodiment, an SMI sensing device for eye tracking includes a plurality of SMI sensing units distributed in an array, wherein the accompanying micro-optical device may be a micro-lens array, and each micro-lens calibrates the light outlet of the VCSEL of each SMI sensing unit to generate a large field of view (FOV) projected sensing light, for example, a projected sensing light with a FOV of 60*45, but the present application is not limited thereto.

[0172] According to one embodiment, the light transmission distance of the SMI sensing device for eye tracking is generally between 25 and 30 mm, and the spot size of the projected sensing light is generally no greater than 200 μm, but the present application is not limited thereto.

[0173] It is worth noting that the SMI sensing device shown in one or more embodiments of the present application can also be used to detect rotation (movement) offset or speed information of other types of objects (such as body movements, car movement, etc.).

[0174] 7A to 7K are schematic cross-sectional views illustrating multiple steps of a process for manufacturing a package structure of an optoelectronic device according to an embodiment.

[0175] As shown in FIG7A , an epitaxial wafer is provided. The epitaxial wafer includes a light receiving layer 7200 and a light emitting layer (epi-light emitting layer 7100) formed on a conductive base layer 7700. The epitaxial light emitting layer 7100 is located on the light receiving layer 7200. The epitaxial light emitting layer 7100 includes a first-type semiconductor layer 7100U, a second-type semiconductor layer 7100L, and an active layer 7100A located between the first-type semiconductor layer 7100U and the second-type semiconductor layer 7100L.

[0176] The first-type semiconductor layer 7100U and / or the second-type semiconductor layer 7100L can be a multi-layer structure. In this embodiment, the first-type semiconductor layer 7100U is a P-type semiconductor layer, and the second-type semiconductor layer 7100L is an N-type semiconductor layer. The light receiving structure 7200 and the light emitting structure (epi-structure 7100) can be grown on the conductive base layer 7700 using epitaxial deposition methods, including but not limited to metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, etc. The light receiving structure 7200 can be an avalanche photodiode or a PIN photodiode. The conductive base layer 7700 includes but is not limited to a Group III-V material, whose lattice constant matches that of the semiconductor stack layer 10. In this embodiment, the conductive base layer 7700 is made of gallium arsenide (GaAs). In other embodiments, the conductive base layer 7700 can be made of indium phosphide (InP), sapphire, gallium nitride (GaN), or silicon carbide (SiC).

[0177] 7A , a ring-shaped electrode structure 7100R is formed on the first-type semiconductor layer 7100U of the epitaxial chip, wherein the ring-shaped electrode structure 7100R is electrically connected to the first-type semiconductor layer 7100U. The material of the ring-shaped electrode structure 7100R can be a conductive metal.

[0178] Next, referring to FIG. 7B , a protection layer PL is formed to cover the first-type semiconductor layer 7100U of the epitaxial chip. The material of the protection layer PL may be an insulating material, including but not limited to silicon nitride.

[0179] 7C , an etching process is performed on the semiconductor stacking layer of the epitaxial chip, and a mask with a specific pattern is used to etch away part of the first-type semiconductor layer 7100U, part of the active layer 7100A and part of the second-type semiconductor layer 7100L and expose the second-type semiconductor layer 7100L, thereby forming a mesa structure 7100M1.

[0180] Next, as also shown in FIG7C , a current confining layer 7125 is formed in the epitaxial light-emitting layer 7100. In this embodiment, the current confining layer 7125 can be formed by oxidizing the material in the region designated to form the current confining region 7125B through an oxidation process. For example, the aluminum content of at least one layer of the first-type semiconductor layer 7100U (defined as the layer designated to form the current confining layer 7125) is greater than 97% and greater than the aluminum content of the active layer 7100A and the second-type semiconductor layer 7100L. Therefore, during the oxidation process, the high-aluminum-content layer region (defined as the layer designated to form the current confining layer 7125) in the epitaxial light-emitting layer 7100 is oxidized inward at a higher rate than other regions, thereby forming the current confining region 7125B having low conductivity in the current confining layer 7125. Alternatively, a low-conductivity current confinement region 7125B can be formed in the epitaxial light-emitting layer 7100 by an ion implantation process, and the current conduction region 7125A can be defined by a mask. Ion implantation can be performed by implanting hydrogen ions (H ions) in the region where the current confinement region 7125B is to be formed. + ), helium ions (He + ) or argon ions (Ar + ) etc., the ion concentration of the current limiting region 7125B is much greater than that of the current conducting region 7125A, so that the current limiting region 7125B has a lower conductivity.

[0181] 7D , an etching process is again performed on the light-emitting epitaxial layer 7100 of the epitaxial chip, and a mask with a specific pattern is used to etch away a portion of the second-type semiconductor layer 7100L and expose the light receiving layer 7200 , thereby forming a mesa structure 7100M2 .

[0182] 7E , an electrode structure 7409 is formed on the light receiving layer 7200 of the epitaxial chip, wherein the electrode structure 7409 is electrically connected to the light receiving layer 7200 and is also electrically connected to the second-type semiconductor layer 7100L through the light receiving layer 7200. The material of the electrode structure 7409 can be a conductive metal.

[0183] Next, as shown in FIG7F , an etching process is performed on the light receiving layer 7200 of the epitaxial chip, and a mask with a specific pattern is used to etch away a portion of the light receiving layer 7200 and expose the conductive base layer 7700 , thereby forming a mesa structure 7200M.

[0184] 7G , an insulating layer 7901 is formed to cover the epitaxial light emitting layer 7100 , the light receiving layer 7200 , and the conductive base layer 7700 . An opening 7901A is further formed in the insulating layer 7901 to expose a portion of the electrode structure 7409 .

[0185] Next, referring to Figure 7H, an extended electrode 7409E is formed in the opening 7901A and extended to the light receiving layer 7200 and the conductive base layer 7700 of the epitaxial chip, so that the electrode structure 7409 is electrically connected to the light receiving layer 7200 and the extended electrode 7409E is electrically connected to the second-type semiconductor layer 7100L through the light receiving layer 7200, and the distribution range of the extended electrode 7409E is increased.

[0186] 7I , an insulating layer 7902 is formed again to cover the epitaxial light-emitting layer 7100, the light-receiving layer 7200, and the conductive base layer 7700. An opening 7902A is further formed in the insulating layer 7902 to expose the annular electrode structure 7100R of the first-type semiconductor layer 7100U in the epitaxial light-emitting layer 7100 and a portion of the extended electrode 7409E on the conductive base layer 7700.

[0187] Next, as shown in FIG7J , a ring-shaped electrode structure 7100R is formed that is electrically connected to the first-type semiconductor layer 7100U of the epitaxial light-emitting layer 7100 and extends onto the insulating layer 7902 located on the light-receiving layer 7200 and the conductive base layer 7700. Furthermore, an opening 7902A is formed in the conductive base layer 7700 for the conductive structure 7400. In this embodiment, the conductive structure 7400 is electrically connected to the light-receiving structure 7200 via the electrode structure 7409 and the extended electrode 7409E, and is also electrically connected to the second-type semiconductor layer 7100L via the light-receiving structure 7200. Therefore, the conductive structure 7400 serves as a common electrode for the epitaxial light-emitting structure 7100 and the light-receiving structure 7200. In this embodiment, the conductive structure 7400 serves as both the N-electrode of the epitaxial light-emitting structure 7100 and the P-electrode of the light-receiving structure 7200.

[0188] 7K , a conductive structure 7200N is formed on the other side of the conductive base layer 7700 relative to the epitaxial light emitting layer 7100. The conductive structure 7200N is electrically connected to the light receiving layer 7200 via the conductive base layer 7700.

[0189] Typically, a single epitaxial wafer is singulated to produce multiple vertical cavity surface emitting laser (VCSEL) chips.

[0190] Figure 8A is a top-down image of a portion of a VCSEL wafer, taken using an optical microscope. Figure 8B is a top-down image of a portion of a VCSEL wafer, taken using an optical microscope. The magnification of the image in Figure 8B is greater than that in Figure 8A. Referring to Figure 8A, the VCSEL wafer includes 48 VCSEL units arrayed on a GaAs wafer.

[0191] Figures 9A and 9B illustrate a conventional VCSEL die singulation process performed from the front side 9000F of a thinned VCSEL wafer 9000 using an ablation laser or saw 9900. This singulation process requires maintaining scribe lines approximately 30 to 40 microns wide in the VCSEL wafer 9000. It should be noted that by reducing the scribe line size, the number of chips (dies) singulated from the VCSEL wafer 9000 can be increased, thereby reducing overall production costs.

[0192] The VCSEL wafer 9000 includes a bottom metal layer 9300 , a thinned wafer layer 9200 on the bottom metal layer 9300 , and an epitaxial layer 9100 on the thinned wafer layer 9200 .

[0193] Figures 10A to 10C are schematic diagrams illustrating a singulation process for singulating a thinned VCSEL wafer to produce a plurality of die according to one embodiment. According to the method illustrated in Figures 10A to 10C , the width of the dicing street can be reduced to 20 microns or less. In this embodiment, a singulation process for an epitaxial wafer 10000 is provided, wherein the epitaxial wafer 10000 includes a semiconductor stack 10020 (e.g., a VCSEL stack), a base layer 10010, and a metal layer 10030. The base layer 10010 is positioned between the semiconductor stack 10020 and the metal layer 10030. The base layer 10010 may be a growth wafer layer of the semiconductor stack 10020 (e.g., a growth wafer of the VCSEL stack). Generally, to facilitate efficient singulation, the base layer 10010 may be a thinned growth wafer layer. In addition, the base layer 10010 can be made of glass (such as silicon-based glass or sapphire glass) or a III-V compound. In some embodiments, the III-V compound is GaAs, InP, or GaSb.

[0194] In this embodiment, the singulation process method includes a processing step, a cutting step, and a cleaving step. Each step is described below.

[0195] Processing steps: Referring to FIG. 10A , a stealth dicing process is used to process a portion of the interior of the base layer 10010 from the upper surface 10000T of the epitaxial wafer 10000 (e.g., a VCSEL epitaxial wafer), thereby forming a processing area 10011 in the portion of the interior of the base layer 10010. The processing area 10011 includes at least one row of breakage points 10012, and the extension direction of the at least one row of breakage points 10012 is substantially parallel to the extension direction of the lower surface 10000B of the epitaxial wafer 10000. The distance between the processing area 10011 and the upper surface 10000T of the epitaxial wafer 10000 is generally no more than 60 microns. In other words, in this embodiment, a stealth dicing process is used to process an area within a depth of 60 microns from the top surface 10000T of the epitaxial wafer 10000, causing a change in the crystal phase of the processed area 10011 within the base layer 10010, thereby generating a fracture point 10012 (or a structural weakening point). In some embodiments, the stealth dicing process is achieved using a laser having a wavelength of 1064 nanometers. In some embodiments, the top surface 10000T of the epitaxial wafer 10000 is flat. It should be noted that the location of the fracture point 10012 must avoid the semiconductor stack layer 10020 of the epitaxial wafer to avoid affecting the performance of the semiconductor laser.

[0196] Cutting step: Referring to FIG. 10B , laser lift-off technology or wheel cutting technology (e.g., using an ablation laser or cutting machine 10900) is used to cut the metal layer 10030 and another portion of the base layer 10010 from the lower surface 10000B of the epitaxial wafer 10000, thereby forming a cutting street 10013 (cutting groove) in the other portion of the metal layer 10030 and the base layer 10010. The cutting street 10013 has a cutting width W10 and a cutting depth D10, wherein the cutting width W10 is less than 20 microns and the cutting depth D10 is 30 microns, but the present application is not limited thereto.

[0197] Splitting step: Referring to FIG. 10C , a cleaving technique is used on the scribe line 10013 to split the epitaxial wafer into multiple dies (chips). In this embodiment, a cleaving force (e.g., using a cleaving jig, as indicated by the arrows in the figure) is applied to each groove (scribe line 10013) to form a crack G010 extending from the top of each groove to the top surface 10000T of the epitaxial wafer 10000, thereby splitting the epitaxial wafer 10000 into multiple VCSEL dies (chips). In this embodiment, the jig can be fixed to a specific location on the epitaxial wafer 10000 and an external force can be applied to split the epitaxial wafer 10000 into multiple semiconductor lasers.

[0198] According to the singulation method of this embodiment, for the epitaxial wafer 10000 of the same size, a narrower width of the dicing street 10013 can be obtained, and more semiconductor lasers can be cut out, thereby reducing the overall production cost.

[0199] In some embodiments, during the aforementioned step of forming the processing areas 10011, a plurality of first processing areas are formed on the base layer 10010 along the length direction of the epitaxial wafer 10000 in a top view, and a plurality of second processing areas are formed along the width direction of the epitaxial wafer 10000 in a top view. Each first processing area includes at least one row of first rupture points, and each second processing area includes at least one row of second rupture points. Furthermore, the at least one row of first rupture points extends in a direction substantially parallel to the length direction of the epitaxial wafer 10000 in a top view, while the at least one row of second rupture points extends in a direction substantially parallel to the width direction of the epitaxial wafer 10000 in a top view. That is to say, in this embodiment, the invisible cutting processing technology can be used to process multiple parts of the epitaxial wafer 10000 (simultaneously or in batches), and multiple processing areas 10011 are formed in the length direction and the width direction respectively, and each processing area 10011 includes at least one row of rupture points 10012. Furthermore, according to the thickness of the base layer 10010, multiple rows of rupture points 10012 can be formed in the same processing area. For example, when the thickness of the base layer 10010 increases, the number of rows of rupture points 10012 can be further increased to more effectively control the direction in which the crack G010 extends.

[0200] 11A to 11D are schematic perspective views illustrating processing steps of a method for singulating an epitaxial wafer according to some embodiments.

[0201] As shown in Figure 11A, in this embodiment, each first processing area 11011A of the epitaxial wafer 11000A includes a row of first rupture points 11012A, and each second processing area 11011A' includes a row of second rupture points 11012A'. The extension direction of the row of first rupture points 11012A is substantially parallel to the length direction LD of the top view of the epitaxial wafer 11000A, and the extension direction of the row of second rupture points 11012A' is substantially parallel to the width direction WD of the top view of the epitaxial wafer 11000A.

[0202] As shown in Figure 11B, in this embodiment, each first processing area 11011B of the epitaxial wafer 11000B includes two rows of first breaking points 11012B, and each second processing area 11011B' includes two rows of second breaking points 11012B'. The extension direction of each row of first breaking points 11012B is substantially parallel to the length direction LD of the top view of the epitaxial wafer 11000B, and the extension direction of each row of second breaking points 11012B' is substantially parallel to the width direction WD of the top view of the epitaxial wafer 11000B.

[0203] As shown in FIG11C , in this embodiment, each first processing area 11011C of the epitaxial wafer 11000C includes two rows of first rupture points 11012C, and each second processing area 11011C′ includes a row of second rupture points 11012C′. The direction in which each row of first rupture points 11012C extends is substantially parallel to the length direction LD of the epitaxial wafer 11000C in the top view, and the direction in which each row of second rupture points 11012C′ extends is substantially parallel to the width direction LD of the epitaxial wafer 11000C in the top view. In some embodiments, the number of rows of first rupture points 11012C and the number of rows of second rupture points 11012C′ may differ.

[0204] As shown in Figure 11D, in this embodiment, each first processing area 11011D of the epitaxial wafer 11000D includes three rows of first breaking points 11012D, and each second processing area 11011D' includes two rows of second breaking points 11012D'. The extension direction of each row of first breaking points 11012D is substantially parallel to the length direction LD of the top view of the epitaxial wafer 11000D, and the extension direction of each row of second breaking points 11012D' is substantially parallel to the width direction WD of the top view of the epitaxial wafer 11000D.

[0205] As shown in FIG. 11C and FIG. 11D , in some embodiments, the first row of rupture points 11012C, 11012D and the second row of rupture points 11012C′, 11012D′ are arranged alternately.

[0206] Figures 12A and 12B illustrate a process for singulating a thinned VCSEL wafer to produce a plurality of dies according to one embodiment. According to the method shown in Figures 12A and 12B, the width of the scribe line 12013 can be reduced to 10 microns or less.

[0207] In this embodiment, a method for performing a singulation process on an epitaxial wafer is provided, wherein the epitaxial wafer 12000 includes a semiconductor stacking layer 12020 (for example, a VCSEL stacking layer), a base layer 12010 and a metal layer 12030, and the base layer 12010 is located between the semiconductor stacking layer 12020 and the metal layer 12030. The base layer 12010 can be a growth wafer layer of the semiconductor stacking layer 12010 (for example, a growth wafer of the VCSEL stacking layer).

[0208] In this embodiment, the monomerization method includes a cutting step and a cleaving step, and each step is described below.

[0209] Cutting step: Use laser stripping technology or wheel cutting technology (for example: use ablation laser or cutting machine 12900) to cut the metal layer 12030 and a portion of the base layer 12010 from the lower surface of the epitaxial wafer 12000, and form a cutting road 12013 in the portion of the metal layer 12030 and the base layer 12010. The cutting road 12013 has a cutting width W12 and a cutting depth D12. The cutting width W12 is less than 10 microns, and the cutting depth D12 generally does not exceed 90 microns.

[0210] Splitting step: using a splitting technique (eg, using a splitting tool, as indicated by the arrows in the figure) on the scribe line 12030 to split the epitaxial wafer 12000 into a plurality of semiconductor lasers.

[0211] 12A , in this embodiment, a dicing process (eg, using an ablation laser or a saw 12900 ) is performed on the back side of the thinned epitaxial wafer 12000 to form trenches (dicing streets 12013 ) in the thinned epitaxial wafer 12000 .

[0212] Referring to FIG. 12B , in this embodiment, a cleaving force is applied to form cracks G012 extending from the apex of each trench to the front side of the epitaxial wafer 12000 , thereby splitting the epitaxial wafer 12000 into a plurality of VCSEL dies (chips).

[0213] According to some embodiments of the present invention, the singulation method of the epitaxial wafer 12000 can reduce the cutting width D12 to less than 10 microns.

[0214] According to the singulation method of this embodiment, for an epitaxial wafer of the same size, a narrower dicing street width can be obtained, and more semiconductor lasers can be cut out, thereby reducing the overall production cost.

[0215] 13A to 13C , FIG13A is a schematic cross-sectional view of a VCSEL chip 13000 according to one embodiment, and FIG13B and FIG13C are cross-sectional images of a VCSEL chip taken with an optical microscope, wherein the VCSEL chip is cut from a VCSEL wafer.

[0216] As shown in Figures 13A to 13C , in this embodiment, the semiconductor laser includes a base layer 13010, an epitaxial structure 13020 located on the base layer 13010, an insulating layer 13030, a first electrode 13040, and a second electrode 13050. The epitaxial structure 13020 includes an upper reflector 13020U, a lower reflector 13020L, and an active region 13020A located between the upper reflector 13020U and the lower reflector 13020L. The upper reflector 13020U, the active region 13020A, and the lower reflector 13020L are stacked on the base layer 13010. The second electrode 13050 is located on the epitaxial structure 13020 and is electrically connected to the semiconductor layer of the upper reflector 13020U. The first electrode 13040 is located on the base layer 13010 and is electrically connected to the semiconductor layer of the lower reflector 13020L. The second electrode 13050 comprises at least one metal layer and a P-type contact layer, connecting to the P-type semiconductor layer of the upper reflector 13020U. The first electrode 13040 comprises at least one metal layer, connecting to the base layer 13010 and electrically connecting to the N-type semiconductor layer of the lower reflector 13020L. An insulating layer 13030 is positioned between the epitaxial structure 13020 and the second electrode 13050 and extends to the side surface E13 of the epitaxial structure 13020 to prevent the second electrode 13050 from directly contacting the active area 13020A and the lower reflector 13020L. The side surface of the base layer 13010 has at least one row of cracks 13011. As shown in Figures 13A and 13B, in this embodiment, the side surface of the base layer 13010 has two rows of cracks 13011, which are generated by the singulation process employed in the aforementioned embodiment.

[0217] In one or more embodiments, as shown in FIG13A , the upper reflector 13020U is a multilayer structure, the lower reflector 13020L is a multilayer structure, and at least one or both of the upper reflector 13020U and the lower reflector 13020L include a distributed Bragg reflector (DBR) structure.

[0218] In some embodiments, the semiconductor laser may be a vertical chip VCSEL or a flip-chip VCSEL.

[0219] Referring to Figure 13B , in this embodiment, the semiconductor laser is a VCSEL with a vertical chip structure. For a vertical chip VCSEL, the base layer serves as the growth substrate. In other words, in this embodiment, the semiconductor stack is formed directly on the base layer through a semiconductor epitaxial growth process. In this embodiment, the fracture point is formed in the base layer, which serves as the growth substrate.

[0220] Referring to Figure 13C , in this embodiment, the semiconductor laser is a flip-chip VCSEL. For a flip-chip VCSEL, the base layer serves as a bonding substrate. In other words, in this embodiment, the semiconductor stack is first formed on the growth substrate through an epitaxial semiconductor process and then transferred to the base layer via a bonding layer. In this embodiment, the fracture point is formed in the base layer, which serves as the bonding substrate.

[0221] Generally speaking, multiple VCSEL chips are produced separately by singulating the same VCSEL epitaxial wafer (epi-wafer), and the optoelectronic properties of all chips are first tested in the epitaxial wafer state before the singulation process. Then, the optoelectronic properties of each VCSEL chip produced by the epitaxial wafer after the singulation process are tested again. After the singulation process, because all the singulated chips have similar appearance and structure, it is difficult to trace the position of each chip in the epitaxial wafer state. Therefore, it is difficult to understand the optoelectronic properties of each chip in the epitaxial wafer state before the singulation process, and it is also difficult to trace the test results of any singulated chip back to the test results of the same chip in the epitaxial wafer state before singulation.

[0222] This application provides a manufacturing method for forming multiple pattern structures of different shapes on each chip before the singulation process, with each chip having its own corresponding set of pattern structures. Therefore, after the singulation process, the position of each chip in the epitaxial wafer state can be traced based on the set of pattern structures each chip possesses.

[0223] Figures 14A and 14B illustrate different schematic diagrams of a VCSEL chip 14000 according to one embodiment. Figure 14A is a top view of the VCSEL chip 14000 according to one embodiment. Figure 14B is a schematic cross-sectional view taken along line 14B-14B' in Figure 14A. VCSEL chip 14000 has a stacked structure comprising a base layer 14010, an epitaxial structure 14020 located on the base layer 14010, an insulating layer 14040, an electrode 14050, and an electrode 14030.

[0224] In one or more embodiments, as shown in FIG14B , the epitaxial structure 14020 includes an upper reflector 14020U, a lower reflector 14020L, and an active region 14020A located between the upper reflector 14020U and the lower reflector 14020L. The upper reflector 14020U, the active region 14020A, and the lower reflector 14020L are stacked on a base layer 14010. In this embodiment, as shown in FIG14B , the base layer 14010 is a growth substrate on which the epitaxial structure 14020 is grown. For example, the lower reflector 14020L, the active region 14020A, and the upper reflector 14020U may be epitaxially grown on the base layer 14010.

[0225] In this embodiment, as shown in FIG. 14B , the base layer 14010 includes a semiconductor layer, such as a GaAs layer, an InP layer, and / or the like.

[0226] In one or more embodiments, the base layer 14010 may include a support substrate adhered to the VCSEL stack structure / epitaxial structure.

[0227] In one or more embodiments, as shown in FIG14B , the upper reflector 14020U is a multilayer structure, the lower reflector 14020L is a multilayer structure, and at least one or both of the upper reflector 14020U and the lower reflector 14020L include a distributed Bragg reflector (DBR) structure.

[0228] In one or more embodiments, as shown in FIG14B , the upper reflector 14020U and the lower reflector 14020L include semiconductor layers. In this embodiment, as shown in FIG14B , the upper reflector 14020U includes a P-type semiconductor layer and the lower reflector 14020L includes an N-type semiconductor layer, but the present application is not limited thereto. In some embodiments, the upper reflector 14020U includes an N-type semiconductor layer and the lower reflector 14020L includes a P-type semiconductor layer.

[0229] In this embodiment, as shown in Figure 14B, the upper reflector 14020U includes a P-doped reflector, such as a P-doped distributed Bragg reflector (P-doped DBR, PDBR), for example, the upper reflector 14020U includes a group of alternatingly stacked P-doped GaAs (P-GaAs) layers and P-doped AlGaAs (P-AlGaAs) or a group of alternatingly stacked P-doped AlGaAs with a low aluminum percentage (low Al P-AlGaAs) and P-doped AlGaAs with a high aluminum percentage (high Al P-AlGaAs).

[0230] In this embodiment, as shown in Figure 14B, the lower reflecting mirror 14020L includes an N-doped reflecting mirror, such as an N-doped distributed Bragg reflector (N-doped DBR, NDBR), for example, the lower reflecting mirror 14020L includes a group of alternatingly stacked N-doped GaAs (N-GaAs) layers and N-doped AlGaAs (N-AlGaAs) or a group of alternatingly stacked N-doped AlGaAs with a low aluminum percentage (low Al N-AlGaAs) and N-doped AlGaAs with a high aluminum percentage (high Al N-AlGaAs).

[0231] In this embodiment, the N-doped semiconductor layer may be doped with Te, Se or other N-type dopants, and the P-doped semiconductor layer may be doped with C or other P-type dopants.

[0232] In one or more embodiments, a DBR structure is formed from a plurality of thin films of alternating materials having different refractive indices, wherein the optical thickness of each film is substantially equal to m*1 / 4 of the emission wavelength, where m is an odd number. The DBR structure includes at least one pair of optical thin films (DBR pair), one of which has a higher refractive index than the other.

[0233] In one or more embodiments, the active region 14010A includes a multiple quantum well (MQW) structure.

[0234] In one or more embodiments, as shown in FIG14B , the epitaxial structure 14020 further includes a current confinement layer 14104, which is selectively positioned between the active region 14020A and the upper reflector 14020U or between the active region 14020A and the lower reflector 14020L. The current confinement layer 14104 includes a current confinement region 14104B and a current conduction region 14104A surrounded by the current confinement region 14104B. The current conduction region 14104A has a higher conductivity than the current confinement region 14104B, thereby concentrating the current in the current conduction region 14104A. In one or more embodiments, the current confinement layer 14104 includes aluminum oxide in the current confinement region 14104B.

[0235] In one or more embodiments, as shown in Figures 14A and 14B , electrode 14050 is disposed on epitaxial structure 14020 and electrically connected to the semiconductor layer of upper reflector 14020U. Electrode 14050 has a light outlet O14 (as shown in Figure 14A ), corresponding to current conduction region 14104A of current confining layer 14104. Electrode 14030 is disposed on base layer 14010 and electrically connected to the semiconductor layer of lower reflector 14020L. For example, in the embodiment shown in Figure 14B , electrode 14050 comprises at least one metal layer and a P-type contact layer, connected to the P-type semiconductor layer of upper reflector 14020U, while electrode 14030 comprises at least one metal layer, connected to base layer 14010, and electrically connected to the N-type semiconductor layer of lower reflector 14020L.

[0236] In one or more embodiments, as shown in FIG14B , an insulating layer 14040 is positioned between the epitaxial structure 14020 and the electrode 14050 and extends to the side surface E14 of the epitaxial structure 14020 to prevent the electrode 14050 from directly contacting the active area 14020A and the lower reflector 14020L. The insulating layer 14040 is electrically insulating and comprises an inorganic or organic insulating material. In this embodiment, as shown in FIG14B , the insulating layer 14040 comprises a silicon oxide layer, but the present application is not limited to this embodiment.

[0237] Table 1A

[0238] Table 1B

[0239] Tables 1A and 1B are tables of decimal numbers and ternary codes using pattern codes. In one or more embodiments, as shown in Tables 1A and 1B, pattern codes of different shapes are provided to represent decimal values. For example, as shown in Tables 1A and 1B, the pattern codes of group A include pattern codes of three shapes, namely, a square, a parallelogram, and a triangle. In this embodiment, as shown in Tables 1A and 1B, the pattern codes of the three shapes in group A represent three numbers in a ternary system, for example, the pattern code of the square represents the number "0", the pattern code of the parallelogram represents the number "1", and the pattern code of the triangle represents the number "2". Therefore, referring to Tables 1A and 1B, the decimal number "998" can be converted into the ternary number "1100222", and the ternary number "1100222" can be converted into the ternary number "1100222" by the pattern code of group A. It should be noted that the present application is not limited to the ternary number system. In one or more embodiments, group A may be a set of pattern codes having N different shapes to represent decimal values, where N is a positive integer greater than 1.

[0240] FIG15A illustrates a top view of a VCSEL chip 15000 with pattern coding according to an exemplary embodiment. Referring to Table 1A, Table 1B, and FIG15A , in one or more embodiments, as shown in FIG15A , electrode 15050 exposes at least one set of patterns 510, 511, and 512 on epitaxial structure 15020. This set of patterns may utilize pattern coding from set A to provide identification of VCSEL chip 15000. For example, the identification may include the location of VCSEL chip 15000 on the epitaxial wafer, the serial number or production date of VCSEL chip 15000, or any other specific information about VCSEL chip 15000.

[0241] Referring to Table 1A, Table 1B and Figures 15A and 15B, in this embodiment, as shown in Figures 15A and 15B, patterns 512, 511, and 510 are arranged in order from right to left along the horizontal direction, and the shape of pattern 510 is a square pattern code, the shape of pattern 511 is a parallelogram pattern code, and the shape of pattern 512 is a triangle pattern code. Therefore, in this embodiment, as shown in Figure 15, the group of patterns 512, 511, and 510 are arranged so as to be encoded by the pattern code of group A. 1A and 1B, the set of patterns 512, 511, 510 can be the decimal number "22".

[0242] Figures 15A and 15B illustrate various schematic diagrams of a VCSEL chip according to one or more embodiments. Figure 15B is a schematic cross-sectional view taken along line 15B-15B' in Figure 15A. Figures 15C and 15D are top views of a VCSEL chip according to one or more embodiments.

[0243] In one or more embodiments, as shown in FIG15A and FIG15C-15D , the electrode has one or more sets of patterns on the epitaxial structure 15020. For example, in one embodiment, as shown in FIG15A , the electrode 15050 has two sets of patterns on the epitaxial structure 15020: a first set of patterns 510, 511, 512 and a second set of patterns 520, 521, 522. In this embodiment, as shown in FIG15A , the patterns 520, 521, 522 are arranged in a direction different from the direction of the patterns 510, 511, 512 (in this embodiment, a perpendicular direction).

[0244] In one or more embodiments, as shown in Figures 15A and 15B , the pattern of the electrode 15050 may be an opening structure of the electrode 15050. For example, as shown in Figure 15B , patterns 520, 521, and 522 are opening structures at different locations of the electrode 15050. These opening structures 520, 521, and 522 having different shapes may be formed during the manufacturing process of the VCSEL chip 15000 (i.e., formed in an epitaxial wafer state before the singulation process).

[0245] In one or more embodiments, as shown in FIG. 15C , the electrode 15050 has two sets of patterns, and each set includes more than one pattern (eg, seven patterns).

[0246] In one or more embodiments, as shown in FIG. 15D , the electrode 15050 has at least one set of patterns, and each set of patterns may be located in a corner region of the electrode 15050 .

[0247] FIG16 illustrates a top view of a VCSEL chip according to one embodiment. In one or more embodiments, as shown in FIG16 , the stacked structure of VCSEL chip 16000 further includes an insulating layer 16060 covering electrode 16050. Insulating layer 16060 may form at least one opening having a set of pattern structures 620-627 on electrode 16050, as shown in FIG16 . Consequently, a set of patterns 520-526 corresponding to pattern structures 620-627 in opening 16060 may be exposed on electrode 16050.

[0248] 17A to 17F are schematic cross-sectional views illustrating multiple steps of a fabrication process for the VCSEL chip 15000 shown in FIG. 15B according to one embodiment.

[0249] Referring to FIG. 17A , a stacked structure 1500 comprising a second-type semiconductor layer 15020L, an active layer 15020A, and a first-type semiconductor layer 15020U is epitaxially grown on a growth substrate 15100. Stacked structure 1500 can be formed on growth substrate 15100 via an epitaxial process. The epitaxial process may include, but is not limited to, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and the like. In this embodiment, as shown in FIG. 17A , the material of growth substrate 15100 is GaAs. In other embodiments, the material of growth substrate 15100 may be InP, sapphire, GaN, SiC, and the like.

[0250] 17B , a protective layer PL is formed on the stacked structure 1500, and an etching process is then performed to remove a portion of the first-type semiconductor layer 15020U and a portion of the active structure 15020A to expose a portion of the surface of the second-type semiconductor layer 15020L and form the epitaxial structure 15020. In this embodiment, the protective layer PL is electrically insulating.

[0251] Next, as shown in FIG17C , a current confining layer 15104 is formed in the epitaxial structure 15020. In this embodiment, the current confining region of the current confining layer 15104 is formed by an oxidation process. For example, the first-type semiconductor layer 15020U includes multiple AlGaAs layers, one or more of which have a higher aluminum content than the other layers. The current confining layer 15104 can then be formed by an oxidation process on the layer or layers having a higher aluminum content.

[0252] Next, as shown in FIG. 17D , an insulating layer 15040 is provided to cover the epitaxial structure 15020 , and the insulating layer 15040 has an opening (not shown) to expose a portion of the upper surface of the epitaxial structure 15020 .

[0253] Next, as shown in Figure 17E, a metal layer having pattern structures 520, 521, and 522 is formed on the insulating layer 15040 (for example, using etching and mask processing) and fills the openings of the insulating layer 15040 to electrically connect the first-type semiconductor layer 15020U, thereby forming an electrode 15050 having a set of pattern structures 520, 521, and 522.

[0254] Next, as shown in FIG. 17F , the growth substrate 15100 is thinned and then a metal layer is formed on the thinned growth substrate 15100 to form an electrode 15030 , thereby forming the VCSEL chip shown in FIG. 15A and FIG. 15B .

[0255] 18A to 18G are schematic cross-sectional views illustrating multiple steps of a VCSEL chip fabrication process along line 18 - 18 ′ in FIG. 16 according to one embodiment.

[0256] Referring to FIG. 18A , a stacked structure 1600 comprising a second-type semiconductor layer 16020L, an active layer 16020A, and a first-type semiconductor layer 16020U is epitaxially grown on a growth substrate 16100. Stacked structure 1600 can be formed on growth substrate 16100 using an epitaxial process, which may include, but is not limited to, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (CVPE), molecular beam epitaxy (MBPE), liquid phase epitaxy, and the like. In this embodiment, as shown in FIG. 18A , the material of growth substrate 16100 is GaAs. In other embodiments, the material of growth substrate 16100 may be InP, sapphire, GaN, SiC, and the like.

[0257] Next, as shown in FIG18B , a protection layer PL is formed on the stacked structure 1600 , and then an etching process is performed to remove a portion of the first-type semiconductor layer 16020U and a portion of the active structure 16020A to expose a portion of the surface of the second-type semiconductor layer 16020L and form an epitaxial structure 16020 .

[0258] Next, as shown in FIG18C , a current confining layer 16104 is formed in the epitaxial structure 16020. In this embodiment, the current confining region of the current confining layer 16104 is formed by an oxidation process. For example, the first-type semiconductor layer 16020U includes multiple AlGaAs layers, one or more of which have a higher aluminum content than the other layers. The current confining layer 16104 can then be formed by an oxidation process on the layer or layers having a higher aluminum content.

[0259] For example, the aluminum content of at least one layer of the first-type semiconductor layer 16020U is greater than 97% (defined as the layer predetermined to form the current limiting layer 16104) and is greater than the aluminum content of the active layer 16020A and the second-type semiconductor layer 16020L. Therefore, when the oxidation process is performed, the high aluminum content layer region (defined as the layer predetermined to form the current limiting layer 16104) in the epitaxial structure 16020 is oxidized from the side to the inside at a higher rate than other regions, thereby forming a current limiting region with low conductivity in the current limiting layer 16104. Alternatively, a current limiting region with low conductivity can be formed in the epitaxial structure 16020 by an ion implantation process, and the above-mentioned current conduction region can be defined at the same time by a mask. Ion implantation can be performed by implanting hydrogen ions (H + ), helium ions (He + ) or argon ions (Ar + ) etc., the ion concentration in the current limiting region is much greater than that in the current conducting region, so that the current limiting region has a lower conductivity.

[0260] Next, as shown in FIG. 18D , an insulating layer 16040 is provided to cover the epitaxial structure 16020 , and the insulating layer 16040 has an opening (not shown) to expose a portion of the upper surface of the epitaxial structure 16020 .

[0261] Next, as shown in FIG. 18E , a metal layer is formed on the insulating layer 16040 and fills the openings to electrically connect to the first-type semiconductor layer 16020U, thereby forming an electrode 16050 .

[0262] Next, as shown in FIG18F , an insulating layer 16060 having an opening (the opening having a set of pattern structures 620-627) is provided to cover the electrode 16050. As shown in FIG18F and FIG16 , the opening having the pattern structures 620-627 is formed on the electrode 16050. Therefore, a set of patterns 520-526 corresponding to the pattern structures 620-627 of the opening of the insulating layer 16060 can be exposed on the electrode 16050.

[0263] Next, as shown in FIG. 18G , the growth substrate 16100 is thinned and a metal layer is formed on the thinned growth substrate 16100 to form an electrode 16030 , thereby forming a VCSEL chip, as shown in FIG. 16 .

[0264] In one or more embodiments, the pattern code may be formed on the side surface E14 of the epitaxial structure 14020 (as shown in FIG. 14B ), but the present application is not limited to this embodiment.

[0265] Therefore, according to some embodiments, after a semiconductor laser package with a pattern structure leaves the factory, if a defect problem occurs subsequently, the specific arrangement and combination of the pattern structure on the semiconductor laser chip can be used to understand its position in the epitaxial wafer state or the production date or production batch number, etc., thereby achieving a traceability effect.

[0266] FIG19A is a schematic diagram illustrating the bottom / back surface of an epitaxial wafer 19001 (e.g., a VCSEL wafer) for an optoelectronic device according to one embodiment. FIG19B is a schematic cross-sectional view taken along line 19B-19B' in FIG19A. FIG19C is a schematic cross-sectional view illustrating a semiconductor laser chip 19000 (e.g., a VCSEL chip) cut from the epitaxial wafer 19001 for an optoelectronic device shown in FIG19A according to one embodiment. FIG19D is a schematic cross-sectional view illustrating the semiconductor laser chip 19000 (e.g., a VCSEL chip) of FIG19C being soldered to a carrier 19900.

[0267] 19A and 19B , a plurality of strip-shaped grooves G019 are formed on the backside of an epitaxial wafer 19001 (e.g., a VCSEL wafer) for an optoelectronic device by etching. In some embodiments, after etching a portion of the base layer 19100 of the epitaxial wafer 19001 on the backside 19001B (i.e., the base layer 19100 side of the epitaxial wafer 19001), the aforementioned singulation process for the epitaxial wafer 19001 can be used to obtain a plurality of semiconductor laser chips 19000 (e.g., VCSEL chips) each having a stepped structure 19000S with the base layer 19100.

[0268] 19B and 19C , due to the etched strip grooves G019 on the back side 19001B of an epitaxial wafer 19001 for an optoelectronic device (e.g., a VCSEL wafer), the bottom of the VCSEL chip generated after the singulation process retains a stepped structure 19000S having an etched pattern. Specifically, in one embodiment, the semiconductor laser chip 19000 includes a base layer 19100 and a semiconductor stacked layer 19020 formed on the base layer 19100. The base layer 19100 has a stepped structure 19000S on a side facing the semiconductor stack layer 19020. Subsequently, the semiconductor laser chip 19000 (e.g., a VCSEL chip) is further formed with an upper electrode 19030 and a lower electrode 19040. The upper electrode 19030 is formed on the semiconductor stack layer 19020 of the semiconductor laser chip 19000, and the lower electrode 19040 is formed on the bottom surface 19000B of the semiconductor laser chip 19000. The upper electrode 19030 is electrically connected to the first-type semiconductor layer of the semiconductor stack layer 19020, and the lower electrode 19040 is electrically connected to the second-type semiconductor layer of the semiconductor stack layer 19020 through the base layer 19100.

[0269] Referring to the embodiments shown in FIG. 19C and FIG. 19D , in the embodiment shown in FIG. 19D , due to the stepped structure with an etched pattern on the bottom of the semiconductor laser chip 19000 (e.g., a VCSEL chip), the semiconductor laser chip 19000 (e.g., a VCSEL chip) can be soldered obliquely to a carrier 19900, thereby changing the direction of light emission. Specifically, when the semiconductor laser chip 19000 is mounted on the carrier 19900 (e.g., a circuit board) via solder, the direction of laser light emitted from the semiconductor laser chip 19000 is not parallel to the normal direction of the carrier 19900 (the angle between the laser light direction and the normal direction of the carrier 19900 is θ, i.e., it is tilted at the aforementioned angle θ). In addition to incorporating optical elements into the light-emitting sensor package to change the light emission direction as described in the previous embodiments, the stepped structure formed on the bottom of the semiconductor laser chip 19000 can also be used to change the light emission direction.

[0270] Continuing to refer to the embodiments shown in FIG. 19B and FIG. 19C , the etching pattern of the semiconductor laser chip 19000 (for example, a VCSEL chip) substantially retains the same or similar width L019 and depth D019 of the groove as that of the epitaxial wafer 19001 type. Therefore, the angle of change in the light emitting direction of the semiconductor laser package can be pre-set by forming the width L019 and depth D019 of the etching pattern of the preset groove on the bottom surface of the base layer 19100 when the epitaxial wafer of the optoelectronic device is subjected to the etching process.

[0271] In some embodiments, the depth D019 is between 10 micrometers and 300 micrometers depending on the size of the semiconductor laser and the desired change in the light emission direction of the semiconductor laser.

[0272] FIG20 is a schematic cross-sectional view of a VCSEL chip 20000 mounted on a carrier 20900 and soldered to electrode pads 20900e on the carrier 20900. Referring to FIG20 , the upper electrode layer (first electrode structure 20020) of the VCSEL chip 20000 extends to the sidewalls of the VCSEL chip 20000 and / or the sidewalls of the base layer 20040, thereby increasing the electrode area of ​​the VCSEL chip 20000 and enabling stable soldering to the carrier 20900. Furthermore, the planar dimension A of the VCSEL chip 20000 can be reduced, thereby further increasing the utilization rate of the VCSEL wafer.

[0273] FIG20 is a cross-sectional view showing a VCSEL chip 20000 mounted on a carrier 20900 and soldered to an electrode pad 20900 e of the carrier 20900 .

[0274] Referring to FIG. 20 , in this embodiment, the upper electrode layer (first electrode structure 20020) of the VCSEL chip 20000 extends to the sidewalls of the VCSEL chip 20000 and / or the sidewalls of the base layer 20040, thereby increasing the electrode area of ​​the VCSEL chip 20000, thereby enabling stable soldering to the carrier 20900. Furthermore, the planar dimension A of the VCSEL chip 20000 can be reduced, thereby further increasing the utilization rate of the VCSEL wafer. In one or more embodiments, the carrier 20900 can be a circuit board, a ceramic substrate, etc.

[0275] In one or more embodiments, the VSCEL chip 20000 may include a single VCSEL structure, a plurality of VCSEL structures arranged in an array, or a plurality of the aforementioned self-mixing interference sensing units arranged in an array.

[0276] In this embodiment, the VSCEL chip 20000 includes: a base layer 20040 , a semiconductor stack layer 20010 , a first electrode structure 20020 , a second electrode structure 20050 and an insulating layer 20030 .

[0277] Semiconductor stacked layer 20010 is located on base layer 20040. Semiconductor stacked layer 20010 has a first surface 20011, a second surface 20012, and a side surface 20013. Second surface 20012 is opposite first surface 20011, and side surface 20013 is located between first surface 20011 and second surface 20012. Semiconductor stacked layer 20010 includes a first-type semiconductor layer 20010U, a second-type semiconductor layer 20010L, and an active layer 20010A. Active layer 20010A is located between first-type semiconductor layer 20010U and second-type semiconductor layer 20010L.

[0278] The base layer 20040 is located on the side of the second-type semiconductor layer 20010L opposite the first-type semiconductor layer 20010U. The base layer 20040 can serve as a growth substrate for the semiconductor stacked layer 20010, that is, the semiconductor stacked layer 20010 is grown directly on the base layer 20040. The base layer 20040 is conductive and has a bottom portion 20041 and a plateau portion 20042 extending from the bottom portion 20041. The plateau portion 20042 has a plateau surface 20042A (connected to the second surface 20012) and a plateau side surface 20042B. The plateau side surface 20042B is connected to the plateau surface 20042A. The bottom portion 20041 has a first bottom surface 20041A, a second bottom surface 20041B, and a side surface 20041C. The bottom first surface 20041A is connected to the platform side surface 20042B, the bottom second surface 20041B is opposite to the bottom first surface 20041A, and the bottom side surface 20041C is located between the bottom first surface 20041A and the bottom second surface 20041B.

[0279] The insulating layer 20030 is located on the first surface 20011 and extends through the side surface 20013, the plateau surface 20042A, and the plateau side surface 20042B to the bottom first surface 20041A. The insulating layer 20030 has an opening 20031. The opening 20031 is located on the first surface 20011. The first electrode structure 20020 is located in the opening 20031 and contacts the first-type semiconductor layer 20010U. The first electrode structure 20020 is further located on the first surface 20011 and extends through the side surface 20013, the plateau surface 20042A, and the plateau side surface 20042B to the bottom first surface 20041A. The insulating layer 20030 further extends through the bottom first surface 20041A to the bottom side surface 20041C.

[0280] The second-type semiconductor layer 20010L in the semiconductor stack 20010 further includes terraces 20012A and 20012B extending laterally above the terrace surface 20042A. The insulating layer 20030 and the first electrode structure 20020 are further located on the terraces 20012A and 20012B. A second electrode structure 20050 is located on the bottom second surface 20041B.

[0281] Therefore, when the VSCEL chip 20000 is subsequently electrically bonded to the electrode pads 20900e on the carrier 20900, the first electrode structure 20020 extends to the platform side surface 20042B. This increases the bonding area between the electrode structure 20020 on one side of the VSCEL chip 20000 and the bonding structure CS (e.g., solder paste) bonded to the carrier 20900 without increasing the size of the VSCEL chip 20000. This allows the VSCEL chip 2000 to be packaged while maintaining the spacing between the electrode pads 20900e on the carrier 20900 while reducing chip size.

[0282] In some embodiments, the height of the plateau 20042 is 70 to 90 microns.

[0283] In some embodiments, the platform side surface 20042B of the platform portion 20042 has an angle θ' relative to the platform surface 20042A, and the angle θ' ranges from 90 degrees to 120 degrees.

[0284] In one or more embodiments, the optoelectronic module includes a light emitting device, a light receiving device, and a driving chip electrically connected to the light emitting device and / or the light receiving device.

[0285] In one or more embodiments, the light emitting device includes at least one semiconductor light source, such as a semiconductor laser, such as a VCSEL structure.

[0286] In one or more embodiments, the light receiving device includes at least one semiconductor sensor, such as a single-photon avalanche diode (SPAD).

[0287] 21 is a cross-sectional diagram illustrating an optoelectronic module 21000 that can be applied as a time-of-flight ranging module according to an embodiment. The optoelectronic module 21000 includes a light emitting device 21020 mounted on a driver chip 21010 , and the driver chip 21010 has one or more SPADs 21030 .

[0288] Referring to this embodiment, as shown in FIG21 , the optoelectronic module 21000 further includes a lens assembly 21011 mounted on the area of ​​the SPAD 21030. In this embodiment, as shown in FIG21 , when the optoelectronic module 21000 is applied as a time-of-flight ranging module, the driver chip 21010 provides an electrical signal, voltage, or current to drive the light emitting device 21020 to emit light toward an object and drive the SPAD 21030 to receive light reflected from the object. Furthermore, the light emitted by the light emitting device 21020 can be a patterned light source, and its pattern can be a dot pattern, a line pattern, a planar pattern, or a mixture of two or more of the above patterns, which illuminates the field of illumination (FOI).

[0289] Please refer to this embodiment again, as shown in Figure 21, the ball grid array (BGA) structure 21040 can be located on the back side 21010B of the driver chip 21010 (the side opposite to the light emitting device 21020 and the SPAD 21030) to electrically connect to a circuit board, such as a printed circuit board (PCB).

[0290] FIG22 is a schematic cross-sectional view of a transmitter module 22000 according to one embodiment, wherein the transmitter module 22000 integrates a flip-chip light emitting device 22020, a passive component 22030, and a driver chip 22010. The light emitting device 22020 can be mounted directly on the driver chip 22010, or the light emitting device 22020 can be mounted on a carrier board, which in turn is mounted on the driver chip 22010. The driver chip 22010 provides an electrical signal, voltage, or current to drive the light emitting device 22020 as a light source and is electrically connected to a printed circuit board via a BGA structure 22040. The light source can be a point light source, a linear light source, a surface light source, or a patterned light source that combines two or more of these. One or more passive components 22030 are used together with the driver chip 22010 to regulate the electrical signal.

[0291] Figure 23A is a schematic cross-sectional view of a transmitter module according to one embodiment. Figure 23B is a schematic cross-sectional view of a transmitter module according to one embodiment. In one or more embodiments, as shown in Figures 23A and 23B, a transmitter module 23000 is provided. Transmitter module 23000 integrates a light emitting device 23020, a passive component 23030, a driver chip 23010, and a carrier 23900. The light emitting device 23020, the passive component 23030, and the driver chip 23010 are mounted on the carrier 23900. The light emitting device 23020, the passive component 23030, and the driver chip 23010 can be mounted on the same side or different sides of the carrier 23900. The carrier 23900 provides power distribution through multiple through-holes and multiple metal layers located between the components (including the driver chip 23010, the light-emitting device 23020, and the passive components 23030) and is electrically connected to the printed circuit board via the BGA structure 23040. The driver chip 23900 provides an electrical signal, voltage, or current to drive the light-emitting device 23020 as a light source. The light source can be a point light source, a line light source, a surface light source, or a patterned light source that is a mixture of two or more of the above. In this embodiment, as shown in Figure 23A, the driver chip 23010 is electrically connected to the carrier 23900 via the BGA structure 23040. In one or more embodiments, the driver chip 23010 is electrically connected to the carrier 23900 by wire bonding, as shown in Figure 23B. A molding material 23060 is required to cover the driver chip 23010 and the metal wires 23050 to protect the metal wires 23050.

[0292] In some embodiments, an underfill may be included between the driver chip 23010 and the carrier board 23900 , and the underfill may cover the BGA structure 23040 .

[0293] In one or more embodiments, the light emitting device includes a semiconductor layer, a spacer layer, a pattern layer, and a cover layer, as shown in Figures 24A to 24C. Figure 24A is a schematic cross-sectional view of a light emitting device according to one embodiment. Figure 24B is a schematic cross-sectional view of a light emitting device according to one embodiment. Figure 24C is a schematic cross-sectional view of a light emitting device according to one embodiment. The spacer layer surrounds the VCSEL chip and is similar to a chip scale package (CSP). The pattern layer includes one or more optical elements, such as a metasurface, a photonic crystal, a microlens array, or a diffraction optical element (DOE). In one embodiment, as shown in Figure 24A, the light emitting device 24000A includes a semiconductor layer 24010, a transparent base layer 24015, a spacer layer 24020, a first pattern layer 24031, and a cover layer 24040. A first patterned layer 24031 is formed on the upper surface 24020T of the spacer layer 24020, followed by a cover layer 24040 formed on the first patterned layer 24031. The cover layer 24040 protects the first patterned layer 24031 from damage by scratches, moisture, or solvents. In one or more embodiments, the light emitting device integrates a meta-interface optical element to shorten the optical focal length, thereby reducing the overall package height.

[0294] In one or more embodiments, the pattern layer may be a single layer or multiple layers and may be formed between different interfaces, as shown in Figures 24A to 24C. In one embodiment, as shown in Figure 24B, a light emitting device 24000B includes a semiconductor layer 24010, a transparent base layer 24015, a spacer layer 24020, a first pattern layer 24031, a second pattern layer 24032, and a capping layer 24040. In one embodiment, as shown in Figure 24C, a light emitting device 24000C includes a semiconductor layer 24010, a transparent base layer 24015, a spacer layer 24020, a first pattern layer 24031, a second pattern layer 24032, a third pattern layer 24033, and a capping layer 24040. The first pattern layer 24031 is formed on the spacer layer 24020. The second pattern layer 24032 is formed between the transparent base layer 24015 and the spacer layer 24020. The third pattern layer 24033 is formed between the transparent base layer 24015 and the semiconductor layer 24010. It should be noted that the transparent base layer 24015 is transparent to the light from the light emitting device 24000. Therefore, objects beneath the transparent base layer 24015 do not need to be clearly visible to the naked eye, and can be transparent to UV light, visible light, or infrared light, but this application is not limited thereto.

[0295] In one or more embodiments, as shown in Figures 25A to 25E , a light emitting device may integrate one or more patterned layers and be formed at different interfaces. Figure 25A is a schematic cross-sectional view of a light emitting device according to one embodiment. Figure 25B is a schematic cross-sectional view of a light emitting device according to one embodiment. Figure 25C is a schematic cross-sectional view of a light emitting device according to one embodiment. Figure 25D is a schematic cross-sectional view of a light emitting device according to one embodiment. Figure 25E is a schematic cross-sectional view of a light emitting device according to one embodiment.

[0296] In one embodiment, as shown in FIG25A , a light emitting device 25000A includes a semiconductor layer 25010, a first transparent base layer 25021, a first pattern layer 25031, and a cover layer 25040. The first transparent base layer 25021 is located on the semiconductor layer 25010, the first pattern layer 25031 is formed on the upper surface 25021T of the first transparent base layer 25021, and the cover layer 25040 is located on the first pattern layer 25031.

[0297] In one embodiment, as shown in FIG25B , a light emitting device 25000B includes a semiconductor layer 25010, a first transparent base layer 25021, a first pattern layer 25031, a second pattern layer 25032, and a cover layer 25040. The first transparent base layer 25021 is located on the semiconductor layer 25010, the second pattern layer 25032 is formed between the first transparent base layer 25021 and the semiconductor layer 25010, the first pattern layer 25031 is formed on the upper surface 25021T of the first transparent base layer 25021, and the cover layer 25040 is located on the first pattern layer 25031.

[0298] In one embodiment, as shown in FIG25C , a light emitting device 25000C includes a semiconductor layer 25010, a first transparent base layer 25021, a second transparent base layer 25022, and a first patterned layer 25031. The first transparent base layer 25021 is located on the semiconductor layer 25010, the first patterned layer 25031 is formed between the two transparent base layers (the first transparent base layer 25021 and the second transparent base layer 25022), and the adhesive layer may be further located on one side of the first patterned layer 25031.

[0299] In one or more embodiments, as shown in FIG. 25C to FIG. 25E , the light emitting device may include stacked transparent base layers, and the subsequent layer may be interposed between the stacked transparent base layers.

[0300] In this embodiment, as shown in FIG25C , a light emitting device 25000C includes a semiconductor layer 25010, a first transparent base layer 25021, a first pattern layer 25031, and a second transparent base layer 25022. The light emitting device 25000C has the second transparent base layer 25022 stacked on the first pattern layer 25031. In some embodiments, the first pattern layer 25031 can be formed on either the first transparent base layer 25021 or the second transparent base layer 25022. Another adhesive layer can be further positioned between the first transparent base layer 25021 and the second transparent base layer 25022.

[0301] According to one or more embodiments, as shown in FIG25D , a light emitting device 25000D includes a semiconductor layer 25010, a first transparent base layer 25021, an adhesive layer 25050, a second transparent base layer 25022, and a pattern layer 25030. The first transparent base layer 25021 is disposed on the semiconductor layer 25010, the second transparent base layer 25022 is bonded to the first transparent base layer 25021 using the adhesive layer 25050, and the pattern layer 25030 is formed on the second transparent base layer 25022.

[0302] In one or more embodiments, as shown in FIG25E , a light emitting device 25000E includes a semiconductor layer 25010, a first transparent base layer 25021, an adhesive layer 25050, a second transparent base layer 25022, a pattern layer 25030, and a third transparent base layer 25023. The first transparent base layer 25021 is disposed on the semiconductor layer 25010, the second transparent base layer 25022 is bonded to the first transparent base layer 25021 via the adhesive layer 25050, and the pattern layer 25030 is formed on the second transparent base layer 25022. The third transparent base layer 25023 covers the pattern layer 25030 to protect it from scratches, moisture, or solvents, thereby preventing damage that may affect the optical function of the pattern layer 25030.

[0303] FIG26 is a schematic cross-sectional view of a laser element according to one embodiment. In one or more embodiments, the light emitting device may be a laser element, as shown in FIG26 . Referring to this embodiment, as shown in FIG26 , the laser element 26000 includes a transparent base layer 26001, a bonding layer 26002, a laser unit 26003, and a plurality of first channels 26034. The transparent base layer 26001 includes a conductive layer 26010. For example, the transparent base layer 26001 includes sapphire, glass, or silicon carbide (SiC). In some embodiments, the transparent base layer 26001 is an optical element and may be patterned to produce a specific optical effect. For example, the optical element may enable the light emitting device to generate a patterned light source, such as a point light source, a surface light source, or a multi-pattern light source with a predetermined field of illumination (FOI). The conductive layer 26010 includes a transparent conductive film (Transparent Conductive Oxide) or a metal. The transparent conductive film can be indium tin oxide (ITO) or indium zinc oxide (IZO). In this embodiment, the conductive layer 26010 is disposed between the transparent base layer 26001 and the adhesive layer 26002 .

[0304] One side of the adhesive layer 26002 is connected to the conductive layer 26010 of the transparent base layer 26001, and the other side is connected to the light-emitting side 26003S of the laser unit 26003. For example, the adhesive layer 26002 can be made of benzocyclobutene (BCB), silicon dioxide, or a transparent conductive film.

[0305] Laser unit 26003 includes a front conductive structure 26030, a first-type semiconductor layer 26031, an active layer 26033, a second-type semiconductor layer 26035, an insulating layer 26036, and a back conductive structure 26032. Back conductive structure 26032 includes separate conductive electrodes 26032C and 26032D. Herein, the terms "first type" and "second type" refer to semiconductor structures of different electrical properties. A semiconductor structure with holes as the majority carrier is a p-type semiconductor, while a semiconductor structure with electrons as the majority carrier is an n-type semiconductor. For example, first-type semiconductor layer 26031 is an n-type semiconductor, and second-type semiconductor layer 26035 is a p-type semiconductor, or vice versa. Active layer 26033 is located between first-type semiconductor layer 26031 and second-type semiconductor layer 26035 and includes a pn junction to create a depletion region for electron-hole recombination to generate light. In some embodiments, the active layer 26033 is composed of multiple quantum wells, thereby achieving better luminous efficiency than a pn junction, but the present invention is not limited thereto. In one embodiment, the materials of the first-type semiconductor layer 26031, the second-type semiconductor layer 26035, and the active layer 26033 include Group III and V compound semiconductors, such as GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, etc. In the embodiments of the present application, unless otherwise specified, the chemical expressions include "stoichiometric compounds" and "non-stoichiometric compounds." A "stoichiometric compound" is, for example, one in which the total elemental content of Group III elements is the same as the total elemental content of Group V elements. Conversely, a "non-stoichiometric compound" is, for example, one in which the total elemental content of Group III elements is different from the total elemental content of Group V elements. For example, the chemical formula AlGaAs means that it contains Group III elements aluminum (Al) and / or gallium (Ga), and Group V elements arsenic (As), wherein the total element content of Group III elements (aluminum and / or gallium) can be the same as or different from the total element content of Group V elements (arsenic). In addition, if the compounds represented by the chemical formula are stoichiometric compounds, AlGaAs means Al x1 Ga (1-x1) As, where 0≦x1≦1; AlInP represents Al x2 In (1-x2) P, where 0≦x2≦1; AlGaInP represents (Al y1 Ga (1-y1) ) 1-x3 In x3 P, where 0≦x3≦1, 0≦y1≦1; AlGaN represents Alx4 Ga (1-x4) N, where 0≦x4≦1; AlAsSb represents AlAs x5 Sb (1-x5) , where 0≦x5≦1; InGaP represents In x6 Ga 1-x6 P, where 0≦x6≦1; InGaAsP represents In x Ga 1-x6 As 1-y2 P y2 , where 0≦x6≦1, 0≦y2≦1; InGaAsN represents In x8 Ga 1-x8 As 1-y3 N y3 , where 0≦x8≦1, 0≦y3≦1; AlGaAsP represents Al x9 Ga 1- x9 As 1-y4 P y4 , where 0≦x9≦1, 0≦y4≦1; InGaAs represents In x10 Ga 1-x10 As, where 0 ≤ x10 ≤ 1. Depending on the material of the active layer 26033, when the materials of the semiconductor layers 26031 and 26035 are AlGaAs series, the active layer 26033 can emit infrared light with a peak wavelength between 700 nm and 1700 nm. When the materials of the semiconductor layers 26031 and 26035 are AlGaInP series, the active layer 26033 can emit red light with a peak wavelength between 610 nm and 700 nm, or yellow light with a peak wavelength between 530 nm and 570 nm. When the materials of the semiconductor layers 26031 and 26035 are InGaN series, the active layer 26033 can emit blue light or deep blue light with a peak wavelength between 400 nm and 490 nm, or green light with a peak wavelength between 490 nm and 550 nm. When the material of the semiconductor layers 26031 and 26035 is AlGaN series, the active layer 26033 can emit ultraviolet light with a peak wavelength between 250 nm and 400 nm.

[0306] In this embodiment, the first-type semiconductor layer 26031 and the second-type semiconductor layer 26035 include a DBR structure, so that the light emitted by the active layer 26033 can be reflected back and forth between the two DBR structures to form coherent light, and then the coherent light is emitted from the direction of the first-type semiconductor layer 26031 to form laser light L26.

[0307] 26 , the insulating layer 26036 is located between the back conductive structure 26032 and the second-type semiconductor layer 26035. In one embodiment, the material of the protective layer 26036 includes silicon oxide.

[0308] In this embodiment, the contact resistance between the back conductive structure 26032 and the second-type semiconductor layer 26035 is less than 10 -4 Ωcm 2 , and an ohmic contact is formed between the back conductive structure 26032 and the second-type semiconductor layer 26035. The mechanism for forming an ohmic contact is that the metal work function must be smaller than the semiconductor work function, allowing electrons from the semiconductor to the metal and vice versa to easily jump across this energy level, enabling bidirectional current conduction. For example, the metal component of the second conductive electrode 26032D of the back conductive structure 26032 is primarily a titanium-aluminum alloy. This is because titanium can form titanium nitride with the Group III-V compound (e.g., aluminum gallium nitride) of the second-type semiconductor layer 26035, causing nitrogen atoms on the surface to become n-type doped. After high-temperature annealing, a good ohmic contact is formed, but this is not limited to this.

[0309] In this embodiment, as shown in FIG26 , the first-type semiconductor layer 26031 is connected to the positive conductive structure 26030, which is connected to the conductive electrode 26032C via the second channel 26320. The conductive electrode 26032D and the conductive electrode 26032C are separated from each other to prevent short circuits. The second-type semiconductor layer 26035 is connected to the second conductive electrode 260324. To prevent the conductive medium filled in the second channel 26320 from contacting the second-type semiconductor layer 26035 of the laser unit 26003 and thus forming a short circuit, the laser unit 26003 further includes an insulating layer 26340 located on the inner wall of the second channel 26320. Through this conductive structure, the laser unit 26003 receives external driving voltage / current and generates laser light L26. Positive conductive structure 26030 is located on light-emitting side 26003S of laser unit 26003 and is connected to adhesive layer 26002. Therefore, laser light L26 emitted by laser unit 26003 passes through adhesive layer 26002 and transparent substrate 26001 and is output to the outside world. It should be noted that transparent substrate 26001 is transparent to light L26 from laser unit 26003. Therefore, objects beneath transparent substrate 26001 do not need to be clearly visible to the naked eye, and can be UV light, visible light, or infrared light, but this application is not limited thereto.

[0310] In one or more embodiments, when a time-of-flight ranging module including a laser element 26000 is applied to a living object (e.g., a human face or eye), the coherent light emitted by the laser element 26000 has a relatively high energy, necessitating a corresponding optical element (e.g., a transparent substrate) to process the coherent light and output laser light L26 of appropriate intensity. To effectively monitor the laser element 26000 for damage and prevent the laser light L26, which has not been optically processed by the transparent substrate 26001, from leaking directly into the human eye, the laser element 26000 of this embodiment includes an eye safety monitoring circuit that can instantly detect abnormal damage to the light-emitting side 26003S of the laser unit 26003. The following examples illustrate the operating principles of the laser element 26000 in some embodiments.

[0311] Continuing with this embodiment, as shown in FIG. 26 , in addition to the aforementioned semiconductor structures required for emitting laser light, the laser unit 26003 further includes a back conductive structure 26032. This back conductive structure 26032 includes a plurality of detection electrodes 26032A and 26032B, and is disposed on opposite sides of the laser unit 26003, opposite the front conductive structure 26030. A plurality of first trenches 26034 extend from the back conductive structure 26032, penetrate the front conductive structure 26030 and the adhesive layer 26002, and connect to the conductive layer 26010. In other words, in this embodiment, the ends of the first trenches 26034 are respectively connected to the plurality of detection electrodes 26032A and 26032B and the conductive layer 26010. In some embodiments, a plurality of separated detection electrodes 26032A and 26032B are connected across the conductive layer 26010 via a first channel 26034. Therefore, by connecting the plurality of detection electrodes 26032A and 26032B to an external control circuit, changes in the resistance of the conductive layer 26010 can be monitored in real time. When the laser element 26000 is damaged by external force, particularly when the light-emitting side 26003S is damaged, the conductive layer 26010 is also damaged, causing its resistance to increase, or even causing a short circuit due to damage. The control circuit, through a monitoring circuit, determines whether to cut off the power supply to the laser unit 26003 based on the change in the resistance of the conductive layer 26010. This prevents the laser light L26 emitted by the laser unit 26003 from leaking through the damaged gap in the transparent base layer 26001 and directly irradiating the human eye, thereby achieving the effect of real-time monitoring of abnormal conditions.

[0312] In this embodiment, as shown in FIG26 , in order to prevent the conductive medium filled in the first channel 26034 from contacting the positive conductive structure 26030 , the first-type semiconductor layer 26031 , or the second-type semiconductor layer 26035 of the laser unit 26003 and forming a short circuit, the laser unit 26003 further includes an insulating layer 26340 located between the inner wall of the laser unit 26003 and the first channel 26034 .

[0313] In some embodiments, the back conductive structure 26032 includes a plurality of detection electrodes 26032A and 26032B and a plurality of conductive electrodes 26032C and 26032D that are separated from each other and coplanar, as shown in FIG6 . This allows the laser device to be flip-chip mounted on a substrate, such as the driver chip shown in FIG26 , without requiring a wire bonding process, thereby reducing package size. In one or more embodiments, the back conductive structure 26032 includes a plurality of detection electrodes 26032A and 26032B, and the plurality of detection electrodes 26032A and 26032B extend from the back conductive structure 26032, penetrate the front conductive structure 26030 and the adhesive layer 26002, and connect to the conductive layer 26010.

[0314] In one or more embodiments, the light-emitting device may be a laser element, as shown in Figures 27A to 27C. Figure 27B is a bottom view of the laser element 27000 shown in Figure 27A (as viewed from the direction of arrow C in Figure 27A, i.e., from the direction of the first pad structure 27902 and the second pad structure 27904), while Figure 27A is a cross-sectional schematic diagram along the line AA' in Figure 27B. Figure 27C is a top view of the laser element 27000 shown in Figure 27A, i.e., a view of the laser element 27000 viewed from the direction of the transparent substrate 27010 (as shown by arrow D in Figure 27A), and Figure 27A is a cross-sectional schematic diagram along the line BB' in Figure 27C.

[0315] Figure 27A is a schematic cross-sectional view of a semiconductor light-emitting device according to one embodiment. In this embodiment, the semiconductor light-emitting device is a laser device 27000 and includes a transparent substrate 27010 and an epitaxial structure 27020 located on one side of the transparent substrate 27010. The epitaxial structure 27020 includes at least one pillar structure P27. In this embodiment, the epitaxial structure 27020 includes multiple pillar structures P27. Each pillar structure P27 includes a first semiconductor structure 27202, a current confining layer 27205, and an active structure 27204, sequentially located on the transparent substrate 27010.

[0316] The plurality of columnar structures P27 can be arranged regularly or randomly on the second semiconductor structure 27206. The so-called regular arrangement means that the plurality of columnar structures P27 have a specific spatial relationship and are arranged in a fixed, repetitive manner. For example, in some regularly arranged columnar structures P27, the spacing between adjacent columnar structures P27 is roughly the same; in other regularly arranged columnar structures P27, the plurality of columnar structures P27 are arranged along a specific direction. Each columnar structure P27 includes an upper surface P271 facing the transparent base layer 27010 and a side surface P272 connecting the upper surface P271 and the second semiconductor structure 27206. In addition, the epitaxial structure 27020 also includes a lower surface 27206B away from the transparent base layer 27010, and the lower surface 27206B is the surface of the second semiconductor structure 27206. In this embodiment, the conductivity type of the first semiconductor structure 27202 is P-type, while the conductivity type of the second semiconductor structure 27206 is N-type. For simplicity, FIG27A illustrates only five pillar structures P27. However, in actual VCSEL products, the number of pillar structures P27 can be adjusted based on the current and power requirements of the application, for example, 100 to 1000, but not limited to this.

[0317] In this embodiment, as shown in Figures 27A to 27C , the current confining layer 27205 can be selectively located between the active structure 27204 and the first semiconductor structure 27202, or between the active structure 27204 and the second semiconductor structure 27206. The current confining layer 27205 includes a current confining region 27205B and a current conducting region 27205A surrounded by the current confining region 27205B. The current conducting region 27205A has a higher conductivity than the current confining region 27205B, so that the current is concentrated in the current conducting region 27205A.

[0318] In this embodiment, as shown in Figures 27A to 27C , the first semiconductor structure 27202 and the active structure 27204 partially cover the second semiconductor structure 27206, exposing an end surface 27206A of the second semiconductor structure 27206. The laser device 27000 further includes a first insulating layer 27032 and a first metal connection layer 27034. The first insulating layer 27032 covers the side surfaces P272 of the columnar structure P27, the end surfaces 27206A of the second semiconductor structure 27206, and a portion of the upper surface P271 of the columnar structure P27. The first insulating layer 27032 has a plurality of first openings 27322, exposing a portion of the upper surface P271 from the first insulating layer 27032. The first metal connection layer 27034 is located on the first insulating layer 27032 and is electrically connected to the first semiconductor structure 27202 through the first openings 27322. The first metal connection layer 27034 has a plurality of second openings 27342, allowing light emitted from the active structure 27204 to be emitted from the second openings 27342 toward the transparent substrate 27010 and out of the laser element 27100. Furthermore, the second semiconductor structure 27206 has a first side S271 and a second side S272 opposite the first side S11. The first metal connection layer 27034 has a first protrusion 27341a extending beyond the first side S271 and a second protrusion 27341b extending beyond the second side S272. The first protrusion 27341a and the second protrusion 27341b can be used for subsequent electrical connections. The detailed structure and electrical connection method will be described in detail below.

[0319] In this embodiment, as shown in Figures 27A to 27C , the laser device 27000 further includes an adhesive layer 27040. The epitaxial structure 27020 is connected to the transparent substrate 27010 via the adhesive layer 27040. A second metal connection layer 27050 is provided on the second semiconductor structure 270206, which is remote from the transparent substrate 27010. The second metal connection layer 27050 is electrically connected to the second semiconductor structure 27206. The laser device 27000 of the present application includes a second insulating layer 27060, which covers the second metal connection layer 27050. The second insulating layer 27060 has two side portions 27060A. Four openings (a first opening 27602a, a second opening 27602b, a third opening 27602c, and a fourth opening 27602d) further penetrate the second insulating layer 27060. Side portion 27060A covers the first side S271 and the second side S272 of the second semiconductor structure 27206. A first opening 27602a further penetrates the first insulating layer 27032 to expose the first protrusion 27341a of the first metal connection layer 27034, and a second opening 27602b further penetrates the first insulating layer 27032 to expose the second protrusion 27341b of the first metal connection layer 27034. The second insulating layer 27060 also has a fifth opening 27603 that exposes the second metal connection layer 27050. The laser device 27000 of the present application includes a first electrode 27702 and a second electrode 27704. The first electrode 27702 and the second electrode 27704 are located on the same side of the transparent base layer 27010 and are physically separated from each other.

[0320] In this embodiment, as shown in Figures 27A to 27C , the laser device 27000 is a flip-chip laser device. The laser device 27000 can subsequently be flip-chip bonded to an external substrate (e.g., a printed circuit board or the driver chip 21010 shown in Figure 21 ) using solder via a flip-chip bonding process. The first electrode 27702 is connected to the first metal connection layer 27034 through the first opening 27602a through the fourth opening 27602d, and is electrically connected to the first semiconductor structure 27202 through the first protrusion 27341a and the second protrusion 27341b of the first metal connection layer 27034. Furthermore, the first electrode 27702 covers the side portion 27060A of the second insulating layer 27060 and extends to cover the second metal connection structure 27050. The second insulating layer 27060 is located between the first electrode 27702 and the second metal connection structure 27050 to prevent the formation of a short circuit. The second electrode 27704 is connected to the second metal connection layer 27050 through the fifth opening 27603 , thereby electrically connecting the second electrode 27704 to the second semiconductor structure 27206 .

[0321] In this embodiment, as shown in Figures 27A to 27C , the laser device 27000 of the present application may further include a first pad structure 27902 and a second pad structure 27904, each located on the first electrode 27702 and the second electrode 27704, respectively. The laser device 27000 of the present application further includes a third insulating layer 27080 covering the first electrode 27702 and the second electrode 27704. The third insulating layer 27080 has a first hole 27802 exposing the first electrode 27702 and a second hole 27804 exposing the second electrode 27704. The first pad structure 27902 is electrically connected to the first electrode 27702 through the first hole 27802, and the second pad structure 27904 is electrically connected to the second electrode 27904 through the second hole 27804. Furthermore, a gap G27 between the first pad structure 27902 and the second pad structure 27904 is between 10 μm and 200 μm. In this embodiment, as viewed from the bottom view of the laser element 27000 , the shape of the first pad structure 27902 is different from the shape of the second pad structure 27904 for electrical identification.

[0322] In this embodiment, as shown in Figures 27A to 27C , the laser element 27000 of the present application may optionally include an anti-reflection structure 27101 located on the transparent substrate 27010 and away from the first electrode 27702 and the second electrode 27704. The anti-reflection structure 27101 can be used to reduce reflection of light emitted by the laser element 27000 at the interface between the transparent substrate 27010 and air, thereby preventing a decrease in the luminous efficiency of the laser element 27000 or the generation of an unintended light pattern.

[0323] In this embodiment, as shown in Figures 27A to 27C , the first semiconductor structure 27202 and the second semiconductor structure 27206 include a plurality of layers with different refractive indices that are periodically stacked alternately (e.g., a high-aluminum-content AlGaAs layer and a low-aluminum-content AlGaAs layer that are periodically stacked alternately) to form a DBR structure. This allows light emitted from the active structure 27204 to be reflected back and forth between the two DBR structures to form coherent light. The reflectivity of the first semiconductor structure 27202 is lower than that of the second semiconductor structure 27206, thereby directing the coherent light toward the transparent substrate 27010. The materials of the first semiconductor structure 27202, the second semiconductor structure 27206, and the active structure 27204 include Group III and V compound semiconductors, such as AlGaInAs series, AlGaInP series, AlInGaN series, AlAsSb series, InGaAsP series, InGaAsN series, and AlGaAsP series, such as AlGaInP, GaAs, InGaAs, AlGaAs, GaAsP, GaP, InGaP, AlInP, GaN, InGaN, or AlGaN compounds. In the embodiments of the present application, unless otherwise specified, the chemical expressions include "stoichiometric compounds" and "non-stoichiometric compounds." A "stoichiometric compound" is, for example, one in which the total element content of Group III elements is the same as the total element content of Group V elements, whereas a "non-stoichiometric compound" is, for example, one in which the total element content of Group III elements is different from the total element content of Group V elements. For example, the chemical formula AlGaInAs series means that it contains the group III elements aluminum (Al) and / or gallium (Ga) and / or indium (In), and the group V element arsenic (As), wherein the total element content of the group III elements (aluminum and / or gallium and / or indium) can be the same as or different from the total element content of the group V element (arsenic). In addition, if the compounds represented by the chemical formula are stoichiometric compounds, the AlGaInAs series means (Al y1 Ga (1-y1) ) 1-x1 In x1 As, where 0≦x1≦1, 0≦y1≦1; AlGaInP series represents (Al y2 Ga (1-y2) ) 1-x2 In x2 P, where 0≦x2≦1, 0≦y2≦1; AlInGaN series represents (Al y3 Ga (1-y3) ) 1-x3 In x3 N, where 0≦x3≦1, 0≦y3≦1; AlAsSb series represents AlAs x4 Sb(1- x4) , where 0≦x4≦1; InGaAsP series represents In x5 Ga 1-x5 As 1-y4 P y4 , where 0≦x5≦1, 0≦y4≦1; InGaAsN series represents In x6 Ga 1-x6 As 1-y5 N y5 , where 0≦x6≦1, 0≦y5≦1; AlGaAsP series represents Al x7 Ga 1-x7 As 1-y6 P y6 , where 0≦x7≦1, 0≦y6≦1.

[0324] Depending on the material, active structure 27204 can emit infrared light with a peak wavelength between 700 nm and 1700 nm, red light with a peak wavelength between 610 nm and 700 nm, yellow light with a peak wavelength between 530 nm and 570 nm, green light with a peak wavelength between 490 nm and 550 nm, blue or deep blue light with a peak wavelength between 400 nm and 490 nm, or ultraviolet light with a peak wavelength between 250 nm and 400 nm. In this embodiment, the peak wavelength of active structure 27204 is infrared light between 750 nm and 1200 nm.

[0325] The material of the current confining layer 27205 can be the aforementioned Group III-V semiconductor material. In this embodiment, as shown in Figures 27A to 27C , the material of the current confining layer 27205 is AlGaAs, and the active structure 27204, the first semiconductor structure 27202, and the second semiconductor structure 27206 are made of a material containing aluminum. The aluminum content of the current confining layer 27205 is greater than the aluminum content of the active structure 27204, the first semiconductor structure 27202, and the second semiconductor structure 27206. For example, the aluminum content of the current confining layer 27205 is greater than 97%. In this embodiment, the oxygen content of the current confining region 27205B of the current confining layer 27205 is greater than the oxygen content of the current conducting region 27205A, resulting in the current confining region 27205B having a lower conductivity than the current conducting region 27205A. The subsequent layer 27040 is a material having a high transmittance to the light emitted by the active structure 27204, such as a transmittance greater than 80%. The material of the subsequent layer 27040 is an insulating material, such as: benzocyclobutene resin (BCB), epoxy resin, polyimide, spin-on glass (SOG), silicone or octafluorocyclobutane (PFCB).

[0326] In this embodiment, as shown in Figures 27A to 27C, the first insulating layer 27032, the second insulating layer 27060 and the third insulating layer 27080 are made of non-conductive materials. The non-conductive material includes an organic material or an inorganic material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin (Acrylic Resin), cyclic olefin copolymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide) or fluorocarbon polymer (Fluorocarbon Polymer). The inorganic material includes silicone or glass, aluminum oxide (Al2O3), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x In one embodiment, the first insulating layer 27032, the second insulating layer 27060 and / or the third insulating layer 27080 include one or more layers (e.g., a Bragg reflector (DBR) structure formed by alternately stacking two sub-layers, such as SiO x Sublayer and TiO x sub-layer).

[0327] In this embodiment, as shown in Figures 27A to 27C , the materials of the first metal connection layer 27034 and the second metal connection layer 27050 may include metals such as aluminum (Al), silver (Ag), chromium (Cr), platinum (Pt), nickel (Ni), germanium (Ge), beryllium (Be), gold (Au), titanium (Ti), tungsten (W), or zinc (Zn). The materials of the first electrode 27702 and the second electrode 27704 may be metal materials such as gold (Au), tin (Sn), titanium (Ti), or alloys thereof. In this embodiment, the first electrode 27702 may have a multilayer electrode structure, for example, including a titanium (Ti) layer and a gold (Au) layer in a direction away from the transparent base layer 27010. The second electrode 27704 has the same material and structural composition as the first electrode 27702. The first pad structure 27902 and the second pad structure 27904 are made of a metal material, such as gold (Au), tin (Sn), titanium (Ti), copper (Cu), nickel (Ni), platinum (Pt), or alloys thereof. The first electrode 27702 is made of a different material than the first pad structure 27902, and the second electrode 27704 is made of a different material than the second pad structure 27904. For example, the first pad structure 27902 and the second pad structure 27904 contain an element that is absent from the first and second electrodes 27702 and 27704. This prevents external (tin-containing) solder from damaging the first and second electrodes 27702 and 27704 during die bonding or high-current operation, potentially causing electrical failure. This further improves the reliability of the laser device 27000 of the present invention. The element, such as nickel (Ni) and / or platinum (Pt), can be used to prevent solder from diffusing into the first and second electrodes 27702 and 27704. Specifically, the first pad structure 27902 and the second pad structure 27904 can each have a multi-layer structure, comprising, in order away from the transparent base layer 27010, an intermediate layer 27902A, an intermediate layer 27904A, and a bonding layer 27902B, and a bonding layer 27904B. The intermediate layers 27902A and 27904A are made of different materials than the first electrode 27702 and the second electrode 27704 to prevent solder (e.g., tin or gold-tin alloy (AuSn)) from diffusing into the first electrode 27702 and the second electrode 27704. Therefore, the material of the intermediate layers 27902A and 27904A preferably includes a metal element other than gold (Au), tin (Sn), and copper (Cu), such as nickel (Ni) and / or platinum (Pt). The material of the bonding layers 27902B and 27904B includes a highly ductile metal material, such as gold (Au). In this embodiment, the materials of the intermediate layers 27902A and 27904A are platinum (Pt) and nickel (Ni) stacked in sequence in a direction away from the transparent base layer 27010, and the material of the bonding layers 27902B and 27904B is gold (Au).In other words, in the direction away from the transparent base layer 27010, the first pad structure 27902 and the second pad structure 27904 include a nickel layer, a platinum layer and a gold layer.

[0328] 27A and 27B , the transparent base layer 27010 has a central region and a peripheral region surrounding the central region. The second insulating layer 27060 has a plurality of openings (e.g., a first opening 27602a, a second opening 27602b, a third opening 27602c, and a fourth opening 27602d) dispersed within the peripheral region of the transparent base layer 27010. Furthermore, four gaps G271-G274 are defined between the four openings. More specifically, in this embodiment, the first opening 27602a and the fourth opening 27602d are separated by a first gap G271, the first opening 2760a2 and the second opening 27602b are separated by a second gap G272, the second opening 27602b and the third opening 27602c are separated by a third gap G273, and the third opening 27602c and the fourth opening 27602d are separated by a fourth gap G274.

[0329] Furthermore, as shown in FIG27C , in this embodiment, the first metal connection layer 27034 is formed with several marking structures 27344A-27344D to facilitate machine identification and facilitate subsequent packaging processes. Marking structures 27344B and 27344D are connected and face each other to define line L1, while marking structures 27344A and 27344C are connected and face each other to define line L2. Line L1 and line L2 intersect at center position O27. Referring to FIG27B and FIG27C , marking structure 27344A corresponds to first pitch G271, marking structure 27344B corresponds to second pitch G272, marking structure 27344C corresponds to third pitch G273, and marking structure 27344D corresponds to fourth pitch G274. It should be noted that dashed lines in FIG27B and FIG27C indicate structures that are not directly visible from the bottom or top views; only the outlines of the dashed lines are visible.

[0330] In this embodiment, the second-type semiconductor structure 27206 may be located in the middle region of the transparent substrate 27010. In one embodiment, the distances from any side of the second-type semiconductor structure 27206 to an adjacent edge of the transparent substrate 27010 are substantially equal. This allows the first pad structure 27902 and the second pad structure 27904 (or the first electrode 27702 and the second electrode 27704) to be symmetrical about the line L1, facilitating structural design for subsequent packaging processes and increasing the active area. As shown in FIG27B , when viewed from the second semiconductor structure 27206 of the laser element 27000 toward the active structure 27204, the transparent substrate 27010 has a first boundary C271 adjacent to the first side S271 and a second boundary C272 opposite the first boundary C271 and adjacent to the second side S272. The first boundary C271 and the second boundary C272 correspond to each other and are each located on a side of the transparent substrate 27010. The difference between a first distance D271 between the first side S271 and the first boundary C271 and a second distance D272 between the second side S272 and the second boundary C272 is less than 30% of the first distance D271. That is, the difference between the first distance D271 and the second distance D272 is 0≦(D271-D272) / D271<30%. In another embodiment, 0≦(D271-D272) / D271<20%. Preferably, 0≦(D271-D272) / D271<15%. In another embodiment, 1%<(D271-D272) / D271<10%. In this embodiment, the first distance D271 is equal to the second distance D272.

[0331] In one or more embodiments, the light emitting device may be a semiconductor light emitting element 28000 , as shown in FIG. 28 .

[0332] FIG28 is a schematic cross-sectional view of a semiconductor light-emitting device 28000 according to one embodiment. The semiconductor light-emitting device 28000 of this embodiment is a laser diode and includes a substrate 28110, an epitaxial stack 28120 formed on the substrate 28110, and a first electrode structure 28132 and a second electrode structure 28134 located on the epitaxial stack 28120. The substrate 28110 is a high-transmittance gallium arsenide (GaAs) substrate and has a first surface 28110A and a second surface 28110B. The light-emitting surface of the semiconductor light-emitting device 28100 (indicated by the arrow in FIG28 ) is defined as the first surface 28110A. The epitaxial stack 28120 is located on the second surface 28110B of the substrate 28110 and sequentially includes a first semiconductor structure 28121 , a second semiconductor structure 28122 , an intermediate layer 28123 , a third semiconductor structure 28124 , an active structure 28126 , and a fourth semiconductor structure 28127 .

[0333] In this embodiment, as shown in FIG28 , the substrate 28110 includes a dopant to have a p-type or n-type conductivity type. Alternatively, in another embodiment, the substrate 28110 does not include a dopant or is an undoped substrate layer. The first semiconductor structure 28121 is a semiconductor material that does not include a dopant, thereby reducing the problem of light absorption by the dopant. The second semiconductor structure 28122, the intermediate layer 28123, the third semiconductor structure 28124, and the fourth semiconductor structure 28127 are semiconductor materials that include a dopant. The second semiconductor structure 28122, the intermediate layer 28123, and the third semiconductor structure 28124 have the same conductivity type, and the third semiconductor structure 28124 (or the second semiconductor structure 28122 or the intermediate layer 28123) and the fourth semiconductor structure 28127 have different conductivity types. In this embodiment, the second semiconductor structure 28122, the intermediate layer 28123, and the third semiconductor structure 28124 have a p-type conductivity type, and the fourth semiconductor structure 28127 has an n-type conductivity type. In another embodiment, the second semiconductor structure 28122, the intermediate layer 28123, and the third semiconductor structure 28124 have an n-type conductivity type, and the fourth semiconductor structure 28127 has a p-type conductivity type. The first electrode structure 28132 and the second electrode structure 28134 are located on the fourth semiconductor structure 28127. Dopants may include beryllium, magnesium, zinc, carbon, silicon, or antimony.

[0334] 28 , the third semiconductor structure 28124 or the fourth semiconductor structure 28127 optionally includes a current confining layer 28125. Alternatively, in this embodiment, the current confining layer 28125 is formed in the third semiconductor structure 28124 or the fourth semiconductor structure 28127. The current confining layer 28125 includes a current confining region 28125B and a current conducting region 28125A defined by the current confining region 28125B.

[0335] In this embodiment, as shown in FIG. 28 , the semiconductor light-emitting device 28000 further includes a recessed structure 28140 and a protective layer 28150. The recessed structure 28140 is formed within the epitaxial stack 28120. Specifically, in this embodiment, the recessed structure 28140 is formed within the fourth semiconductor structure 28127, the active structure 28126, and the third semiconductor structure 28124. In other words, in this embodiment, the recessed structure 28140 penetrates the fourth semiconductor structure 28127, the active structure 28126, and the third semiconductor structure 28124, exposing the intermediate layer 28123. The protective layer 28150 fills the recessed structure 28140 and is located between the first electrode structure 28132 and the fourth semiconductor structure 28127. The first electrode structure 28132 includes a first portion 28132A and a second portion 28132B. The first portion 28132A fills the recessed structure 28140 and contacts and electrically connects to the intermediate layer 28123. The second portion 28132B extends from the first portion 28132A and is located on the protective layer 28150. The second electrode structure 28134 is disposed on and electrically connected to the fourth semiconductor structure 28127.

[0336] In this embodiment, as shown in FIG28 , the semiconductor light emitting device 28000 optionally further includes an optical element 28160 covering the first surface 28110A of the substrate 28110. For example, the optical element 28160 may be an anti-reflection element to further reduce reflection of light emitted by the semiconductor light emitting device 28000 at the interface between the substrate 28110 and air, thereby preventing a decrease in the luminous efficiency of the semiconductor light emitting device 28000 or preventing interference between light reflected from the interface and light emitted from the semiconductor device 28000.

[0337] In this embodiment, as shown in FIG28 , the first semiconductor structure 28121, the second semiconductor structure 28122, the third semiconductor structure 28124, and the fourth semiconductor structure 28127 may each include a periodically alternating stack of multiple layers having different refractive indices (e.g., periodically alternating stacks of high-aluminum-content AlGaAs layers and low-aluminum-content AlGaAs layers) to form a distributed Bragg reflector (DBR). This allows light emitted from the active structure 28126 to be reflected in the Bragg reflector to form coherent light. The reflectivities of the first semiconductor structure 28121, the second semiconductor structure 28122, and the third semiconductor structure 28124 are lower than the reflectivity of the fourth semiconductor structure 28127, thereby directing the coherent light toward the substrate 28110. The materials of the first semiconductor structure 28121, the second semiconductor structure 28122, the third semiconductor structure 28124, the fourth semiconductor structure 28127, and the active structure 28126 include Group III and V compound semiconductors, such as AlGaInAs series, AlGaInP series, AlInGaN series, AlAsSb series, InGaAsP series, InGaAsN series, AlGaAsP series, and compounds such as AlGaInP, GaAs, InGaAs, AlGaAs, GaAsP, GaP, InGaP, AlInP, GaN, InGaN, and AlGaN. In the embodiments of the present application, unless otherwise specified, the chemical formulas include "stoichiometric compounds" and "non-stoichiometric compounds." A "stoichiometric compound" is, for example, one in which the total element content of Group III elements is the same as the total element content of Group V elements, whereas a "non-stoichiometric compound" is, for example, one in which the total element content of Group III elements is different from the total element content of Group V elements. For example, the chemical formula AlGaInAs series means that it contains the group III elements aluminum (Al) and / or gallium (Ga) and / or indium (In), and the group V element arsenic (As), wherein the total element content of the group III elements (aluminum and / or gallium and / or indium) can be the same as or different from the total element content of the group V element (arsenic). In addition, if the compounds represented by the chemical formula are stoichiometric compounds, the AlGaInAs series means (Al y1 Ga (1-y1) ) 1-x1 In x1 As, where 0≦x1≦1, 0≦y1≦1; AlGaInP series represents (Al y2 Ga (1-y2) ) 1-x2 In x2 P, where 0≦x2≦1, 0≦y2≦1; AlInGaN series represents (Al y3 Ga (1- y3)) 1-x3 In x3 N, where 0≦x3≦1, 0≦y3≦1; AlAsSb series represents AlAs x4 Sb (1-x4) , where 0≦x4≦1; InGaAsP series represents In x5 Ga 1-x5 As 1-y4 P y4 , where 0≦x5≦1, 0≦y4≦1; InGaAsN series represents In x6 Ga 1-x6 As 1-y5 N y5 , where 0≦x6≦1, 0≦y5≦1; AlGaAsP series represents Al x7 Ga 1-x7 As 1-y6 P y6 , where 0≦x7≦1, 0≦y6≦1.

[0338] Depending on the material, active structure 28126 can emit infrared light with a peak wavelength between 700 nm and 1700 nm, red light with a peak wavelength between 610 nm and 700 nm, yellow light with a peak wavelength between 530 nm and 570 nm, green light with a peak wavelength between 490 nm and 550 nm, blue or deep blue light with a peak wavelength between 400 nm and 490 nm, or ultraviolet light with a peak wavelength between 250 nm and 400 nm. In this embodiment, the peak wavelength of active structure 28126 is infrared light between 750 nm and 2000 nm.

[0339] The current limiting layer 28125 can be formed using an oxidation process or an ion implantation process. In this embodiment, when the first semiconductor structure 28121, the second semiconductor structure 28122, the third semiconductor structure 28124, the active structure 28126, and the fourth semiconductor structure 28127 comprise multiple film layers and all contain aluminum, the aluminum content of one or more layers in the third semiconductor structure 28124 can be designed to be greater than 97% (defined as the current limiting layer 28125) and greater than the aluminum content of the active structure 28126, the other film layers of the third semiconductor structure 28124, the second semiconductor structure 28122, the first semiconductor structure 28121, and the fourth semiconductor structure 28127. Consequently, after the oxidation process, the layer or layers having an aluminum content greater than 97% will be oxidized to form the current limiting region 28125B (e.g., aluminum oxide), while the unoxidized portion will become the current conducting region 28125A. During the oxidation process, oxygen passes through the recessed structure 28140 and performs an oxidation reaction on the epitaxial stack 28120 .

[0340] The materials of the first electrode structure 28132 and the second electrode structure 28134 include metal materials, such as gold (Au), tin (Sn), titanium (Ti), copper (Cu), silver (Ag), germanium (Ge), platinum (Pt), palladium (Pd), nickel (Ni) or their alloys.

[0341] In this embodiment, as shown in FIG28 , the material of the intermediate layer 28123 is different from that of the first semiconductor structure 28121, the second semiconductor structure 28122, and the third semiconductor structure 28124. The intermediate layer 28123 may be a single layer or a multilayer and serves as an etching stop layer to control the depth of the recessed structure 28140. The intermediate layer 28123 comprises a semiconductor material, such as GaAs or InGaP, and has a thickness that is an odd multiple of 1 / 4n of the peak wavelength of the light emitted by the active structure 28126, where n is the refractive index. In one embodiment, since the material of the intermediate layer 28123 is different from that of the first semiconductor structure 28121, the second semiconductor structure 28122, and the third semiconductor structure 28124, the optical properties of the semiconductor light emitting element 28000 (e.g., reflectivity, threshold current (I th ), the thickness of the intermediate layer 28123 is designed to be between 0.05 μm and 0.5 μm. In one embodiment, the intermediate layer 28123 may reduce lateral current diffusion. Therefore, the second-type semiconductor layer 28122 may serve as a current diffusion layer in addition to optical considerations. When the intermediate layer 28123 is multi-layered (for example, comprising two layers, with the first layer being InGaP and the second layer being GaAs), the combined thickness of these layers is between 0.05 μm and 0.5 μm.

[0342] In one embodiment, as shown in FIG28 , when the first semiconductor structure 28121, the second semiconductor structure 28122, and the third semiconductor structure 28124 are all distributed Bragg reflectors (DBRs), the number of pairs of periodically stacked film layers in the first semiconductor structure 28121 may be greater than, equal to, or less than that of the second semiconductor structure 28122, and / or the number of pairs of periodically stacked film layers in the first semiconductor structure 28121 may be greater than, equal to, or less than that of the third semiconductor structure 28124. In one embodiment, the number of pairs of film layers in the second semiconductor structure 28122 is less than that of the third semiconductor structure 28124. In one embodiment, the number of pairs of film layers in the first semiconductor structure 28121 may be 5 to 15 pairs, the number of pairs of film layers in the second semiconductor structure 28122 may be 2 to 5 pairs, and the number of pairs of film layers in the third semiconductor structure 28124 may be 5 to 15 pairs.

[0343] In one embodiment, as shown in Figure 28, based on the requirements of optical properties, the sum of the number of film layer pairs of the first semiconductor structure 28121, the second semiconductor structure 28122 and the third semiconductor structure 28124 is less than the number of film layer pairs of the fourth semiconductor layer 28127. For example, the sum of the number of film layer pairs of the first semiconductor structure 28121, the second semiconductor structure 28122 and the third semiconductor structure 28124 is 15 to 25 pairs, and the number of film layer pairs of the fourth semiconductor layer 28127 is 30 to 60 pairs.

[0344] In one embodiment, as shown in FIG28 , due to the manufacturing process, the P-type semiconductor layer has a lower doping concentration than the N-type semiconductor layer, and in design, the sum of the film layer logarithms of the second semiconductor structure 28122 and the third semiconductor structure 28124 is less than the film layer logarithm of the fourth semiconductor layer 28127. Therefore, the conductivity type of the first semiconductor structure 28122 and the third semiconductor structure 28124 can be designed to be P-type, and the conductivity type of the fourth semiconductor structure 28127 is n-type, thereby reducing the series resistance of the overall semiconductor light-emitting element 28000 and improving the luminous efficiency.

[0345] FIG29 is a schematic cross-sectional view illustrating a semiconductor light-emitting device 29000 according to one embodiment. In this embodiment, semiconductor light-emitting device 29000 includes a substrate 29010, and an epitaxial structure 29020 and an epitaxial structure 29030 located on one side of substrate 29010. Epitaxial structure 29020 and epitaxial structure 29030 are separated by a predetermined distance and do not contact each other, but the present invention is not limited thereto. Semiconductor light-emitting device 29000 also includes a metal connection layer 29040 located between epitaxial structure 29020 and substrate 29010, and between epitaxial structure 29030 and substrate 29010. The semiconductor light-emitting element 29000 also includes an electrode structure 29050, an electrode structure 29060, an electrode structure 29070 and an electrode structure 29080. The electrode structure 29050 and the electrode structure 29060 are located on the surface 29020A of the epitaxial structure 29020 away from the substrate 29010, and the electrode structure 29070 and the electrode structure 29080 are located on the surface 29030A of the epitaxial structure 29030 away from the substrate 29010; the electrode structure 29050 and the electrode structure 29060 are respectively connected to a semiconductor layer with the same conductivity, and the electrode structure 29070 and the electrode structure 29080 are respectively connected to a semiconductor layer with the same conductivity.

[0346] The epitaxial structure 29020 includes multiple (two in the embodiment shown in Figure 29, but the present invention is not limited to this) epitaxial columnar structures P291, P292 and a platform structure 29226, and the epitaxial structure 29030 includes multiple (two in the embodiment shown in Figure 29, but the present invention is not limited to this) epitaxial columnar structures P293, P294 and a platform structure 29326; wherein, the epitaxial columnar structures P291, P292 and the epitaxial columnar structures P293, P294 have the same or substantially the same structure. In this embodiment, each epitaxial columnar structure P291 (P292) includes a semiconductor structure 29222, a current confining layer 29225, and an active region 29224, which are sequentially located on a substrate 29010. Multiple epitaxial columnar structures P291 and P292 are located between a platform structure 29226 and the substrate 29010 and are arranged regularly or irregularly. Similarly, epitaxial columnar structure P293 (P294) of epitaxial structure 29030 includes a semiconductor structure 29322, a current confining layer 29325, and an active region 29324, which are sequentially located on the substrate 29010. Multiple epitaxial columnar structures P293 and P294 are located on the platform structure 29326 and are arranged regularly or irregularly. The term "regular arrangement" as used in this application means that multiple epitaxial columnar structures have a specific spatial relationship with each other and are arranged in a fixed, repetitive manner. In some regularly arranged epitaxial columnar structures, the spacing between adjacent epitaxial columnar structures is approximately the same; in other regularly arranged epitaxial columnar structures, multiple epitaxial columnar structures are arranged along a specific direction. In the present application, the current limiting layer 29225 or the current limiting layer 29325 can be respectively arranged between the active structure 29224 and the semiconductor structure 29222, and between the active structure 29324 and the semiconductor structure 29322, as shown in the embodiment of Figure 29; alternatively, the current limiting layers 29225 and 29325 can also be respectively arranged between the active structure 29224 and the platform structure 29226, and between the active structure 29324 and the platform structure 29326. In one embodiment, current confining layers 29225 and 29325 are disposed between active structure 29224 and semiconductor structure 29222, between active structure 29324 and semiconductor structure 29322, between active structure 29224 and terrace structure 29226, and between active structure 29324 and terrace structure 29326. That is, multiple current confining layers may be disposed in epitaxial structure 29020 and / or epitaxial structure 29020. Terrace structure 29226 and terrace structure 29326 have semiconductor structures, and the semiconductor structures of terrace structure 29226 and terrace structure 29326 have substantially the same composition.In this embodiment, semiconductor structure 29222 and semiconductor structure 29322 have the same conductivity type (e.g., P-type), while the semiconductor structure of mesa structure 29226 and the semiconductor structure of mesa structure 29326 have the same conductivity type (e.g., N-type). Furthermore, semiconductor structure 29222 and the semiconductor structure of mesa structure 29226 have opposite conductivity types, and semiconductor structure 29322 and the semiconductor structure of mesa structure 29326 have opposite conductivity types. In this embodiment, mesa structure 29226 has a width W291, and mesa structure 29326 has a width W292 that is the same as width W291. In other embodiments, width W291 may be greater than or less than width W292.

[0347] Referring to FIG. 29 , in this embodiment, epitaxial columnar structures P291, P292, and epitaxial columnar structures P293, P294 each have a corresponding contact structure 29220 and contact structure 29320 on their surfaces near substrate 29010. Contact structures 29220 and 29320 may be, for example, multilayer metal structures. The multilayer metal structure contacting the P-type semiconductor structure may be Ti / Pt / Au, while the multilayer metal structure contacting the N-type semiconductor structure may be Au / GeAu / Au, but the present invention is not limited thereto. Contact structures 29220 and 29320 connect to semiconductor structures 29222 and 29322, respectively. From a top view, contact structures 29220 and 29320 appear ring-shaped.

[0348] Referring to FIG. 29 , the semiconductor light-emitting device 29000 of this embodiment further includes an insulating layer 29090 covering the sides and portions of the top surfaces of each of the epitaxial columnar structures P291 and P292, and the sides and portions of the top surfaces of each of the epitaxial columnar structures P293 and P294. Insulating layer 29090 is transparent to light emitted from each of the epitaxial columnar structures. Specifically, insulating layer 29090 has a plurality of insulating layer openings 29090A, thereby exposing contact structures 29220 on epitaxial structure 29020 and contact structures 29320 on epitaxial structure 29030. In this embodiment, insulating layer openings 29090A are annular in shape when viewed from above. Metal connection layer 29040 overlies insulating layer 29090. In this embodiment, metal connection layer 29040 is located between epitaxial structure 29020 and epitaxial structure 29030. Metal connection layer 29040 is electrically connected to contact structure 29220 and contact structure 29320 through insulating layer opening 29090A. Metal connection layer 29040 has a plurality of connection layer openings 29040A located above epitaxial columnar structures P291, P292, P293, and P294. This allows light emitted from active structure 29224 and active structure 29324 to be emitted toward substrate 29010 through connection layer openings 29040A. Referring also to FIG. 29 , the semiconductor light-emitting device 29000 of this embodiment further includes a spacer 29040B located between the epitaxial columnar structure P292 and the epitaxial columnar structure P293, separating the connecting layer 29040 therebetween. Spacer 40B is a schematic cross-sectional view of the long groove-like structure between the connecting layer 29040 in the light-emitting region 100A and the connecting layer 29040 in the light-emitting region 29000B. The semiconductor light-emitting device 29000 of this embodiment further includes an adhesive layer 29901, which connects the epitaxial structure 29020 and the epitaxial structure 29030 to the substrate 29010. The substrate 29010 and the adhesive layer 29901 are transparent to light emitted from each epitaxial columnar structure. The insulating layer 29090 further has a plurality of insulating layer openings 29090B. When viewed from above, the insulating layer openings 29090B are, for example, circular in shape, and the metal connection layer 29040 fills the openings therebetween to form conduction with the underlying structure, which will be explained in more detail below.

[0349] Referring to FIG. 29 , a semiconductor light-emitting device 29000 of this embodiment includes an electrode connection layer 29420 and an electrode connection layer 29520 located on the sides of platform structures 29226 and 29326, respectively, away from substrate 29010. Electrode connection layers 29420 and 29520 are electrically connected to the semiconductor structure and the semiconductor structure, respectively. Semiconductor light-emitting device 29000 includes an insulating layer 29082, which covers the sides and portions of the surfaces of electrode connection layers 29420 and 29520, as well as the sides and portions of the surfaces of platform structures 29226 and 29326. Specifically, the insulating layer 29082 has a side portion 29821 , an upper portion 29822 and a plurality of openings 29082A, wherein the electrode connection layer 29420 and the electrode connection layer 29520 are exposed through the openings 29082A and are electrically connected to the electrode structure 29050 and the electrode structure 29070 through the openings 29082A. The epitaxial structure 29020 has a through hole 29201 passing through the platform structure 29226, and the epitaxial structure 29030 has a through hole 29301 passing through the platform structure 29326. The insulating layer 29082 fills the through hole 29201 and the through hole 29301, and the insulating layer 29082 also includes multiple openings 29082B respectively located in the through hole 29201 and the through hole 29301. The conductive layer 29421 fills the opening 29082B in the through hole 29201, and the conductive layer 29422 fills the opening 29082B in the through hole 29301, and the conductive layer 29421 and the conductive layer 29422 are electrically connected to the metal connection layer 29040 through the insulating layer opening 29090B and the opening 29082B. In this embodiment, the electrode structure 29060 is connected to the conductive layer 29421 and electrically connected to the metal connection layer 29040 on the epitaxial structure 29020 ; the electrode structure 29080 is connected to the conductive layer 29422 and electrically connected to the metal connection layer 29040 on the epitaxial structure 29030 .

[0350] Please refer to Figure 29. The semiconductor light-emitting element 29000 of this embodiment also includes an insulating layer 29084, which covers the side 29821 and a portion of the upper portion 29822 of the insulating layer 29082, and has a plurality of openings 29084A and a plurality of openings 29084B corresponding to the plurality of openings 29082A and the plurality of openings 29082B respectively; the electrode structure 29050 and the electrode structure 29070 are electrically connected to the electrode connection layer 29420 and the electrode connection layer 29520 respectively through the opening 29084A, and the electrode structure 29060 and the electrode structure 29080 are electrically connected to the metal connection layer 29040 through the opening 29084B.

[0351] 29 , in this embodiment, the conductivity type of semiconductor structure 29222 and semiconductor structure 29322 is P-type, while the conductivity type of semiconductor structure (platform 29226) and semiconductor structure (platform 29326) is N-type. Since electrode structure 29060 and electrode structure 29080 are electrically connected to metal connection layer 29040, and metal connection layer 29040 is electrically connected to semiconductor structure 29222 and semiconductor structure 29322, electrode structure 29060 and electrode structure 29080 are P-electrodes. Electrode structure 29050 and electrode structure 29070 are electrically connected to their corresponding semiconductor structures, and therefore, electrode structure 29050 and electrode structure 29070 are both N-electrodes. The electrical properties of epitaxial structure 29020 are controlled by electrode structure 29050 and electrode structure 29060, and the electrical properties of epitaxial structure 29030 are jointly controlled by electrode structure 29070 and electrode structure 29080. In addition, the electrode structures 29050, 29060, 29070, and 29080 are separated from each other, so epitaxial structure 29020 and epitaxial structure 29030 can be independently controlled. For example, epitaxial structure 29020 or epitaxial structure 29030 can be lit up separately.

[0352] For the sake of simplicity, FIG29 uses two epitaxial structures (epistructure 29020 and epitaxial structure 29030), and each epitaxial structure includes two epitaxial columnar structures (epistructure 29020 has two epitaxial columnar structures P291 and P292, and epitaxial structure 29030 has two epitaxial columnar structures P293 and P294) as an example. However, in actual product applications, the number of epitaxial structures and epitaxial columnar structures can be adjusted (for example, but not limited to, 10 to 1000) according to the current and power requirements of the semiconductor light-emitting element (such as VCSEL) when it is used. The current limiting layer 29225 includes a current limiting region 29225B and a current conducting region 29225A. The current limiting region 29225B surrounds the current conducting region 29225A. The conductivity of the current conducting region 29225A is higher than that of the current limiting region 29225B, so that the current is concentrated in the current conducting region 29225A. Similarly, the current limiting layer 29325 includes a current limiting region 29325B and a current conducting region 29325A. The current limiting region 29325B surrounds the current conducting region 29325A. The conductivity of the current conducting region 29325A is higher than that of the current limiting region 29325B.

[0353] 29 , the semiconductor light emitting element 29000 in this embodiment is a flip-chip vertical cavity surface emitting laser (VCSEL) element. The semiconductor light emitting element 29000 can be subsequently bonded to an external circuit substrate (eg, a printed circuit board) using solder.

[0354] Referring to FIG. 29 , in this embodiment, electrode structure 29050 may be a multilayer structure. Moving away from substrate 29010, electrode structure 29050 may include, for example, a titanium (Ti) layer and a gold (Au) layer, or a titanium (Ti) layer and a platinum (Pt) layer and a gold (Au) layer, or a titanium tungsten (TiW) layer and a gold (Au) layer. Electrode structure 29050 includes an intermediate layer 29502 and a bonding layer 29504; electrode structure 29060 includes an intermediate layer 29602 and a bonding layer 29604; electrode structure 29070 includes an intermediate layer 29702 and a bonding layer 29704; and electrode structure 29080 also includes an intermediate layer 29802 and a bonding layer 29804. Electrode structures 29050, 29060, 29070, and 29080 may contain at least one element, while electrode connection layers 29420, 29520, and conductive layers 29421, 29422 do not contain that element. This prevents external (tin-containing) solder from damaging electrode connection layers 29420, 29520, and conductive layers 29421, 29422 during die bonding or high-current operation, thereby further improving the reliability of semiconductor light-emitting device 29000 of the present application. The aforementioned element, such as nickel (Ni) and / or platinum (Pt), can be used to prevent solder from diffusing into electrode connection layers 29420, 29520, and conductive layers 29421, 29422. Specifically, electrode structure 29050, electrode structure 29060, electrode structure 29070 and electrode structure 29080 may respectively include multiple layers. For example, the materials of intermediate layer 29502, intermediate layer 29602, intermediate layer 29702 and intermediate layer 29802 are different from those of electrode connection layer 29420, electrode connection layer 29520 and conductive layer 29421, conductive layer 29422, thereby preventing solder (for example, tin or gold-tin alloy (AuSn)) from diffusing into electrode connection layer 29420, electrode connection layer 29520 and conductive layer 29421, conductive layer 29422. Therefore, the materials of intermediate layer 29502, intermediate layer 29602, intermediate layer 29702 and intermediate layer 29802 preferably include metal elements other than gold (Au), tin (Sn) and copper (Cu), such as nickel (Ni) and / or platinum (Pt). Bonding layer 29504, bonding layer 29604, bonding layer 29704, and bonding layer 29804 comprise a highly ductile metal material, preferably gold (Au). In other words, referring to FIG. 29 , moving away from substrate 29010, electrode structure 29050, electrode structure 29060, electrode structure 29070, and electrode structure 29080 may comprise, in order, a nickel layer, a platinum layer, and a gold layer, respectively.In another embodiment, the electrode structure 29050 , the electrode structure 29060 , the electrode structure 29070 , and the electrode structure 29080 may include only the bonding layer 29504 , the bonding layer 29604 , the bonding layer 29704 , and the bonding layer 29804 , respectively.

[0355] In one or more embodiments, the light-emitting device may be a semiconductor light-emitting element 30000, as shown in Figures 30A to 30E. Referring to Figures 30C to 30E, schematic cross-sectional views of the semiconductor light-emitting element 30000 of the present application are shown. Figure 30C schematically illustrates the cross-sectional structure along line 30C-30C' in Figure 30A, Figure 30D schematically illustrates the cross-sectional structure along line 30D-30D' in Figure 30A, and Figure 30E schematically illustrates the cross-sectional structure along line 30E-30E' in Figure 30A. The semiconductor light-emitting element 30000 of this embodiment has a similar composition to the semiconductor light-emitting element 29000 shown in Figure 29.

[0356] Please refer to Figures 30A to 30E , which are schematic bottom perspective views, top perspective views, and cross-sectional views of a semiconductor light-emitting device 30000 according to an exemplary embodiment. In this embodiment, as shown in Figure 30C , the semiconductor light-emitting device 30000 includes a base layer 30010, an adhesive layer 30901, a plurality of epitaxial columnar structures P30 (P3011-P3014), and a mesa structure 30226. The epitaxial columnar structures P30 are formed on the mesa structure 30226 and bonded to the base layer 30010 via the adhesive layer 30901. The semiconductor light-emitting element 30000 further includes a metal connection layer 30040, which is located between the epitaxial columnar structure P30 and the base layer 30010, and the metal connection layer 30040 is electrically connected to the first semiconductor structure 30222 of each epitaxial columnar structure P30 (P3011~P3014), and the insulating layer 30090 is located between the metal connection layer 30040 and the columnar structure P30.

[0357] In this embodiment, as shown in Figures 30B to 30E , the semiconductor light-emitting device 30000 further includes electrode structures 30050A, 30050B, 30060A, 30060B, 30070A, 30070B, 30080A, and 30080B. In this embodiment, as shown in Figure 30B , the electrode structures 30050A, 30050B, 30060A, 30060B, 30070A, 30070B, 30080A, and 30080B of the semiconductor light-emitting device 30000 are located outside the light-emitting regions 30000A, 30000B, 30000C, and 30000D, and the electrode structures do not overlap with the light-emitting regions. Specifically, in this embodiment, the structure of the semiconductor light-emitting device comprises a light-emitting region structure and a non-light-emitting region structure. The structure of the light-emitting area of ​​the semiconductor light-emitting element 30000 includes four light-emitting areas 30000A, 30000B, 30000C, and 30000D, and the structure of the non-light-emitting area of ​​the semiconductor light-emitting element 30000 includes electrode structures 30050A, 30050B, 30060A, 30060B, 30070A, 30070B, 30080A, and 30080B, but the number of light-emitting areas and the number of electrode structures of the present invention are not limited to this. In this embodiment, as shown in FIG30B , electrode structures 30050A and 30060A located outside light-emitting region 30000A control light-emitting region 30000A; electrode structures 30070A and 30080A located outside light-emitting region 30000B control light-emitting region 30000B; electrode structures 30070B and 30080B located outside light-emitting region 30000C control light-emitting region 30000C; and electrode structures 30050B and 30060B located outside light-emitting region 30000D control light-emitting region 30000D. In this embodiment, as shown in FIG30B , multiple electrode structures 30050A, 30060A, 30070A, 30080A, 30050B, 30060B, 30070B, and 30080B are separated from one another.

[0358] In this embodiment, the semiconductor light-emitting device 30000 may optionally further include a heat-conducting structure TP30 located on the back surfaces of the plurality of light-emitting regions 30000A, 30000B, 30000C, and 30000D to conduct heat generated by each light-emitting region to the outside world, thereby enhancing the heat dissipation efficiency of the semiconductor light-emitting device 30000. The heat-conducting structure TP30 may be made of, for example, a metal heat-conducting structure, and the distribution area of ​​the heat-conducting structure TP30 may encompass the corresponding area of ​​all epitaxial columnar structures P30 to facilitate heat conduction and dissipation from each light-emitting region, but the present invention is not limited thereto. In one embodiment, for example, the electrode structure 30060A and the electrode structure 30080A may have an interconnecting structure that is electrically conductive to each other, so that the electrode structure 30060A and the electrode structure 30080A form a common electrode structure. In another embodiment, for example, the electrode structure 30060A and the electrode structure 30080B located at the diagonal position, or the electrode structure 30060B and the electrode structure 30080A located at the diagonal position may have an internal connection structure that is electrically conductive with each other to form two electrode structures with different electrical properties, thereby further improving the current distribution, but the present invention is not limited to this.

[0359] As shown in FIG30C , the four epitaxial columnar structures (corresponding to the light-emitting apertures) P301, P302, P303, and P304 of the light-emitting region 30000A are located above the same platform structure 30226. Electrical control signals pass through electrode structures 30050A and 30060A located outside the platform structure 30226 to control the light-emitting state of the light-emitting region 30000A. In this embodiment, electrode structure 30050A is electrically connected to the semiconductor structure (corresponding to the platform structure 30226) via electrode connection layer 30420. Electrode structure 30060A is connected to conductive layer 30421, thereby electrically connecting to the metal connection layer 30040 of the semiconductor light-emitting element 30000. In this embodiment, the semiconductor light-emitting element 30400 also includes a thermally conductive structure TP30, which is disposed on the insulating layer 30084 to conduct heat dissipation.

[0360] 30D shows epitaxial columnar structures P3015 , P3016 , P3021 , and P3022 located in different light-emitting regions 30000A and 30000B, wherein the epitaxial columnar structures P3015 and P3016 are located on the platform structure 30226 , and the epitaxial columnar structures P3021 and P3022 are located on the platform structure 30326 . As shown in FIG30D , electrode structures 30050A and 30070A are electrically connected to platform structures 30226 and 30326, respectively. Electrode structures 30050A and 30070A are not electrically connected to each other (i.e., they are isolated by insulating layer 30084). This allows electrical control signals to pass through electrode structures 30050A and 30070A outside of light-emitting regions 30000A and 30000B, respectively, to control the light-emitting states of light-emitting regions 30000A and 30000B. Similarly, thermally conductive structures TP30 are disposed on insulating layer 30084 and encompass all areas where epitaxial columnar structures P30 are located, providing heat conduction and dissipation for each light-emitting region.

[0361] In the cross-sectional structure shown in FIG30E , epitaxial columnar structures P3023 and P3024 in light-emitting region 30000B and epitaxial columnar structures P3031 and P3032 in light-emitting region 30000C are located on the same platform structure 30326. As shown, electrode structures 30080A and 30080B, located outside light-emitting region 30000B and 30000C, respectively, are not electrically connected to each other, allowing the light-emitting states of light-emitting region 30000B and light-emitting region 30000C to be independently controlled. Similarly, thermally conductive structure TP30 is provided on insulating layer 30084 to conduct heat away from the light-emitting region. As shown in FIG30E , a spacer 30040B is also formed in the metal connection layer 30040 on the platform structure 30226 to separate the metal connection layer 30040 into mutually separated portions 30040a and 30040b, i.e., a groove structure is formed between the portions 30040a and 30040b and a portion of the surface of the insulating layer 30090 is exposed.

[0362] 30A to 30E , in this embodiment, the electrode structures 30050A, 30060A, 30070A, 30080A, and 30080B may each include an intermediate layer (eg, intermediate layers 30502A and 30702A) and a bonding layer (eg, bonding layers 30504A and 30704A).

[0363] In this embodiment, as shown in Figures 30A to 30E , the semiconductor light emitting element 30000 is a flip-chip laser element. Subsequently, the semiconductor light emitting element 30000 can be bonded to an external carrier (e.g., a printed circuit board or a driver chip 21010 as shown in Figure 21 ) using solder via a flip-chip bonding process. In one or more embodiments, the light emitting device can be a semiconductor light emitting element 31000 , as shown in Figure 31 .

[0364] According to the present application, the selection and configuration design of the insulating layer material can be further utilized to reduce the overall capacitance of the semiconductor light emitting device, thereby improving the operating efficiency of the semiconductor light emitting device. Please refer to Figure 31, which is a cross-sectional schematic diagram of a semiconductor light emitting device 31000 according to one embodiment.

[0365] As shown in FIG31 , the semiconductor light-emitting device 31000 of this embodiment further includes a metal connection layer 31040 positioned between the epitaxial structure 31720 and the substrate 31010, and between the epitaxial structure 31730 and the substrate 31010. As shown in FIG31 , the semiconductor light-emitting device 31000 of this embodiment further includes an adhesive layer 31901, and the epitaxial structure 31720 and the epitaxial structure 31730 are connected to the substrate 31010 via the adhesive layer 31901. As shown in FIG31 , the semiconductor light-emitting device 31000 of this embodiment further includes an insulating layer 31090, which covers the sides and a portion of the top surface of each epitaxial columnar structure P311 and P312, and the sides and a portion of the top surface of each epitaxial columnar structure P313 and P314. The insulating layer 31090 is transparent to light emitted from each epitaxial columnar structure. As shown in FIG31 , the semiconductor light-emitting device 31000 of this embodiment further includes an insulating layer 31084. The insulating layer 31084 covers the sides and portions of the surfaces of the electrode structures 31770 and 31780, as well as the sides and portions of the surfaces of the platform structures 31226 and 31326. As shown in FIG31 , the semiconductor light-emitting device 31000 of this embodiment includes an electrode connection layer 31242 and an electrode connection layer 31342, respectively, located on the sides of the platform structures 31226 and 31326, respectively, away from the substrate 31010. The electrode connection layers 31242 and 31342 are electrically connected to the epitaxial structure 31720 and the epitaxial structure 31730, respectively.

[0366] In the embodiment shown in FIG31 , the electrode structures 31770 and 31780 of the semiconductor light-emitting device 31000 are located outside the epitaxial structures 31720 and 31730. Specifically, in this embodiment, the electrode structure 31770 is located on the side of the epitaxial structure 31720 that is close to the side edge 31010A of the substrate 31010, while the electrode structure 31780 is located on the side of the epitaxial structure 31730 that is close to the side edge 31010B of the substrate 31010. In this embodiment, the electrode structures 31770 and 31780 are located outside the electrode structures 31750 and 31760, respectively, as shown in FIG31 . Furthermore, each electrode structure 31750 and 31760 includes an intermediate layer and an adhesive layer. In this embodiment, as shown in FIG31 , the semiconductor light emitting element 31000 is a flip-chip laser element, which can be subsequently bonded to an external carrier (such as a printed circuit board or a driver chip 21010 as shown in FIG21 ) using solder through a flip-chip bonding process.

[0367] In the embodiment shown in FIG31 , epitaxial columnar structures P311 and P312 have a width W311, and platform structures 31726 and platform structures 31736 have a width W312. In some embodiments, width W311 is smaller than width W312; in other words, in some embodiments, platform structures 31726 and platform structures 31736 are formed as elevated platforms with their outer sides protruding beyond epitaxial columnar structures P311 and P312, thereby forming a two-stage elevated platform structure with epitaxial columnar structures P311 and P312.

[0368] Alternatively, as shown in the present embodiment in FIG31 , the width W312 of the platform structure 31726 and the platform structure 31736 of the semiconductor light-emitting element 31000 is equal to or close to the width W311 of the epitaxial columnar structures P311 and P312, that is, the width w312 is equal to the width w311; in other words, in this embodiment, the platform structure 31726 and the platform structure 31736 and the epitaxial columnar structures P311 and P312 form a platform of the same segment, so the epitaxial structure 31720 and the epitaxial structure 31730 do not have a two-stage platform structure.

[0369] In the embodiment shown in FIG31 , because epitaxial structure 31720 and epitaxial structure 31730 each form a mesa structure and their electrode structures 31770 and electrode structures 31780 are disposed outside epitaxial structure 31720 and epitaxial structure 31730, the depth and width of the gap between epitaxial structure 31720 and epitaxial structure 31730 are greater than those of conventional semiconductor light-emitting devices. Therefore, the present application uses a low-k dielectric material (e.g., spin-on-glass (SOG)) as the insulating material for insulating layer 31782 in semiconductor light-emitting device 31000.

[0370] Therefore, the adhesive layer not only easily fills the gap between epitaxial structure 31720 and epitaxial structure 31730, but also allows epitaxial structures 31720, 31730, and the insulating layer 31782 therebetween to form a co-planarized surface 31720B, thereby flattening the entire device surface to facilitate metal layer distribution and reduce resistance. Furthermore, the adhesive layer can serve as a buffer layer to protect the chip during the subsequent die attach process. Furthermore, the use of the adhesive layer can increase the thickness of the semiconductor light-emitting device, further reducing the overall capacitance of the semiconductor light-emitting device 31000.

[0371] In one or more embodiments, the light emitting device may be a semiconductor light emitting element, as shown in Figures 32A to 32C. Figure 32A is a schematic top perspective view of a semiconductor light emitting element 32000 according to one embodiment, while Figures 32B and 32C are schematic cross-sectional views taken along lines 32B-32B' and 32C-32C' in Figure 32A, respectively. In this embodiment, as shown in Figures 32B and 32C, the semiconductor light emitting element 32000 is a flip-chip laser element. Subsequently, the semiconductor light emitting element 32000 may be bonded to an external carrier (e.g., a printed circuit board or the driver chip 21010 shown in Figure 21) using solder via a flip-chip bonding process.

[0372] Please refer to the embodiment shown in Figures 32A to 32C, which are top-view schematic diagrams and cross-sectional schematic diagrams of a semiconductor light-emitting element 32000 of another embodiment, wherein Figure 32A is a top-view perspective schematic diagram of the semiconductor light-emitting element 32000, and Figures 32B and 32C are cross-sectional schematic diagrams along the sections indicated by the line segments 32B-32B' and 32C-32C' in Figure 32A, respectively.

[0373] According to one or more embodiments of the present application, when forming the light-emitting holes of the semiconductor light-emitting element, the structural design of the light-emitting area can be adjusted to change the positions and number of the light-emitting holes, so as to further increase the density of the light-emitting holes in the light-emitting area and the flexibility of addressing control, wherein the light-emitting holes are formed by, for example, utilizing a wet oxidation process.

[0374] As shown in the embodiment of FIG32A , a semiconductor light emitting device 32000 includes a plurality of light emitting apertures 32825A, such as openings 32825A1, 32825A2, 32825A3, and 32825A4 shown in FIG32B and FIG32C , and the light emitting apertures 32825A are arranged in an array. In the top view of FIG32A , the plurality of openings (light emitting apertures) 32825A in the semiconductor light emitting device 32000 are arranged in a closest-packed manner, for example, in a hexagonal closest-packed manner. That is, each opening 32825A is surrounded by six adjacent openings 32825A, and each opening 32825A is surrounded by six recessed structures 32840. The recessed structures 32840 are used to perform an oxidation process to form current confinement regions in the current confinement layers 328251-328254 of the semiconductor light emitting device 32000, but the present invention is not limited thereto. In this manner, six recessed structures are formed in the epitaxial structure surrounding each light-emitting hole, evenly distributed (i.e., spaced 60 degrees apart around the periphery). Therefore, by performing a wet oxidation process using these six recessed structures, a generally circular opening (i.e., the light-emitting hole of the semiconductor light-emitting element) can be formed in the epitaxial structure of the semiconductor light-emitting element. According to one or more embodiments of the present application, each recessed structure is shared by two adjacent light-emitting holes, thereby enabling the multiple light-emitting holes in the semiconductor light-emitting element of the present application to be arranged in a densely packed manner, thereby increasing the layout space for the light-emitting hole structure in the semiconductor light-emitting element.

[0375] As shown in Figure 32B, in the cross-section shown by the line segment 32B-32B' in Figure 32A, there is no recessed structure between the openings (i.e., light-emitting holes) 32825A1 and 32825A2, that is, the current limiting regions in their current limiting layers 328252 and 328251 are respectively formed by the outer wall surfaces of the recessed structures 32850A and 32850B on both sides of the same platform structure 32826 through a wet oxidation process, so that the openings (i.e., light-emitting holes) 32825A1 and 32825A2 are located on the same platform structure 32826. As shown in Figure 32C, in the cross-section shown by the line segment 32C-32C' in Figure 32A, in addition to the recessed structures 32850C and 32850D on the outside, two recessed structures 32840 are also formed between the opening 32825A3 and the adjacent opening 32825A4, that is, the outer wall surface of the recessed structure 32850C and the side wall surface of the recessed structure 32840 are subjected to a wet oxidation process to form a current limiting region in the current limiting layer 328253 to define the opening 32825A3; the side wall surface of the recessed structure 32840 and the outer wall surface of the recessed structure 32850D are subjected to a wet oxidation process to form a current limiting layer 328254 to define the opening 32825A4. In one embodiment, two adjacent openings may share a concave structure therebetween, or there may be only one concave structure between the two adjacent openings, so as to further reduce the distance between the adjacent openings and arrange the light-emitting holes of the semiconductor light-emitting element more closely.

[0376] As shown in Figures 32B and 32C , the semiconductor light-emitting device 32000 of this embodiment further includes a metal connection layer 32040 positioned between the platform structure 32326 and the base layer 32010. As shown in Figures 32B and 32C , the semiconductor light-emitting device 32000 of this embodiment further includes an adhesive layer 32901, connecting the platform structure 32326 to the base layer 32010 via the adhesive layer 32901. As shown in Figures 32B and 32C , the semiconductor light-emitting device 32000 of this embodiment further includes an insulating layer 32090 covering the sides and top surfaces of the epitaxial structures. The insulating layer 32090 is transparent to light emitted from each epitaxial structure.

[0377] In one or more embodiments, the light emitting device may be a semiconductor light emitting element 33000, as shown in FIG33 . FIG33 is a schematic cross-sectional view of a semiconductor light emitting element according to one embodiment. In this embodiment, a semiconductor light emitting element 33000 is provided. The semiconductor light emitting element 33000 includes a semiconductor stack 33200 formed on a growth substrate 33900. The semiconductor stack 33200 sequentially includes a semiconductor layer 33206, an active layer 33204, and a semiconductor layer 33202 located on the growth substrate 33900. Next, a corresponding contact structure 33220 is formed on the semiconductor light emitting element 33000, where a portion of the epitaxial columnar structure P33 is to be subsequently formed. Next, an insulating layer 33090 is formed on the contact structure 33220 and the semiconductor stack 33200 as a protective layer. Next, an etching process is performed to form a through hole U33, thereby exposing the end surface of the growth substrate 33900. The shape of the through hole is not limited; in other words, the shape of the through hole can be a circular columnar hole, a polygonal columnar hole, or a columnar hole of any shape. Next, an etching process is further performed to form an epitaxial columnar structure P33 and a recessed structure 33104 to expose a portion of the end surface of the semiconductor layer 33206. The epitaxial columnar structure P33 has a side surface PB33.

[0378] Next, a wet oxidation process is used to form a current confinement layer in the epitaxial columnar structure P33. In this embodiment, a current confinement layer 33225 is formed between the semiconductor layer 33202 and the active layer 33204. The current confinement layer 33225 includes a current confinement region 33225B and a current conduction region 33225A surrounded by the current confinement region 33225B. An insulating layer 33090 is formed in the through hole U33 and the recessed structure 33104, covering the side surface PB33 of the epitaxial columnar structure P33, the end surface of the semiconductor layer 33206, and the end surface of the growth substrate 33900. Next, an insulating layer opening 33090A is formed in the insulating layer 33090 to expose a portion of the surface of the contact structure 33220. The top-view shape of the insulating layer opening 33090A can be, for example, an annular, circular, elliptical, square, or irregular. In this embodiment, the shape of the insulating layer opening 33090A is ring-shaped when viewed from above, but the present invention is not limited thereto.

[0379] Next, a metal connection layer 33040 is formed on the insulating layer 33090. The metal connection layer 33040 covers the insulating layer 33090 and fills the insulating layer opening 33090A, thereby connecting to the contact structure 33220 and further electrically connecting to the semiconductor layer 33202. The metal connection layer 33040 has a connection layer opening 33040A above the epitaxial columnar structure P33. The location of the connection layer opening 33040A corresponds to the location of the current conduction region 33225A and exposes the insulating layer 33090 below. Next, the epitaxial columnar structure P33 and the semiconductor layer 33206 are bonded to the substrate 33100 via the bonding layer 33901. In this embodiment, the substrate 33100 is a permanent substrate.

[0380] Next, a portion of the growth substrate 33900 is removed to expose portions of the surface of the metal connection layer 33040 and the insulating layer 33090. In this embodiment, the growth substrate 33900 is, for example, a GaAs substrate. Next, an electrode connection layer 33420 is formed on the substrate 33900. Next, an insulating layer 33082 is formed to cover a portion of the electrode connection layer 33420. The insulating layer 33082 is defined with a plurality of openings 33082A and 33082B to expose at least portions of the electrode connection layer 33420 and the metal connection layer 33040, respectively.

[0381] Finally, conductive material is filled into openings 33082A and 33082B to form electrode structures 33105 and 33106 of the semiconductor light-emitting device, respectively, as shown in FIG33 . In one or more embodiments, the light-emitting device may be a semiconductor laser, as shown in FIG34 . Referring to FIG34 , FIG34 is a schematic cross-sectional view of a semiconductor laser device 34000 according to one embodiment. Semiconductor laser device 34000 includes a semiconductor stack 34010, an electrode structure 34020, an insulating layer 34030, and a base layer 34040. Semiconductor stack 34010 includes a first-type semiconductor layer 34101, a second-type semiconductor layer 34102, and an active layer 34103, wherein active layer 34103 is located between first-type semiconductor layer 34101 and second-type semiconductor layer 34102. In this embodiment, as shown in FIG34 , the first-type semiconductor layer 34101 is, for example, a P-type semiconductor layer, and the second-type semiconductor layer 34102 is, for example, an N-type semiconductor layer, but the present invention is not limited thereto. In another embodiment, the first-type semiconductor layer 34101 is, for example, an N-type semiconductor layer, and the second-type semiconductor layer 34102 is, for example, a P-type semiconductor layer.

[0382] In this embodiment, as shown in FIG34 , the base layer 34040 may be a semiconductor layer and may be a growth substrate for the semiconductor stack layer 34010. In one or more other embodiments, the base layer 34040 may also be a packaging substrate for the semiconductor stack layer 34010, that is, the semiconductor stack layer 34010 is first grown on the growth substrate and then transferred to the base layer 34040.

[0383] Referring again to the embodiment of FIG. 34 , the semiconductor laser device 34000 further includes an electrode structure 34050 located on the surface 34011 and the side surface 34013 , and an insulating layer 34030 located between the semiconductor stacked layer 34010 and the electrode structure 34050 .

[0384] In some embodiments, as shown in FIG34 , the base layer 34040 can be conductive or insulating. As shown in FIG34 , the base layer 34040 has a surface 34041 and a side surface 34042 connected to the surface 34041. The second-type semiconductor layer 34102 in the semiconductor stack 34010 further includes terraces 34102A and 34102B extending laterally from the surface 34041. The insulating layer 34030 and the electrode structure 34050 are further located on the surfaces of the terraces 34102A and 340102B. The insulating layer 34030 has an insulating layer opening 34032 on the terrace 340102A, and the electrode structure 34050 extends into the insulating layer opening 34032 and contacts the terrace 34102A of the second-type semiconductor layer 34102. In this embodiment, the electrode structure 34050 is not only located within the insulating layer opening 34032 of the insulating layer 34030 but also extends onto the side surface 34042 of the base layer 34040. Furthermore, the electrode structure 34020 also extends from the side surface 34013 of the semiconductor stack 34010, through the terrace portion 34102B, to the side surface 34042 of the base layer 34040. Therefore, according to the semiconductor laser device 34000 of this embodiment, the bonding area available for the electrode structure 34020 and the electrode structure 34050 of the semiconductor laser device 34000 to be bonded to a carrier (e.g., a printed circuit board or the driver chip 21010 shown in FIG. 21 ) via a flip chip bonding process or lateral solder bonding can be further increased.

[0385] The foregoing description of the embodiments of the present application has been presented for purposes of illustration and description and is not intended to be exhaustive or to limit the embodiments of the invention to the precise form disclosed herein.

[0386] It is obvious to those skilled in the art to which the present invention pertains that, based on the above description of the embodiments, various modifications, changes or combinations may be made to the above embodiments.

Claims

1. A packaging structure, comprising: A light-emitting epitaxial structure, comprising an upper distributed Bragg reflector, an active structure and a lower distributed Bragg reflector stacked in sequence; The light receiving structure is located under the active structure and contacts the light emitting epitaxial structure; A first conductive structure contacts the upper distributed Bragg reflector; A second conductive structure contacts the light receiving structure on the lower surface; as well as A third conductive structure contacts an upper surface of the lower distributed Bragg reflector; The first conductive structure is insulated from the second conductive structure, the first conductive structure is insulated from the third conductive structure, and the second conductive structure is insulated from the third conductive structure. 2 . The package structure as claimed in claim 1 , wherein the upper distributed Bragg reflector comprises a P-type semiconductor structure, and the lower distributed Bragg reflector comprises an N-type semiconductor structure. 3 . The packaging structure as claimed in claim 2 , wherein the first conductive structure is a P-electrode of the light-emitting epitaxial structure. 4 . The package structure as claimed in claim 2 , wherein the second conductive structure is an N-electrode of the light receiving structure. 5 . The packaging structure as claimed in claim 2 , wherein the third conductive structure is a common electrode of the light-emitting epitaxial structure and the light-receiving structure. 6 . The package structure as claimed in claim 1 , wherein the light receiving structure is integrally formed as a part of the lower distributed Bragg reflector.

7. The packaging structure according to claim 1, further comprising: include: The transparent base layer is connected to the light-emitting epitaxial structure via a first bonding layer, wherein the transparent base layer and the first bonding layer are transparent to the light emitted from the light-emitting epitaxial structure. 8 . The packaging structure as claimed in claim 1 , wherein the light receiving structure is bonded to the lower distributed Bragg reflector via a second bonding layer. 9 . The package structure as claimed in claim 8 , wherein the second adhesive layer is conductive. 10 . The packaging structure as claimed in claim 9 , further comprising another distributed Bragg reflector located under the light receiving structure.

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