An automated testing method, system, device, and computer-readable storage medium for chip particles

Abstract

The present invention relates to the field of chip detection technology, and specifically discloses an automated testing method, system, and device for chip particles, as well as a computer-readable storage medium. The present invention first obtains the installation and matching parameters of the chip and the test device (including associated data and contact characteristic parameters), and accordingly obtains an installation and matching index to determine whether the installation and matching index exceeds a threshold. If it does not exceed a threshold, the physical distribution parameters and electrical characteristic parameters of the chip are obtained. Electrical response characteristics such as timing delay, current ripple, and power consumption fluctuation are obtained from the electrical characteristic parameters, and an electrical performance index is calculated. Surface temperature and humidity distribution fields are obtained based on the physical distribution parameters, and then a physical energy index is obtained. The two are then integrated to obtain a comprehensive performance index to determine whether the preset value is exceeded. If the preset value is exceeded, the chip is determined to be defective. This process achieves automated and comprehensive detection of chip defects through quantitative parameter and multi-dimensional fusion, avoiding the one-sidedness of single indicator judgment and ensuring reliable results.

Description

Technical Field

[0001] The present invention relates to the field of chip detection technology, and in particular to an automated testing method, system, and device for chip particles, and a computer-readable storage medium. Background Art

[0002] Chip particles (often referred to as "bare chips") are the smallest core units with complete circuit functions that are cut and separated from the wafer during the integrated circuit (chip) manufacturing process. Chip testing refers to the process of comprehensively inspecting and verifying the electrical performance (such as voltage, current, frequency, power consumption, etc.), functional integrity (whether it can accurately execute preset instructions), physical structure (such as the presence of manufacturing defects, scratches, impurities, and whether the packaging is intact), and reliability (such as stability in different temperature, humidity, and vibration environments, service life, etc.) of integrated circuits (chips) throughout their entire life cycle from design, manufacturing, packaging to application through a series of professional technical means, instruments, equipment, and testing processes.

[0003] Existing chip testing typically only performs independent quality judgments based on a single set of attributes (such as electrical performance and physical structure), but is unable to correlate and judge the comprehensive attributes of multiple data points. This leads to one-sided judgments on chip particles. An automated testing method for chip particles is needed to solve the above problem. Summary of the Invention

[0004] The object of the present invention is to provide an automated testing method, system, and device for chip particles, as well as a computer-readable storage medium, to solve the technical problems raised in the above-mentioned background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] An automated testing method for chip particles, applied to automated testing equipment, comprising:

[0007] Acquiring installation and matching parameters between the chip particles and the automated testing equipment, wherein the installation and matching parameters include association data and contact characteristic parameters between the chip particles and the automated testing equipment;

[0008] Obtaining an installation fit index according to the associated data and the contact characteristic parameter, and determining whether the installation fit index exceeds a threshold;

[0009] If the installation fit index does not exceed the threshold, obtaining physical distribution parameters and electrical characteristic parameters of the chip particles, and obtaining electrical response characteristics based on the electrical characteristic parameters, wherein the electrical response characteristics include timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics, and obtaining the electrical performance index based on the timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics;

[0010] Obtaining a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters, and obtaining a physical energy index according to the surface temperature distribution field and the surface humidity distribution field;

[0011] Obtaining a comprehensive performance index of a chip particle according to the physical energy index and the electrical performance index;

[0012] Determining whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index;

[0013] If the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index, it is determined that the chip particle has a defect.

[0014] Preferably, the step of obtaining the installation fit index according to the association data and the contact characteristic parameters includes:

[0015] Acquire the point space offset, attitude angle, standard geometric center offset and height characteristic parameters of the chip particles according to the associated data;

[0016] Obtaining a mechanical coupling error offset index according to the point space offset, attitude angle, and geometric center offset;

[0017] Obtaining the height difference between the mounting groove reference surface of the automated testing equipment and the highest point on the chip particle surface according to the height characteristic parameter, and obtaining a height adaptation factor according to the height difference and a preset standard limit height;

[0018] Obtaining a contact resistance nominal value and a contact force stability coefficient according to the contact characteristic parameters, and obtaining a contact reliability index according to the contact resistance nominal value and the contact force stability coefficient;

[0019] An installation fit index is obtained according to the mechanical coupling error offset index, the height adaptation factor, and the contact reliability index.

[0020] Preferably, the step of obtaining the physical distribution parameters and electrical characteristic parameters of the chip particles, and obtaining electrical response characteristics based on the electrical characteristic parameters, wherein the electrical response characteristics include timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics, comprises:

[0021] Acquire test timing data, test current sampling data, and test power consumption monitoring data of the chip particles according to the electrical characteristic parameters;

[0022] Acquire a delay time set and a clock jitter sequence within a preset test time according to the test timing data, wherein the delay time set includes a maximum delay time and an average delay time;

[0023] Obtaining a jitter standard deviation according to the clock jitter sequence;

[0024] Acquire a timing characteristic value according to the maximum delay time, the average delay time, and the jitter standard deviation, and use the timing characteristic value as a timing delay feature;

[0025] Acquire a current waveform according to the test current sampling data, and perform low-pass filtering on the current waveform to obtain a DC component;

[0026] Performing high-pass filtering on the current waveform to obtain an AC component, and obtaining a ripple peak-to-peak value and a ripple effective value based on the AC component;

[0027] Calculating a ripple coefficient according to the DC component and the ripple peak-to-peak value, obtaining a current ripple characteristic value according to the ripple coefficient and the ripple effective value, and using the current ripple characteristic value as a current ripple characteristic;

[0028] Acquire a power consumption sequence according to the test power consumption monitoring data, and divide the power consumption sequence into a plurality of subsequences of equal time windows;

[0029] Obtaining variances of corresponding subsequences according to the subsequences of the multiple equal-time windows, obtaining an average variance according to the variances of the multiple subsequences, and using the average variance as a global volatility index;

[0030] Acquire multiple power consumption peak values ​​according to the power consumption sequence, acquire an average peak value according to the multiple power consumption peak values, obtain a power consumption fluctuation characteristic value according to a ratio of the average peak value to a global fluctuation index, and use the power consumption fluctuation characteristic value as a power consumption fluctuation characteristic;

[0031] The electrical response characteristics include timing delay characteristics, current ripple characteristics and power consumption fluctuation characteristics as electrical response characteristics.

[0032] Preferably, the step of obtaining the electrical performance index according to the timing delay characteristics, the current ripple characteristics, and the power consumption fluctuation characteristics includes:

[0033] Mapping the timing delay feature, the current ripple feature, and the power consumption fluctuation feature into independent components of a three-dimensional vector space, respectively, wherein the independent components include a timing delay feature component, a current ripple feature component, and a power consumption fluctuation feature component;

[0034] Obtaining a collection time of electrical characteristic parameters, and dividing the collection time into equal parts to obtain multiple time nodes;

[0035] Combining the timing delay characteristic component, the current ripple characteristic component, and the power consumption fluctuation characteristic component according to a plurality of the time nodes to form an initial coordination matrix;

[0036] Normalizing the initial synergy matrix to eliminate dimensional differences among different parameters, thereby obtaining a multimodal synergy matrix;

[0037] Obtaining a covariance matrix according to the multimodal collaborative matrix, performing eigenvalue decomposition on the covariance matrix, and extracting eigenvectors corresponding to the first K largest eigenvalues;

[0038] Obtaining variance contribution rate according to the plurality of eigenvectors;

[0039] The total contribution rate of the eigenvectors in the multimodal cooperative matrix is ​​obtained, and the contribution rate ratio is calculated according to the ratio of the variance contribution rate to the total contribution rate, and the contribution rate ratio is defined as the electrical performance index.

[0040] Preferably, the step of obtaining the surface temperature distribution field and the surface humidity distribution field of the chip particles according to the physical distribution parameters, and obtaining the physical energy index according to the surface temperature distribution field and the surface humidity distribution field includes:

[0041] Obtain discrete temperature measurement data at different locations on the chip surface and obtain a continuous surface temperature distribution field through interpolation algorithm;

[0042] Identify the highest temperature area in the temperature distribution field and mark it as a hot spot concentration area;

[0043] Obtaining hotspot temperature values ​​at multiple consecutive sampling moments in the hotspot concentration area, and generating temperature change gradients at adjacent moments based on the hotspot temperature values ​​at the multiple consecutive sampling moments;

[0044] Obtain discrete humidity measurement data at different locations on the chip surface and obtain a continuous surface humidity distribution field through interpolation algorithm;

[0045] Identify the highest humidity area in the humidity distribution field and record it as the wet spot concentration area;

[0046] Obtaining hotspot humidity values ​​at multiple consecutive sampling moments in the hotspot concentration area, and generating a humidity change gradient at adjacent moments based on the hotspot humidity values ​​at multiple consecutive sampling moments;

[0047] The humidity change gradient and the temperature change gradient are weightedly calculated to obtain a surface comprehensive change value, and the surface comprehensive change value is used as the physical energy index.

[0048] Preferably, the step of obtaining the chip particle comprehensive performance index according to the physical energy index and the electrical performance index includes:

[0049] Normalizing the physical energy index to obtain a normalized physical energy value;

[0050] Obtaining a physical energy normalized value weight according to the physical energy normalized value;

[0051] Normalizing the electrical performance index to obtain a normalized electrical performance value;

[0052] Obtaining an electrical performance normalized value weight according to the electrical performance normalized value;

[0053] The chip particle comprehensive performance index is calculated according to the physical energy normalized value, the physical energy normalized value weight, the electrical performance normalized value and the electrical performance normalized value weight.

[0054] The present application also provides an automated testing system for chip particles, comprising:

[0055] A first acquisition module is used to acquire installation and matching parameters between the chip particles and the automated testing equipment, wherein the installation and matching parameters include association data and contact characteristic parameters between the chip particles and the automated testing equipment;

[0056] A second acquisition module is configured to acquire an installation fit index based on the associated data and the contact characteristic parameter, and determine whether the installation fit index exceeds a threshold;

[0057] If the installation fit index does not exceed the threshold, obtaining physical distribution parameters and electrical characteristic parameters of the chip particles, and obtaining electrical response characteristics based on the electrical characteristic parameters, wherein the electrical response characteristics include timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics, and obtaining the electrical performance index based on the timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics;

[0058] A third acquisition module is used to acquire a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters, and to acquire a physical energy index according to the surface temperature distribution field and the surface humidity distribution field;

[0059] A fourth acquisition module is used to obtain a chip particle comprehensive performance index according to the physical energy index and the electrical performance index;

[0060] A judgment module, configured to judge whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index;

[0061] If the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index, it is determined that the chip particle has a defect.

[0062] Preferably, the second acquisition module includes:

[0063] A first acquisition unit is used to acquire the point space offset, attitude angle, standard geometric center offset and height characteristic parameters of the chip particles according to the associated data;

[0064] A second acquiring unit is configured to acquire a mechanical coupling error offset index according to the point space offset, the attitude angle, and the geometric center offset;

[0065] A third obtaining unit is configured to obtain a height difference between a mounting groove reference surface of the automated test equipment and a highest point on a chip particle surface according to the height characteristic parameter, and obtain a height adaptation factor according to the height difference and a preset standard limit height;

[0066] a third acquiring unit, configured to acquire a contact resistance nominal value and a contact force stability coefficient according to the contact characteristic parameter, and to acquire a contact reliability index according to the contact resistance nominal value and the contact force stability coefficient;

[0067] The fourth acquiring unit is configured to acquire an installation fit index according to the mechanical coupling error offset index, the height adaptation factor, and the contact reliability index.

[0068] The present application also provides an automated testing device for chip particles, comprising a control module and a drive module, wherein the control module is used to control parts on the automated testing device;

[0069] The driving module is used to drive the parts on the automated testing equipment to implement the steps of the above method.

[0070] The present application also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0071] The beneficial effects of the present application are as follows: the present invention first obtains the installation and matching parameters of the chip and the test equipment (including associated data and contact characteristic parameters), and obtains the installation and matching index based on this to determine whether it exceeds the threshold. If it does not exceed, the physical distribution parameters and electrical characteristic parameters of the chip are obtained, and the electrical response characteristics such as timing delay, current ripple, and power consumption fluctuation are obtained from the electrical characteristic parameters to calculate the electrical performance index; the surface temperature and humidity distribution field are obtained according to the physical distribution parameters, and then the physical energy index is obtained, and the two are integrated to obtain a comprehensive performance index to determine whether it exceeds the preset value. If it exceeds, the chip is determined to be defective. This process realizes automatic and comprehensive detection of chip defects through quantitative parameters and multi-dimensional fusion, avoids the one-sidedness of single indicator judgment, and ensures reliable results. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 This is a schematic diagram of a method flow chart according to an embodiment of the present application.

[0073] Figure 2 This is a schematic diagram of the system structure of an embodiment of the present application.

[0074] Figure 3This is a schematic diagram of the structure of an automated testing device for chip particles according to an embodiment of the present application.

[0075] Figure 4 A top view of an automated testing device for chip particles according to an embodiment of the present application.

[0076] Figure 5 A side view of an automated testing device for chip particles according to an embodiment of the present application.

[0077] Figure 6 A structural diagram of a power supply and signal board, a pass-through board, a backplane board, and a chip loading platform board in an automated testing device for chip particles according to an embodiment of the present application is provided.

[0078] Figure 7 This is a diagram of the first board and the first board structure in the automated testing equipment for chip particles according to an embodiment of the present application.

[0079] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0080] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0081] like Figure 1 As shown, the present application provides an automated testing method for chip particles, comprising:

[0082] S1. Obtaining installation and matching parameters between the chip particles and the automated testing equipment, wherein the installation and matching parameters include association data and contact characteristic parameters between the chip particles and the automated testing equipment;

[0083] S2. Obtaining an installation fit index according to the associated data and the contact characteristic parameter, and determining whether the installation fit index exceeds a threshold;

[0084] If the installation fit index does not exceed the threshold, obtaining physical distribution parameters and electrical characteristic parameters of the chip particles, and obtaining electrical response characteristics based on the electrical characteristic parameters, wherein the electrical response characteristics include timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics, and obtaining the electrical performance index based on the timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics;

[0085] S3. Obtaining a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters, and obtaining a physical energy index according to the surface temperature distribution field and the surface humidity distribution field;

[0086] S4. Obtaining a comprehensive performance index of the chip particle according to the physical energy index and the electrical performance index;

[0087] S5. Determine whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index;

[0088] If the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index, it is determined that the chip particle has a defect.

[0089] As described in steps S1-S5 above, existing chip testing typically only performs independent quality judgments based on a single set attribute (such as electrical performance and physical structure), and is unable to correlate and judge the comprehensive attributes of multiple data sets. This leads to one-sided judgments on chip particles. Therefore, the present invention first obtains the installation and matching parameters between the chip particles and the automated testing equipment. The installation and matching parameters include correlation data and contact characteristic parameters between the chip particles and the automated testing equipment. In this way, the correlation data and contact characteristic parameters can be used to quantify the installation and matching status of the two. Whether the installation and matching is good directly affects the accuracy of subsequent test data, and this step lays a reliable foundation for subsequent testing.

[0090] Next, obtaining an installation fit index according to the associated data and the contact characteristic parameter, and determining whether the installation fit index exceeds a threshold;

[0091] If the installation fit index does not exceed the threshold, the physical distribution parameters and electrical characteristic parameters of the chip particles are obtained, and the electrical response characteristics are obtained based on the electrical characteristic parameters, wherein the electrical response characteristics include timing delay characteristics, current ripple characteristics and power consumption fluctuation characteristics, and the electrical performance index is obtained based on the timing delay characteristics, current ripple characteristics and power consumption fluctuation characteristics. In this way, the installation parameters can be converted into a quantifiable "installation fit index", and the chips suitable for testing can be screened out through threshold judgment (such as index ≤ threshold value, the installation is qualified), while avoiding the installation of unqualified chips into subsequent testing processes, reducing resource waste. Among them, the electrical response characteristics reflect the circuit performance of the chip: excessive timing delay will cause data transmission errors; excessive current ripple will interfere with power supply stability; severe power consumption fluctuations may cause circuit overheating. In this way, the electrical performance of the chip can be fully quantified to avoid the limitations of a single indicator;

[0092] Secondly, the surface temperature and humidity distribution fields of the chip particles are obtained based on the physical distribution parameters, and the physical energy index is obtained based on the surface temperature and humidity distribution fields. The temperature and humidity distributions reflect the chip's heat dissipation capacity and environmental tolerance: concentrated hot spots and rapid temperature increases may cause localized burning; excessively high humidity and drastic changes may cause leakage. By quantifying the chip's physical environmental adaptability, we can make up for the shortcomings of focusing only on electrical performance.

[0093] The chip's comprehensive performance index is then derived based on the physical energy index and the electrical performance index. This comprehensive performance index combines electrical functionality with physical environmental adaptability. For example, if a chip's electrical parameters meet standards but its hotspot temperature rises sharply, its comprehensive index may exceed the standard, indicating a potential heat dissipation defect. This enables multi-dimensional defect assessment and avoids complex defects masked by a single qualified indicator.

[0094] Finally, determining whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index;

[0095] If the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index, the chip particle is determined to be defective. This integrates installation status, electrical performance, and physical environmental influences into a unified system, addressing the one-sidedness of traditional testing. Each step utilizes quantitative calculations of specific parameters to ensure an interpretable test process and reliable results, enabling automated and comprehensive detection of chip particle defects while also avoiding the one-sidedness of chip particle detection caused by single, independent data judgments.

[0096] In one embodiment, the step S2 of obtaining the installation fit index according to the association data and the contact characteristic parameters includes:

[0097] S201, obtaining the point space offset, attitude angle, standard geometric center offset and height characteristic parameters of the chip particle according to the associated data;

[0098] S202, obtaining a mechanical coupling error offset index according to the point space offset, attitude angle, and geometric center offset;

[0099] S203, obtaining a height difference between a mounting groove reference surface of the automated testing equipment and the highest point on the chip particle surface according to the height characteristic parameter, and obtaining a height adaptation factor according to the height difference and a preset standard limit height;

[0100] S204, obtaining a contact resistance nominal value and a contact force stability coefficient according to the contact characteristic parameter, and obtaining a contact reliability index according to the contact resistance nominal value and the contact force stability coefficient;

[0101] S205 : Obtain an installation fit index according to the mechanical coupling error offset index, the height adaptation factor, and the contact reliability index.

[0102] As described in steps S201-S207 above, the present invention first obtains the point spatial offset, attitude angle, standard geometric center offset, and height characteristic parameters of the chip particles based on the associated data. The associated data is jointly obtained by the visual sensor (such as an industrial camera) and displacement sensor (such as a laser rangefinder) of the automated testing equipment. The specific process is as follows: 1. Point spatial offset: By photographing a preset mark point on the chip surface (such as a pin positioning point), the position deviation in three-dimensional space is calculated with comparison with the standard point position of the equipment test probe. 2. Attitude angle: By identifying the edge contour of the chip and comparing it with the standard contour of the equipment mounting slot, the rotation angle and tilt angle of the chip on the horizontal plane are calculated. 3. Standard geometric center offset: By locating the physical center of the chip (such as the intersection of the diagonals) and the geometric center of the equipment mounting slot, the distance deviation in the two-dimensional plane is calculated. 4. Height characteristic parameter: By measuring the vertical distance between the highest point on the chip surface and the reference plane of the equipment mounting slot using a laser rangefinder, these parameters are the core indicators of the chip's mechanical positioning accuracy. For example, a large point spatial offset indicates a large misalignment between the chip pins and the device probes, potentially preventing some pins from contacting. A large attitude angle indicates chip "tilt," exacerbating poor contact at certain points and providing basic data for subsequent calculations of mechanical positioning-related indices, enabling a more refined description of installation position deviations.

[0103] Afterwards, the mechanical coupling error offset index is obtained according to the point space offset, attitude angle and geometric center offset. Secondly, the maximum allowable offset, maximum allowable attitude angle and maximum allowable center offset are obtained in sequence, wherein the mechanical coupling error offset index = (point space offset / maximum allowable offset) × first weight value (point space offset / weight value of maximum allowable offset) + (attitude angle / maximum allowable attitude angle) × second weight value (attitude angle / weight value of maximum allowable attitude angle) + (geometric center offset / maximum allowable center offset) × third weight value (geometric center offset / weight value of maximum allowable center offset), and the "maximum allowable value" is the qualified threshold preset by the device, and the index comprehensively reflects the overall positioning error of the chip in three-dimensional space. For example, if the chip point offset is 0.08mm (80% of the maximum allowable value), the attitude angle is 0.3 degrees (60% of the maximum allowable value), and the center offset is 0.05mm (50% of the maximum allowable value), then the offset index = 0.8×0.4+0.6×0.3+0.5×0.3=0.65, indicating a significant positioning deviation. The spatial offset of the point directly determines the "contact misalignment probability" between the probe and the pin. The larger the offset, the more difficult it is for the probe to accurately contact the pin. This is the most basic "contact prerequisite" and therefore has the highest weight. Secondly, the attitude angle affects the "uniformity" of contact. Posture tilt can cause excessive pressure on local chip pins and localized poor contact, but this can be compensated by slight deformation. Its impact is weaker than the point offset and has the second highest weight. Finally, the geometric center offset affects the "symmetry" of contact. Center offset can cause uneven distribution of overall contact pressure, but compared with the "contact misalignment risk" of point offset, it is less destructive and has the lowest weight. This converts multiple scattered mechanical positioning parameters into a single quantitative indicator, facilitating rapid assessment of positioning accuracy.

[0104] Then, the height difference between the installation groove reference plane of the automated test equipment and the highest point on the chip particle surface is obtained based on the height characteristic parameter, and the height adaptation factor is obtained based on the height difference and the preset standard limit height, where the height adaptation factor = 1-height difference / preset standard limit height (the preset standard limit height is the maximum height difference allowed by the equipment). At the same time, the height adaptation factor reflects the vertical compatibility of the chip with the equipment. The closer the factor is to 1, the smaller the height difference is, and the more appropriate the vertical distance between the chip and the equipment is (neither too high to make contact nor too low to cause physical squeezing); when the factor is negative, it indicates that the height exceeds the safe range and may cause mechanical damage. Secondly, the rationality of the vertical installation is quantified to avoid physical damage or contact failure caused by height mismatch.

[0105] Secondly, the nominal contact resistance value and contact force stability coefficient are obtained based on the contact characteristic parameters, and the contact reliability index is obtained based on the nominal contact resistance value and the contact force stability coefficient. The contact characteristic parameters are derived from measuring the contact resistance (nominal contact resistance value) between the chip pin and the probe using the device's resistance tester, and collecting real-time contact force fluctuation data (calculating the contact force stability coefficient) using a pressure sensor. Secondly, the contact force stability coefficient is calculated by calculating the standard deviation of the contact force sampling data (e.g., 100 samples) and dividing it by the average to obtain the fluctuation coefficient (the smaller the coefficient, the higher the stability). Simultaneously, the contact reliability index is calculated using the formula "(1-nominal contact resistance value / maximum allowable contact resistance) × (1-contact force fluctuation coefficient)". This reflects the quality of the electrical contact through the contact reliability index. Lower contact resistance indicates lower current transmission loss; higher contact force stability indicates a more stable contact state (no intermittent contact due to vibration, etc.). The closer the index is to 1, the more reliable the electrical contact. Furthermore, a comprehensive assessment of the stability and low loss of the electrical contact is performed to avoid distortion of electrical test data caused by contact problems.

[0106] Finally, the installation fit index is obtained according to the mechanical coupling error offset index, the height adaptation factor, and the contact reliability index, where the installation fit index = (1-mechanical coupling error offset index) × the fourth weight value (1-the weight value of the mechanical coupling error offset index) + the height adaptation factor × the fifth weight value (the weight value of the height adaptation factor) + the contact reliability index × the sixth weight value (the weight value of the contact reliability index). Secondly, the weight distribution is based on the degree of influence of each factor on the installation quality, and the contact reliability has the greatest impact on the electrical test, so it has the highest weight; mechanical positioning has the second highest weight, and the height adaptability has the lowest weight). For example, if the mechanical coupling error offset index = 0.2 (i.e., 1-0.2=0.8), the height adaptation factor = 0.75, and the contact reliability index = 0.45, then the installation fit index = 0.8×0.3+0.75×0.2+0.45×0.5=0.24+0.15+0.225=0.615. The installation fit index is a comprehensive quantitative indicator of installation quality, and its value range is [0,1]. The closer the index is to 1, the more precise the mechanical positioning of the chip, the more adaptable the height, the more reliable the electrical contact, and the more the installation status meets the test requirements; the lower the index, the worse the installation quality, which may make subsequent test data invalid, and convert the scattered installation parameters into a single comparable index, providing a clear basis for subsequent judgment of whether the installation is qualified.

[0107] In one embodiment, the step S2 of obtaining the physical distribution parameters and electrical characteristic parameters of the chip particles and obtaining the electrical response characteristics based on the electrical characteristic parameters, wherein the electrical response characteristics include timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics, includes:

[0108] S208, obtaining test timing data, test current sampling data, and test power consumption monitoring data of the chip particles according to the electrical characteristic parameters;

[0109] S209, obtaining a delay time set and a clock jitter sequence within a preset test time according to the test timing data, wherein the delay time set includes a maximum delay time and an average delay time;

[0110] S2010, obtaining a jitter standard deviation according to the clock jitter sequence;

[0111] S2011: Acquire a timing characteristic value according to the maximum delay time, the average delay time, and the jitter standard deviation, and use the timing characteristic value as a timing delay feature;

[0112] S2012, obtaining a current waveform according to the test current sampling data, and performing low-pass filtering on the current waveform to obtain a DC component;

[0113] S2013, performing high-pass filtering on the current waveform to obtain an AC component, and obtaining a ripple peak-to-peak value and a ripple effective value based on the AC component;

[0114] S2014. Calculate a ripple coefficient based on the DC component and the ripple peak-to-peak value, obtain a current ripple characteristic value based on the ripple coefficient and the ripple effective value, and use the current ripple characteristic value as a current ripple characteristic;

[0115] S2015: Acquire a power consumption sequence according to the test power consumption monitoring data, and divide the power consumption sequence into a plurality of subsequences of equal time windows;

[0116] S2016. Obtaining variances of corresponding subsequences according to the subsequences of the multiple equal-time windows, obtaining an average variance according to the variances of the multiple subsequences, and using the average variance as a global volatility index;

[0117] S2017. Acquire multiple power consumption peak values ​​according to the power consumption sequence, acquire an average peak value according to the multiple power consumption peak values, obtain a power consumption fluctuation characteristic value according to a ratio of the average peak value to a global fluctuation index, and use the power consumption fluctuation characteristic value as a power consumption fluctuation characteristic;

[0118] S2018. The electrical response characteristics including the timing delay characteristics, the current ripple characteristics and the power consumption fluctuation characteristics are used as electrical response characteristics.

[0119] As described in steps S208-S2018 above, since only a single electrical parameter (such as the average value of voltage and current) is tested and the correlation between parameters (such as the coupling relationship between timing delay and power consumption fluctuation) is ignored, the present invention first obtains the test timing data, test current sampling data and test power consumption monitoring data of the chip particles based on the electrical characteristic parameters. Among them, the test timing data: the transmission time of the key signal path of the chip (such as the delay from the rising edge of the clock signal to the data output) is collected by an oscilloscope, the sampling frequency is 1GHz, and the collection is continuous for 10ms (a total of 10,000 sampling points). Secondly, the test power consumption monitoring data: the real-time power consumption of the chip is collected by a power meter, the sampling frequency is 10kHz, and the collection is continuous for 1s (a total of 10,000 sampling points). These data are the "time domain portrait" of the chip's electrical behavior: the timing data reflects the signal transmission efficiency, the current data reflects the energy consumption pattern, and the power consumption data reveals the overall energy conversion characteristics. At the same time, they provide raw data for subsequent feature extraction to ensure that the analysis covers multiple dimensions of the chip's electrical performance.

[0120] Then, according to the test timing data, a delay time set and a clock jitter sequence within a preset test time are obtained, wherein the delay time set includes a maximum delay time and an average delay time. Then, a jitter standard deviation is obtained according to the clock jitter sequence. Then, a timing characteristic value is obtained according to the maximum delay time, the average delay time and the jitter standard deviation, and the timing characteristic value is used as a timing delay feature to calculate the delay parameters: the delay time of each sampling point is extracted from the timing data, and the maximum delay time (Tmax) and average delay time (Tavg) of the sampling points within the preset time (such as 10000) are counted. The clock jitter is analyzed: the difference sequence of the delay times of adjacent sampling points is calculated to obtain a clock jitter sequence, and then the standard deviation (CZ) of the sequence is calculated to synthesize the timing characteristic value: the three parameters are combined into a single characteristic value (the larger the value, the worse the timing performance), and the timing characteristic value quantifies the "instability" of the signal transmission. For example, if Tmax = 5ns (the pass threshold is 4ns), Tavg = 3ns, and CZ = 0.2ns, then the timing characteristic value = (5 + 3) × 0.2 = 1.6, indicating a serious timing problem (possibly due to an unreasonable circuit design or manufacturing defect that causes an excessively long signal path). It can also convert complex timing data into a single, comparable metric, facilitating subsequent collaborative analysis with other electrical characteristics.

[0121] Secondly, a current waveform is obtained according to the test current sampling data, and the current waveform is low-pass filtered to obtain a DC component. At the same time, the current waveform is high-pass filtered to obtain an AC component, and the ripple peak-to-peak value and the ripple effective value are obtained according to the AC component. After that, the ripple coefficient is calculated according to the DC component and the ripple peak-to-peak value, and the current ripple characteristic value is obtained according to the ripple coefficient and the ripple effective value, and the current ripple characteristic value is used as the current ripple characteristic, wherein the filtering separates the DC and AC components: the current sampling data is low-pass filtered (cut-off frequency 50Hz) to obtain a DC component (IDC), and high-pass filtered (cut-off frequency 1kHz) to obtain an AC component (IAC), and then multiple AC components (IAC) are obtained according to the preset acquisition time. The ripple coefficient = AC component peak-to-peak value / DC component, and the ripple effective value = , n represents the number of multiple AC components. The current ripple characteristic value = ripple factor × ripple effective value, and the current ripple characteristic value reflects the "purity" of the power supply. For example, if IDC = 1A, the peak-to-peak value of the AC component = 0.2A (ripple factor = 0.2), and the ripple effective value = 0.05A, then the current ripple characteristic value = 0.2 × 0.05 = 0.01. If this value exceeds the preset threshold (such as 0.005), it indicates that the power supply filter circuit may have failed, affecting the stability of the chip. At the same time, it quantifies the severity of the current fluctuation and identifies potential defects in the power supply design or filter components.

[0122] Then, a power consumption sequence is obtained according to the test power consumption monitoring data, and the power consumption sequence is divided into a plurality of subsequences of equal time windows. Next, the variances of the corresponding plurality of subsequences are obtained according to the plurality of subsequences of equal time windows, and the variance average is obtained according to the variances of the plurality of subsequences, and the variance average is used as the global fluctuation index. Next, a plurality of power consumption peaks are obtained according to the power consumption sequence, and an average peak is obtained according to the plurality of power consumption peaks, and a power consumption fluctuation characteristic value is obtained according to the ratio of the average peak value to the global fluctuation index, and the power consumption fluctuation characteristic value is used as the power consumption fluctuation characteristic value. In this way, the power consumption fluctuation characteristic value captures the "dynamic instability" of the chip, and at the same time, identifies the power consumption anomalies of the chip under different working states, and discovers intermittent defects that cannot be detected by traditional average power consumption testing. Moreover, this value can distinguish between "high peak value but stable fluctuation" (such as normal program load) and "high peak value and violent fluctuation" (such as abnormal short circuit), so as to avoid misjudging reasonable peak values.

[0123] Finally, the electrical response characteristics including timing delay characteristics, current ripple characteristics and power consumption fluctuation characteristics are taken as electrical response characteristics. These three types of characteristics cover the core dimensions of chip electrical performance from "time response", "current stability" and "power consumption rationality" respectively. Their collaborative analysis can capture defects that a single feature cannot reflect (such as timing delay + excessive current ripple may be caused by internal short circuit). At the same time, it also solves the problems of one-sidedness and insufficient dynamic feature characterization of traditional electrical tests, laying a multi-dimensional and high-precision foundation for the subsequent calculation of electrical performance indexes.

[0124] In one embodiment, the step S2 of obtaining the electrical performance index according to the timing delay characteristics, the current ripple characteristics, and the power consumption fluctuation characteristics includes:

[0125] S2019. Mapping the timing delay feature, the current ripple feature, and the power consumption fluctuation feature into independent components of a three-dimensional vector space, respectively, wherein the independent components include a timing delay feature component, a current ripple feature component, and a power consumption fluctuation feature component;

[0126] S2020: Obtaining a collection time of electrical characteristic parameters, and dividing the collection time into equal parts to obtain a plurality of time nodes;

[0127] S2021, combining the timing delay characteristic component, the current ripple characteristic component, and the power consumption fluctuation characteristic component according to a plurality of the time nodes to form an initial coordination matrix;

[0128] S2022. Standardizing the initial synergy matrix to eliminate dimensional differences among different parameters to obtain a multimodal synergy matrix.

[0129] S2023. Obtain a covariance matrix according to the multimodal collaborative matrix, perform eigenvalue decomposition on the covariance matrix, and extract eigenvectors corresponding to the first K largest eigenvalues;

[0130] S2024. Obtain variance contribution rate according to the plurality of eigenvectors;

[0131] S2025. Obtain the total contribution rate of the eigenvectors in the multimodal collaborative matrix, and calculate the contribution rate ratio based on the ratio of the variance contribution rate to the total contribution rate, and define the contribution rate ratio as an electrical performance index.

[0132] As described in steps S2019-S2025 above, the present invention first maps the timing delay feature, the current ripple feature, and the power consumption fluctuation feature into independent components of a three-dimensional vector space, wherein the independent components include a timing delay feature component, a current ripple feature component, and a power consumption fluctuation feature component, unifying the scattered features into the same vector space, laying the foundation for subsequent multi-feature collaborative analysis and solving the problem of "dimensional isolation" of features;

[0133] Then, the acquisition time of the electrical characteristic parameters is obtained and divided into multiple time nodes. The dynamic changes of the characteristics over time (such as the gradual increase of the timing delay during the chip heating process) are captured through the time dimension to avoid the randomness of using only a single moment of data.

[0134] Next, the timing delay characteristic component, the current ripple characteristic component, and the power consumption fluctuation characteristic component are combined according to multiple time nodes to form an initial synergy matrix, wherein the multiple time nodes correspond to the timing delay characteristic component, the current ripple characteristic component, and the power consumption fluctuation characteristic component of the node, respectively. After matrixing, the temporal correlation of the characteristics is made explicit, providing a structural basis for subsequent analysis of characteristic coupling patterns.

[0135] Next, the initial synergy matrix is ​​normalized to eliminate dimensional differences among parameters, resulting in a multimodal synergy matrix. After normalization, the numerical ranges of the three types of features are unified (for example, they are all converted to a normal distribution with a mean of 0 and a standard deviation of 1). This ensures that a 1-unit increase in timing delay and a 1-unit increase in current ripple have equal weight in the analysis, thus avoiding misjudgment of feature importance due to dimensional differences.

[0136] At the same time, a covariance matrix is ​​obtained according to the multimodal collaborative matrix, and the covariance matrix is ​​subjected to eigenvalue decomposition, and the eigenvectors corresponding to the first K largest eigenvalues ​​are extracted, so that the eigenvalue decomposition compresses the high-dimensional features into the main dimensions, so that;

[0137] Secondly, the variance contribution rate is obtained based on the multiple feature vectors. Secondly, the higher the contribution rate, the more the extracted main feature mode can reflect the true state of the chip electrical performance and reduce the interference of noise on the evaluation results. Among them, the variance contribution rate in, Obtain variance contribution rate for the Kth eigenvector, k=1, 2, 3...K, K is the sequence number of the eigenvector for obtaining variance contribution rate;

[0138] Finally, the total contribution rate of the eigenvectors in the multimodal collaborative matrix is ​​obtained, and the contribution rate is calculated based on the ratio of the variance contribution rate to the total contribution rate, and the contribution rate is defined as the electrical performance index. The complex multi-feature, multi-time point data is converted into a single comparable index to achieve an overall quantitative evaluation of the chip's electrical performance. The physical meaning of the index is clear (based on the interpretability of data variation), avoiding the bias of subjective weighting. At the same time, through the collaborative analysis of multi-dimensional electrical features, the dimensional differences and noise interference are eliminated, and the correlation and temporal dynamics between features are retained. The final electrical performance index can objectively reflect the overall quality of the chip's electrical performance, providing a reliable electrical dimension basis for subsequent comprehensive performance evaluation.

[0139] In one embodiment, the step S3 of obtaining the surface temperature distribution field and the surface humidity distribution field of the chip particles according to the physical distribution parameters, and obtaining the physical energy index according to the surface temperature distribution field and the surface humidity distribution field includes:

[0140] S301, obtaining discrete temperature measurement data at different locations on the chip surface, and obtaining a continuous surface temperature distribution field through an interpolation algorithm;

[0141] S302, identifying the highest temperature area in the temperature distribution field and marking it as a hotspot concentration area;

[0142] S303, obtaining hotspot temperature values ​​at multiple consecutive sampling moments in the hotspot concentration area, and generating temperature change gradients at adjacent moments based on the hotspot temperature values ​​at the multiple consecutive sampling moments;

[0143] S304, obtaining discrete humidity measurement data at different locations on the chip surface, and obtaining a continuous surface humidity distribution field through an interpolation algorithm;

[0144] S305, identifying the highest humidity area in the humidity distribution field, and recording it as a wet point concentration area;

[0145] S306, obtaining hotspot humidity values ​​at multiple consecutive sampling moments in the hotspot concentration area, and generating a humidity change gradient at adjacent moments based on the hotspot humidity values ​​at the multiple consecutive sampling moments;

[0146] S307 , performing weighted calculation on the humidity change gradient and the temperature change gradient to obtain a surface comprehensive change value, and using the surface comprehensive change value as a physical energy index.

[0147] As described in steps S301-S307 above, the present invention first obtains discrete temperature measurement data at different locations on the chip surface, and then uses an interpolation algorithm to obtain a continuous surface temperature distribution field. This local temperature measurement is expanded into a global temperature "portrait," solving the problem that traditional single-point measurement cannot reflect uneven temperature distribution and providing a basis for locating hotspot areas.

[0148] Secondly, the highest temperature areas in the temperature distribution field are identified and marked as hotspots. Focusing on the areas with the highest temperature and the greatest potential for failure avoids indiscriminate analysis of the entire temperature range and improves defect location efficiency. (For example, hotspots may correspond to areas with a high concentration of internal power devices, where overheating may be caused by device short circuits.)

[0149] Next, the hotspot temperature values ​​at multiple consecutive sampling moments in the hotspot concentration area are obtained, and a temperature change gradient at adjacent moments is generated based on the hotspot temperature values ​​at multiple consecutive sampling moments. The temperature change gradient reflects the heating rate of the hotspot. The larger the gradient, the worse the heat dissipation capacity (for example, the heat dissipation channel inside the chip is blocked, resulting in heat being unable to dissipate), and the higher the potential burnout risk.

[0150] At the same time, discrete humidity measurement data is obtained at different locations on the chip surface, and a continuous surface humidity distribution field is obtained through interpolation algorithms. By constructing a global humidity distribution, local high humidity areas that may be caused by poor sealing or environmental exposure are identified (for example, abnormal humidity at edge pins may cause corrosion).

[0151] Then, identify the highest humidity area in the humidity distribution field and record it as the wet point concentration area. Among them, locate the area with the highest humidity and the most likely to cause leakage or corrosion. If its location coincides with the pin, it may cause an increase in contact resistance.

[0152] Next, the hotspot humidity values ​​at multiple consecutive sampling moments in the hotspot concentration area are obtained, and a humidity change gradient at adjacent moments is generated based on the hotspot humidity values ​​at multiple consecutive sampling moments. The humidity change gradient reflects the moisture absorption rate of the wet point. The larger the gradient, the worse the moisture resistance (for example, packaging gaps allow rapid moisture intrusion) and the higher the potential leakage risk.

[0153] Finally, the humidity and temperature gradients are weighted to obtain a comprehensive surface change value, which is used as a physical energy index. The dynamic change characteristics of temperature and humidity are integrated into a single index to comprehensively evaluate the chip's heat dissipation capacity and moisture resistance, avoiding the limitations of single physical parameter evaluation (e.g., if a chip's temperature is normal but the humidity rises too quickly, its physical energy index will still exceed the standard). Secondly, through spatial field reconstruction and dynamic gradient analysis, a refined assessment of the chip's physical characteristics is achieved. From discrete measurement to continuous field construction, from key area identification to change trend quantification, the resulting integrated physical energy index comprehensively reflects the chip's adaptability to the physical environment, providing a reliable physical dimension basis for comprehensive performance evaluation and addressing the shortcomings of traditional methods that focus solely on electrical performance.

[0154] In one embodiment, the step S4 of obtaining the chip particle comprehensive performance index according to the physical energy index and the electrical performance index includes:

[0155] S401, normalizing the physical energy index to obtain a normalized physical energy value;

[0156] S402, obtaining a physical energy normalized value weight according to the physical energy normalized value;

[0157] S403, performing normalization processing on the electrical performance index to obtain a normalized electrical performance value;

[0158] S404, obtaining an electrical performance normalized value weight according to the electrical performance normalized value;

[0159] S405 , calculating a comprehensive performance index of the chip particle according to the physical energy normalized value, the physical energy normalized value weight, the electrical performance normalized value, and the electrical performance normalized value weight.

[0160] As described in steps S401-S405 above, the present invention first normalizes the physical energy index to obtain a normalized physical energy value. After normalization, the numerical range of the physical energy index is unified with the electrical performance index (normalized to [0, 1]), thereby resolving fusion deviations caused by dimensional differences (for example, avoiding the inability to directly compare a "physical energy index of 2.6" and an "electrical performance index of 0.8" due to different units).

[0161] Then, a physical energy normalization value weight is obtained based on the physical energy normalization value. Secondly, dynamic weighting ensures that when physical performance is on the verge of failure, its voice in the comprehensive evaluation is increased, avoiding the risk of "electrical compliance" masking "imminent physical failure" (for example, if a chip is electrically normal but the physical energy index is close to the threshold, its physical defects need to be paid special attention to).

[0162] Secondly, the electrical performance index is normalized to obtain a normalized electrical performance value. Through reverse normalization, the trend of the normalized electrical performance value is made consistent with the normalized physical energy value (both follow the principle of "larger values ​​indicate worse performance"), ensuring that the two are logically unified in weight distribution (for example, large indices indicate performance close to the defect threshold);

[0163] Next, the normalized electrical performance value weight is obtained based on the normalized electrical performance value. When the electrical performance is on the verge of failure, its weight is automatically increased to avoid ignoring the core problem of "electrical function failure" due to "physical compliance" (for example, if a chip is physically stable but has severe timing delays, its electrical defect needs to be highlighted).

[0164] Finally, a comprehensive chip performance index is calculated based on the normalized physical energy value, the weighted normalized physical energy value, the normalized electrical performance value, and the weighted normalized electrical performance value. This comprehensive performance index incorporates the "defect risk" of both physical and electrical performance. A higher value indicates significant issues in at least one dimension (or both) of the chip. Secondly, dynamic weighting is used to achieve a comprehensive "defect-dominated" assessment, avoiding misjudgments in a single dimension while highlighting the most impactful defect types. Normalization eliminates dimensional differences, and dynamic weighting is used to reflect the defect risks of different performance dimensions. The resulting integrated comprehensive performance index comprehensively and objectively reflects the overall chip quality. This process addresses the one-sidedness of traditional independent assessments, ensuring that the synergistic impact of physical and electrical performance is incorporated into the defect judgment system, providing a scientific, quantitative basis for automated chip testing.

[0165] like Figure 2 As shown, the present application also provides an automated testing system for chip particles, including:

[0166] A first acquisition module is used to acquire installation and matching parameters between the chip particles and the automated testing equipment, wherein the installation and matching parameters include association data and contact characteristic parameters between the chip particles and the automated testing equipment;

[0167] A second acquisition module is configured to acquire an installation fit index based on the associated data and the contact characteristic parameter, and determine whether the installation fit index exceeds a threshold;

[0168] If the installation fit index does not exceed the threshold, obtaining physical distribution parameters and electrical characteristic parameters of the chip particles, and obtaining electrical response characteristics based on the electrical characteristic parameters, wherein the electrical response characteristics include timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics, and obtaining the electrical performance index based on the timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics;

[0169] A third acquisition module is used to acquire a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters, and to acquire a physical energy index according to the surface temperature distribution field and the surface humidity distribution field;

[0170] A fourth acquisition module is used to obtain a chip particle comprehensive performance index according to the physical energy index and the electrical performance index;

[0171] A judgment module, configured to judge whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index;

[0172] If the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index, it is determined that the chip particle has a defect.

[0173] In one embodiment, the second acquisition module includes:

[0174] A first acquisition unit is used to acquire the point space offset, attitude angle, standard geometric center offset and height characteristic parameters of the chip particles according to the associated data;

[0175] A second acquiring unit is configured to acquire a mechanical coupling error offset index according to the point space offset, the attitude angle, and the geometric center offset;

[0176] A third obtaining unit is configured to obtain a height difference between a mounting groove reference surface of the automated test equipment and a highest point on a chip particle surface according to the height characteristic parameter, and obtain a height adaptation factor according to the height difference and a preset standard limit height;

[0177] a third acquiring unit, configured to acquire a contact resistance nominal value and a contact force stability coefficient according to the contact characteristic parameter, and to acquire a contact reliability index according to the contact resistance nominal value and the contact force stability coefficient;

[0178] The fourth acquiring unit is configured to acquire an installation fit index according to the mechanical coupling error offset index, the height adaptation factor, and the contact reliability index.

[0179] like Figure 3-Figure 7 As shown, an automated testing device for chip particles includes a control module and a drive module, wherein the control module is used to control parts on the automated testing device;

[0180] The driving module is used to drive the parts on the automated testing equipment and implement the steps of the above method when executing the computer program.

[0181] Among them, the control module mainly consists of the following:

[0182] The driver module mainly consists of: first board 1, second board 2, housing 3, display 5, electronic control system 6, host 7, tray 9, mouse 10, power button 11, and three-color light 12;

[0183] The driving module mainly consists of: a test system 4 and a pressing area 8;

[0184] The test system 4 is composed of a power supply and signal board 44, a pass-through board 43, a backplane card 42, and a board 41 for loading a chip under test. The backplane card 42, the pass-through board 43, and the power supply and signal board 44 in the test equipment are installed and fixed on the bracket, and the board 41 for loading a chip under test is a mobile component.

[0185] Among them, the present application needs to focus on realizing the automatic docking and automatic separation of the first board 1 and the second board 2. The second board 2 is fixed and the first board 1 moves with the automation device.

[0186] The second board 2 is provided with one coarse positioning pin and six fine positioning pins, and correspondingly one coarse positioning pin hole and six fine positioning pin holes are provided on the second board 2. A female connector is placed on the second board 2, and a male connector is placed on the first board 1.

[0187] Four sloped guide blocks are positioned at the four corners of the pallet 100. These blocks provide initial alignment when the second board 2 is manually placed on the pallet 100. Four sensors are also installed on the pallet 100 to detect whether the second board 2 is placed flat on the pallet 100, preventing any corners from tilting. A pair of full optical barriers 20 are positioned at the front and rear ends of the docking device to detect the entry of foreign objects during the movement of the second board 2, specifically for safety avoidance.

[0188] The motion mechanism is driven by a motor (other power sources, such as a pneumatic cylinder, are also possible). A servo motor 40 is connected to a screw module 50 via a coupling. A connecting plate 60 is mounted on the top of the screw module and connected to a support plate 100 via screws. A sensor block 90 is mounted on the connecting plate 60 to detect the movement position. Pull blocks 80 and push blocks 70 are located at the front and rear ends of the support plate 100.

[0189] When the second board 2 needs to be docked with the first board 1, the motor drives the screw rod to amplify the power to drive the support plate, and the push block at the end of the support plate pushes the end of the second board 2 to move closer to the first board 1. When the sensor receives a signal (or the encoder reaches the set value), the motor stops working, and the second board 2 is docked with the first board 1 in place. Similarly, when the second board 2 needs to be separated from the first board 1, the motor runs in reverse and drives the pull block 80 to move backward through the screw rod. The pull block 80 pushes the front end of the second board 2 to move backward until the sensor detects that it is in place or the encoder reaches the set value, and the second board 2 is separated from the first board 1.

[0190] Specific test implementation steps:

[0191] Area button 9 powers on. Board 41, filled with particles to be tested, is placed on pallet 100. Area 8 enables + boardinsert. Sensor 10 detects board 41 is in place, and grating 20 detects that the motion area is unobstructed. The motor drives board 41 toward backplane 42. Sensor 90 detects that it is in place and the motor encoder reaches the set value, and the motor stops. The boardinsert indicator lights up, indicating that the board is properly docked. Area 8 teststart button is pressed to begin the test. Tricolor indicator 10 flashes green, and the test ends. Area 8 enables + boardremove is pressed to exit board 41, ending the entire test and entering the next cycle.

[0192] The above is only one embodiment of the device of the present application and is not intended to be the only reference. It is only provided here for reference to understand the operation and functional characteristics of the implementation device.

[0193] The present application also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0194] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided in this application and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct RAM bus dynamic RAM (DRDRAM), and RAM bus dynamic RAM (RDRAM).

[0195] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, apparatus, article, or method comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, apparatus, article, or method. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, apparatus, article, or method comprising the element.

[0196] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An automated testing method for chip particles, applied to automated testing equipment, characterized in that: include: Acquiring installation and matching parameters between the chip particles and the automated testing equipment, wherein the installation and matching parameters include association data and contact characteristic parameters between the chip particles and the automated testing equipment; The specific steps of obtaining the installation fit index according to the association data and the contact characteristic parameters are as follows: Acquire the point space offset, attitude angle, standard geometric center offset and height characteristic parameters of the chip particles according to the associated data; Obtaining a mechanical coupling error offset index according to the point space offset, attitude angle, and geometric center offset; Obtaining the height difference between the mounting groove reference surface of the automated testing equipment and the highest point on the chip particle surface according to the height characteristic parameter, and obtaining a height adaptation factor according to the height difference and a preset standard limit height; Obtaining a contact resistance nominal value and a contact force stability coefficient according to the contact characteristic parameters, and obtaining a contact reliability index according to the contact resistance nominal value and the contact force stability coefficient; Obtaining an installation fit index according to the mechanical coupling error offset index, the height adaptation factor, and the contact reliability index, and determining whether the installation fit index exceeds a threshold; If the installation fit index does not exceed the threshold, obtaining physical distribution parameters and electrical characteristic parameters of the chip particles, and obtaining electrical response characteristics based on the electrical characteristic parameters, wherein the electrical response characteristics include timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics, and obtaining the electrical performance index based on the timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics; Obtaining a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters, and obtaining a physical energy index according to the surface temperature distribution field and the surface humidity distribution field; Obtaining a comprehensive performance index of a chip particle according to the physical energy index and the electrical performance index; Determining whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index; If the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index, it is determined that the chip particle has a defect.

2. The automated testing method for chip particles according to claim 1, characterized in that: The step of obtaining the physical distribution parameters and electrical characteristic parameters of the chip particles, and obtaining electrical response characteristics based on the electrical characteristic parameters, wherein the electrical response characteristics include timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics, includes: Acquire test timing data, test current sampling data, and test power consumption monitoring data of the chip particles according to the electrical characteristic parameters; Acquire a delay time set and a clock jitter sequence within a preset test time according to the test timing data, wherein the delay time set includes a maximum delay time and an average delay time; Obtaining a jitter standard deviation according to the clock jitter sequence; Acquire a timing characteristic value according to the maximum delay time, the average delay time, and the jitter standard deviation, and use the timing characteristic value as a timing delay feature; Acquire a current waveform according to the test current sampling data, and perform low-pass filtering on the current waveform to obtain a DC component; Performing high-pass filtering on the current waveform to obtain an AC component, and obtaining a ripple peak-to-peak value and a ripple effective value based on the AC component; Calculating a ripple coefficient according to the DC component and the ripple peak-to-peak value, obtaining a current ripple characteristic value according to the ripple coefficient and the ripple effective value, and using the current ripple characteristic value as a current ripple characteristic; Acquire a power consumption sequence according to the test power consumption monitoring data, and divide the power consumption sequence into a plurality of subsequences of equal time windows; Obtaining variances of corresponding subsequences according to the subsequences of the multiple equal-time windows, obtaining an average variance according to the variances of the multiple subsequences, and using the average variance as a global volatility index; Acquire multiple power consumption peak values ​​according to the power consumption sequence, acquire an average peak value according to the multiple power consumption peak values, obtain a power consumption fluctuation characteristic value according to a ratio of the average peak value to a global fluctuation index, and use the power consumption fluctuation characteristic value as a power consumption fluctuation characteristic; The electrical response characteristics include timing delay characteristics, current ripple characteristics and power consumption fluctuation characteristics as electrical response characteristics.

3. The automated testing method for chip particles according to claim 1, characterized in that: The step of obtaining the electrical performance index according to the timing delay characteristics, the current ripple characteristics, and the power consumption fluctuation characteristics includes: Mapping the timing delay feature, the current ripple feature, and the power consumption fluctuation feature into independent components of a three-dimensional vector space, respectively, wherein the independent components include a timing delay feature component, a current ripple feature component, and a power consumption fluctuation feature component; Obtaining a collection time of electrical characteristic parameters, and dividing the collection time into equal parts to obtain multiple time nodes; Combining the timing delay characteristic component, the current ripple characteristic component, and the power consumption fluctuation characteristic component according to a plurality of the time nodes to form an initial coordination matrix; Normalizing the initial synergy matrix to eliminate dimensional differences among different parameters, thereby obtaining a multimodal synergy matrix; Obtaining a covariance matrix according to the multimodal collaborative matrix, performing eigenvalue decomposition on the covariance matrix, and extracting eigenvectors corresponding to the first K largest eigenvalues; Obtaining variance contribution rate according to the plurality of eigenvectors; The total contribution rate of the eigenvectors in the multimodal cooperative matrix is ​​obtained, and the contribution rate ratio is calculated according to the ratio of the variance contribution rate to the total contribution rate, and the contribution rate ratio is defined as the electrical performance index.

4. The automated testing method for chip particles according to claim 1, characterized in that: The step of obtaining the surface temperature distribution field and the surface humidity distribution field of the chip particles according to the physical distribution parameters, and obtaining the physical energy index according to the surface temperature distribution field and the surface humidity distribution field includes: Obtain discrete temperature measurement data at different locations on the chip surface and obtain a continuous surface temperature distribution field through interpolation algorithm; Identify the highest temperature area in the temperature distribution field and mark it as a hot spot concentration area; Obtaining hotspot temperature values ​​at multiple consecutive sampling moments in the hotspot concentration area, and generating temperature change gradients at adjacent moments based on the hotspot temperature values ​​at the multiple consecutive sampling moments; Obtain discrete humidity measurement data at different locations on the chip surface and obtain a continuous surface humidity distribution field through interpolation algorithm; Identify the highest humidity area in the humidity distribution field and record it as the wet spot concentration area; Obtaining hotspot humidity values ​​at multiple consecutive sampling moments in the hotspot concentration area, and generating a humidity change gradient at adjacent moments based on the hotspot humidity values ​​at multiple consecutive sampling moments; The humidity change gradient and the temperature change gradient are weightedly calculated to obtain a surface comprehensive change value, and the surface comprehensive change value is used as the physical energy index.

5. The automated testing method for chip particles according to claim 1, characterized in that: The step of obtaining the chip particle comprehensive performance index according to the physical energy index and the electrical performance index includes: Normalizing the physical energy index to obtain a normalized physical energy value; Obtaining a physical energy normalized value weight according to the physical energy normalized value; Normalizing the electrical performance index to obtain a normalized electrical performance value; Obtaining an electrical performance normalized value weight according to the electrical performance normalized value; The chip particle comprehensive performance index is calculated according to the physical energy normalized value, the physical energy normalized value weight, the electrical performance normalized value and the electrical performance normalized value weight.

6. An automated testing system for chip particles, used to execute the automated testing method for chip particles according to any one of claims 1 to 5, characterized in that: include: A first acquisition module is used to acquire installation and matching parameters between the chip particles and the automated testing equipment, wherein the installation and matching parameters include association data and contact characteristic parameters between the chip particles and the automated testing equipment; A second acquisition module is configured to acquire an installation fit index based on the associated data and the contact characteristic parameter, and determine whether the installation fit index exceeds a threshold; If the installation fit index does not exceed the threshold, obtaining physical distribution parameters and electrical characteristic parameters of the chip particles, and obtaining electrical response characteristics based on the electrical characteristic parameters, wherein the electrical response characteristics include timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics, and obtaining the electrical performance index based on the timing delay characteristics, current ripple characteristics, and power consumption fluctuation characteristics; A third acquisition module is used to acquire a surface temperature distribution field and a surface humidity distribution field of the chip particles according to the physical distribution parameters, and to acquire a physical energy index according to the surface temperature distribution field and the surface humidity distribution field; A fourth acquisition module is used to obtain a chip particle comprehensive performance index according to the physical energy index and the electrical performance index; A judgment module, configured to judge whether the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index; If the chip particle comprehensive performance index exceeds a preset chip particle comprehensive performance index, it is determined that the chip particle has a defect.

7. The automatic chip particle testing system according to claim 6, characterized in that: The second acquisition module includes: A first acquisition unit is used to acquire the point space offset, attitude angle, standard geometric center offset and height characteristic parameters of the chip particles according to the associated data; A second acquiring unit is configured to acquire a mechanical coupling error offset index according to the point space offset, the attitude angle, and the geometric center offset; A third obtaining unit is configured to obtain a height difference between a mounting groove reference surface of the automated test equipment and a highest point on a chip particle surface according to the height characteristic parameter, and obtain a height adaptation factor according to the height difference and a preset standard limit height; a third acquiring unit, configured to acquire a contact resistance nominal value and a contact force stability coefficient according to the contact characteristic parameter, and to acquire a contact reliability index according to the contact resistance nominal value and the contact force stability coefficient; The fourth acquiring unit is configured to acquire an installation fit index according to the mechanical coupling error offset index, the height adaptation factor, and the contact reliability index.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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