Driving circuit

Abstract

Disclosed is a driving circuit including: an output circuit connected between a first terminal and a second terminal and configured to output an output signal of a first voltage level or a second voltage level according to voltage levels of a first node and a second node; and a control circuit connected to the output circuit and the input terminal, and for controlling voltage levels of the first node and the second node. The control circuit includes: a first transistor connected between an input terminal and a third node; a second transistor connected between the third node and the fourth node; a third transistor connected between the fourth node and the first node; and an inverter connected between the first terminal and the second terminal and configured to control a voltage of the second node to a voltage level obtained by inverting a voltage level of the first node.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2024-0028153, filed on February 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device, and more particularly, to a driving circuit configured to output a gate signal and a display device including the driving circuit. Background Art

[0003] The display device includes a pixel region including a plurality of pixels, a gate driving circuit, a data driving circuit, a controller, etc. The gate driving circuit includes a stage connected to a gate line, and the stage is configured to supply a gate signal to the gate line connected to the stage in response to a signal received from the controller. Summary of the Invention

[0004] One or more embodiments include a drive circuit configured to stably output a gate signal and a display device including the drive circuit. The technical aspects to be implemented by the embodiments are not limited to the technical aspects mentioned above, and those skilled in the art will clearly understand other technical aspects not mentioned from the disclosed description.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed present embodiments.

[0006] According to one or more embodiments, a driver circuit includes a plurality of stages, wherein each of the plurality of stages includes: an output circuit connected between a first terminal and a second terminal and configured to output an output signal of a first voltage level or a second voltage level depending on the voltage levels of a first node and a second node, wherein the first voltage is input to the first terminal and the second voltage is input to the second terminal; and a control circuit connected to the output circuit and an input terminal and configured to control the voltage levels of the first node and the second node, wherein a start signal is input to the input terminal. The control circuit includes: a first transistor connected between the input terminal and a third node and including a gate connected to the third terminal, wherein a third voltage is input to the third terminal; a second transistor connected between the third node and a fourth node and including a gate connected to a clock terminal, wherein a clock signal is input to the clock terminal; a third transistor connected between the fourth node and the first node and including a gate connected to the third terminal; and an inverter connected between the first terminal and the second terminal and configured to control the voltage of the second node to a voltage level obtained by inverting the voltage level of the first node.

[0007] The second voltage may be lower than the first voltage, and the third voltage may be lower than the first voltage and higher than the second voltage.

[0008] The second transistor may be an N-channel transistor, and the first and third transistors may be P-channel transistors.

[0009] The clock signal may be a signal in which a high-level voltage lower than the first voltage and a low-level voltage higher than the second voltage alternate, and the low-level voltage of the clock signal may be a third voltage.

[0010] The clock signal input to the clock terminal of the even-numbered stages among the plurality of stages may be a signal whose phase is shifted by ½ cycle compared to the clock signal input to the clock terminal of the odd-numbered stages.

[0011] The inverter may include: a fourth transistor connected between the first terminal and the second node and including a gate connected to the first node or the fourth node; and a fifth transistor connected between the second node and the second terminal and including a gate connected to the first node or the fourth node.

[0012] The fourth transistor may be a P-channel transistor, and the fifth transistor may be an N-channel transistor.

[0013] The second transistor may further include a back gate, and a fourth voltage lower than the third voltage is input to the back gate.

[0014] The output circuit may include: a sixth transistor connected between the second terminal and the output terminal and including a gate connected to the first node, and the output signal is output from the output terminal; a seventh transistor connected between the first terminal and the output terminal and including a gate connected to the second node; and a capacitor connected between the first node and the output terminal.

[0015] Each of the plurality of stages may further include an eighth transistor connected between the first terminal and the fourth node and including a gate connected to a reset terminal to which a reset signal is input.

[0016] According to one or more embodiments, a driver circuit includes: a plurality of stages, wherein each of the plurality of stages includes: an output circuit connected between a first terminal and a second terminal and configured to output an output signal of a first voltage level or a second voltage level depending on the voltage levels of a first node and a second node, wherein the first voltage is input to the first terminal and the second voltage is input to the second terminal; and a control circuit connected to the output circuit and an input terminal and configured to control the voltage levels of the first node and the second node, wherein a start signal is input to the input terminal. The control circuit includes: a first transistor connected between the input terminal and a third node and including a gate connected to the third terminal, wherein a third voltage is input to the third terminal; a second transistor connected between the third node and a fourth node and including a gate connected to a clock terminal, wherein a clock signal is input to the clock terminal; a third transistor connected between a fourth node and a fifth node and including a gate connected to the third terminal; a fourth transistor connected between the fifth node and the first node and including a gate connected to a fourth terminal, wherein a fourth voltage is input to the fourth terminal; and an inverter connected between the first terminal and the second terminal and configured to control the voltage of the second node to a voltage level obtained by inverting the voltage level of the first node.

[0017] The second voltage may be lower than the first voltage, the third voltage may be lower than the first voltage, and the fourth voltage may be lower than the third voltage and higher than the second voltage.

[0018] The first transistor and the third transistor may be N-channel transistors, and the second transistor and the fourth transistor may be P-channel transistors.

[0019] The clock signal may be a signal alternating between a high level voltage less than the first voltage and a low level voltage greater than the second voltage, the high level voltage of the clock signal may be a third voltage, and the low level voltage of the clock signal may be a fourth voltage.

[0020] The clock signal input to the clock terminal of the even-numbered stages among the plurality of stages may be a signal whose phase is shifted by ½ cycle compared to the clock signal input to the clock terminal of the odd-numbered stages.

[0021] The inverter may include: a fifth transistor connected between the first terminal and the second node and including a gate connected to the first node or the fifth node; and a sixth transistor connected between the second node and the second terminal and including a gate connected to the first node or the fifth node.

[0022] The fifth transistor may be a P-channel transistor, and the sixth transistor may be an N-channel transistor.

[0023] The first transistor and the third transistor may further include a back gate, and a fifth voltage lower than the fourth voltage is input to the back gate.

[0024] The output circuit may include: a seventh transistor connected between the second terminal and the output terminal and including a gate connected to the first node, and the output signal is output from the output terminal; an eighth transistor connected between the first terminal and the output terminal and including a gate connected to the second node; and a capacitor connected between the first node and the output terminal.

[0025] Each of the plurality of stages may further include a ninth transistor connected between the first terminal and the fifth node and including a gate connected to a reset terminal to which a reset signal is input. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects, features and advantages of the disclosed embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic diagram of a driving circuit according to an embodiment; Figure 2 is a schematic diagram of input / output signals of a driving circuit according to an embodiment; Figure 3 and Figure 4 It is shown that the Figure 1 A schematic diagram of an example of a stage in a driving circuit; Figure 5 It is an explanation Figure 3 The timing diagram of the level drive; Figures 6 to 8 is a schematic diagram of a stage according to an embodiment; Figures 9 to 11 is a schematic diagram of a stage according to an embodiment; Figures 12 to 14 is a schematic diagram of a stage according to an embodiment; Figure 15 is a schematic diagram of a driving circuit according to an embodiment; Figure 16 and Figure 17 It is shown that the Figure 15 A schematic diagram of an example of a stage in a driving circuit; Figure 18 It is an explanation Figure 16 and Figure 17 The timing diagram of the level drive; Figures 19 to 21 is a schematic diagram of a stage according to an embodiment; Figures 22 to 24 is a schematic diagram of a stage according to an embodiment; Figures 25 to 27 is a schematic diagram of a stage according to an embodiment; Figures 28 to 30 is a schematic diagram of a stage according to an embodiment; Figures 31 to 33 is a schematic diagram of a stage according to an embodiment; Figures 34 to 36 is a schematic diagram of a stage according to an embodiment; Figures 37 to 39 is a schematic diagram of a stage according to an embodiment; and Figure 40 is a schematic diagram of a display device according to an embodiment. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to the embodiments, examples of which are shown in the accompanying drawings, in which like reference numerals represent like elements throughout. In this regard, the embodiments may have different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below solely with reference to the accompanying drawings to illustrate aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0028] Because the disclosure allows for various changes and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in the written description. The effects and features of the disclosure and methods for achieving them will be explained with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the disclosure is not limited to the following embodiments and may be embodied in various forms.

[0029] Although terms such as "first" and "second" may be used to describe various elements, these elements must not be limited to the above terms. The above terms are used to distinguish one element from another.

[0030] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0031] It will be understood that the terms “comprises,” “comprising,” and / or variations thereof as used herein specify the presence of stated features or elements, but do not preclude the addition of one or more other features or elements.

[0032] For the convenience of explanation, the size of the elements in the drawings may be enlarged or reduced. As an example, for the convenience of description, the size and thickness of each element shown in the drawings are arbitrarily represented, and therefore, the disclosure is not necessarily limited thereto.

[0033] In the present specification, “A and / or B” means A or B, or A and B. In the present specification, “at least one of A and B” means A or B, or A and B.

[0034] In the following embodiments, when it is described that X is connected to Y, X may be physically connected to Y, X may be functionally connected to Y, or X may be electrically connected to Y. In addition, when it is described that X is connected to Y, X may be directly connected to Y, or X may be indirectly connected to Y with another element between X and Y. Here, X and Y may be elements (e.g., devices, elements, circuits, wirings, electrodes, terminals, layers, films, regions, etc.).

[0035] As an example, when X and Y are electrically connected to each other, this may include a case where X and Y are directly electrically connected to each other, and / or a case where X and Y are indirectly electrically connected to each other with another element between X and Y. The case where X is directly electrically connected to Y may include a case where at least one element (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) that enables electrical connection between X and Y is connected between X and Y. Therefore, X and Y are not limited to the preset connection relationship and the connection relationship shown and made in the drawings and detailed description, but may include connection relationships other than the connection relationships shown and made in the drawings and detailed description.

[0036] In the following embodiments, "ON" used in association with an element state may represent the activated state of the element, and "OFF" may represent the deactivated state of the element. "ON" used in association with a signal received by an element may represent a signal that activates the element, and "OFF" may represent a signal that deactivates the element. An element can be activated by a high-level voltage or a low-level voltage. As an example, a P-channel transistor (P-type transistor) can be activated by a low-level voltage, and an N-channel transistor (N-type transistor) can be activated by a high-level voltage. Therefore, it should be understood that the "ON" voltages for P-channel transistors and N-channel transistors are opposite (low and high) voltage levels. Hereinafter, the voltage that activates (turns on) a transistor is referred to as the gate-on voltage, and the voltage that deactivates (turns off) a transistor is referred to as the gate-off voltage.

[0037] Figure 1 is a schematic diagram of a driving circuit DRV according to an embodiment. Figure 2 FIG. 1 is a schematic diagram of input / output signals of a driving circuit DRV according to an embodiment.

[0038] Reference Figure 1 According to an embodiment, the driving circuit DRV may include a plurality of stages ST1 to STn. The plurality of stages ST1 to STn may be configured to sequentially output output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n], respectively.

[0039] Each of the stages ST1 to STn can be connected to a signal line. Each of the stages ST1 and STn can receive at least one clock signal and at least one voltage signal and generate an output signal OUT (see Figure 3 ), and transmits the output signal OUT to the signal line connected thereto. Stages ST1 to STn-1 may be configured to generate carry signals CR[1], CR[2], CR[3], CR[4], ..., CR[n-1], respectively, and output them to the next stage. In an embodiment, the carry signals CR[1], CR[2], CR[3], CR[4], ..., CR[n-1] may be output signals output by the previous stage (hereinafter referred to as previous output signals).

[0040] Each of the stages ST1 to STn may include a plurality of terminals to which a plurality of signals are input or output. The plurality of signals may include a clock signal and a voltage signal. The plurality of terminals may include an input terminal IN, a first voltage input terminal V11, a second voltage input terminal V12, a third voltage input terminal V13, a clock terminal CK, and an output terminal GOUT.

[0041] A start signal may be input (transmitted) to an input terminal IN. A plurality of stages ST1 to STn may be configured to output output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n], respectively, in response to the start signal. The start signal may be an external signal FLM or carry signals CR[1], CR[2], CR[3], CR[4], ..., CR[n-1]. The external signal FLM as a start signal may be input to the input terminal IN of the first stage ST1, and a previous output signal may be input as a start signal to the input terminal IN of each of the second stage ST2 to the nth stage STn. The previous stage may be a stage located at least one previous stage before the current stage. Figure 1 An example in which the previous stage is the immediately previous stage is shown. As an example, the third output signal OUT[3] output from the third stage ST3 may be input to the input terminal IN of the fourth stage ST4 as a carry signal and a start signal.

[0042] The first voltage VGH can be input to the first voltage input terminal V11, the second voltage VGL can be input to the second voltage input terminal V12, and the third voltage VGL2 can be input to the third voltage input terminal V13. The second voltage VGL can be a voltage lower than the first voltage VGH. The third voltage VGL2 can be lower than the first voltage VGH and higher than the second voltage VGL. The voltage level of the second voltage VGL can be lower than the voltage level of the first voltage VGH. The voltage level of the third voltage VGL2 can be between the voltage levels of the first voltage VGH and the second voltage VGL. The first voltage VGH can be represented by a high-level voltage, and the second voltage VGL and the third voltage VGL2 can be represented by low-level voltages. In an embodiment, although the first voltage VGH can be approximately 6.5V, the second voltage VGL can be approximately -9.5V, and the third voltage VGL2 can be approximately -7V, the embodiment is not limited thereto.

[0043] Clock signal CLK (see Figure 3 ) can be input to the clock terminal CK. The clock signal CLK may include a first clock signal CLK1 and a second clock signal CLK2. The first clock signal CLK1 or the second clock signal CLK2 can be input to the clock terminal CK. In an embodiment, the first clock signal CLK1 can be input to the clock terminals CK of the odd-numbered stages ST1, ST3, ..., and the second clock signal CLK2 can be input to the clock terminals CK of the even-numbered stages ST2, ST4, .... In an embodiment, the second clock signal CLK2 can be input to the clock terminals CK of the odd-numbered stages ST1, ST3, ..., and the first clock signal CLK1 can be input to the clock terminals CK of the even-numbered stages ST2, ST4, ....

[0044] like Figure 2 As shown in , the first clock signal CLK1 and the second clock signal CLK2 may be square wave signals in which a high-level voltage and a low-level voltage are repeated. In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 may be square wave signals in which a high-level voltage CLK_HL less than the first voltage VGH and a low-level voltage CLK_LL greater than the second voltage VGL are repeated. In an embodiment, the low-level voltage CLK_LL of the clock signal CLK may be a third voltage VGL2. In an embodiment, although the high-level voltage CLK_HL of the clock signal CLK may be approximately 4V and the low-level voltage CLK_LL of the clock signal CLK may be approximately -7V, the embodiment is not limited thereto.

[0045] The first clock signal CLK1 and the second clock signal CLK2 can be signals having the same waveform with a phase shift. As an example, the second clock signal CLK2 can have the same waveform as the first clock signal CLK1 and be input with a phase shift (phase delay) of a preset interval. The second clock signal CLK2 can be shifted from the first clock signal CLK1 by half a cycle. In an embodiment, the duration of maintaining a high-level voltage during a cycle of the first clock signal CLK1 and the second clock signal CLK2 can be equal to the duration of maintaining a low-level voltage. In an embodiment, the duration of maintaining a high-level voltage during a cycle of the first clock signal CLK1 and the second clock signal CLK2 can be less than the duration of maintaining a low-level voltage.

[0046] The output signal can be output from the output terminal GOUT. Figure 2 As shown in FIG, the output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n] outputted from the output terminals GOUT of the stages ST1 to STn may be sequentially shifted by a preset interval. In an embodiment, the stages ST1 to STn may be configured to sequentially shift the output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n] of the high-level voltage by 1 / 2 cycle of the clock signal and output them. In an embodiment, the high-level voltage OUT_HL and the low-level voltage OUT_LL of the output signal may be a first voltage VGH and a second voltage VGL, respectively.

[0047] In an embodiment, the variation width of the high-level voltage CLK_HL and the low-level voltage CLK_LL of the clock signal CLK may be smaller than the variation width of the high-level voltage OUT_HL and the low-level voltage OUT_LL of the output signal OUT. Therefore, the increase in power consumption due to the capacitance formed between the clock lines, etc., can be effectively reduced.

[0048] Figure 3 and Figure 4 It is shown that the Figure 1 A schematic diagram of an example of a driving circuit in stage ST. Figure 5 It is an explanation Figure 3 The driving timing diagram of stage ST.

[0049] Reference Figure 3 and Figure 4, stage ST may include a control circuit 131 and an output circuit 135. Each of the control circuit 131 and the output circuit 135 may include at least one transistor. In an embodiment, the at least one transistor may include an N-channel transistor and / or a P-channel transistor. In an embodiment, the impurity conductivity type of the second transistor T12 and the fifth transistor T15 of stage ST may be opposite to the impurity conductivity type of the remaining transistors. As an example, the second transistor T12 and the fifth transistor T15 may be N-channel transistors, and the first transistor T11, the third transistor T13, the fourth transistor T14, the sixth transistor T16, and the seventh transistor T17 may be P-channel transistors.

[0050] The N-channel transistor may be an oxide transistor. The oxide transistor may include an oxide semiconductor that is a Zn oxide-based material and may include Zn oxide, In-Zn oxide, and / or Ga-In-Zn oxide, etc. In an embodiment, the oxide semiconductor may be an In-Ga-Zn-O ("IGZO") semiconductor. In an embodiment, the oxide semiconductor may be an In-Sn-Ga-Zn-O ("ITGZO") semiconductor. As an example, the oxide transistor may be a low-temperature polycrystalline silicon oxide ("LTPS") thin film transistor. The gate turn-on voltage of the N-channel transistor may be a high-level voltage, and the gate turn-off voltage of the N-channel transistor may be a low-level voltage.

[0051] The P-channel transistor may be a silicon transistor. The silicon transistor may include a silicon semiconductor, which may include amorphous silicon and / or polycrystalline silicon. For example, the silicon transistor may be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The gate turn-on voltage of the P-channel transistor may be a low-level voltage, and the gate turn-off voltage of the P-channel transistor may be a high-level voltage.

[0052] The control circuit 131 may be configured to control the voltages of the first node Q2 and the second node QB in response to a signal input to the input terminal IN. As an example, the control circuit 131 may be configured to control the voltages of the first node Q2 and the second node QB in response to a start signal STV (eg, an external signal FLM or a carry signal CR (see Figure 1 )) to control the voltage of the first node Q2 and the second node QB. In an embodiment, the carry signal CR can be the previous output signal OUT' (see Figure 5 ). The control circuit 131 may include first to fifth transistors T11 to T15.

[0053] The first to third transistors T11 to T13 may be connected between the input terminal IN and the first node Q2. For ease of description, hereinafter, the node between the first transistor T11 and the second transistor T12 is referred to as the third node FQ, and the node between the second transistor T12 and the third transistor T13 is referred to as the fourth node Q1.

[0054] The first transistor T11 may be connected between the input terminal IN and the third node FQ. The gate of the first transistor T11 may be connected to the third voltage input terminal V13. The first transistor T11 may be turned on by the third voltage VGL2 input to the third voltage input terminal V13 and may be configured to transmit the start signal STV to the third node FQ. When a low-level clock signal CLK is input to the gate of the second transistor T12, the first transistor T11 may prevent the second transistor T12 from being turned on by the low-level start signal STV.

[0055] The second transistor T12 can be connected between the third node FQ and the fourth node Q1. The gate of the second transistor T12 can be connected to the clock terminal CK. The second transistor T12 can be controlled to be turned on and off based on the voltage of the third node FQ, the voltage of the fourth node Q1, and the voltage of the clock signal CLK input to the clock terminal CK, and is configured to transmit the signal transmitted to the third node FQ to the fourth node Q1 when it is turned on. The clock signal CLK can be the first clock signal CLK1 or the second clock signal CLK2. The second transistor T12 can be configured to control the electrical connection between the third node FQ and the fourth node Q1. The second transistor T12 can disconnect the third node FQ from the fourth node Q1, allowing the first node Q2 and the fourth node Q1 to be self-boosted.

[0056] The third transistor T13 may be connected between the fourth node Q1 and the first node Q2. The gate of the third transistor T13 may be connected to the third voltage input terminal V13. The third transistor T13 may be configured to be turned on or off based on the voltage of the fourth node Q1, the voltage of the first node Q2, and the third voltage VGL2 input to the third voltage input terminal V13. When turned on, the third transistor T13 may transmit a signal transmitted to the fourth node Q1 to the first node Q2 or transmit a signal from the first node Q2 to the fourth node Q1. The third transistor T13 may be configured to control the electrical connection between the fourth node Q1 and the first node Q2. The third transistor T13 may disconnect the fourth node Q1 from the first node Q2, thereby bootstrapping the first node Q2 downward. When the voltage VQ2 of the first node Q2 is low and the voltage VQ1 of the fourth node Q1 is less than the third voltage VGL2, the third transistor T13 may be turned off, and the voltage VQ2 of the first node Q2 may be unaffected by the oscillation of the voltage VQ1 of the fourth node Q1.

[0057] The fourth transistor T14 may be connected between the first voltage input terminal V11 and the second node QB. Figure 3 As shown in FIG, the gate of the fourth transistor T14 may be connected to the first node Q2. Figure 4 As shown in FIG, the gate of the fourth transistor T14 can be connected to the fourth node Q1. When the voltage of the first node Q2 or the fourth node Q1 is at a low level, the fourth transistor T14 can be turned on and configured to transmit the first voltage VGH input to the first voltage input terminal V11 to the second node QB. Due to the fourth transistor T14, the voltage level of the second node QB can be opposite to the voltage level of the fourth node Q1.

[0058] The fifth transistor T15 may be connected between the second node QB and the second voltage input terminal V12. Figure 3 As shown in FIG, the gate of the fifth transistor T15 may be connected to the first node Q2. Figure 4 As shown in FIG, the gate of the fifth transistor T15 can be connected to the fourth node Q1. When the voltage of the first node Q2 or the fourth node Q1 is at a high level, the fifth transistor T15 can be turned on and configured to transmit the second voltage VGL input to the second voltage input terminal V12 to the second node QB. Due to the fifth transistor T15, the voltage level of the second node QB can be opposite to the voltage level of the fourth node Q1.

[0059] The fourth transistor T14 and the fifth transistor T15 may be configured to control a voltage level of a voltage of the second node QB according to a voltage level of a voltage of the first node Q2 or the fourth node Q1 , and may function as an inverter or a level shifter.

[0060] The output circuit 135 may be connected between the first voltage input terminal V11 and the second voltage input terminal V12. The output circuit 135 may be configured to output an output signal OUT of a high-level voltage or a low-level voltage according to the voltage level of the first node Q2 or the second node QB. The output circuit 135 may include a sixth transistor T16 and a seventh transistor T17. The output circuit 135 may also include a capacitor C1.

[0061] The sixth transistor T16 may be connected between the output terminal GOUT and the second voltage input terminal V12. The gate of the sixth transistor T16 may be connected to the first node Q2. The sixth transistor T16 may be a pull-down transistor configured to transmit a low-level voltage to the output terminal GOUT. When the voltage of the first node Q2 is at a low level, the sixth transistor T16 may be turned on and configured to transmit the second voltage VGL input to the second voltage input terminal V12 to the output terminal GOUT.

[0062] The seventh transistor T17 may be connected between the first voltage input terminal V11 and the output terminal GOUT. The gate of the seventh transistor T17 may be connected to the second node QB. The seventh transistor T17 may be a pull-up transistor configured to transmit a high-level voltage to the output terminal GOUT. When the voltage of the second node QB is at a low level, the seventh transistor T17 may be turned on and configured to transmit the first voltage VGH input to the first voltage input terminal V11 to the output terminal GOUT.

[0063] The capacitor C1 may be connected between the output terminal GOUT and the first node Q2 .

[0064] In the following, reference is made to Figure 5 right Figure 3 and Figure 4 The operation of the stage ST shown in FIG is described. For the convenience of description, the Figure 3 and Figure 4 In this example, the stage ST (the current stage) is an odd-numbered stage, and the first clock signal CLK1 is input to the clock terminal CK. The even-numbered stages are identical in configuration and operation to the odd-numbered stages, differing only in that the second clock signal CLK2 is input to the clock terminal CK of the even-numbered stages. The start signal STV of the first stage (that is, the first stage ST1) can be the external signal FLM, and the start signal STV of subsequent stages can be the previous output signal OUT'. Figure 5 yes Figure 3 and Figure 4 Stage ST is a timing diagram of an example of an arbitrary stage among odd-numbered stages after the second stage.

[0065] The high-level voltage OUT_HL of the previous output signal OUT' and the output signal OUT may be approximately the first voltage VGH, and the low-level voltage OUT_LL may be approximately the second voltage VGL. The high-level voltage CLK_HL of the first clock signal CLK1 may be lower than the first voltage VGH, and the low-level voltage CLK_LL may be a third voltage VGL2 greater than the second voltage VGL.

[0066] During the first section P11 , a high-level previous output signal OUT′ may be input to the input terminal IN, and a low-level first clock signal CLK1 may be input to the clock terminal CK.

[0067] The first transistor T11 can be turned on according to the low-level third voltage VGL2, the high-level previous output signal OUT' can be transmitted through the turned-on first transistor T11, and the voltage VFQ of the third node FQ can be increased to a high-level voltage FQ_HL approximately equal to the high-level voltage OUT_HL of the previous output signal OUT'.

[0068] Because, when the voltage VQ1 of the fourth node Q1 is a low-level voltage Q1_LL2 less than the third voltage VGL2, the voltage VFQ of the third node FQ is a high-level voltage FQ_HL, and the first clock signal CLK1 is a low-level voltage CLK_LL, the second transistor T12 is turned on, and the voltage VQ1 of the fourth node Q1 can rise. When the low-level voltage Q1_LL1 of the fourth node Q1 reaches the third voltage VGL2, the second transistor T12 can be turned off.

[0069] When the low-level voltage Q1_LL1 of the fourth node Q1 changes to the third voltage VGL2, the third transistor T13 may be turned off and the voltage VQ2 of the first node Q2 may maintain the low-level voltage Q2_LL of the previous section. The sixth transistor T16 having a gate connected to the first node Q2 may be turned on, the second voltage VGL may be transmitted to the output terminal GOUT through the turned-on sixth transistor T16, and a low-level output signal OUT may be output from the output terminal GOUT.

[0070] Since the fourth transistor T14 having a gate connected to the first node Q2 or the fourth node Q1 is turned on and the fifth transistor T15 is turned off, the voltage VQB of the second node QB remains high, and thus the seventh transistor T17 may be turned off. The high-level voltage QB_HL of the second node QB may be approximately the first voltage VGH.

[0071] During the second section P12 , the previous output signal OUT′ of a high level may be input to the input terminal IN, and the first clock signal CLK1 of a high level may be input to the clock terminal CK.

[0072] The high-level previous output signal OUT' can be transmitted to the third node FQ through the first transistor T11 turned on according to the low-level third voltage VGL2, and the voltage VFQ of the third node FQ can be the high-level voltage FQ_HL approximately equal to the high-level voltage OUT_HL of the previous output signal OUT'.

[0073] The second transistor T12 can be turned on in response to the high-level first clock signal CLK1, and the third transistor T13 can be turned on in response to the low-level third voltage VGL2. The third node FQ, the fourth node Q1, and the first node Q2 can be electrically connected to each other through the turned-on second transistor T12 and the third transistor T13, and the voltage VQ1 of the fourth node Q1 and the voltage VQ2 of the first node Q2 can rise to a high level. When the voltage VQ1 of the fourth node Q1 reaches the high-level voltage CLK_HL of the first clock signal CLK1, the second transistor T12 can be turned off. The sixth transistor T16, having a gate connected to the first node Q2, can be turned off.

[0074] The fourth transistor T14 having a gate connected to the first node Q2 or the fourth node Q1 may be turned off, and the fifth transistor T15 may be turned on. The low-level second voltage VGL may be transmitted to the second node QB through the turned-on fifth transistor T15, and the low-level voltage QB_LL of the second node QB may be approximately the second voltage VGL.

[0075] The seventh transistor T17, having a gate connected to the second node QB, may be turned on. The first voltage VGH may be transmitted to the output terminal GOUT through the turned-on seventh transistor T17, and a high-level output signal OUT may be output from the output terminal GOUT. In this case, as the output signal OUT rises from a low level to a high level, the first node Q2 is bootstrapped upward through the coupling of the capacitor C1, and the voltage VQ2 of the first node Q2 may rise further. The voltage VQ1 of the fourth node Q1 may further rise due to the turned-on third transistor T13. During the second section P12, the high-level voltage Q2_HL of the first node Q2 and the high-level voltage Q1_HL of the fourth node Q1 may be greater than the first voltage VGH. During the second section P12, the high-level voltage Q2_HL of the first node Q2 and the high-level voltage Q1_HL of the fourth node Q1 may be greater than the high-level voltage FQ_HL of the third node FQ.

[0076] During the third section P13 , the previous output signal OUT′ of a high level may be input to the input terminal IN, and the first clock signal CLK1 of a low level may be input to the clock terminal CK.

[0077] The high level previous output signal OUT' may be transmitted to the third node FQ through the first transistor T11 turned on according to the low level third voltage VGL2, and the third node FQ may be at a high level voltage FQ_HL approximately equal to the high level voltage OUT_HL of the previous output signal OUT'.

[0078] The second transistor T12 can be turned off according to the high-level voltage FQ_HL of the third node FQ and the low-level voltage CLK_LL of the first clock signal CLK1, and the third transistor T13 can be turned on according to the low-level third voltage VGL2. The voltage VQ2 of the first node Q2 and the voltage VQ1 of the fourth node Q1 maintain a high level in the previous section due to the capacitor C1, and the sixth transistor T16 can maintain a turned-off state.

[0079] Because the fourth transistor T14 having the gate connected to the first node Q2 or the fourth node Q1 is turned off and the fifth transistor T15 is turned on, the second node QB is in a low level state due to the fifth transistor T15, and a high level output signal OUT can be output from the output terminal GOUT through the turned-on seventh transistor T17.

[0080] During the fourth section P14 , the previous output signal OUT′ of a high level may be input to the input terminal IN, and the first clock signal CLK1 of a high level may be input to the clock terminal CK.

[0081] The high-level previous output signal OUT' can be transmitted to the third node FQ through the first transistor T11 turned on according to the low-level third voltage VGL2, and the voltage VFQ of the third node FQ can be the high-level voltage FQ_HL approximately equal to the high-level voltage OUT_HL of the previous output signal OUT'.

[0082] Because the high-level voltage CLK_HL of the first clock signal CLK1 is lower than the high-level voltage FQ_HL of the third node FQ, the second transistor T12 may be turned off and the third transistor T13 may be turned on according to the low-level third voltage VGL2. The voltage VQ2 of the first node Q2 and the voltage VQ1 of the fourth node Q1 remain at a high level in the previous section due to the capacitor C1, and the sixth transistor T16 may remain in a turned-off state.

[0083] The fourth transistor T14 having a gate connected to the first node Q2 or the fourth node Q1 may be turned off, and the fifth transistor T15 may be turned on. The low-level second voltage VGL may be transmitted to the second node QB through the turned-on fifth transistor T15, and the seventh transistor T17 may be turned on. The first voltage VGH may be transmitted to the output terminal GOUT through the turned-on seventh transistor T17, and a high-level output signal OUT may be output from the output terminal GOUT.

[0084] During the fifth section P15 , the previous output signal OUT′ of a high level may be input to the input terminal IN, and the first clock signal CLK1 of a low level may be input to the clock terminal CK.

[0085] The high-level previous output signal OUT' may be transmitted to the third node FQ through the first transistor T11 turned on by the low-level third voltage VGL2, and the voltage VFQ of the third node FQ may be a high-level voltage FQ_HL approximately equal to the high-level voltage OUT_HL of the previous output signal OUT'.

[0086] The second transistor T12 can be turned off according to the low-level first clock signal CLK1, and the third transistor T13 can be turned on according to the low-level third voltage VGL2. The voltage VQ2 of the first node Q2 and the voltage VQ1 of the fourth node Q1 maintain the high level of the previous section due to the capacitor C1, and the sixth transistor T16 can be kept in the off state.

[0087] The fifth transistor T15 having the gate connected to the first node Q2 and the fourth node Q1 may maintain a turned-on state, and a high-level output signal OUT may be output from the output terminal GOUT through the turned-on seventh transistor T17 .

[0088] During the sixth section P16 , the previous output signal OUT′ of a low level may be input to the input terminal IN, and the first clock signal CLK1 of a low level may be input to the clock terminal CK.

[0089] The low-level previous output signal OUT' can be transmitted to the third node FQ through the first transistor T11 that is turned on by the low-level third voltage VGL2, and the voltage VFQ of the third node FQ can decrease. In this case, due to the threshold voltage loss of the first transistor T11, the low-level voltage FQ_LL1 of the third node FQ can be greater than the low-level voltage OUT_LL of the previous output signal OUT'. When the low-level voltage FQ_LL1 of the third node FQ reaches the third voltage VGL2, the second transistor T12 can be turned off.

[0090] The third transistor T13 is turned on due to the low-level third voltage VGL2 , the voltage VQ2 of the first node Q2 and the voltage VQ1 of the fourth node Q1 can maintain the high level of the previous section due to the capacitor C1 , and the sixth transistor T16 can maintain the off state.

[0091] The fifth transistor T15 having the gate connected to the first node Q2 or the fourth node Q1 may maintain a turned-on state, and a high-level output signal OUT may be output from the output terminal GOUT through the turned-on seventh transistor T17 .

[0092] During the seventh section P17 , the previous output signal OUT′ of a low level may be input to the input terminal IN, and the first clock signal CLK1 of a high level may be input to the clock terminal CK.

[0093] The low-level previous output signal OUT′ may be transmitted to the third node FQ through the first transistor T11 turned on by the low-level third voltage VGL2 , and the voltage VFQ of the third node FQ may be the low-level voltage FQ_LL1 equal to the low-level voltage FQ_LL1 of the sixth section P16 .

[0094] The second transistor T12 can be turned on according to the high-level first clock signal CLK1, and the third transistor T13 can be turned on according to the low-level third voltage VGL2. The third node FQ, the fourth node Q1, and the first node Q2 can be electrically connected to each other through the turned-on second transistor T12 and the third transistor T13, and the voltages of the fourth node Q1 and the first node Q2 can drop to a low level. When the low-level voltage Q1_LL1 of the fourth node Q1 reaches the third voltage VGL2, the third transistor T13 can be turned off.

[0095] The sixth transistor T16, having a gate connected to the first node Q2, may be turned on. The second voltage VGL may be transmitted to the output terminal GOUT through the turned-on sixth transistor T16, and a low-level output signal OUT may be output from the output terminal GOUT. In this case, as the output signal OUT drops from a high level to a low level, the first node Q2 is bootstrapped downward through the coupling of the capacitor C1, and the voltage VQ2 of the first node Q2 may drop further. During the seventh section P17, the low-level voltage Q2_LL of the first node Q2 may be lower than the second voltage VGL. During the seventh section P17, the low-level voltage Q2_LL of the first node Q2 may be lower than the low-level voltage FQ_LL1 of the third node FQ and the low-level voltage Q1_LL1 of the fourth node Q1.

[0096] The fourth transistor T14 having a gate connected to the first node Q2 or the fourth node Q1 may be turned on, and the fifth transistor T15 may be turned off. The high level first voltage VGH may be transmitted to the second node QB through the turned-on fourth transistor T14, and the seventh transistor T17 may be turned off.

[0097] After the seventh section P17 , the previous output signal OUT′ of a low level may be input to the input terminal IN, and the first clock signal CLK1 of a low level and the first clock signal CLK1 of a high level may be alternately input to the clock terminal CK.

[0098] Since the low-level voltage Q2_LL of the first node Q2 maintained by the capacitor C1 is lower than the second voltage VGL, the third transistor T13 may be in an off state. The sixth transistor T16 may remain in an on state and may output a low-level output signal OUT from the output terminal GOUT.

[0099] The low-level previous output signal OUT' can be transmitted to the third node FQ through the first transistor T11 that is turned on by the low-level third voltage VGL2. When the low-level first clock signal CLK1 is input, the second transistor T12 can be turned off, the voltage VFQ of the third node FQ can drop to the low-level voltage FQ_LL2 due to coupling of the parasitic capacitor of the second transistor T12, and the voltage VQ1 of the fourth node Q1 can drop to the low-level voltage Q1_LL2. When the high-level first clock signal CLK1 is input, the second transistor T12 can be turned on, and the voltage VQ1 of the fourth node Q1 can become the low-level voltage Q1_LL1 equal to the low-level voltage FQ_LL1 of the third node FQ.

[0100] When the voltage VQ2 of the first node Q2 maintains the low-level voltage Q2_LL, the third transistor T13 may be turned off, and the voltage VQ2 of the first node Q2 may not be affected by the voltage oscillation of the fourth node Q1 .

[0101] Figures 6 to 8 is a schematic diagram of a stage according to an embodiment.

[0102] Figure 6 and Figure 7 The level ST shown in Figure 3 and Figure 4 The stage ST shown in FIG. 1 is different in that a fourth voltage VGL3 is input to the back gate of the second transistor T12 . Figure 6 and Figure 7 The other configurations and operations of the stage ST shown in Figure 3 and Figure 4 The configuration and operation of the stage ST shown in are the same.

[0103] In an embodiment, Figure 8 As shown in , the stage ST may further include a fourth voltage input terminal V14 to which the fourth voltage VGL3 is input. The second transistor T12 may be a dual-gate transistor further including a back gate connected to the fourth voltage input terminal V14. The gate of the second transistor T12 may be a top gate provided on the upper portion of the semiconductor, and the back gate may be a bottom gate provided on the lower portion of the semiconductor.

[0104] When a (-) voltage is applied to the back gate of the oxide transistor, the threshold voltage can increase and positively shift, and when a (+) voltage is applied to the back gate, the threshold voltage can decrease and negatively shift. When the fourth voltage VGL3 is input to the back gate of the second transistor T12, the threshold voltage of the second transistor T12 is positively shifted, and the second transistor T12 can be prevented from operating in the depletion mode due to the negative shift.

[0105] The fourth voltage VGL3 may be lower than the third voltage VGL2. The difference between the fourth voltage VGL3 and the third voltage VGL2 may be approximately 3V, and the fourth voltage VGL3 may be approximately -10V. However, the embodiment is not limited thereto. The difference between the fourth voltage VGL3 and the third voltage VGL2 may be determined by the amount of change in the threshold voltage of the second transistor T12. The fourth voltage VGL3 may be represented by a low-level voltage.

[0106] Figures 9 to 11 is a schematic diagram of a stage ST according to an embodiment.

[0107] Figure 9 and Figure 10 The level ST shown in Figure 3 and Figure 4 The stage ST shown in FIG. 1 is different in that the stage ST may further include an eighth transistor T18 as a reset circuit. Figure 9 and Figure 10 The other configurations and operations of the stage ST shown in Figure 3 and Figure 4 The configuration and operation of the stage ST shown in are the same.

[0108] In an embodiment, Figure 11 As shown in , the stage ST may further include a reset terminal RS, to which a reset signal ESR is input. The eighth transistor T18 may be configured to reset the fourth node Q1 based on the reset signal ESR supplied to the reset terminal RS. The eighth transistor T18 may be connected between the first voltage input terminal V11 and the fourth node Q1, and the gate of the eighth transistor T18 may be connected to the reset terminal RS. When a low-level reset signal ESR is input to the reset terminal RS, the eighth transistor T18 may be turned on to reset the fourth node Q1 to the first voltage VGH. Therefore, the fifth transistor T15 may be turned on and a high-level output signal OUT may be output, and an error in which the sixth transistor T16 is turned on and outputs a low-level output may be prevented.

[0109] In an embodiment, when an operation error occurs, the reset signal ESR may be supplied as a low level to the first to n-th stages ST1 to STn at a specific time point. The reset signal ESR may be supplied as a pulse form having a low level of the second voltage VGL at a preset timing, and supplied as the first voltage VGH at other timings.

[0110] Figures 12 to 14 is a schematic diagram of a stage ST according to an embodiment.

[0111] Figure 12 and Figure 13 The level ST shown in Figure 3 and Figure 4The stage ST shown in FIG. 1 is different in that a fourth voltage VGL3 is input to the back gate of the second transistor T12 and an eighth transistor T18 is further included as a reset circuit. Figure 12 and Figure 13 The other configurations and operations of the stage ST shown in Figure 3 and Figure 4 The configuration and operation of the stage ST shown in are the same.

[0112] In an embodiment, Figure 14 As shown in FIG, the stage ST may further include a fourth voltage input terminal V14 and a reset terminal RS, the fourth voltage VGL3 is input to the fourth voltage input terminal V14, and the reset signal ESR is input to the reset terminal RS. Figures 6 to 11 The configurations and operations of the second transistor T12 and the eighth transistor T18 are described, so descriptions thereof are omitted below.

[0113] Figure 15 Schematic diagram of a driving circuit DRV according to an embodiment. Figure 1 The differences between the driving circuits DRV shown in FIG. 1 and FIG. 2 are omitted, and detailed description of the same configuration is omitted.

[0114] Reference Figure 15 According to an embodiment, the driving circuit DRV may include a plurality of stages ST1 to STn. The plurality of stages ST1 to STn may be configured to sequentially output output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n].

[0115] Each of the stages ST1 to STn may include an input terminal IN, a first voltage input terminal V21 , a second voltage input terminal V22 , a third voltage input terminal V23 , a fourth voltage input terminal V24 , a clock terminal CK, and an output terminal GOUT.

[0116] A start signal may be input (supplied or provided) to the input terminal IN. A plurality of stages ST1 to STn may be configured to output output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n], respectively, in response to the start signal. The start signal may be an external signal FLM or carry signals CR[1], CR[2], CR[3], CR[4], ..., CR[n-1]. The external signal FLM as the start signal may be input to the input terminal IN of the first stage ST1, and the previous output signal OUT' may be input as the start signal to the input terminal IN of each of the second stage ST2 to the nth stage STn.

[0117] A first voltage VGH may be input to a first voltage input terminal V21, a second voltage VGL may be input to a second voltage input terminal V22, a third voltage VGL2 may be input to a third voltage input terminal V23, and a fifth voltage VGH2 may be input to a fourth voltage input terminal V24. The second voltage VGL may be a voltage lower than the first voltage VGH. The third voltage VGL2 may be lower than the first voltage VGH and higher than the second voltage VGL. The fifth voltage VGH2 may be lower than the first voltage VGH and higher than the third voltage VGL2. The voltage level of the second voltage VGL may be lower than the voltage level of the first voltage VGH. The voltage level of the third voltage VGL2 may be between the voltage levels of the first voltage VGH and the second voltage VGL. The voltage level of the fifth voltage VGH2 may be between the voltage levels of the first voltage VGH and the third voltage VGL2. The first voltage VGH and the fifth voltage VGH2 may be represented by high-level voltages, while the second voltage VGL and the third voltage VGL2 may be represented by low-level voltages. In an embodiment, the first voltage VGH may be about 6.5 V, the fifth voltage VGH2 may be about 4 V, the second voltage VGL may be about -9.5 V, and the third voltage VGL2 may be about -7 V. However, the embodiment is not limited thereto.

[0118] The clock signal CLK can be input to the clock terminal CK. The clock signal CLK may include a first clock signal CLK1 and a second clock signal CLK2. The first clock signal CLK1 or the second clock signal CLK2 may be input to the clock terminal CK. In an embodiment, the first clock signal CLK1 may be input to the clock terminals of the odd-numbered stages ST1, ST3, ..., and the second clock signal CLK2 may be input to the clock terminals CK of the even-numbered stages ST2, ST4, .... In an embodiment, the second clock signal CLK2 may be input to the clock terminals of the odd-numbered stages ST1, ST3, ..., and the first clock signal CLK1 may be input to the clock terminals CK of the even-numbered stages ST2, ST4, .... In an embodiment, although the high-level voltage CLK_HL of the clock signal CLK may be approximately 4V and the low-level voltage CLK_LL of the clock signal CLK may be approximately -7V, the embodiment is not limited thereto.

[0119] The first clock signal CLK1 and the second clock signal CLK2 may be signals having the same waveform with a shifted phase. As an example, the second clock signal CLK2 may have the same waveform as the first clock signal CLK1 and be input with a phase shift (phase delay) of a preset interval. The second clock signal CLK2 may be shifted from the first clock signal CLK1 by half a cycle. In an embodiment, in the first clock signal CLK1 and the second clock signal CLK2, the duration of maintaining a high level voltage during one cycle may be equal to the duration of maintaining a low level voltage. In an embodiment, as Figure 18 As shown in FIG, in the first clock signal CLK1 and the second clock signal CLK2, a duration for maintaining a high level voltage during one cycle may be greater than a duration for maintaining a low level voltage.

[0120] like Figure 2 As shown in FIG, the output signals OUT[1], OUT[2], OUT[3], OUT[4], ..., OUT[n] of the high-level voltages of the output terminals GOUT of the stages ST1 to STn may be sequentially shifted by 1 / 2 cycle of the clock signal. In an embodiment, the high-level voltage OUT_HL and the low-level voltage OUT_LL of the output signals may be a first voltage VGH and a second voltage VGL, respectively.

[0121] Figure 16 and Figure 17 It is shown that the Figure 15 A schematic diagram of an example of a driving circuit in stage ST. Figure 18 It is an explanation Figure 16 and Figure 17 The driving timing diagram of stage ST.

[0122] Reference Figure 16 and Figure 17 , stage ST may include a control circuit 141 and an output circuit 145. Each of the control circuit 141 and the output circuit 145 may include at least one transistor. In an embodiment, the at least one transistor may include an N-channel transistor and / or a P-channel transistor. In an embodiment, the impurity conductivity type of the first transistor T21, the third transistor T23, and the sixth transistor T26 of stage ST may be opposite to the impurity conductivity type of the remaining transistors. As an example, the first transistor T21, the third transistor T23, and the sixth transistor T26 may be N-channel transistors, and the second transistor T22, the fourth transistor T24, the fifth transistor T25, the seventh transistor T27, and the eighth transistor T28 may be P-channel transistors.

[0123] The control circuit 141 may be configured to control the voltages of the first node Q2 and the second node QB in response to a signal input to the input terminal IN. As an example, the control circuit 141 may be configured to control the voltages of the first node Q2 and the second node QB in response to a start signal STV (eg, an external signal FLM or a carry signal CR (see Figure 15 )) to control the voltages of the first node Q2 and the second node QB. In an embodiment, the carry signal CR may be the previous output signal OUT'. The control circuit 141 may include first to sixth transistors T21 to T26.

[0124] The first to fourth transistors T21 to T24 may be connected between the input terminal IN and the first node Q2. For ease of description, hereinafter, a node between the first transistor T21 and the second transistor T22 is referred to as a third node FQ, a node between the third transistor T23 and the fourth transistor T24 is referred to as a fourth node Q1, and a node between the second transistor T22 and the third transistor T23 is referred to as a fifth node Q0.

[0125] The first transistor T21 may be connected between the input terminal IN and the third node FQ. The gate of the first transistor T21 may be connected to the fourth voltage input terminal V24. The first transistor T21 may be turned on by the fifth voltage VGH2 input to the fourth voltage input terminal V24 and may be configured to transmit the start signal STV to the third node FQ. Because the voltage of the third node FQ becomes lower than the high level voltage of the start signal STV due to the first transistor T21, when the high level clock signal CLK is input to the gate of the second transistor T22, the second transistor T22 may be prevented from turning on.

[0126] The second transistor T22 may be connected between the third node FQ and the fifth node Q0. The gate of the second transistor T22 may be connected to the clock terminal CK. The second transistor T22 may be controlled to be turned on and off based on the voltage of the third node FQ, the voltage of the fifth node Q0, and the voltage of the clock signal CLK input to the clock terminal CK. When turned on, the second transistor T22 is configured to transmit a signal transmitted to the third node FQ to the fifth node Q0. The clock signal CLK may be the first clock signal CLK1 or the second clock signal CLK2. The second transistor T22 may be configured to control the electrical connection between the third node FQ and the fifth node Q0.

[0127] The third transistor T23 may be connected between the fifth node Q0 and the fourth node Q1. The gate of the third transistor T23 may be connected to the fourth voltage input terminal V24. The third transistor T23 may be controlled to be turned on and off based on the voltage of the fifth node Q0, the voltage of the fourth node Q1, and the fifth voltage VGH2 input to the fourth voltage input terminal V24. When turned on, the third transistor T23 is configured to transmit a signal transmitted to the fifth node Q0 to the fourth node Q1. The third transistor T23 may be configured to control the electrical connection between the fifth node Q0 and the fourth node Q1. The third transistor T23 may disconnect the fifth node Q0 from the fourth node Q1, thereby bootstrapping the first node Q2 and the fourth node Q1.

[0128] The fourth transistor T24 can be connected between the fourth node Q1 and the first node Q2. The gate of the fourth transistor T24 can be connected to the third voltage input terminal V23. The fourth transistor T24 can be configured to be turned on or off based on the voltage of the fourth node Q1, the voltage of the first node Q2, and the third voltage VGL2 input to the third voltage input terminal V23. When turned on, the fourth transistor T24 is configured to transmit a signal transmitted to the fourth node Q1 to the first node Q2, or to transmit a signal from the first node Q2 to the fourth node Q1. The fourth transistor T24 can be configured to control the electrical connection between the fourth node Q1 and the first node Q2. The fourth transistor T24 can disconnect the fourth node Q1 from the first node Q2, thereby bootstrapping the first node Q2 downward. When the voltage of the first node Q2 is at a low level, the fourth transistor T24 can be turned off, and the voltage VQ2 of the first node Q2 can be unaffected by the voltage oscillation of the fifth node Q0.

[0129] The fifth transistor T25 may be connected between the first voltage input terminal V21 and the second node QB. Figure 16 As shown in FIG, the gate of the fifth transistor T25 may be connected to the first node Q2. Figure 17 As shown in FIG, the gate of the fifth transistor T25 can be connected to the fourth node Q1. When the voltage of the first node Q2 or the fourth node Q1 is at a low level, the fifth transistor T25 can be turned on and is configured to transmit the first voltage VGH input to the first voltage input terminal V21 to the second node QB. Due to the fifth transistor T25, the voltage level of the second node QB can be opposite to the voltage level of the first node Q2 or the fourth node Q1.

[0130] The sixth transistor T26 may be connected between the second node QB and the second voltage input terminal V22. Figure 16 As shown in FIG, the gate of the sixth transistor T26 may be connected to the first node Q2. Figure 17As shown in FIG, the gate of the sixth transistor T26 can be connected to the fourth node Q1. When the voltage of the first node Q2 or the fourth node Q1 is at a high level, the sixth transistor T26 can be turned on and configured to transmit the second voltage VGL input to the second voltage input terminal V22 to the second node QB. Due to the sixth transistor T26, the voltage level of the second node QB can be opposite to the voltage level of the fourth node Q1.

[0131] The fifth transistor T25 and the sixth transistor T26 may be configured to control a voltage level of a voltage of the second node QB according to a voltage level of a voltage of the first node Q2 or the fourth node Q1 , and may function as inverters or level shifters.

[0132] The output circuit 145 can be connected between the first voltage input terminal V21 and the second voltage input terminal V22. The output circuit 145 can be configured to output an output signal OUT of a high-level voltage or a low-level voltage according to the voltage level of the first node Q2 or the second node QB. The output circuit 145 can include a seventh transistor T27 and an eighth transistor T28. The output circuit 145 can also include a capacitor C2.

[0133] The seventh transistor T27 may be connected between the output terminal GOUT and the second voltage input terminal V22. The gate of the seventh transistor T27 may be connected to the first node Q2. The seventh transistor T27 may be a pull-down transistor configured to transmit a low-level voltage to the output terminal GOUT. When the voltage of the first node Q2 is at a low level, the seventh transistor T27 may be turned on and configured to transmit the second voltage VGL input to the second voltage input terminal V22 to the output terminal GOUT.

[0134] The eighth transistor T28 may be connected between the first voltage input terminal V21 and the output terminal GOUT. The gate of the eighth transistor T28 may be connected to the second node QB. The eighth transistor T28 may be a pull-up transistor configured to transmit a high-level voltage to the output terminal GOUT. When the voltage of the second node QB is at a low level, the eighth transistor T28 may be turned on and configured to transmit the first voltage VGH input to the first voltage input terminal V21 to the output terminal GOUT.

[0135] The capacitor C2 may be connected between the output terminal GOUT and the first node Q2 .

[0136] In the following, reference is made to Figure 18 describe Figure 16 and Figure 17 The operation of the stage ST shown in FIG. For ease of description, the Figure 16 and Figure 17In this example, the stage ST (the current stage) is an odd-numbered stage, and the first clock signal CLK1 is input to the clock terminal CK. The even-numbered stages are identical in configuration and operation to the odd-numbered stages, differing only in that the second clock signal CLK2 is input to the clock terminal CK of the even-numbered stages. The start signal STV of the first stage (that is, the first stage ST1) can be the external signal FLM, and the start signal STV of subsequent stages can be the previous output signal OUT'. Figure 18 yes Figure 16 and Figure 17 Stage ST is a timing diagram of an example of an arbitrary stage among odd-numbered stages after the second stage.

[0137] During the first section P21 , a high-level previous output signal OUT′ may be input to the input terminal IN, and a high-level first clock signal CLK1 may be input to the clock terminal CK.

[0138] The first transistor T21 may be turned on according to the high-level fifth voltage VGH2, and the high-level previous output signal OUT' may be transmitted to the third node FQ, and the voltage VFQ of the third node FQ may rise to the high-level voltage FQ_HL2. Since the high-level voltage FQ_HL2 of the third node FQ is lower than the high-level voltage OUT_HL of the previous output signal OUT' due to the threshold loss of the first transistor T21 and is close to the high-level voltage CLK_HL of the first clock signal CLK1, the second transistor T22 may be turned off.

[0139] The third transistor T23 may be turned on according to the high-level fifth voltage VGH2, the fourth transistor T24 may be turned on according to the low-level third voltage VGL2, and the voltage VQ0 of the fifth node Q0, the voltage VQ1 of the fourth node Q1, and the voltage VQ2 of the first node Q2 may respectively maintain the low-level voltages Q0_LL, Q1_LL, and Q2_LL of the previous section. The seventh transistor T27 having a gate connected to the first node Q2 may be turned on, the second voltage VGL may be transmitted to the output terminal GOUT through the turned-on seventh transistor T27, and a low-level output signal OUT may be output from the output terminal GOUT.

[0140] Because the fifth transistor T25 having the gate connected to the first node Q2 or the fourth node Q1 maintains a turned-on state and the voltage of the second node QB maintains a high level, the eighth transistor T28 may be in a turned-off state.

[0141] During the second section P22 , the previous output signal OUT′ of a high level may be input to the input terminal IN, and the first clock signal CLK1 of a low level may be input to the clock terminal CK.

[0142] The high-level previous output signal OUT' can be transmitted to the third node FQ via the first transistor T21, which is turned on by the high-level fifth voltage VGH2. The voltage VFQ at the third node FQ can be the high-level voltage FQ_HL2. The second transistor T22 can be turned on by the low-level first clock signal CLK1, the third transistor T23 can be turned on by the high-level fifth voltage VGH2, and the fourth transistor T24 can be turned on by the low-level third voltage VGL2. The voltage VQ0 at the fifth node Q0, the voltage VQ1 at the fourth node Q1, and the voltage VQ2 at the first node Q2 can rise to a high level due to the turned-on second transistor T22, the third transistor T23, and the fourth transistor T24. The seventh transistor T27, having a gate connected to the first node Q2, can be turned off. When the voltage VQ0 at the fifth node Q0 reaches the high-level voltage CLK_HL of the first clock signal CLK1, the third transistor T23 can be turned off.

[0143] The fifth transistor T25, having a gate connected to the first node Q2 or the fourth node Q1, may be turned off, and the sixth transistor T26 may be turned on. The low-level second voltage VGL may be transmitted to the second node QB via the turned-on sixth transistor T26, and the eighth transistor T28 may be turned on. The first voltage VGH may be transmitted to the output terminal GOUT via the turned-on eighth transistor T28, and a high-level output signal OUT may be output from the output terminal GOUT. In this case, as the output signal OUT rises from a low level to a high level, the voltage VQ2 of the first node Q2 and the voltage VQ1 of the fourth node Q1 electrically connected to the first node Q2 may rise even more due to coupling via the capacitor C2. During the second section P22, the high-level voltage Q2_HL of the first node Q2 and the high-level voltage Q1_HL of the fourth node Q1 may be greater than the first voltage VGH. During the second section P22 , the high voltages Q2_HL of the first and fourth nodes Q2 and Q1 may be greater than the high voltages FQ_HL2 of the third and fifth nodes FQ and Q0_HL2 .

[0144] During the third section P23 , the previous output signal OUT′ of a high level may be input to the input terminal IN, and the first clock signal CLK1 of a high level may be input to the clock terminal CK.

[0145] The high-level previous output signal OUT' can be transmitted to the third node FQ through the first transistor T21 that is turned on by the low-level third voltage VGL2. When the voltage VFQ of the third node FQ reaches the high-level voltage CLK_HL of the first clock signal CLK1, the second transistor T22 can be turned off, the voltage VFQ of the third node FQ rises to the high-level voltage FQ_HL1 due to coupling of the parasitic capacitor of the second transistor T22, and the voltage VQ0 of the fifth node Q0 can rise to the high-level voltage Q0_HL1. The high-level voltages FQ_HL1 of the third node FQ and Q0_HL1 of the fifth node Q0 can be greater than the fifth voltage VGH2.

[0146] The third transistor T23 can be turned off according to the high-level voltage VQ0 of the fifth node Q0 and the high-level fifth voltage VGH2, and the fourth transistor T24 can be in a conductive state according to the low-level third voltage VGL2. The voltages of the first node Q2 and the fourth node Q1 maintain a high level in the previous section due to the capacitor C2, and the seventh transistor T27 can remain in a turned-off state.

[0147] The sixth transistor T26 having the gate connected to the first node Q2 or the fourth node Q1 may maintain a turned-on state, and a high-level output signal OUT may be output from the output terminal GOUT through the turned-on eighth transistor T28 .

[0148] During the fourth section P24 , the previous output signal OUT′ of a high level may be input to the input terminal IN, and the first clock signal CLK1 of a low level may be input to the clock terminal CK.

[0149] The high-level previous output signal OUT' can be transmitted to the third node FQ through the first transistor T21 that is turned on according to the high-level fifth voltage VGH2, and the voltage VFQ of the third node FQ can be the high-level voltage FQ_HL2. The second transistor T22 can be turned on according to the high-level voltage FQ_HL2 of the third node FQ and the low-level first clock signal CLK1, and the voltage VQ0 of the fifth node Q0 can be the high-level voltage Q0_HL2 equal to the high-level voltage FQ_HL2 of the third node FQ.

[0150] The third transistor T23 can be in the off state according to the high level voltage VQ0 of the fifth node Q0 and the high level fifth voltage VGH2. The voltages of the first node Q2 and the fourth node Q1 maintain the high level of the previous section due to the capacitor C2, and the sixth transistor T26 can remain in the off state.

[0151] The fifth transistor T25 having the gate connected to the first node Q2 or the fourth node Q1 may maintain a turned-on state and may output a high-level output signal OUT from the output terminal GOUT.

[0152] During the fifth section P25 , the previous output signal OUT′ of a high level may be input to the input terminal IN, and the first clock signal CLK1 of a high level may be input to the clock terminal CK.

[0153] The high-level previous output signal OUT' can be transmitted to the third node FQ through the first transistor T21 that is turned on by the low-level third voltage VGL2. When the voltage VFQ of the third node FQ reaches the high-level voltage CLK_HL of the first clock signal CLK1, the second transistor T22 can be turned off, the voltage VFQ of the third node FQ rises to the high-level voltage FQ_HL1 due to coupling of the parasitic capacitor of the second transistor T22, and the voltage VQ0 of the fifth node Q0 can rise to the high-level voltage Q0_HL1. The high-level voltages FQ_HL1 of the third node FQ and Q0_HL1 of the fifth node Q0 can be greater than the fifth voltage VGH2.

[0154] The third transistor T23 can be turned off according to the high-level voltage VQ0 of the fifth node Q0 and the high-level fifth voltage VGH2, and the fourth transistor T24 can be in a conductive state according to the low-level third voltage VGL2. The voltages of the first node Q2 and the fourth node Q1 maintain a high level in the previous section due to the capacitor C2, and the seventh transistor T27 can remain in a turned-off state.

[0155] The sixth transistor T26 having the gate connected to the first node Q2 or the fourth node Q1 may maintain a turned-on state, and a high-level output signal OUT may be output from the output terminal GOUT through the turned-on eighth transistor T28 .

[0156] During the sixth section P26 , the previous output signal OUT′ of a low level may be input to the input terminal IN, and the first clock signal CLK1 of a high level may be input to the clock terminal CK.

[0157] The first transistor T21 may be turned on according to the high-level fifth voltage VGH2, and the low-level previous output signal OUT' may be transmitted to the third node FQ, and the voltage VFQ of the third node FQ may drop to the low-level voltage FQ_LL. The low-level voltage FQ_LL of the third node FQ may be the low-level voltage OUT_LL of the previous output signal OUT'.

[0158] The second transistor T22 may be turned off according to the first clock signal CLK1 of a high level, and the third transistor T23 in the off state may be turned on when the voltage VQ0 of the fifth node Q0 drops to the fifth voltage VGH2 .

[0159] The fourth transistor T24 may be turned on according to the low-level third voltage VGL2 , the voltages of the first node Q2 and the fourth node Q1 may maintain a high level in the previous section due to the capacitor C2 , and the seventh transistor T27 may be turned off.

[0160] The sixth transistor T26 having the gate connected to the first node Q2 or the fourth node Q1 may maintain a turned-on state, and a high-level output signal OUT may be output from the output terminal GOUT through the turned-on eighth transistor T28 .

[0161] During the seventh section P27 , the previous output signal OUT′ of a low level may be input to the input terminal IN, and the first clock signal CLK1 of a low level may be input to the clock terminal CK.

[0162] The first transistor T21 is turned on according to the high-level fifth voltage VGH2 , the low-level previous output signal OUT′ may be transmitted to the third node FQ, and the voltage VFQ of the third node FQ may be the low-level voltage FQ_LL equal to the low-level voltage OUT_LL of the previous output signal OUT′.

[0163] The second transistor T22 may be turned on according to the low-level first clock signal CLK1 , and the voltage VQ0 of the fifth node Q0 may drop to a low-level voltage Q0_LL greater than the low-level voltage FQ_LL of the third node FQ due to threshold voltage loss of the second transistor T22 .

[0164] The third transistor T23 may be turned on according to the high-level fifth voltage VGH2 , and the voltage VQ1 of the fourth node Q1 may drop to a low-level voltage Q1_LL equal to the low-level voltage Q0_LL of the fifth node Q0 .

[0165] The third transistor T23 may be turned on in response to the low-level third voltage VGL2, and the voltage of the first node Q2 may drop to a low level due to the turned-on third transistor T23. A seventh transistor T27, having a gate connected to the first node Q2, may be turned on, and the second voltage VGL may be transmitted to the output terminal GOUT via the turned-on seventh transistor T27, allowing a low-level output signal OUT to be output from the output terminal GOUT. In this case, as the output signal OUT drops from a high level to a low level, the low-level voltage of the first node Q2 may further drop due to coupling via the capacitor C2. During the seventh segment P27, the low-level voltage Q2_LL of the first node Q2 may be lower than the second voltage VGL. During the seventh segment P27, the low-level voltage Q2_LL of the first node Q2 may be lower than the low-level voltage FQ_LL of the third node FQ, the low-level voltage Q0_LL of the fifth node Q0, and the low-level voltage Q1_LL of the fourth node Q1.

[0166] The fifth transistor T25 having a gate connected to the first node Q2 or the fourth node Q1 may be turned on, and the sixth transistor T26 may be turned off. The high-level first voltage VGH may be transmitted to the second node QB through the turned-on fifth transistor T25, and the eighth transistor T28 may be turned off.

[0167] When the voltage VQ2 of the first node Q2 maintains the high-level voltage Q2_HL, the third transistor T23 may be turned off, and the voltage VQ2 of the first node Q2 may not be affected by the oscillation of the voltage VQ0 of the fifth node Q0 .

[0168] Figures 19 to 21 is a schematic diagram of a stage ST according to an embodiment.

[0169] Figure 19 and Figure 20 The level ST shown in Figure 16 and Figure 17 The stage ST shown in FIG. 2 is different in that a fourth voltage VGL3 is input to the back gates of the first transistor T21 and the third transistor T23 . Figure 19 and Figure 20 The other configurations and operations of the stage ST shown in Figure 16 and Figure 17 The configuration and operation of the stage ST shown in are the same.

[0170] In an embodiment, Figure 21As shown in FIG, the stage ST may further include a fifth voltage input terminal V25 to which the fourth voltage VGL3 is input. The first transistor T21 and the third transistor T23 may be dual-gate transistors further including a back gate connected to the fifth voltage input terminal V25. The gate of each of the first transistor T21 and the third transistor T23 may be a top gate, and the back gate may be a bottom gate provided below the semiconductor.

[0171] The fourth voltage VGL3 may be lower than the third voltage VGL2. The difference between the fourth voltage VGL3 and the third voltage VGL2 may be approximately 3V, and the fourth voltage VGL3 may be approximately -10V. However, the embodiment is not limited thereto. The difference between the fourth voltage VGL3 and the third voltage VGL2 may be determined by the amount of change in the threshold voltages of the first transistor T21 and the third transistor T23. The fourth voltage VGL3 may be represented by a low-level voltage.

[0172] Figures 22 to 24 is a schematic diagram of a stage ST according to an embodiment.

[0173] Figure 22 and Figure 24 The level ST shown in Figure 16 and Figure 17 The stage ST shown in FIG. 1 is different in that the stage ST may further include a ninth transistor T29 as a reset circuit. Figure 22 and Figure 23 The other configurations and operations of the stage ST shown in Figure 16 and Figure 17 The configuration and operation of the stage ST shown in are the same.

[0174] In an embodiment, Figure 24 As shown in , the stage ST may further include a reset terminal RS, to which a reset signal ESR is input. The ninth transistor T29 may be configured to reset the fourth node Q1 based on the reset signal ESR supplied to the reset terminal RS. The ninth transistor T29 may be connected between the first voltage input terminal V21 and the fourth node Q1, and the gate of the ninth transistor T29 may be connected to the reset terminal RS. When a low-level reset signal ESR is applied to the reset terminal RS, the ninth transistor T29 may be turned on to reset the fourth node Q1 to the first voltage VGH. Therefore, the sixth transistor T26 may be turned on and may output a high-level output signal OUT, and the error of the seventh transistor T27 being turned on and the low-level output signal OUT being output may be prevented.

[0175] In an embodiment, when an operation error occurs, the reset signal ESR may be supplied as a low level to the first to n-th stages ST1 to STn at a specific timing. The reset signal ESR may be supplied as a pulse form having a low level of the second voltage VGL at a preset timing, and may be supplied as the first voltage VGH at other timings.

[0176] Figures 25 to 27 is a schematic diagram of a stage ST according to an embodiment.

[0177] Figure 25 and Figure 26 The level ST shown in Figure 16 and Figure 17 The stage ST shown in FIG. 1 is different in that a fourth voltage VGL3 is input to back gates of the first transistor T21 and the third transistor T23 , and further includes a ninth transistor T29 as a reset circuit. Figure 25 and Figure 26 The other configurations and operations of the stage ST shown in Figure 16 and Figure 17 The configuration and operation of the stage ST shown in are the same.

[0178] In an embodiment, Figure 27 As shown in FIG, the stage ST may further include a fifth voltage input terminal V25 and a reset terminal RS, the fourth voltage VGL3 is input to the fifth voltage input terminal V25, and the reset signal ESR is input to the reset terminal RS. Figures 19 to 24 The configurations and operations of the first transistor T21 , the third transistor T23 , and the ninth transistor T29 are described, so descriptions thereof are omitted below.

[0179] Figures 28 to 30 is a schematic diagram of a stage ST according to an embodiment. Figure 28 and Figure 29 The level ST shown in Figure 16 and Figure 17 The stage ST shown in FIG2 is different in that the second voltage VGL is input to the gate of the fourth transistor T24. Figure 28 and Figure 29 The other configurations and operations of the stage ST shown in Figure 16 and Figure 17 The configuration and operation of the stage ST shown in are the same.

[0180] In an embodiment, the gate of the fourth transistor T24 may be connected to the second voltage input terminal V22, and as shown in FIG. Figure 30 As shown in , the third voltage input terminal V23 to which the third voltage VGL2 of the stage ST is input may be omitted.

[0181] Figures 31 to 33 is a schematic diagram of a stage ST according to an embodiment. Figures 31 to 33 The level ST shown in Figures 19 to 21 The stage ST shown in FIG2 is different in that the third voltage input terminal V23 to which the third voltage VGL2 is input is omitted, and the gate of the fourth transistor T24 is connected to the second voltage input terminal V22 and receives the second voltage VGL. Figures 31 to 33 The other configurations and operations of the stage ST shown in Figures 19 to 21 The configuration and operation of the stage ST shown in are the same.

[0182] Figures 34 to 36 is a schematic diagram of a stage ST according to an embodiment. Figures 34 to 36 The level ST shown in Figures 22 to 24 The stage ST shown in FIG2 is different in that the third voltage input terminal V23 to which the third voltage VGL2 is input is omitted, and the gate of the fourth transistor T24 is connected to the second voltage input terminal V22 and receives the second voltage VGL. Figures 34 to 36 The other configurations and operations of the stage ST shown in Figures 22 to 24 The configuration and operation of the stage ST shown in are the same.

[0183] Figures 37 to 39 is a schematic diagram of a stage ST according to an embodiment. Figures 37 to 39 The level ST shown in Figures 25 to 27 The stage ST shown in FIG2 is different in that the third voltage input terminal V23 to which the third voltage VGL2 is input is omitted, and the gate of the fourth transistor T24 is connected to the second voltage input terminal V22 and receives the second voltage VGL. Figures 37 to 39 The other configurations and operations of the stage ST shown in Figures 25 to 27 The configuration and operation of the stage ST shown in are the same.

[0184] Figure 40 is a schematic diagram of a display device 10 according to an embodiment.

[0185] The display device 10 according to the embodiment may be an organic light emitting display device, an inorganic light emitting display device, or a quantum dot light emitting display device.

[0186] Reference Figure 40 , the display device 10 according to the embodiment may include a pixel region 110 , a gate driving circuit 130 , a data driving circuit 150 , a power supply circuit 170 , and a controller 190 .

[0187] The pixel region 110 may correspond to a display area in which an image is displayed. Various wires configured to transmit electrical signals to be applied to the display area, external driver circuits electrically connected to the pixel circuits, and pads (also referred to as "pads" or "bonding pads") to which a printed circuit board or driver integrated circuit ("IC") chip is attached may be located in a peripheral region (non-display region) outside the display area. As an example, the gate driver circuit 130, the data driver circuit 150, the power supply circuit 170, and the controller 190 may be provided in the peripheral region.

[0188] A plurality of gate lines GL, a plurality of data lines DL and a plurality of pixels PX connected thereto may be arranged in the pixel region 110. The plurality of pixels PX may be repeatedly arranged in a first direction (x direction, row direction) and a second direction (y direction, column direction). The plurality of pixels PX may be arranged in a stripe structure, a pentile structure or a plurality of other structures. ® The pixels PX may be arranged in various configurations, such as a red, diamond, and / or mosaic configuration, to display an image. Each of the plurality of pixels PX may include an organic light-emitting diode as a display element. The organic light-emitting diode may be connected to a pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. The pixels PX may be configured to emit, for example, red, green, blue, or white light from the organic light-emitting diode. Each pixel PX may be connected to a corresponding gate line among a plurality of gate lines GL and a corresponding data line among a plurality of data lines DL.

[0189] In an embodiment, the plurality of transistors included in the pixel region 110 may be P-channel silicon transistors. In an embodiment, the plurality of transistors included in the pixel circuit may be N-channel oxide transistors. In an embodiment, some of the plurality of transistors included in the pixel circuit may be P-channel silicon transistors, and other transistors included in the plurality of transistors included in the pixel circuit may be N-channel oxide transistors.

[0190] Each gate line GL may extend in the x-direction (row direction) and be connected to pixels PX arranged in the same row. Each gate line GL may be configured to transmit a gate signal to pixels PX in the same row. Each data line DL may extend in the y-direction (column direction) and be connected to pixels PX arranged in the same column. Each data line DL may be configured to transmit a data signal to pixels PX in the same column in synchronization with the gate signal.

[0191] The gate drive circuit 130 may be connected to a plurality of gate lines GL and configured to generate a gate signal GS based on a gate drive control signal GCS from the controller 190 and sequentially supply the gate signal GS to the gate lines GL. The gate lines GL may be connected to the gates of the transistors included in the pixels PX, and the gate signal GS may be a gate control signal that controls the on and off state of the transistors to which the gate lines are connected. The gate signal GS may include a gate-on voltage at which the transistors may be turned on and a gate-off voltage at which the transistors may be turned off. The gate drive circuit 130 may include a plurality of stages configured to sequentially generate and output the gate signal GS.

[0192] In an embodiment, the gate drive circuit 130 may be implemented as a circuit including Figures 1 to 39 . As an example, the gate signal GS output by the gate driving circuit 130 to each gate line GL may correspond to the high-level output signal OUT output to the signal line by the plurality of stages ST1 to STn of the driving circuit DRV. Each of the stages ST1 to STn may be connected to a gate line arranged in a corresponding row of the pixel area 110. Each of the stages ST1 to STn may be configured to generate a gate signal GS and output it to the gate line GL connected to each of the stages ST1 to STn. That is, each of the stages ST1 and STn may be configured to supply a high-level gate signal GS to the gate line GL provided for the corresponding row.

[0193] The number of stages configuring the gate driving circuit 130 employing the driving circuit DRV may be variously changed according to the number of rows (horizontal lines) prepared in the pixel region 110 .

[0194] The data driving circuit 150 may be connected to a plurality of data lines DL and configured to supply data signals DATA to the data lines DL according to data drive control signals DCS from the controller 190. The data signals DATA supplied to the data lines DL may be supplied to the pixels PX supplied with gate signals. The data driving circuit 150 may be configured to convert input image data having grayscale and input from the controller 190 into data signals DATA in the form of voltage or current.

[0195] The power circuit 170 may be configured to generate signals (voltage and current) to drive the pixels PX in the pixel area 110 in response to a power drive control signal PCS from the controller 190. If the display device 10 is an organic light-emitting display device, the power circuit 170 may be configured to generate a first power voltage ELVDD and a second power voltage ELVSS, and supply the first and second power voltages ELVDD and ELVSS to the pixels PX. The first power voltage ELVDD may be a high-level voltage supplied to one terminal of a drive transistor connected to the first electrode (pixel electrode or anode) of the organic light-emitting diode included in each pixel PX. The second power voltage ELVSS may be a low-level voltage supplied to the second electrode (counter electrode or cathode) of the organic light-emitting diode connected to the other terminal of the drive transistor. The first and second power voltages ELVDD and ELVSS may be driving voltages configured to allow the plurality of pixels PX to emit light.

[0196] The power supply circuit 170 may be configured to generate a first voltage VGH, a second voltage VGL, a third voltage VGL2, a fourth voltage VGL3, and a fifth voltage VGH2, and supply them to the gate driving circuit 130. The power supply circuit 170 may be configured to generate clock signals CLK1 and CLK2 in which the third voltage VGL2 and the fifth voltage VGH2 alternate, and an external signal FLM, and supply them to the gate driving circuit 130.

[0197] The controller 190 may be configured to generate a gate drive control signal GCS, a data drive control signal DCS, and a power drive control signal PCS based on signals input from the outside. The controller 190 may be configured to supply the gate drive control signal GCS to the gate drive circuit 130, supply the data drive control signal DCS to the data drive circuit 150, and supply the power drive control signal PCS to the power supply circuit 170.

[0198] although Figure 40 The display device 10 includes a separate power supply circuit 170 and a controller 190 , but the embodiment is not limited thereto. In another embodiment, the power supply circuit 170 may be included in the controller 190 .

[0199] The display device 10 may include a display panel, and the display panel may include a substrate. Pixels PX may be arranged in a display area of ​​the substrate. Part or all of the gate driver circuit 130 may be formed directly in a peripheral area of ​​the substrate during the process of forming transistors that construct pixel circuits in the display area of ​​the substrate. The data driver circuit 150, the power supply circuit 170, and the controller 190 may be formed as separate integrated circuit chips, or as one integrated circuit chip and disposed on a flexible printed circuit board ("FPCB") electrically connected to pads disposed on one side of the substrate. In another embodiment, the data driver circuit 150, the power supply circuit 170, and the controller 190 may be disposed directly on the substrate using a chip-on-glass ("COG") method or a chip-on-plastic ("COP") method.

[0200] The driving circuit DRV according to the embodiment may be configured to reduce power consumption caused by switching of the clock signal by making the swing width (amplitude) of the clock signal input to each stage ST smaller than the swing width (amplitude) of the start signal (or output signal).

[0201] The drive circuit DRV according to an embodiment may alternately connect P-channel transistors and N-channel transistors in series between an input terminal and a first node Q2, with the gate of a full-down transistor connected to the first node Q2. The transistors connected between the input terminal and the first node Q2 may include a transistor to which a clock signal is input and a transistor connected in series with the transistor to which the clock signal is input. The transistor to which the clock signal is input may be a P-channel transistor or an N-channel transistor. Among the transistors connected in series with the transistor to which the clock signal is input, a low-level voltage of the clock signal may be input to the gate of the P-channel transistor, and a high-level voltage of the clock signal may be input to the gate of the N-channel transistor. Therefore, even if the swing width of the clock signal is small, normal bootstrap operation of the first node Q2 is allowed, and thus stable output due to the full-down transistor is possible.

[0202] According to the embodiment, a driving circuit configured to stably output a gate signal with reduced power consumption and a display device including the driving circuit can be provided. The disclosed effects are not limited to the above effects, but can be variously expanded without departing from the scope of the disclosure.

[0203] It should be understood that the embodiments described herein should be considered merely illustrative and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A driving circuit comprising a plurality of stages, wherein: Each of the plurality of stages comprises: an output circuit connected between a first terminal and a second terminal and configured to output an output signal of a first voltage level or a second voltage level according to voltage levels of a first node and a second node, wherein the first voltage is input to the first terminal and the second voltage is input to the second terminal; and a control circuit connected to the output circuit and an input terminal, and configured to control voltage levels of the first node and the second node, a start signal being input to the input terminal, Wherein, the control circuit includes: a first transistor connected between the input terminal and a third node and including a gate connected to a third terminal to which a third voltage is input; a second transistor connected between the third node and the fourth node and including a gate connected to a clock terminal to which a clock signal is input; a third transistor connected between the fourth node and the first node and including a gate connected to the third terminal; and An inverter is connected between the first terminal and the second terminal and is configured to control the voltage of the second node to a voltage level obtained by inverting the voltage level of the first node.

2. The driving circuit according to claim 1, wherein: The second voltage is lower than the first voltage, and the third voltage is lower than the first voltage and higher than the second voltage.

3. The driving circuit according to claim 1, wherein: The second transistor is an N-channel transistor, and the first transistor and the third transistor are P-channel transistors.

4. The driving circuit according to claim 1, wherein: The clock signal is a signal in which a high-level voltage lower than the first voltage and a low-level voltage higher than the second voltage alternate, and the low-level voltage of the clock signal is the third voltage.

5. The driving circuit according to claim 1, wherein: The clock signal input to the clock terminal of the even-numbered stages among the plurality of stages is a signal whose phase is shifted by 1 / 2 cycle compared with the clock signal input to the clock terminal of the odd-numbered stages. The driving circuit according to claim 1 , wherein: The inverter comprises: a fourth transistor connected between the first terminal and the second node and including a gate connected to the first node or the fourth node; and A fifth transistor is connected between the second node and the second terminal and includes a gate connected to the first node or the fourth node.

7. The driving circuit according to claim 6, wherein: The fourth transistor is a P-channel transistor, and the fifth transistor is an N-channel transistor.

8. The driving circuit according to claim 1, wherein: The second transistor further includes a back gate, and a fourth voltage lower than the third voltage is input to the back gate.

9. The driving circuit according to claim 1, wherein: The output circuit includes: a sixth transistor connected between the second terminal and an output terminal, the output signal being output from the output terminal, and including a gate connected to the first node; a seventh transistor connected between the first terminal and the output terminal and including a gate connected to the second node; and A capacitor is connected between the first node and the output terminal.

10. The driving circuit according to claim 1, wherein: Each of the plurality of stages further includes an eighth transistor connected between the first terminal and the fourth node and including a gate connected to a reset terminal to which a reset signal is input.

11. A driving circuit comprising a plurality of stages, wherein: Each of the plurality of stages comprises: an output circuit connected between a first terminal and a second terminal and configured to output an output signal of a first voltage level or a second voltage level according to voltage levels of a first node and a second node, wherein the first voltage is input to the first terminal and the second voltage is input to the second terminal; and a control circuit connected to the output circuit and an input terminal and configured to control the voltage levels of the first node and the second node, a start signal being input to the input terminal, Wherein, the control circuit includes: a first transistor connected between the input terminal and a third node and including a gate connected to a third terminal to which a third voltage is input; a second transistor connected between the third node and the fourth node and including a gate connected to a clock terminal to which a clock signal is input; a third transistor connected between the fourth node and the fifth node and including a gate connected to the third terminal; a fourth transistor connected between the fifth node and the first node and including a gate connected to a fourth terminal to which a fourth voltage is input; and An inverter is connected between the first terminal and the second terminal and is configured to control the voltage of the second node to a voltage level obtained by inverting the voltage level of the first node.

12. The driving circuit according to claim 11, wherein: The second voltage is lower than the first voltage, the third voltage is lower than the first voltage, and the fourth voltage is lower than the third voltage and higher than the second voltage.

13. The driving circuit according to claim 11, wherein: The first transistor and the third transistor are N-channel transistors, and the second transistor and the fourth transistor are P-channel transistors.

14. The driving circuit according to claim 11, wherein: The clock signal is a signal that alternates between a high-level voltage lower than the first voltage and a low-level voltage higher than the second voltage, the high-level voltage of the clock signal is the third voltage, and the low-level voltage of the clock signal is the fourth voltage.

15. The driving circuit according to claim 11, wherein: The clock signal input to the clock terminal of the even-numbered stages among the plurality of stages is a signal whose phase is shifted by 1 / 2 cycle compared with the clock signal input to the clock terminal of the odd-numbered stages.

16. The driving circuit according to claim 11, wherein: The inverter comprises: a fifth transistor connected between the first terminal and the second node and including a gate connected to the first node or the fifth node; and A sixth transistor is connected between the second node and the second terminal and includes a gate connected to the first node or the fifth node.

17. The driving circuit according to claim 16, wherein: The fifth transistor is a P-channel transistor, and the sixth transistor is an N-channel transistor.

18. The driving circuit according to claim 11, wherein: The first transistor and the third transistor further include back gates, and a fifth voltage lower than the fourth voltage is input to the back gates.

19. The driving circuit according to claim 11, wherein: The output circuit includes: a seventh transistor connected between the second terminal and an output terminal, and including a gate connected to the first node, the output signal being output from the output terminal; an eighth transistor connected between the first terminal and the output terminal and including a gate connected to the second node; and A capacitor is connected between the first node and the output terminal.

20. The driving circuit according to claim 11, wherein: Each of the plurality of stages further includes a ninth transistor connected between the first terminal and the fifth node and including a gate connected to a reset terminal to which a reset signal is input.

Images