Chip packaging body and preparation method thereof

Abstract

The invention discloses a chip packaging body and a preparation method thereof, and the method comprises the steps: obtaining a plastic packaging plate which is internally provided with a metal matrix and a chip disposed at one side of the metal matrix in a plastic packaging manner; performing double-sided laser drilling and hole filling treatment on the plastic package plate to obtain a first metalized blind hole connected with the chip and a metalized through hole penetrating through the plastic package plate; the middle aperture of the metalized through hole is smaller than the apertures of the two opposite ends; conductive circuits are prepared on the two opposite sides of the plastic packaging plate to be connected with the plated-through holes, and a chip packaging body is obtained; wherein a fine circuit is prepared on the side, close to the chip, of the plastic package plate, and the fine circuit is connected with the first metalized blind hole. By means of the mode, the metal base, the fine circuit and the X-shaped hole can be integrated into the chip packaging body, so that balance between high integration and performance of the packaging body is guaranteed.

Description

Technical Field

[0001] The present invention is applied to the technical field of chip packages, and in particular to a chip package and a preparation method thereof. Background Art

[0002] Packaging is the process of assembling integrated circuits into final chip products. Simply put, it is to place the chips produced by the foundry on a supporting substrate, lead out the pins, and then fix the package into a whole.

[0003] Driven by 5G and AI, semiconductor device density continues to increase, pad pitch continues to decrease, and miniaturization and high integration are becoming the mainstream trends in the industry. To maximize chip performance, minimize packaged size, and enable customization, SIP packaging technology has become one of the most important technologies in the semiconductor industry.

[0004] However, a balance needs to be maintained between the high integration and performance of the package. How to specifically achieve the balance between the high integration and performance of embedded package products is a difficult problem that needs to be solved urgently. Summary of the Invention

[0005] The present invention provides a chip package and a preparation method thereof, so as to solve the problem of achieving a balance between high integration and performance of embedded package products.

[0006] To solve the above technical problems, the present invention provides a method for preparing a chip package, comprising: obtaining a plastic-sealed plate, wherein a metal base and a chip bonded to one side of the metal base are sealed in the plastic-sealed plate; performing double-sided laser drilling and hole filling on the plastic-sealed plate to obtain a first metallized blind hole connecting the chip and a metallized through hole passing through the plastic-sealed plate; the middle aperture of the metallized through hole is smaller than the apertures at its opposite ends; conductive circuits are prepared on opposite sides of the plastic-sealed plate to connect the metallized holes to obtain a chip package; wherein, a fine circuit is prepared on the side of the plastic-sealed plate close to the chip, and the fine circuit is connected to the first metallized blind hole.

[0007] Among them, the plastic-sealed plate is subjected to double-sided laser drilling and hole filling processing to obtain a first metallized blind hole connecting the chip and a metallized through hole passing through the plastic-sealed plate, including: laser drilling on the side of the plastic-sealed plate close to the chip to obtain a first blind hole exposing the chip, and forming a first-stage blind hole on the plastic-sealed plate; wherein the depth of the first-stage blind hole is half of the thickness of the plastic-sealed plate; laser drilling is performed on the side of the plastic-sealed plate away from the chip to form a second-stage blind hole reaching the bottom of the first-stage blind hole to connect with the first-stage blind hole to form a through hole; double-sided hole filling and electroplating is performed on the plastic-sealed plate to fill the first blind hole to form a first metallized blind hole and fill the through hole to form a metallized through hole, and electroplated metal layers are formed on opposite sides of the plastic-sealed plate.

[0008] Among them, laser drilling is performed on the side of the plastic-sealed plate away from the chip, and it also includes: laser drilling is performed on the side of the plastic-sealed plate away from the chip based on the position of the metal substrate to form a second blind hole exposing the metal substrate; double-sided hole filling and electroplating is performed on the plastic-sealed plate, and it also includes: filling and electroplating the second blind hole to form a second metallized blind hole.

[0009] Among them, conductive circuits are prepared on opposite sides of the plastic-sealed plate to connect the metallized through holes, including: laminating, exposing and etching the electroplated metal layers on opposite sides of the plastic-sealed plate in sequence to retain the electroplated metal layers corresponding to the openings of each metallized hole and removing the electroplated metal layers in other areas; sputtering the entire plate on opposite sides of the plastic-sealed plate to form sputtered layers on opposite sides of the plastic-sealed plate; and preparing conductive circuits on the sputtered layers on opposite sides of the plastic-sealed plate to connect the metallized holes.

[0010] Among them, preparing conductive circuits on the sputtering layers on opposite sides of the plastic-sealed plate to connect the metallized holes includes: sequentially performing film lamination, exposure, development, pattern electroplating, film stripping and flash etching on the sputtering layers on opposite sides of the plastic-sealed plate to prepare fine circuits on the side of the plastic-sealed plate close to the chip, and preparing target circuits on the side of the plastic-sealed plate away from the chip; wherein the target circuits are connected to the second metallized blind holes.

[0011] In order to solve the above technical problems, the present invention provides a chip package, comprising: a plastic-sealed plate, at least one first metallized blind hole, a conductive circuit and at least one metallized through-hole, wherein a metal base and a chip bonded to one side of the metal base are sealed in the plastic-sealed plate, one end of the first metallized blind hole is connected to the side of the chip away from the metal base, and the other end of the first metallized blind hole extends in the plastic-sealed plate until it is exposed from one side of the plastic-sealed plate, and the conductive circuit is bonded to the opposite sides of the plastic-sealed plate, wherein the conductive circuit located on the side of the plastic-sealed plate close to the chip is a fine circuit, and the fine circuit is connected to the first metallized blind hole on one side of the plastic-sealed plate, and the metallized through-hole is set through the opposite ends of the plastic-sealed plate and connected to the conductive circuit, and the aperture of the middle section of the metallized through-hole is smaller than the aperture of the opposite ends.

[0012] The chip package includes at least one second metallized blind hole; one end of the second metallized blind hole is connected to the metal base, and the other end of the second metallized blind hole extends to connect to the conductive circuit on the side of the plastic package plate away from the chip.

[0013] The first metalized blind hole has a diameter ranging from 30 to 50 microns.

[0014] Among them, the aperture range of the metallized through hole is 4-5 mil.

[0015] Among them, the line width range of fine lines is 30-50 microns.

[0016] In order to solve the above technical problems, the chip package of the present invention obtains a plastic-sealed plate, in which a metal base and a chip attached to one side of the metal base are plastic-sealed; the plastic-sealed plate is double-sided laser drilled and filled to obtain a first metallized blind hole connecting the chip and a metallized through hole passing through the plastic-sealed plate; the middle aperture of the metallized through hole is smaller than the aperture at its opposite ends; conductive circuits are prepared on opposite sides of the plastic-sealed plate to connect the metallized holes to obtain a chip package; wherein, a fine circuit is prepared on the side of the plastic-sealed plate close to the chip, and the fine circuit is connected to the first metallized blind hole, thereby integrating the metal base, fine circuit and X-shaped hole into the chip package to achieve the effects of high integration, small size and fast signal transmission of embedded packaging products, and can also be compatible with large current conduction, thereby ensuring a balance between high integration and performance of the package. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1 is a flow chart of an embodiment of a method for preparing a chip package provided by the present invention;

[0018] Figure 2 is a schematic flow chart of another embodiment of the method for preparing a chip package provided by the present invention;

[0019] Figure 3yes Figure 2 A schematic diagram of a preparation process of a chip package;

[0020] Figure 4 It is a structural schematic diagram of an embodiment of a chip package provided by the present invention. DETAILED DESCRIPTION

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0022] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0023] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0024] See also Figure 1 , Figure 1 It is a flow chart of an embodiment of a method for preparing a chip package provided by the present invention.

[0025] Step S11: obtaining a plastic-sealed plate, wherein a metal base and a chip attached to one side of the metal base are plastic-sealed in the plastic-sealed plate.

[0026] After obtaining a metal base, the chip is mounted on one side of the metal base to obtain a chip assembly. Specifically, the chip can be mounted on one side of the metal base by welding, bonding with an adhesive, or bonding with a conductive adhesive. In a specific application scenario, the metal base can also be laminated, exposed, and etched based on electrical requirements to meet the metal base's connection requirements.

[0027] Metal substrates include, but are not limited to, conductive heat sinks based on copper, aluminum, iron, nickel, silver, or alloys. Chips include, but are not limited to, digital circuit chips, analog circuit chips, mixed digital-analog circuit chips, and specialty circuit chips. After being mounted on one side of the metal substrate, the chip can connect to the metal substrate for electrical conductivity and conduct heat generated by the chip itself during operation, thereby improving the chip's heat dissipation efficiency.

[0028] The chip assembly is double-sidedly plastic-encapsulated to obtain a plastic-encapsulated plate encapsulating the chip assembly. Plastic encapsulation materials include, but are not limited to, ABF (Ajinomoto Build-up Film) or ABF-like films (such as black plastic encapsulation compound, NBF (Non-Conductive Bonding Film), EBF (Epoxy Bonding Film), SIF (Silicone Insulating Film), and other adhesive films.

[0029] Step S12: performing double-sided laser drilling and hole filling processing on the plastic-sealed plate to obtain a first metallized blind via connected to the chip and a metallized through hole penetrating the plastic-sealed plate.

[0030] The plastic-encapsulated plate is laser-drilled and filled on both sides to create a first metalized blind via for connecting to the chip on the side of the plate closest to the chip, and a metalized through-hole is created through the plate. Laser drilling is first performed to create the hole shape, followed by metallization through the filling process, resulting in the first metalized blind via and the metalized through-hole.

[0031] The middle aperture of the metallized through-hole is smaller than the aperture at the opposite ends. The metallized through-hole is a through-hole formed by laser docking on the plastic-sealed board. The through-hole has a large aperture at both ends and a small aperture in the middle. It is also called a waist-shaped hole or an X-shaped hole, which can achieve high current conduction.

[0032] The laser drilling process is highly precise and easy to control, shortening the chip package's current loop and effectively reducing pad pitch. This process uses double-sided laser drilling to create through-holes, followed by electroplating to create metallized through-holes, effectively enabling high current conduction.

[0033] Step S13: preparing conductive circuits on opposite sides of the plastic package plate to connect the metallized holes to obtain a chip package; wherein, preparing fine circuits on the side of the plastic package plate close to the chip and connecting the fine circuits to the first metallized blind holes.

[0034] The conductive circuits are used to realize the electrical functions on the opposite sides of the plastic-encapsulated board. The conductive circuits are connected to the metallized holes to communicate with the chip or conductive structure inside the plastic-encapsulated board to realize the complete circuit network of the chip package.

[0035] Fine circuits are fabricated on the side of the plastic package member closest to the chip and connected to the first metalized blind vias. Fine circuits enable high integration in a small size, enabling more electrical connections in a smaller space, facilitating integration and miniaturization of the chip package.

[0036] This embodiment uses a metal base as a base to dissipate heat for the chip; uses ABF or ABF-like packaging for packaging, and then prepares first metallized blind holes and metallized through holes by laser drilling, and then processes them to obtain fine circuits. This can not only achieve high integration, small size, and fast signal transmission effects for embedded packaging products; it can also achieve large current conduction, providing a possibility for the development direction of embedded packaging products with high integration, miniaturization, and multifunctionality.

[0037] Through the above steps, this embodiment obtains a plastic-sealed plate, in which a metal base and a chip attached to one side of the metal base are plastic-sealed; the plastic-sealed plate is subjected to double-sided laser drilling and hole filling treatment to obtain a first metallized blind hole connecting the chip and a metallized through hole passing through the plastic-sealed plate; the middle aperture of the metallized through hole is smaller than the aperture at its opposite ends; conductive circuits are prepared on opposite sides of the plastic-sealed plate to connect the metallized holes to obtain a chip package; wherein, a fine circuit is prepared on the side of the plastic-sealed plate close to the chip, and the fine circuit is connected to the first metallized blind hole, thereby integrating the metal base, fine circuit and X-shaped hole into the chip package to achieve the effects of high integration, small size and fast signal transmission of the embedded package product, and can also be compatible with large current conduction, thereby ensuring the balance between high integration and performance of the package.

[0038] See also Figure 2-3 , Figure 2 FIG. 1 is a flow chart of another embodiment of the method for preparing a chip package provided by the present invention. Figure 3 yes Figure 2 A schematic diagram of the preparation process of a chip package is provided.

[0039] Step S21: obtaining a plastic-sealed plate, wherein a metal base and a chip attached to one side of the metal base are plastic-sealed in the plastic-sealed plate.

[0040] This step is the same as the aforementioned step S11, please refer to the above text and will not be repeated here.

[0041] See also Figure 3In (3a), a plastic-encapsulated plate 100 is obtained, in which a metal base 110 and a chip 120 attached to one side of the metal base 110 are encapsulated. Metal layers (not marked in the figure) can be provided on opposite sides of the plastic-encapsulated plate 100 to provide a force during vacuum rigid-flex pressing of the plastic-encapsulated plate 100 and to serve as a seed layer for subsequent electroplating to accelerate electroplating efficiency.

[0042] Step S22: laser drilling is performed on the side of the plastic-sealed plate close to the chip to obtain a first blind hole exposing the chip, and a first-stage blind hole is formed on the plastic-sealed plate; wherein the depth of the first-stage blind hole is half of the thickness of the plastic-sealed plate.

[0043] The number of first blind vias can be one or more, determined based on the number of electrodes / pads to be connected on the chip. The bottoms of the first blind vias expose the electrodes / pads on the side of the chip away from the metal substrate. The first blind vias are micro blind vias with a pore size ranging from 30 to 50 microns, specifically 30 microns, 32 microns, 35 microns, 37 microns, 40 microns, 42 microns, 45 microns, 48 ​​microns, or 50 microns, among others.

[0044] The depth of the first-stage blind hole is half the thickness of the plastic-encapsulated panel, resulting in a connected laser-through hole through double-sided laser drilling. Laser drilling is performed at an inclined angle, resulting in a large port area and a small bottom area.

[0045] Please see further Figure 3 In (3b), (3b) is based on (3a), laser drilling is performed on the side of the plastic-sealed plate 100 close to the chip 120 to obtain a first blind hole 101 exposing the chip 120, and a first-stage blind hole 102 is formed on the plastic-sealed plate 100.

[0046] Step S23: laser drilling is performed on the side of the plastic package plate away from the chip to form a second-stage blind hole reaching the bottom of the first-stage blind hole to connect with the first-stage blind hole to form a through hole.

[0047] Please see further Figure 3 In (3c), based on (3b), laser drilling is performed on the side of the plastic package plate 100 away from the chip 120 to form a second-stage blind hole (not marked in the figure) that reaches the bottom of the first-stage blind hole 102, so as to connect with the first-stage blind hole 102 to form a through hole 103. The through hole 103 has a smaller diameter than the diameters of the two opposite ends, and is also called a waist-shaped hole or an X-shaped hole.

[0048] In this step, laser drilling is also performed on the side of the plastic package plate 100 away from the chip 120 based on the position of the metal substrate 110 to form a second blind hole 104 that exposes the metal substrate 110. The number of the second blind holes 104 may be one or more, and is specifically set based on actual needs.

[0049] Step S24: performing double-sided hole filling electroplating on the plastic-sealed board to fill the first blind holes to form first metallized blind holes and fill the through holes to form metallized through holes, and forming electroplated metal layers on opposite sides of the plastic-sealed board.

[0050] Please see further Figure 3 In (3d), (3d) is based on (3c), and the plastic-sealed board 100 is double-sidedly filled with electroplating to fill the first blind hole 101 to form a first metallized blind hole 111, fill the through hole 103 to form a metallized through hole 113, and fill the second blind hole 104 to form a second metallized blind hole 114, and form an electroplated metal layer 140 on the opposite sides of the plastic-sealed board 100.

[0051] Specifically, the hole walls of each hole on the plastic package board 100 are first subjected to a hole-forming treatment, and then the plastic package board 100 is double-sided electroplated to fill each hole and extend to opposite sides of the plastic package board 100 to form an electroplated metal layer 140.

[0052] Step S25 : laminating, exposing, and etching the electroplated metal layers on opposite sides of the plastic-sealed plate in sequence to retain the electroplated metal layers corresponding to the openings of the metallized holes and remove the electroplated metal layers in other areas.

[0053] First, a protective film is applied to the entire plastic-sealed board on opposite sides, and then the area corresponding to the non-metallized hole openings is exposed to eliminate the protective function of the protective film in this area. Double-sided etching is then performed to remove the electroplated metal layer in other areas, and the electroplated metal layer corresponding to the openings of each metallized hole is retained through the remaining protective film. Subsequently, the electroplated metal layer in this part can be used as the soldering pad of each metallized hole for external connection or connection with the conductive circuit.

[0054] Step S26 : performing sputtering on the entire two opposite sides of the plastic package plate to form sputtering layers on the two opposite sides of the plastic package plate.

[0055] Please see further Figure 3 In (3e), (3e) is based on (3d), and the entire two sides of the plastic package plate 100 are sputtered to form a sputtering layer 150 on the two sides of the plastic package plate 100.

[0056] The sputtering layer 150 serves as a seed layer for electroplating, which helps to improve the accuracy of the circuit and realize the formation of fine circuits.

[0057] Step S27: preparing conductive circuits on the sputtering layer on opposite sides of the plastic package plate to connect the metallized holes to obtain a chip package.

[0058] Please see further Figure 3 In (3f), (3f) is based on (3e), and film lamination, exposure, development, pattern electroplating, film stripping and flash etching are performed in sequence on the sputtering layer 150 on the opposite sides of the plastic package board 100 to prepare a fine circuit 160 on the side of the plastic package board 100 close to the chip 120, and the fine circuit 160 is connected to the first metallized blind hole 111, and a target circuit 170 is prepared on the side of the plastic package board 100 away from the chip 120 to obtain a chip package (not marked in the figure); wherein, the target circuit 170 is connected to the second metallized blind hole 114.

[0059] Specifically, a protective film is applied to the entire sputtering layer 150 on opposite sides of the plastic-encapsulated panel 100. The areas where the fine circuits 160 and target circuits 170 are to be formed are then exposed and developed, retaining the protective film in other areas and exposing the sputtering layer 150 in the areas where the fine circuits 160 and target circuits 170 are to be formed. Image plating is then performed on this portion of the sputtering layer 150 to form the fine circuits 160 and target circuits 170. The protective film is then removed, and flash etching is performed to remove the sputtering layer 150 in other areas to ensure insulation between the circuits. The specific shapes of the fine circuits 160 and target circuits 170 are set based on actual connection requirements and are not limited.

[0060] At this time, the first metallized blind via 111 of the micro blind via is connected to the fine circuit 160 , thereby matching the electrical specifications to achieve small-size and high-integration of the chip 120 signal lead-out.

[0061] Through the above steps, the chip package fabrication method of this embodiment utilizes a metal substrate as a base to dissipate heat from the chip; utilizes ABF or ABF-like packaging for encapsulation; and then employs additive manufacturing to fabricate fine circuitry, micro blind vias, and X-shaped via structures. This step-by-step process, first machining the holes and then the patterns, ultimately achieves the fabrication of complex structures. This not only enables embedded package products with high integration, small size, and fast signal transmission, but also enables high current conduction, ensuring a balance between high integration and performance. This opens up a new avenue for the development of embedded package products with high integration, miniaturization, and multifunctionality.

[0062] See also Figure 4 , Figure 4 FIG1 is a schematic structural diagram of an embodiment of a chip package provided by the present invention. The chip package of this embodiment can be applied to the preparation method of the chip package of any of the above embodiments.

[0063] The chip package 200 includes a plastic package board 100, at least one first metalized blind via 111, a conductive circuit (not labeled in the figure), and at least one metalized through-hole 113. The chip package 200 can be applied to power chip communication products or semiconductor testing products.

[0064] The plastic-encapsulated plate 100 has a metal base 110 and a chip 120 attached to one side of the metal base 110 sealed therein; the metal base 110 may be a thick copper structure to help the chip 120 dissipate heat.

[0065] One end of the first metallized blind via 111 is connected to the side of the chip 120 away from the metal base 110 , and the other end of the first metallized blind via 111 extends inside the plastic package board 100 until being exposed from one side of the plastic package board 100 .

[0066] Conductive circuits are bonded to opposite sides of the plastic-encapsulated panel 100. They implement electrical functions on opposite sides of the plastic-encapsulated panel. They connect to metallized vias to communicate with the chip 120 or conductive structures within the plastic-encapsulated panel, completing the complete circuit network of the chip package 200. The conductive circuits located on the side of the plastic-encapsulated panel 100 closest to the chip 120 are fine circuits 160, which connect to first metallized blind vias 111 on one side of the plastic-encapsulated panel 100.

[0067] The metallized through-hole 113 is set through the opposite ends of the plastic-sealed plate 100 and is connected to the conductive circuit. The aperture of the middle section of the metallized through-hole 113 is smaller than the aperture of the opposite ends. It is also called a waist-shaped hole or an X-shaped hole, which can achieve high current conduction.

[0068] Through the above structure, the chip package of this embodiment integrates the metal base, fine circuits and X-shaped holes into the chip package to achieve the high integration, small size and fast signal transmission effects of the embedded package product. It can also be compatible with large current conduction, thereby ensuring the balance between the high integration and performance of the package.

[0069] In some embodiments, the chip package 200 includes at least one second metallized blind via 114 ; one end of the second metallized blind via 114 is connected to the metal base 110 , and the other end of the second metallized blind via 114 extends to connect to the conductive circuit on the side of the plastic package board 100 away from the chip 120 .

[0070] The conductive circuit includes a fine circuit 160 and a target circuit 170. The signal of the chip 120 away from the metal base 110 is led out in sequence through the first metalized blind via 111 and the fine circuit 160 to achieve external connection, wherein this part uses micro blind vias combined with fine circuits to achieve high electrical integration while meeting electrical connection requirements. The signal of the chip 120 close to the metal base 110 is led out in sequence through the metal base 110, the second metalized blind via 114 and the target circuit 170 to achieve external connection, wherein this connection network can utilize the metal base 110 to improve the heat dissipation efficiency of the chip 120, accelerate the speed at which the heat of the chip 120 diffuses to the outside through the metal base 110 and the second metalized blind via 114, and improve the reliability of the chip package 200. wherein, when the chip package 200 is working, the metalized through-hole 113 can also achieve high current conduction to meet the conduction requirements of the chip package 200 and ensure the performance of the chip package 200.

[0071] In some embodiments, the first metallized blind vias 111 have a diameter in the range of 30-50 microns. Specifically, the diameters may be 30 microns, 32 microns, 35 microns, 37 microns, 40 microns, 42 microns, 45 microns, 48 ​​microns, or 50 microns, among others. First metallized blind vias 111 within this diameter range can help achieve miniaturization and high integration of the chip package 200. The provision of micro blind vias allows for smaller pad pitches, smaller product sizes, higher integration, and increased spatial layout.

[0072] In some embodiments, the diameter of the metallized through hole 113 is in the range of 4-5 mils. The metallized through hole 113 within this diameter range can help achieve high current conduction of the chip package 200. That is, the diameter of the middle section of the metallized through hole 113 can be as small as 4 mils, and the diameter of the end of the metallized through hole 113 can be as large as 5 mils.

[0073] The ports at opposite ends of the metallized through hole 113 can be connected to corresponding pads (not marked in the figure), which are arranged on opposite sides of the plastic-encapsulated board 100 to lead out the signals of the metallized through hole 113 to achieve connection with the conductive circuit or the external connection network.

[0074] In some embodiments, the line width of the fine circuit 160 is in the range of 30-50 microns, specifically 30 microns, 31 microns, 33 microns, 36 microns, 40 microns, 44 microns, 45 microns, 49 microns, or 50 microns, etc. Fine circuits 160 within this aperture range can help achieve miniaturization and high integration of the chip package 200.

[0075] The above are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for preparing a chip package, characterized in that: The method for preparing the chip package comprises: Obtaining a plastic-sealed plate, wherein a metal base and a chip attached to one side of the metal base are plastic-sealed in the plastic-sealed plate; Performing double-sided laser drilling and hole filling processing on the plastic-sealed plate to obtain a first metalized blind via connected to the chip and a metalized through-hole penetrating the plastic-sealed plate; the middle aperture of the metalized through-hole is smaller than the apertures at its opposite ends; Conductive circuits are prepared on opposite sides of the plastic package plate to connect the metallized holes to obtain a chip package; wherein, fine circuits are prepared on the side of the plastic package plate close to the chip, and the fine circuits are connected to the first metallized blind holes.

2. The method for preparing a chip package according to claim 1, wherein: The double-sided laser drilling and hole filling process is performed on the plastic-sealed plate to obtain a first metallized blind via connected to the chip and a metallized through hole penetrating the plastic-sealed plate, including: Laser drilling is performed on a side of the plastic-encapsulated plate close to the chip to obtain a first blind hole exposing the chip, and a first-stage blind hole is formed on the plastic-encapsulated plate; wherein the depth of the first-stage blind hole is half the thickness of the plastic-encapsulated plate; Laser drilling is performed on a side of the plastic-encapsulated plate away from the chip to form a second-stage blind hole reaching the bottom of the first-stage blind hole, so as to connect with the first-stage blind hole to form a through hole; Double-sided hole filling electroplating is performed on the plastic-sealed plate to fill the first blind hole to form the first metallized blind hole and fill the through hole to form the metallized through hole, and electroplated metal layers are formed on opposite sides of the plastic-sealed plate.

3. The method for preparing a chip package according to claim 2, wherein: The laser drilling of the side of the plastic package plate away from the chip further comprises: Based on the position of the metal substrate, laser drilling is performed on a side of the plastic package plate away from the chip to form a second blind hole exposing the metal substrate; The double-sided hole filling electroplating of the plastic-sealed plate also includes: The second blind hole is filled with electroplating to form a second metallized blind hole.

4. The method for preparing a chip package according to claim 3, wherein: The step of preparing conductive circuits on opposite sides of the plastic-encapsulated plate to connect the metallized through holes includes: Sequentially laminating, exposing, and etching the electroplated metal layers on opposite sides of the plastic-sealed plate to retain the electroplated metal layers corresponding to the openings of the metallized holes and remove the electroplated metal layers in other areas; performing whole-plate sputtering on opposite sides of the plastic-sealed plate to form sputtering layers on opposite sides of the plastic-sealed plate; Conductive circuits are prepared on the sputtering layers on opposite sides of the plastic package plate to connect the metallized holes.

5. The method for preparing a chip package according to claim 4, wherein: The step of preparing conductive circuits on the sputtering layers on opposite sides of the plastic packaged plate to connect the metallized holes includes: Film lamination, exposure, development, pattern electroplating, film stripping and flash etching are performed in sequence on the sputtering layers on opposite sides of the plastic-sealed plate to prepare the fine circuit on the side of the plastic-sealed plate close to the chip, and to prepare the target circuit on the side of the plastic-sealed plate away from the chip; wherein the target circuit is connected to the second metallized blind via.

6. A chip package, characterized in that: The chip package is prepared by the chip package preparation method according to any one of claims 1 to 5, comprising: A plastic-sealed plate, wherein a metal base and a chip attached to one side of the metal base are plastic-sealed in the plastic-sealed plate; at least one first metallized blind via, one end of the first metallized blind via being connected to a side of the chip away from the metal base, and the other end of the first metallized blind via extending within the plastic-encapsulated plate until being exposed from one side of the plastic-encapsulated plate; Conductive circuits, the conductive circuits being disposed in contact with opposite sides of the plastic-encapsulated plate, wherein the conductive circuits located on a side of the plastic-encapsulated plate close to the chip are fine circuits, and the fine circuits are connected to a first metalized blind via on one side of the plastic-encapsulated plate; At least one metallized through hole is provided through two opposite ends of the plastic-sealed plate and is connected to the conductive circuit, and a middle portion of the metallized through hole has a smaller aperture than the apertures at the opposite ends.

7. The chip package according to claim 6, wherein: The chip package comprises at least one second metallized blind via; One end of the second metallized blind via is connected to the metal base, and the other end of the second metallized blind via extends to be connected to a conductive circuit on a side of the plastic package plate away from the chip.

8. The chip package according to claim 6, wherein: The aperture of the first metallized blind hole is in the range of 30-50 microns.

9. The chip package according to claim 6, wherein: The diameter of the metallized through hole is in the range of 4-5 mil.

10. The chip package according to claim 6, wherein: The line width of the fine circuit is in the range of 30-50 microns.

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