Anti-false-triggering analog signal acquisition circuit

Abstract

The invention discloses an anti-false-triggering analog signal acquisition circuit, and relates to the field of signal acquisition, in which a golden finger key and a contact impedance compensation resistor form a compensation module corresponding to the key; each divider resistor or the series combination of the divider resistor and the preceding-stage divider resistor forms a divider unit of the corresponding key; the reference voltage dividing resistor or the reference voltage dividing resistor is connected in series with the post-stage voltage dividing resistor of the voltage dividing unit corresponding to the key to form a reference voltage dividing unit corresponding to the key; constructing a voltage division network based on the compensation module, the voltage division unit, the first voltage division module and the reference voltage division unit; based on the voltage dividing network, when any golden finger key is pressed down, the corresponding voltage dividing unit and the reference voltage dividing unit are dynamically combined to form a voltage output range corresponding to the key, a voltage reference path corresponding to the key is conducted, and an analog signal is output through the voltage reference path. According to the invention, the state of each key can be accurately acquired even under the condition of high contact impedance.

Description

Technical Field

[0001] The present invention relates to the field of signal acquisition, and in particular to an anti-false trigger analog signal acquisition circuit. Background Art

[0002] Currently, keypad design generally utilizes a "gold finger + conductive rubber" process, which includes various process variations, such as "carbon film + carbon particles" and "gold + nickel particles." The "carbon film + carbon particles" solution offers the lowest cost, but due to its material properties, the contact impedance varies widely, resulting in significant instability. Actual tests have shown that, when pressed lightly, the contact between the gold finger and the conductive rubber is incomplete, and the contact impedance can reach several thousand ohms (kΩ). However, when pressed harder, the contact is more complete, and the impedance drops to a few ohms (Ω). This large fluctuation in contact impedance can easily lead to false triggering when multiple keys share a single ADC acquisition channel, especially when the MCU supply voltage is 3.3V. Summary of the Invention

[0003] In order to ensure that the status of each key can be stably and accurately acquired even under high contact impedance conditions, the present invention proposes an anti-false trigger analog signal acquisition circuit for acquiring analog signals corresponding to multiple gold finger keys; comprising:

[0004] A contact impedance compensation resistor connected to all gold finger keys; the gold finger keys and the contact impedance compensation resistor form a compensation module corresponding to the key; the compensation module is used to reduce the impact of contact impedance changes on analog signals;

[0005] A first voltage divider module, used for connecting to a positive power supply;

[0006] A second voltage divider module includes a plurality of voltage divider resistors sequentially connected in series with the first voltage divider module to form a multi-stage voltage divider resistor; the voltage divider resistors correspond one-to-one to the gold finger keys, and each voltage divider resistor or its series combination with the previous stage voltage divider resistor forms a voltage divider unit for the corresponding key;

[0007] The third voltage-dividing module includes a reference voltage-dividing resistor; for each gold finger key, the reference voltage-dividing resistor or the subsequent voltage-dividing resistor of the voltage-dividing unit corresponding to the key is connected in series to form a reference voltage-dividing unit for the corresponding key; wherein:

[0008] The compensation module is connected in parallel with the corresponding voltage dividing unit, the equivalent resistance formed in parallel is connected in series with the first voltage dividing module, and the total resistance formed in series is connected in series with the corresponding reference voltage dividing unit to form a complete voltage dividing network;

[0009] Based on the above-mentioned voltage divider network, when any gold finger button is pressed, the corresponding voltage divider unit is dynamically combined with the reference voltage divider unit to form the voltage output range corresponding to the button, and the voltage reference path corresponding to the button is turned on, and an analog signal within the corresponding voltage output range is output through the voltage reference path.

[0010] Furthermore, each of the voltage-dividing resistors or its series combination with the preceding voltage-dividing resistor forms a voltage-dividing unit corresponding to the key, specifically:

[0011] The voltage-dividing resistor closest to the first voltage-dividing module is a first-stage voltage-dividing unit, and the subsequent voltage-dividing resistors are connected in series with their preceding voltage-dividing resistors to form a multi-stage voltage-dividing unit corresponding to the key;

[0012] The voltage dividing units correspond to the gold finger buttons one by one.

[0013] Furthermore, one end of the reference voltage-dividing resistor is connected to the last-stage voltage-dividing resistor in the second voltage-dividing module, and the other end is grounded.

[0014] Furthermore, for each gold finger key, the reference voltage-dividing resistor or the subsequent voltage-dividing resistor of the voltage-dividing unit corresponding to the key is connected in series to form the reference voltage-dividing unit of the corresponding key, specifically:

[0015] For the gold finger button corresponding to the last level voltage divider unit, the reference voltage divider resistor alone forms the reference voltage divider unit corresponding to the button;

[0016] For other golden finger keys, the reference voltage-dividing resistor is connected in series with the subsequent voltage-dividing resistor of the voltage-dividing unit corresponding to the key to form the reference voltage-dividing unit corresponding to the key.

[0017] Furthermore, the first voltage dividing module is used to adjust the voltage dividing ratio between the equivalent resistance formed by the compensation module and the corresponding voltage dividing unit in parallel and the corresponding reference voltage dividing unit.

[0018] Furthermore, the voltage reference path of the gold finger key is formed by: a connection line between the first connection point and the second connection point;

[0019] The first connection point is the connection point between the voltage dividing unit corresponding to the key and the reference voltage dividing unit;

[0020] The second connection point is a connection point between the key and the contact impedance compensation resistor.

[0021] Furthermore, the anti-false trigger analog signal acquisition circuit further includes:

[0022] The noise suppression module connected to the parallel end of the gold finger button and the contact impedance compensation resistor is used to filter the analog signal output by the voltage reference path and input it into the analog-to-digital converter.

[0023] Furthermore, the noise suppression module includes: a first capacitor C1, a second capacitor C2 and a sixth resistor R6; wherein:

[0024] One end of the first capacitor C1 is connected to the parallel end of the gold finger button and the contact impedance compensation resistor, and one end of the sixth resistor R6; the other end of the sixth resistor R6 is connected to one end of the second capacitor C2 and then connected to the analog-to-digital converter; the other end of the first capacitor C1 and the other end of the second capacitor C2 are grounded.

[0025] Furthermore, the first voltage divider module includes a first resistor R1; one end of the first resistor R1 is connected to a positive power supply, and the other end is connected to the first-level voltage divider unit.

[0026] Furthermore, the sum of the maximum contact impedance of the sixth resistor R6 and the golden finger key is greater than ten times the sum of the resistance values ​​of the voltage-dividing resistors in the second voltage-dividing module;

[0027] The resistance of the first resistor R1 is greater than the sum of the resistances of the voltage-dividing resistors in the second voltage-dividing module;

[0028] The resistance of the contact impedance compensation resistor R7 is ten times greater than the sum of the sixth resistor R6 and the maximum contact impedance of the gold finger key.

[0029] Compared with the prior art, the present invention has at least the following beneficial effects:

[0030] (1) In the present invention, the gold finger key and the contact impedance compensation resistor form a compensation module corresponding to the key; each voltage-dividing resistor or its series combination with the preceding voltage-dividing resistor forms a voltage-dividing unit of the corresponding key; the reference voltage-dividing resistor or its series combination with the subsequent voltage-dividing resistor of the corresponding voltage-dividing unit of the key forms a reference voltage-dividing unit of the corresponding key; the compensation module is connected in parallel with the corresponding voltage-dividing unit, the equivalent resistance formed in parallel is connected in series with the first voltage-dividing module, and the total resistance formed in series is connected in series with the corresponding reference voltage-dividing unit to form a complete voltage-dividing network; based on the above voltage-dividing network, when any gold finger key is pressed, the corresponding voltage-dividing unit is dynamically combined with the reference voltage-dividing unit to form a voltage output range corresponding to the key, and the voltage reference path corresponding to the key is turned on, and an analog signal within the corresponding voltage output range is output through the voltage reference path. Therefore, the present invention achieves good compatibility with high contact impedance without changing the existing "carbon film + carbon particle" gold finger process, without adding additional ADC acquisition channels or using an IO matrix scanning solution, thereby reducing hardware costs.

[0031] (2) The present invention utilizes a unique voltage divider network, including multiple voltage divider resistors in the second voltage divider module and a reference voltage divider resistor in the third voltage divider module, to generate independent, non-overlapping voltage output ranges for each key when pressed. This design ensures that even in complex operating environments, the signals generated by different keys will not interfere with or overlap each other, effectively preventing false triggering and misidentification of key signals.

[0032] (3) To address the wide range of contact impedance variations in gold finger keys using the "carbon film + carbon particle" process, the present invention introduces a contact impedance compensation resistor (R7), whose resistance is designed to be significantly greater than ten times the sum of the sixth resistor (R6) and the maximum contact impedance. This design maintains circuit stability even when the contact impedance is high, preventing signal loss or misidentification due to poor contact, and ensuring stable and accurate acquisition of each key state under various pressure levels.

[0033] (4) In the present invention, when any gold finger key is pressed, the corresponding voltage divider unit and the reference voltage divider unit dynamically combine to form the voltage reference path of the key, and the analog signal is filtered by the noise suppression module to remove high-frequency noise before being input to the analog-to-digital converter (ADC). This not only improves the purity of the signal, but also further enhances the circuit's resistance to environmental interference and ensures the reliability of signal acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a circuit diagram for collecting analog signals to prevent false triggering according to an embodiment of the present invention;

[0035] Figure 2 for Figure 1 the corresponding first exploded view;

[0036] Figure 3 for Figure 1 corresponding second exploded view;

[0037] Figure 4 for Figure 1 Corresponding third exploded view. DETAILED DESCRIPTION

[0038] The following are specific embodiments of the present invention and the accompanying drawings to further describe the technical solutions of the present invention, but the present invention is not limited to these embodiments.

[0039] Example 1

[0040] When the microcontroller unit (MCU) power supply voltage is 3.3V, the input range of the AD interface is limited. If the change in contact impedance causes the voltage signal to fluctuate greatly, especially when the voltage signal becomes weak under high impedance conditions, errors may occur in the results of AD conversion, resulting in misjudgment or false triggering of the key state. Therefore, it is crucial to design a new circuit that can effectively cope with these impedance changes. The new circuit needs to ensure that even when the contact impedance is large (reaching the kΩ level), a relatively stable voltage signal can be maintained to ensure accurate identification of the key state. This can avoid the problem of false triggering caused by impedance changes and improve the reliability of the system and user experience. This is precisely the core challenge and goal of the present invention.

[0041] Therefore, in order to ensure that the state of each key can be stably and accurately acquired even under high contact impedance conditions, this embodiment proposes an anti-false trigger analog signal acquisition circuit for acquiring analog signals corresponding to multiple gold finger keys;

[0042] In order to explain the circuit of the present invention in detail, Figure 1 As shown, this embodiment takes the circuit including three golden finger buttons as an example for detailed description.

[0043] The anti-false trigger analog signal acquisition circuit includes:

[0044] A contact impedance compensation resistor connected to all gold finger keys; the gold finger keys and the contact impedance compensation resistor form a compensation module corresponding to the key; the compensation module is used to reduce the impact of contact impedance changes on analog signals;

[0045] A first voltage divider module, used for connecting to a positive power supply;

[0046] A second voltage divider module includes a plurality of voltage divider resistors sequentially connected in series with the first voltage divider module to form a multi-stage voltage divider resistor; the voltage divider resistors correspond one-to-one to the gold finger keys, and each voltage divider resistor or its series combination with the previous stage voltage divider resistor forms a voltage divider unit for the corresponding key;

[0047] Each voltage-dividing resistor or its series combination with the preceding voltage-dividing resistor forms a voltage-dividing unit corresponding to a key, specifically:

[0048] The voltage-dividing resistor closest to the first voltage-dividing module is a first-stage voltage-dividing unit, and the subsequent voltage-dividing resistors are connected in series with their preceding voltage-dividing resistors to form a multi-stage voltage-dividing unit corresponding to the key;

[0049] The voltage dividing units correspond to the gold finger buttons one by one.

[0050] The third voltage-dividing module includes a reference voltage-dividing resistor; for each gold finger key, the reference voltage-dividing resistor or the subsequent voltage-dividing resistor of the voltage-dividing unit corresponding to the key is connected in series to form a reference voltage-dividing unit for the corresponding key;

[0051] One end of the reference voltage-dividing resistor is connected to the last-stage voltage-dividing resistor in the second voltage-dividing module, and the other end is grounded.

[0052] For each gold finger key, the reference voltage-dividing resistor or the subsequent voltage-dividing resistor of the voltage-dividing unit corresponding to the key is connected in series to form the reference voltage-dividing unit of the corresponding key, specifically:

[0053] For the gold finger button corresponding to the last level voltage divider unit, the reference voltage divider resistor alone forms the reference voltage divider unit corresponding to the button;

[0054] It should be noted that the reference voltage divider unit of the gold finger button corresponding to the last-level voltage divider unit is composed only of the reference voltage divider resistor R5, and no other resistors need to be connected in series to ensure that the voltage output path is the shortest and the resistance is the smallest, which is convenient for forming an independent voltage reference.

[0055] For other golden finger keys, the reference voltage-dividing resistor is connected in series with the subsequent voltage-dividing resistor of the voltage-dividing unit corresponding to the key to form the reference voltage-dividing unit corresponding to the key.

[0056] For a voltage divider unit other than the last level, its corresponding reference voltage divider unit is formed by connecting the reference voltage divider resistor R5 and the subsequent voltage divider resistor of the voltage divider unit corresponding to the key in series. For example:

[0057] The voltage divider unit corresponding to the gold finger button SW1 is R2, and the reference voltage divider unit is R3+R4+R5.

[0058] The gold finger button SW2 corresponds to the voltage divider unit R2+R3, and the reference voltage divider unit is R4+R5.

[0059] The gold finger button SW3 corresponds to the voltage divider unit R2+R3+R4, and the reference voltage divider unit is R5.

[0060] By connecting the subsequent resistors in series, it is ensured that the resistance values ​​of the reference voltage divider units of different buttons are significantly different, thereby forming a non-overlapping voltage output range.

[0061] The first voltage dividing module is used to adjust the voltage dividing ratio between the equivalent resistance formed by the compensation module and the corresponding voltage dividing unit in parallel and the corresponding reference voltage dividing unit.

[0062] The first voltage divider module includes a first resistor R1; one end of the first resistor R1 is connected to a positive power supply, and the other end is connected to a primary voltage divider unit.

[0063] in:

[0064] The compensation module is connected in parallel with the corresponding voltage divider unit, the equivalent resistance formed in parallel is connected in series with the first voltage divider module, and the total resistance formed in series is connected in series with the corresponding reference voltage divider unit to form a complete voltage divider network; through the parallel design, the compensation module can effectively reduce the impact of contact impedance fluctuations, and the series connection R1 is used to adjust the overall voltage divider ratio to ensure the stable output of the third voltage divider module.

[0065] Based on the above-mentioned voltage divider network, when any gold finger button is pressed, the corresponding voltage divider unit is dynamically combined with the reference voltage divider unit to form the voltage output range corresponding to the button, and the voltage reference path corresponding to the button is turned on, and an analog signal within the corresponding voltage output range is output through the voltage reference path.

[0066] The voltage reference path of the gold finger key is formed by: a connection line between the first connection point and the second connection point;

[0067] The first connection point A is the connection point between the voltage dividing unit corresponding to the key and the reference voltage dividing unit;

[0068] The second connection point B is the connection point between the key and the contact impedance compensation resistor.

[0069] In other words, by dynamically connecting the reference voltage divider resistor and the subsequent voltage divider resistor in series, independent (i.e., differentiated) voltage reference paths are achieved for different buttons, avoiding voltage overlap caused by contact impedance fluctuations and ensuring that the analog-to-digital converter (ADC) can uniquely identify the button status.

[0070] The anti-false trigger analog signal acquisition circuit further includes:

[0071] The noise suppression module connected to the parallel end of the gold finger button and the contact impedance compensation resistor is used to filter the analog signal output by the voltage reference path and input it into the analog-to-digital converter.

[0072] The noise suppression module includes: a first capacitor C1, a second capacitor C2 and a sixth resistor R6; wherein:

[0073] One end of the first capacitor C1 is connected to the parallel end of the gold finger button and the contact impedance compensation resistor, and one end of the sixth resistor R6; the other end of the sixth resistor R6 is connected to one end of the second capacitor C2 and then connected to the analog-to-digital converter; the other end of the first capacitor C1 and the other end of the second capacitor C2 are grounded.

[0074] In the noise suppression module, R6 is a filter resistor, and C1 and C2 are decoupling capacitors. R6 and C1 form an RC low-pass filter unit, which is used to suppress high-frequency noise and stabilize voltage fluctuations at the analog signal input. C2 is used to filter out high-frequency interference on the power line and achieve power supply decoupling. The three together form a high-frequency noise suppression module. Through the synergistic effect of filtering and decoupling, the impact of external electromagnetic interference on the analog-to-digital converter (ADC) input signal is reduced, thereby improving the circuit's anti-interference capability and signal acquisition accuracy.

[0075] The anti-false trigger analog signal acquisition circuit of this embodiment meets the following resistance design conditions:

[0076] First resistance design condition: the sum of the maximum contact impedance of the sixth resistor R6 and the gold finger key is greater than ten times the sum of the resistance values ​​of the voltage divider resistors in the second voltage divider module;

[0077] By limiting the first resistance design condition, ensure that the high impedance path (R6 + the maximum contact impedance of the gold finger button) has no effect on the low impedance path (the sum of the resistance values ​​of each voltage divider resistor is as follows Figure 1 The sum of R2+R3+R4 in the figure has no significant impact on signal transmission, avoiding signal interference or false triggering.

[0078] Second resistance design condition: the resistance of the first resistor R1 is greater than the sum of the resistances of the voltage-dividing resistors in the second voltage-dividing module;

[0079] In the second resistance design condition, R1 is the main control resistor, and its resistance is significantly higher than the sum of the resistances of the voltage divider resistors (for example Figure 1 The sum of R2+R3+R4 in the circuit ensures its dominant position in the circuit, for example, controlling the voltage distribution ratio in a voltage divider network. By limiting the minimum resistance of R1, circuit instability or overload caused by fluctuations in the sum of the voltage divider resistors is prevented.

[0080] The third resistance design condition: the resistance of the contact impedance compensation resistor R7 is greater than ten times the sum of the sixth resistor R6 and the maximum contact impedance of the gold finger key.

[0081] In the third resistance design condition, the resistance of R7 is ten times greater than the sum of the sixth resistor R6 and the maximum contact impedance of the gold finger button. The high resistance suppresses the influence of the contact impedance change on the analog signal, thereby realizing the anti-false triggering function.

[0082] When designing buttons using a gold finger and conductive rubber, the primary source of contact impedance is the contact point between the gold finger and the conductive rubber. This contact impedance varies depending on the degree of pressure applied, with higher impedance for light presses and lower impedance for hard presses. Connecting these switches to a large resistor (R7) effectively reduces the impact of contact impedance variations on voltage distribution within the circuit, thereby ensuring stable signal acquisition.

[0083] In order to clearly display the detailed voltage division data of the voltage division network when each gold finger button is pressed, this embodiment uses Figures 2 to 4 One by one Figure 1 The working principles of each gold finger button in the circuit shown are analyzed in detail. These diagrams provide an intuitive understanding of how the circuit dynamically adjusts the voltage divider path when different buttons are triggered, ensuring that the voltage output range corresponding to each button does not overlap and is stable and reliable. Each diagram focuses on a specific button, showing the combination of its corresponding voltage divider unit and the reference voltage divider unit, as well as the resulting voltage changes, making it easier to fully grasp the core technical details of the entire circuit design.

[0084] 1. Based on Figure 2 Analyze the voltage divider network when SW1 is pressed

[0085] 1.1. Voltage at point A V A (i.e. calculation of the first connection point)

[0086] Voltage division relationship: When SW1 is pressed, the voltage division relationship in the circuit is that the compensation module (R7+SW1) is connected in parallel with the voltage division unit (R2), then connected in series with the first voltage division module (R1), and then divided with the reference voltage division unit (R3+R4+R5). The calculation steps are:

[0087] 1.11. Calculate the equivalent resistance R after (R7+SW1) and (R2) are connected in parallel eq1 :

[0088] R eq1 =((R7+SW1)×R2) / ((R7+SW1)+R2);

[0089] 1.12、R eq1 In series with R1, the total resistance is R total1 :

[0090] R total1 =R1+R eq1 ;

[0091] 1.13, R total1 Divide the voltage by (R3+R4+R5) to get the voltage at point A:

[0092] V A =VDD×((R3+R4+R5) / (R total1 +(R3+R4+R5)));

[0093] 1.2. Voltage at point B V B (i.e. calculation of the second connection point)

[0094] Voltage division relationship: VDD minus the voltage at point A VA The voltage is divided by SW1 and (R1+R7), where the voltage obtained by SW1 plus the voltage at point A equals the voltage at point B. The specific calculation is:

[0095] 1.21: Calculate the voltage divider between SW1 and (R1+R7):

[0096] V B =V A +(VDD-V A )×(SW1 / (SW1+(R1+R7))).

[0097] 2. Based on Figure 3 Analyze the voltage divider network when SW2 is pressed

[0098] 2.1、Point A voltage V A (i.e. calculation of the first connection point)

[0099] Voltage division relationship: The compensation module (SW2+R7) and the voltage division unit (R2+R3) are connected in parallel and then connected in series with the first voltage division module (R1), and then divided with the reference voltage division unit (R4+R5). The calculation steps are:

[0100] 2.11. Calculate the equivalent resistance R after (R7+SW2) and (R2+R3) are connected in parallel eq2 :

[0101] R eq2 =((R2+R3)×(SW2+R7)) / ((R2+R3)+(SW2+R7));

[0102] 2.12、R eq2 In series with R1, the total resistance is R total2 :

[0103] R total2 =R1+R eq2 ;

[0104] 2.13 R total2 Divide the voltage by (R4+R5) to get the voltage at point A:

[0105] V A =VDD×((R4+R5) / (R total2 +(R4+R5)));

[0106] 2.2, Point B voltage V B (i.e. calculation of the second connection point)

[0107] Voltage division relationship: VDD minus the voltage at point A V A The voltage is divided by SW2 and (R1+R7), where the voltage obtained by SW2 plus the voltage at point A equals the voltage at point B. The specific calculation is:

[0108] 2.21: Calculate the voltage divider between SW2 and (R1+R7):

[0109] V B =V A +(VDD-V A )×(SW2 / (SW2+(R1+R7))).

[0110] 3. Based on Figure 4 Analyze the voltage divider network when SW3 is pressed

[0111] 3.1、Point A voltage V A (i.e. calculation of the first connection point)

[0112] Voltage division relationship: The compensation module (SW3+R7) and the voltage division unit (R2+R3+R4) are connected in parallel and then connected in series with the first voltage division module (R1), and then divided with the reference voltage division unit (R5). The calculation steps are:

[0113] 3.11. Calculate the equivalent resistance R after (SW3+R7) and (R2+R3+R4) are connected in parallel eq3 :

[0114] R eq3 =((R2+R3+R4)×(SW3+R7)) / ((R2+R3+R4)+(SW3+R7));

[0115] 3.12、R eq3 In series with R1, the total resistance is R total3 :

[0116] R total3 =R1+R eq3 ;

[0117] 3.13 R total3 Divide the voltage with (R5) to get the voltage at point A:

[0118] V A =VDD×((R5) / (R total3 +R5));

[0119] 3.2. Voltage V at point B B (i.e. calculation of the second connection point)

[0120] Voltage division relationship: VDD minus the voltage at point A V A The voltage is divided by SW3 and (R1+R7), where the voltage obtained by SW3 plus the voltage at point A is the voltage at point B. The specific calculation is:

[0121] 3.21: Calculate the voltage divider between SW3 and (R1+R7):

[0122] V B =V A +(VDD-V A )×(SW3 / (SW3+(R1+R7))).

[0123] The purpose of calculating the voltages at points A and B is to demonstrate that key signals can be accurately and stably acquired and false triggering can be avoided under varying key contact impedance conditions. Through a rational resistor network design and voltage-dividing strategy, stable voltage output is maintained even with large variations in contact impedance, enabling reliable key recognition.

[0124] Specifically:

[0125] The voltage at point A is measured to demonstrate that the voltage divider network design of this embodiment ensures that the voltage at point A remains relatively stable even when the contact impedance varies (for example, when pressing lightly or hard). This ensures that the MCU can correctly identify the key state regardless of contact impedance fluctuations.

[0126] The design goal of the voltage at point B is to ensure that it varies within an acceptable range so that the MCU can reliably read the button status.

[0127] To further demonstrate the feasibility and effectiveness of the circuit design of the present invention, this embodiment will be verified in detail through a series of experimental data. These experimental data cover the performance of the circuit under various working conditions, including but not limited to the voltage output when different buttons are pressed, the impact of contact impedance changes on signal acquisition, and the noise suppression effect. By comparing and analyzing the experimental results, it can be clearly demonstrated that the circuit of the present invention has a high degree of stability and accuracy in practical applications, ensuring that each button state can be accurately identified even under high contact impedance conditions. The experimental data provided provides a solid foundation for evaluating the overall performance of the circuit and proves the significant advantages of the design in preventing false triggering and stabilizing signal acquisition:

[0128] Table 1 (records the parameters of each component, based on the resistance design conditions):

[0129]

[0130]

[0131] Table 1 details the parameter values ​​of the various electronic components in the circuit. It provides the minimum (min), typical (TYP), and maximum (max) values ​​of each resistor (R1 to R7) and switch (SW1 to SW3), along with their units.

[0132] VDD: Positive power supply, ranging from 3.0V to 3.6V, with a typical value of 3.3V.

[0133] Resistors (R1 to R7): Lists the resistance range of each resistor. For example, the resistance range of R1 is 2178Ω to 2222Ω, with a typical value of 2200Ω.

[0134] Switches (SW1 to SW3): The contact resistance range of the switch in the pressed state is 0Ω typical and 200Ω maximum.

[0135] Table 2 (records the resistance data of the voltage divider network when SW1 is pressed. In the table, " / / " indicates parallel connection and "+" indicates connected connection):

[0136]

[0137]

[0138] The measured min, TYP, and max values ​​in Table 2 correspond to the corresponding min, TYP, and max values ​​in Table 1. For example, the min values ​​in Table 2 are experimentally tested based on the min values ​​in Table 1. R1+R2 / / (SW1+R7) indicates that the compensation module (R7+SW1) is connected in parallel with the voltage divider (R2) and then in series with the first voltage divider (R1).

[0139] Table 2 shows the voltage and resistance values ​​of key points in the circuit calculated under the three parameter conditions of minimum (min), typical (TYP) and maximum (max) when SW1 is pressed. Specifically, the voltage V A The voltage V at point B ranges from 1.069V to 1.316V under different conditions. B With V A This shows that even with varying contact impedance, the voltage output range for this button remains stable and does not overlap with other buttons. This ensures that the circuit remains stable and provides accurate signal acquisition even with high contact impedance.

[0140] Table 2-1:

[0141] Contact resistance Ω 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 AD 508 512 516 520 524 528 532 535 539 543 547

[0142] Table 2-1 provides theoretical data calculated based on typical parameters (TYP), showing how the AD converter reading changes when SW1 is pressed under different contact impedance conditions. As the contact impedance increases from 0Ω to 10kΩ, the AD reading only slightly increases from 508 to 547, demonstrating that the circuit maintains a stable voltage output even under high contact impedance conditions. This design ensures that each button has an independent and well-defined voltage output range, preventing false triggering.

[0143] Table 3 (records the resistance data of the voltage divider network when SW2 is pressed. In the table, " / / " indicates parallel connection and "+" indicates connected connection):

[0144]

[0145]

[0146] The measured min, TYP, and max values ​​in Table 3 correspond to the corresponding min, TYP, and max values ​​in Table 1. For example, the min value in Table 3 is experimentally tested based on the min value in Table 1. R1+(R2+R3) / / (SW2+R7) indicates that the compensation module (SW2+R7) and the voltage divider (R2+R3) are connected in parallel and then in series with the first voltage divider (R1).

[0147] Table 3 lists the relevant voltage and resistance values ​​calculated under the minimum, typical and maximum parameter conditions when SW2 is pressed. A The voltage at point B also follows this pattern, ranging from 0.712V to 0.880V under different conditions. This demonstrates that this key has a unique voltage output range and does not overlap with other key signals. This proves that the circuit can provide reliable and stable voltage output even when the contact impedance fluctuates.

[0148] Table 3-1:

[0149] Contact resistance Ω 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 AD 339 344 349 353 358 363 368 373 377 382 387

[0150] Table 3-1 shows theoretical data calculated based on typical parameters (TYP), describing the AD converter readings when SW2 is pressed under different contact impedance conditions. The results show that as the contact impedance increases from 0Ω to 10kΩ, the AD reading increases slightly from 339 to 387, further verifying that the circuit of this invention can maintain stable operation under high contact impedance. This design ensures that each button has a clearly defined voltage output range, effectively preventing false triggering caused by contact impedance.

[0151] Table 4 (records the resistance data of the voltage divider network when SW3 is pressed. In the table, " / / " indicates parallel connection and "+" indicates connected connection):

[0152]

[0153]

[0154] The measured min, TYP, and max values ​​in Table 4 correspond to the corresponding min, TYP, and max values ​​in Table 1. For example, the min value in Table 4 is experimentally tested based on the min value in Table 1. R1+(R2+R3+R4) / / (SW3+R7) indicates that the compensation module (SW3+R7) and the voltage divider (R2+R3+R4) are connected in parallel, then in series with the voltage divider (R1).

[0155] Table 4 records the key voltage and resistance information calculated under the minimum, typical and maximum parameter conditions when SW3 is pressed. A The voltage at point B lies between 0.355V and 0.442V, the same voltage as at point B, demonstrating the unique voltage output range of this key. These values ​​demonstrate that the circuit design successfully assigns a non-overlapping voltage range to each key, maintaining a stable output even with varying contact impedance. This design not only improves system reliability but also enhances the user experience.

[0156] Table 4-1:

[0157] Contact resistance Ω 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 AD 170 170 171 172 173 173 174 175 176 176 177

[0158] Table 4-1 shows theoretical data calculated based on typical parameters (TYP), reflecting the changes in the AD converter readings under different contact impedance conditions when SW3 is pressed. Although the contact impedance increases from 0Ω to 10kΩ, the AD reading only slowly increases from 170 to 177, further proving that the circuit can maintain good stability and accuracy even in a high contact impedance environment. Each button has its own independent voltage output range, ensuring the uniqueness and accuracy of the signal and effectively reducing the possibility of false triggering. This also confirms the effectiveness and superiority of the anti-false trigger analog signal acquisition circuit proposed in this invention.

[0159] In the present invention, the gold finger key and the contact impedance compensation resistor form a compensation module corresponding to the key; each voltage dividing resistor or its series combination with the previous voltage dividing resistor forms a voltage dividing unit of the corresponding key; the reference voltage dividing resistor or its series combination with the subsequent voltage dividing resistor of the corresponding voltage dividing unit of the key forms a reference voltage dividing unit of the corresponding key; the compensation module is connected in parallel with the corresponding voltage dividing unit, the equivalent resistance formed in parallel is connected in series with the first voltage dividing module, and the total resistance formed in series is connected in series with the corresponding reference voltage dividing unit to form a complete voltage dividing network; based on the above-mentioned voltage dividing network, when any gold finger key is pressed, the corresponding voltage dividing unit is dynamically combined with the reference voltage dividing unit to form a voltage output range corresponding to the key, and the voltage reference path corresponding to the key is turned on, and an analog signal within the corresponding voltage output range is output through the voltage reference path. Therefore, the present invention achieves good compatibility with high contact impedance without changing the existing "carbon film + carbon particle" gold finger process, without adding additional ADC acquisition channels or using an IO matrix scanning solution, thereby reducing hardware costs.

[0160] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0161] In addition, in the present invention, descriptions such as "first," "second," and "one" are for descriptive purposes only and should not be understood to indicate or imply their relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0162] In the present invention, unless otherwise specified or limited, the terms "connection" and "fixation" should be understood in a broad sense. For example, "fixation" can mean fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will be able to understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0163] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in this field can implement it. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

Claims

1. A false triggering prevention analog signal acquisition circuit, characterized in that: Used to collect analog signals corresponding to multiple golden finger buttons; including: A contact impedance compensation resistor connected to all gold finger keys; the gold finger keys and the contact impedance compensation resistor form a compensation module corresponding to the key; the compensation module is used to reduce the impact of contact impedance changes on analog signals; A first voltage divider module, used for connecting to a positive power supply; A second voltage divider module includes a plurality of voltage divider resistors sequentially connected in series with the first voltage divider module to form a multi-stage voltage divider resistor; the voltage divider resistors correspond one-to-one to the gold finger keys, and each voltage divider resistor or its series combination with the previous stage voltage divider resistor forms a voltage divider unit for the corresponding key; The third voltage-dividing module includes a reference voltage-dividing resistor; for each gold finger key, the reference voltage-dividing resistor or the subsequent voltage-dividing resistor of the voltage-dividing unit corresponding to the key is connected in series to form a reference voltage-dividing unit for the corresponding key; wherein: The compensation module is connected in parallel with the corresponding voltage dividing unit, the equivalent resistance formed in parallel is connected in series with the first voltage dividing module, and the total resistance formed in series is connected in series with the corresponding reference voltage dividing unit to form a complete voltage dividing network; Based on the above-mentioned voltage divider network, when any gold finger button is pressed, the corresponding voltage divider unit is dynamically combined with the reference voltage divider unit to form the voltage output range corresponding to the button, and the voltage reference path corresponding to the button is turned on, and an analog signal within the corresponding voltage output range is output through the voltage reference path.

2. The anti-false trigger analog signal acquisition circuit according to claim 1, characterized in that: Each voltage-dividing resistor or its series combination with the preceding voltage-dividing resistor forms a voltage-dividing unit corresponding to a key, specifically: The voltage-dividing resistor closest to the first voltage-dividing module is a first-stage voltage-dividing unit, and the subsequent voltage-dividing resistors are connected in series with their preceding voltage-dividing resistors to form a multi-stage voltage-dividing unit corresponding to the key; The voltage dividing units correspond to the gold finger buttons one by one.

3. The anti-false trigger analog signal acquisition circuit according to claim 2, characterized in that: One end of the reference voltage-dividing resistor is connected to the last-stage voltage-dividing resistor in the second voltage-dividing module, and the other end is grounded.

4. The anti-false trigger analog signal acquisition circuit according to claim 3, characterized in that: For each gold finger key, the reference voltage-dividing resistor or the subsequent voltage-dividing resistor of the voltage-dividing unit corresponding to the key is connected in series to form the reference voltage-dividing unit of the corresponding key, specifically: For the gold finger button corresponding to the last level voltage divider unit, the reference voltage divider resistor alone forms the reference voltage divider unit corresponding to the button; For other golden finger keys, the reference voltage-dividing resistor is connected in series with the subsequent voltage-dividing resistor of the voltage-dividing unit corresponding to the key to form the reference voltage-dividing unit corresponding to the key.

5. The anti-false trigger analog signal acquisition circuit according to claim 4, characterized in that: The first voltage dividing module is used to adjust the voltage dividing ratio between the equivalent resistance formed by the compensation module and the corresponding voltage dividing unit in parallel and the corresponding reference voltage dividing unit.

6. The anti-false trigger analog signal acquisition circuit according to claim 5, characterized in that: The voltage reference path of the gold finger key is formed by: a connection line between the first connection point and the second connection point; The first connection point is the connection point between the voltage dividing unit corresponding to the key and the reference voltage dividing unit; The second connection point is a connection point between the key and the contact impedance compensation resistor.

7. The anti-false trigger analog signal acquisition circuit according to claim 6, characterized in that: The anti-false trigger analog signal acquisition circuit further includes: The noise suppression module connected to the parallel end of the gold finger button and the contact impedance compensation resistor is used to filter the analog signal output by the voltage reference path and input it into the analog-to-digital converter.

8. The anti-false trigger analog signal acquisition circuit according to claim 7, characterized in that: The noise suppression module includes: a first capacitor C1, a second capacitor C2 and a sixth resistor R6; wherein: One end of the first capacitor C1 is connected to the parallel end of the gold finger button and the contact impedance compensation resistor, and one end of the sixth resistor R6; the other end of the sixth resistor R6 is connected to one end of the second capacitor C2 and then connected to the analog-to-digital converter; the other end of the first capacitor C1 and the other end of the second capacitor C2 are grounded.

9. The anti-false trigger analog signal acquisition circuit according to claim 8, characterized in that: The first voltage divider module includes a first resistor R1; one end of the first resistor R1 is connected to a positive power supply, and the other end is connected to a primary voltage divider unit.

10. The anti-false trigger analog signal acquisition circuit according to claim 9, characterized in that: The sum of the maximum contact impedance of the sixth resistor R6 and the gold finger key is greater than ten times the sum of the resistance values ​​of the voltage divider resistors in the second voltage divider module; The resistance of the first resistor R1 is greater than the sum of the resistances of the voltage-dividing resistors in the second voltage-dividing module; The resistance of the contact impedance compensation resistor R7 is greater than ten times the sum of the sixth resistor R6 and the maximum contact impedance of the gold finger key.

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