Multilayer circuit board, via structure optimization method and electronic device

Abstract

The present application provides a multi-layer circuit board, a via structure optimization method, and an electronic device, which can be applied to the field of electronic device technology. The multi-layer circuit board includes: multiple signal layers; at least one first differential via structure drilled in the multi-layer circuit board along a direction offset by a first drilling angle relative to the normal direction of the multi-layer circuit board, so as to electrically connect at least two signal layers in the multi-layer circuit board; and at least one second differential via structure drilled in the multi-layer circuit board along a direction offset by a second drilling angle relative to the normal direction of the multi-layer circuit board, so as to electrically connect at least two signal layers in the multi-layer signal layer; wherein the first drilling angle and the second drilling angle are both acute angles, and the at least one first differential via structure and the at least one second differential via structure are arranged to intersect with each other.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and more specifically to a multi-layer circuit board, a via structure optimization method, and an electronic device. Background Art

[0002] With the rapid growth of data processing rates in electronic devices, crosstalk between high-speed signal lines and vias in circuit boards has become increasingly severe. This causes amplitude and phase distortion in transmitted high-speed signals, increasing bit error rates. Existing technologies typically reduce crosstalk between vias during high-speed signal transmission by increasing the distance between adjacent vias or by adding more vias. Summary of the Invention

[0003] In view of the above problems, the present application provides a method for improving a multi-layer circuit board, optimizing a via structure, and an electronic device.

[0004] According to a first aspect of the present application, a multi-layer circuit board is provided, comprising: a multi-layer signal layer; at least one first differential via structure, drilled in the multi-layer circuit board along a direction of a first drilling angle offset relative to the normal of the multi-layer circuit board, so that at least two signal layers in the multi-layer signal layer are electrically connected to each other; and at least one second differential via structure, drilled in the multi-layer circuit board along a direction of a second drilling angle offset relative to the normal of the multi-layer circuit board, so that at least two signal layers in the multi-layer signal layer are electrically connected to each other; wherein the first drilling angle and the second drilling angle are both acute angles, and the at least one first differential via structure and the at least one second differential via structure are arranged to intersect with each other.

[0005] The second aspect of the present application provides a via structure optimization method, including: determining initial via structure parameters for at least one first differential via structure and at least one second differential via structure; simulating the electrical response of a multilayer circuit board under a test electrical signal based on the initial via structure parameters to obtain a simulated response of the multilayer circuit board; adjusting the initial via structure parameters based on the simulated response, and performing simulation based on the adjusted via structure parameters until the simulation response meets the performance requirements of the multilayer circuit board, thereby obtaining target via structure parameters.

[0006] According to an embodiment of the present application, a multi-layer circuit board may include multiple layers of signal layers, at least one first differential via structure and at least one second differential via structure. The multiple layers of signal layers are arranged vertically stacked on each other, and the normal direction of the multiple layers of signal layers is used as a reference direction. In a certain row of the multi-layer circuit board, according to the interconnection design requirements between the signal layers corresponding to the first differential via structure, the first differential via structure is drilled between the corresponding multiple layers of signal layers along the direction of the first drilling angle offset from the normal, thereby forming an electrical connection between at least two layers of signal layers. In an adjacent row where the first differential via structure is set, according to the interconnection design requirements between the signal layers corresponding to the second differential via structure, the second differential via structure is drilled between the corresponding multiple layers of signal layers along the direction of the second drilling angle offset from the normal and different from the first drilling angle. , so that an electrical connection is formed between at least two signal layers, and in a multi-layer circuit board, differential via structures located in different rows are drilled in the multi-layer signal layer at different drilling angles, so that the two adjacent differential via structures are in the form of non-planar intersection, rather than a parallel structure setting, shortening the coupling length between two or more differential via structures with a predetermined interval, so that the coupling length between the two differential via structures is limited to the partial area of ​​non-planar intersection, and the distance between the two ends of the multiple differential via structures is increased, thereby reducing the far-end crosstalk of the differential via structure. At the same time, since the two differential via structures are in non-planar intersection, the crosstalk between the two intersecting vias is offset, further reducing the impact of crosstalk, and improving the transmission integrity and accuracy of high-speed signals and the reliability of the multi-layer circuit board.

[0007] According to the embodiments of the present application, by slanting the differential via structures drilled in the multi-layer circuit board, there is no need to introduce redundant isolation ground holes and other wiring designs to reduce crosstalk between multiple differential via structures, thereby saving the layout design space of the pins and via structures of the multi-layer circuit board. As a result, more differential via structures can be arranged within a limited multi-layer circuit board or the design size of the multi-layer circuit board can be reduced with a certain number of differential via structures, thereby reducing costs and cycles. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0009] Figure 1 A schematic diagram of a multi-layer circuit board according to an embodiment of the present application is shown;

[0010] Figure 2 shows a top view of multiple differential via structures according to an embodiment of the present application;

[0011] Figure 3A schematic diagram showing a cross section of multiple differential via structures according to an embodiment of the present application;

[0012] Figure 4 A schematic diagram showing a cross section of multiple differential via structures according to another embodiment of the present application;

[0013] Figure 5 A schematic diagram showing a cross section of multiple differential via structures according to yet another embodiment of the present application;

[0014] Figure 6 A schematic diagram of via routing of a differential via structure according to an embodiment of the present application is shown;

[0015] Figure 7 A schematic diagram showing via routing of a differential via structure according to another embodiment of the present application is shown;

[0016] Figure 8 A schematic diagram of via routing of a differential via structure according to another embodiment of the present application is shown;

[0017] Figure 9 A schematic diagram showing the pin distribution of a multi-layer circuit board containing isolated ground holes according to an embodiment of the present application is shown;

[0018] Figure 10 A schematic diagram showing an application scenario of a multi-layer circuit board according to an embodiment of the present application is shown;

[0019] Figure 11 A flow chart of a via structure optimization method according to an embodiment of the present application is shown;

[0020] Figure 12 A schematic diagram showing comparison of frequency domain crosstalk according to an embodiment of the present application is shown;

[0021] Figure 13 A schematic diagram showing a comparison of time domain crosstalk according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0023] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0025] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0026] With the rapid growth of data rates in modern electronic devices and systems, signal integrity and electromagnetic compatibility issues are becoming increasingly prominent. In order to improve and ensure the quality of transmitted signals, it is increasingly important to optimize the design of circuit boards. By focusing on circuit board wiring rules, electromagnetic compatibility, and crosstalk issues, the integrity of transmitted signals can be improved.

[0027] During high-speed signal transmission, the rise time of the signal's rising edge is drastically shortened, significantly increasing the spectrum bandwidth. This leads to severe crosstalk between high-speed signal lines and vias on PCBs. When high-speed signals travel along transmission lines, they generate varying electromagnetic fields, which, through capacitive and inductive coupling, couple energy to adjacent signal lines and vias, causing crosstalk. Crosstalk can distort the signal's amplitude and phase, leading to signal distortion. It also affects accurate signal transmission and reception, increasing bit error rates.

[0028] Furthermore, crosstalk will make the affected vias more sensitive to external electromagnetic interference, reducing the anti-interference margin of the signal line that originally has a certain anti-interference ability, and making it more susceptible to external electromagnetic noise, affecting the stability and reliability of the system.

[0029] An embodiment of the present application provides a multi-layer circuit board, comprising: multiple signal layers; at least one first differential via structure, drilled in the multi-layer circuit board along a direction of a first drilling angle offset relative to the normal of the multi-layer circuit board, so that at least two signal layers in the multiple signal layers in the multi-layer circuit board are electrically connected to each other; and at least one second differential via structure, drilled in the multi-layer circuit board along a direction of a second drilling angle offset relative to the normal of the multi-layer circuit board, so that at least two signal layers in the multiple signal layers are electrically connected to each other; wherein the first drilling angle and the second drilling angle are both acute angles, and the at least one first differential via structure and the at least one second differential via structure are arranged to intersect with each other.

[0030] According to an embodiment of the present application, a multi-layer circuit board may include multiple signal layers, at least one first differential via structure, and at least one second differential via structure.

[0031] A multi-layer circuit board may include multiple signal layers stacked on top of each other, and signal lines may be arranged in the signal layers, so that high-speed signals, low-speed signals and other signals can be transmitted through the multiple signal layers.

[0032] According to an embodiment of the present application, at least one first differential via structure is drilled in a multilayer circuit board along a direction offset by a first drilling angle relative to the normal of the multilayer circuit board, so as to electrically connect at least two signal layers among the multiple signal layers in the multilayer circuit board to each other.

[0033] According to an embodiment of the present application, at least one second differential via structure is drilled in the multilayer circuit board along a direction offset by a second drilling angle relative to the normal of the multilayer circuit board, so as to electrically connect at least two signal layers in the multilayer signal layer to each other.

[0034] In a multi-layer circuit board, multiple signal layers can be electrically connected together through the first differential via structure and the second differential via structure, so that high-speed signals can be transmitted in different signal layers.

[0035] With the z-axis direction perpendicular to the multi-layer circuit board as the normal direction of the multi-layer circuit board, the first differential via structure can be drilled obliquely in the multi-layer signal layer at a first drilling angle, and the second differential via structure can be drilled obliquely in the multi-layer signal layer at a second drilling angle, thereby realizing interconnection between part or multiple signal layers.

[0036] According to an embodiment of the present application, the first drilling angle and the second drilling angle are both acute angles, and at least one first differential via structure and at least one second differential via structure are arranged to intersect with each other.

[0037] The first drilling angle and the second drilling angle can both be acute angles between 0° and 90°, or both can be 0°. When the first drilling angle and the second drilling angle are acute angles between 0° and 90°, the first differential via structure and the second differential via structure are obliquely drilled in the multi-layer signal layer and intersect with each other in different planes. When the first drilling angle or the second drilling angle is 0°, the first differential via structure or the second differential via structure can be vertically drilled in the multi-layer signal layer. When the first drilling angle or the second drilling angle is 0° and the other drilling angle is an acute angle between 0° and 90°, the extension line of the first differential via structure and the extension line of the second differential via structure can intersect. Furthermore, the first drilling angle and the second drilling angle can be different. For example, the first drilling angle can be 17° and the second drilling angle can be 39°. Thus, the angle formed by the first differential via structure and the second differential via structure intersecting in different planes can be 0° to 180°.

[0038] According to an embodiment of the present application, a multi-layer circuit board may include multiple layers of signal layers, at least one first differential via structure and at least one second differential via structure. The multiple layers of signal layers are arranged vertically stacked on each other, and the normal direction of the multiple layers of signal layers is used as a reference direction. In a certain row of the multi-layer circuit board, according to the interconnection design requirements between the signal layers corresponding to the first differential via structure, the first differential via structure is drilled between the corresponding multiple layers of signal layers along the direction of the first drilling angle offset from the normal, thereby forming an electrical connection between at least two layers of signal layers. In an adjacent row where the first differential via structure is set, according to the interconnection design requirements between the signal layers corresponding to the second differential via structure, the second differential via structure is drilled between the corresponding multiple layers of signal layers along the direction of the second drilling angle offset from the normal and different from the first drilling angle. , so that an electrical connection is formed between at least two signal layers, and in a multi-layer circuit board, differential via structures located in different rows are drilled in the multi-layer signal layer at different drilling angles, so that the two adjacent differential via structures are in the form of non-planar intersection, rather than a parallel structure setting, shortening the coupling length between two or more differential via structures with a predetermined interval, so that the coupling length between the two differential via structures is limited to the partial area of ​​non-planar intersection, and the distance between the two ends of the multiple differential via structures is increased, thereby reducing the far-end crosstalk of the differential via structure. At the same time, since the two differential via structures are in non-planar intersection, the crosstalk between the two intersecting vias is offset, further reducing the impact of crosstalk, and improving the transmission integrity and accuracy of high-speed signals and the reliability of the multi-layer circuit board.

[0039] According to the embodiments of the present application, by slanting the differential via structures drilled in the multi-layer circuit board, there is no need to introduce redundant isolation ground holes and other wiring designs to reduce crosstalk between multiple differential via structures, thereby saving the layout design space of the pins and via structures of the multi-layer circuit board. As a result, more differential via structures can be arranged within a limited multi-layer circuit board or the design size of the multi-layer circuit board can be reduced with a certain number of differential via structures, thereby reducing costs and cycles.

[0040] Figure 1 A schematic diagram of a multi-layer circuit board according to an embodiment of the present application is shown.

[0041] like Figure 1 As shown, the multi-layer circuit board may include multiple layers of signal layers 103, the first differential via structure 101 may be drilled in the multiple layers of signal layers 103 at a first drilling angle a to electrically connect the multiple layers of signal layers 103, the second differential via structure 102 may be drilled in part of the signal layer 103 at a second drilling angle b to electrically connect part of the signal layer 103, and the first differential via structure 101 and the second differential via structure 102 are arranged to intersect.

[0042] According to an embodiment of the present application, the first drilling angle and the second drilling angle are offset toward opposite sides relative to the normal direction of the multi-layer signal layer.

[0043] For example, the first drilling angle is offset 15° to the right relative to the normal of the multi-layer signal layer, and the second drilling angle is offset 35° to the left relative to the normal of the multi-layer signal layer, so that the first differential via structure drilled according to the first drilling angle and the second differential via structure drilled according to the second drilling angle are drilled in opposite directions to each other, so that the first differential via structure and the second differential via structure form a non-planar intersection or an extended line non-planar intersection.

[0044] According to an embodiment of the present application, by setting the first drilling angle and the second drilling angle to be offset toward opposite sides relative to the normal direction of the multilayer circuit board, it is achieved that at least one first orthogonal differential via structure and at least one second orthogonal differential via structure located on different rows of the multilayer circuit board can be drilled in the multilayer signal layer in the form of eccentric intersections at different angles and in opposite directions. By forming an eccentric intersection between the first differential via structure and the second differential via structure, the coupling length between the two differential via structures is shortened, and the crosstalk in the intersection area of ​​the two differential via structures is offset. At the same time, for the non-intersecting area of ​​the two differential via structures, the far-end crosstalk between the two differential via structures can be reduced by moving the two differential via structures away from each other.

[0045] According to an embodiment of the present application, at least one first differential via structure is offset by a first drilling angle toward a first side in a first lateral direction relative to a normal direction of the multilayer circuit board, and at least one second differential via structure is offset by a second drilling angle toward a second side opposite to the first side in the first lateral direction relative to the normal direction of the multilayer circuit board. At least one first differential via structure and at least one second differential via structure have a predetermined spacing distance in a second lateral direction intersecting the first lateral direction.

[0046] A three-dimensional spatial coordinate system is established with the multi-layer circuit board as the center, the z-axis is confirmed as the normal direction, the x-axis is confirmed as the first lateral direction, and the y-axis is confirmed as the second lateral direction. By using the normal direction, the first lateral direction, and the second lateral direction of the multi-layer circuit board as reference directions for drilling and pin layout of different differential drilling structures, the differential drilling structure of each row and column is designed and laid out.

[0047] At least one first differential via structure and at least one second differential via structure are located on different rows and columns of the multilayer circuit board. Adjacent first differential via structures and second differential via structures can have a predetermined spacing distance in the first horizontal direction and the second horizontal direction. Therefore, in combination with the first differential via structure drilled at a first drilling angle and the second differential via structure drilled at a second drilling angle in the opposite direction to the first drilling angle, the first differential via structure and the second differential via structure can present an effect of non-planar intersection, and the distance between the non-planar intersections can be a predetermined spacing distance.

[0048] According to an embodiment of the present application, by disposing at least one first differential via structure and at least one second differential via structure in adjacent rows and columns with a predetermined spacing distance on a multilayer circuit board, a predetermined spacing distance can be established between the first differential via structure and the second differential via structure, thereby preventing the two differential via structures from being too close together, which would increase the coupling length and cause significant via crosstalk. While maintaining the predetermined spacing distance between adjacent first differential via structures and second differential via structures, combined with the design of drilling in opposite directions at the first drilling angle and the second drilling angle, the ends of the two adjacent differential via structures are kept as far apart as possible from each other, thereby reducing far-end crosstalk of the differential via structures. Furthermore, by locally intersecting the two adjacent differential via structures at different planes, the area prone to crosstalk can be controlled at the intersection, thereby reducing the coupling length between the two structures, further reducing the impact of crosstalk, and improving the transmission integrity and accuracy of high-speed signals and the reliability of the multilayer circuit board.

[0049] According to an embodiment of the present application, at least one first differential via structure and at least one second differential via structure may each include a first differential via unit and a second differential via unit.

[0050] According to an embodiment of the present application, a first differential via unit is drilled in a multi-layer circuit board along a first drilling angle or a second drilling angle to transmit a positive phase differential signal.

[0051] According to an embodiment of the present application, the second differential via unit is arranged in parallel with the first differential via unit in the multi-layer circuit board to transmit an inverted differential signal.

[0052] Each of the first differential via structure and the second differential via structure may include two differential via units, and the transmission of a dual-phase differential signal can be achieved through the two differential via units.

[0053] Figure 2 A top view of multiple differential via structures according to an embodiment of the present application is shown.

[0054] like Figure 2 As shown in the figure, there may be four differential via structures, and the multiple differential via structures may include two first differential via structures 101 located in the same row and two second differential via structures 102 located in adjacent rows, and each differential via structure includes a first differential via unit 203 and a second differential via unit 204.

[0055] Figure 3 A schematic diagram showing a cross section of multiple differential via structures according to an embodiment of the present application is shown.

[0056] like Figure 3 As shown, multiple differential via structures may include a first differential via structure 101 and a second differential via structure 102 located in two adjacent rows. The first differential via structure 101 and the second differential via structure 102 may be arranged orthogonally, thereby offsetting the crosstalk between the differential via structures. Each differential via structure is drilled in a multi-layer signal layer 103, thereby electrically connecting the multi-layer signal layer 103, and a planar layer 301 is provided above and below each signal layer 103.

[0057] According to an embodiment of the present application, the multilayer circuit board may further include at least one third differential via structure and at least one fourth differential via structure.

[0058] According to an embodiment of the present application, at least one third differential via structure is arranged in a first lateral direction with at least one first differential via structure, and at least one third differential via structure is offset toward the first side in the first lateral direction, and is drilled in the multi-layer circuit board along a direction of a third drilling angle offset relative to the normal of the multi-layer circuit board, so that at least two signal layers in the multi-layer signal layer are electrically connected to each other, wherein the first drilling angle and the third drilling angle are different.

[0059] In the same row of the first differential via structure, there may also be at least one third differential via structure drilled in the multilayer circuit board that is not parallel to the first differential via structure, that is, the first drilling angle of the first differential via structure and the third drilling angle of the third differential via structure are different, and the third differential via structure is still offset in the first lateral direction to the first side consistent with the first differential via structure, but the third differential via structure can be drilled in the direction of the third drilling angle offset relative to the normal, so that part of the signal layer is electrically connected.

[0060] According to an embodiment of the present application, at least one fourth differential via structure is arranged in a first lateral direction with at least one second differential via structure, and at least one fourth differential via structure is offset toward the second side in the first lateral direction, and is drilled in the multi-layer circuit board along a direction of a fourth drilling angle offset relative to the normal of the multi-layer circuit board, so that at least two signal layers in the multi-layer signal layer are electrically connected to each other, wherein the second drilling angle and the fourth drilling angle are different.

[0061] In the same row of the second differential via structure, there may also be at least one fourth differential via structure drilled in the multilayer circuit board that is not parallel to the second differential via structure, that is, the second drilling angle of the second differential via structure and the fourth drilling angle of the fourth differential via structure are different, and the fourth differential via structure is still offset to the second side consistent with the second differential via structure in the first lateral direction, but the fourth differential via structure can be drilled in the direction of the fourth drilling angle offset relative to the normal, so that part of the signal layer is electrically connected.

[0062] The first side and the second side in the first transverse direction can generally be characterized as the left and right sides of the multilayer circuit board in the x-axis direction. Each of the third differential via structure and the fourth differential via structure can also include two differential via units, thereby enabling the transmission of a dual-phase differential signal through the two differential via units.

[0063] The drilling angles of different differential via structures can be adjusted in design based on the loss and crosstalk calculations of the multi-layer circuit board.

[0064] According to the embodiments of the present application, based on the design requirements for crosstalk between the via structures of a multi-layer circuit board and the design requirements such as the number and wiring of the differential via structures in the multi-layer circuit board, a first differential via structure and a third differential via structure, or a second differential via structure and a fourth differential via structure with different drilling angles can be set in the same row of the multi-layer circuit board. In this way, more and more complex differential via structures can be flexibly arranged in a multi-layer circuit board with limited space while reducing the impact of crosstalk, so as to meet the current high demand for circuit boards and improve the reliability of the multi-layer circuit board and the differential via structure.

[0065] Figure 4 FIG. 4 is a schematic diagram showing a cross section of multiple differential via structures according to another embodiment of the present application.

[0066] like Figure 4 As shown, the multiple differential via structures may include two first differential via structures 101 located in the same row and in parallel and two second differential via structures 102 located in another row and in parallel, each differential via structure is drilled in the multi-layer signal layer 103, thereby electrically connecting the multi-layer signal layer 103, wherein the first drilling angle of the two first differential via structures 101 located in the same row and in parallel may be a°, and the second drilling angle of the two second differential via structures 102 located in the same row and in parallel may be b°.

[0067] Figure 5 A schematic diagram showing a cross section of multiple differential via structures according to yet another embodiment of the present application is shown.

[0068] like Figure 5 As shown, the multiple differential via structures may include a first differential via structure 101 and a third differential via structure 501 located in the same row and not parallel, and a second differential via structure 102 and a fourth differential via structure 502 located in another row and not parallel, each differential via structure is drilled in the multi-layer signal layer 103, thereby electrically connecting the multi-layer signal layer 103, wherein the first drilling angle of the first differential via structure 101 may be a°, the second drilling angle of the second differential via structure 102 may be b°, the third drilling angle of the third differential via structure 501 may be c°, and the fourth drilling angle of the fourth differential via structure 502 may be d°.

[0069] According to an embodiment of the present application, for the differential via structure, the first drilling angle and the second drilling angle may be complementary angles to each other, so that at least one first differential via structure and at least one second differential via structure are orthogonally arranged.

[0070] The third drilling angle and the fourth drilling angle may also be complementary angles to each other, so that at least one third differential via structure and at least one fourth differential via structure are orthogonally arranged.

[0071] When the first drilling angle, the second drilling angle, the third drilling angle and the fourth drilling angle are 45°, the angle of intersection formed by the first differential via structure and the second differential via structure or the third differential via structure and the fourth differential via structure can be 90°.

[0072] According to an embodiment of the present application, when the first drilling angle and the second drilling angle can be complementary angles to each other, the first differential via structure and the second differential via structure can be designed to be orthogonal, thereby producing a better offsetting effect on the crosstalk between the differential via structures, thereby improving the quality and integrity of the transmitted signal.

[0073] According to an embodiment of the present application, multiple first via routings are respectively led out from at least one first differential via structure and / or at least one third differential via structure along the first lateral direction. When at least one first differential via structure and / or at least one third differential via structure are arranged in multiple in the first lateral direction, the multiple first via routings are respectively arranged in multiple signal layers.

[0074] A first via trace can be characterized as a trace connected to a first differential via structure and / or a third differential via structure located in the same row. When the same row contains at least one first differential via structure and at least one third differential via structure, or contains multiple first differential via structures, or contains multiple third differential via structures, and the traces need to be routed from the first lateral direction toward the first side, the traces of the differential via structures in the same row (first via traces) need to be arranged in different signal layers, so as to be routed out or electrically connected to hardware structures such as other signal layers.

[0075] When the trace of the first differential via structure in the same row needs to be routed from the first lateral direction toward the first side, and the trace of the third differential via structure needs to be routed from the first lateral direction toward the second side, the two first via traces of the first differential via structure and the third differential via structure can be routed in the same signal layer. That is, when multiple differential via structures in the same row are routed in the same lateral direction, the multiple first via traces need to be routed in multiple signal layers.

[0076] According to an embodiment of the present application, multiple second via routings are respectively led out from multiple second differential via structures and / or at least one fourth differential via structure along the first lateral direction. When multiple second differential via structures and / or at least one fourth differential via structure are arranged in multiple in the first lateral direction, multiple second via routings are respectively arranged in multiple signal layers.

[0077] The second via trace can be characterized as a trace connected to the second differential via structure and / or the fourth differential via structure located in the same row. When the same row contains at least one second differential via structure and at least one fourth differential via structure, or contains multiple second differential via structures, or contains multiple fourth differential via structures, and when the trace needs to be led out from the first lateral direction toward the first side, the traces of the differential via structures in the same row (the second via traces) need to be arranged in different signal layers, so as to be led out or electrically connected to hardware structures such as other signal layers.

[0078] When the second differential via structure in the same row needs to be routed from the first lateral direction toward the first side, and the fourth differential via structure needs to be routed from the first lateral direction toward the second side, the two second via traces of the second and fourth differential via structures can be routed in the same signal layer. That is, when multiple differential via structures in the same row are routed in the same lateral direction, the multiple second via traces need to be routed in multiple signal layers.

[0079] Figure 6 A schematic diagram of via routing of a differential via structure according to an embodiment of the present application is shown.

[0080] like Figure 6 As shown, the two first via traces 601 of the first differential via structure located in the same row may be located in different signal layers.

[0081] According to an embodiment of the present application, a first via route led out from at least one first differential via structure and / or one differential via structure in at least one third differential via structure and a second via route led out from at least one second differential via structure and / or one differential via structure in at least one fourth differential via structure can be arranged in the same signal layer in a multi-layer signal layer.

[0082] The first via traces of the first differential via structure and / or the third differential via structure in two adjacent rows, as well as the second via traces of the second differential via structure and / or the fourth differential via structure, can be arranged in the same signal layer. At the same time, the first via traces of the first differential via structure and / or the third differential via structure in two adjacent rows, as well as the second via traces of the second differential via structure and / or the fourth differential via structure, can also be arranged in different signal layers. Based on the wiring space in the multi-layer circuit board and the different route directions of the via traces, the number of via traces in the same signal layer can be flexibly configured.

[0083] The via routing of multiple differential via structures can be arranged based on the connection order between signal layers or in some functional concentrated areas on a multi-layer circuit board, thereby determining the appropriate outlet direction and signal layer for the layout. For example, in a multi-layer circuit board containing four signal layers, based on the signal layer connection requirements and functional zoning design, two differential via structures are required to electrically connect the first signal layer to the second signal layer, one to electrically connect the first signal layer to the third signal layer, two to electrically connect the second signal layer, the third signal layer, and the fourth signal layer, and one to electrically connect the first signal layer, the second signal layer, the third signal layer, and the fourth signal layer.

[0084] In view of the situation where two differential via structures electrically connect the first signal layer and the second signal layer, two parallel first differential via structures and second differential via structures electrically connecting the first signal layer and the second signal layer can be arranged in the first row and the second row of the circuit board respectively, so that the first differential via structure and the second differential via structure are orthogonal, thereby reducing the coupling length, and the first via traces and the second via traces of the first differential via structure and the second differential via structure both exit from the same side of the first signal layer.

[0085] The case where the two second signal layers, the third signal layer and the fourth signal layer are electrically connected is similar to the case where the first signal layer and the second signal layer are electrically connected with the two differential via structures.

[0086] For an electrical connection between a first signal layer and a third signal layer and an electrical connection between a first signal layer, a second signal layer, a third signal layer and a fourth signal layer, taking into account the layout space limitations of the multi-layer circuit board, a third differential via structure and a fourth differential via structure can be respectively arranged in the first row and the second row of the circuit board, so that the third differential via structure and the fourth differential via structure intersect at approximately 90°, thereby reducing the coupling length, and making the first via routing and the second via routing of the third differential via structure and the fourth differential via structure exit from the same side of the second signal layer and the fourth signal layer respectively.

[0087] Figure 7 A schematic diagram of via routing of a differential via structure according to another embodiment of the present application is shown.

[0088] like Figure 7 As shown, the first via trace 601 and the second via trace 701 of the two diametrically intersecting differential via structures located in different rows may be located in the same signal layer.

[0089] According to an embodiment of the present application, a first via routing is electrically connected to the first differential via structure and the third differential via structure, and a second via routing is electrically connected to the second differential via structure and the fourth differential via structure. When the via routing is arranged along the first lateral direction, multiple via routings of multiple differential via structures located in the same row need to be arranged separately in multiple signal layers, thereby avoiding routing interference between multiple routings, and multiple via routings of multiple differential via structures located in different rows can be located in the same signal layer, thereby saving wiring space of the multi-layer circuit board and improving space utilization of the multi-layer circuit board without affecting each other in routing signal transmission.

[0090] According to an embodiment of the present application, a multi-layer circuit board may further include multiple planar layers, and for differential via structures, multiple anti-pads may be provided around the outer sides of the multiple differential via structures.

[0091] According to an embodiment of the present application, multiple layers of plane layers and multiple layers of signal layers are alternately stacked.

[0092] A multi-layer circuit board can be composed of multiple signal layers and multiple plane layers that are alternately stacked. The multiple signal layers are used to transmit signals. The multiple plane layers also include multiple ground layers and multiple power layers. The ground layers and the power layers form a loop with each other.

[0093] According to an embodiment of the present application, multiple anti-pads are respectively arranged in the multi-layer planar layer, surrounding the periphery of at least one first differential via structure or at least one second differential via structure, electrically isolating at least one first differential via structure or at least one second differential via structure from the multi-layer planar layer.

[0094] The first differential via structure, the second differential via structure, the third differential via structure and the fourth differential via structure all have multiple anti-pads surrounding the structure. Each anti-pad can be arranged in the corresponding stratum according to design requirements such as electrical isolation, thereby electrically isolating the differential via structure from the stratum.

[0095] According to an embodiment of the present application, when a differential via structure surrounded by multiple anti-pads is obliquely drilled in a multilayer circuit board, the multilayer circuit board may further include the following routing method for routing along the second transverse direction.

[0096] According to an embodiment of the present application, a first trace may be arranged in a first signal layer among the multiple signal layers, and the first trace includes a portion extending along the second transverse direction.

[0097] The first trace can be characterized as a via trace connected to any differential via structure, and the via trace is arranged in a first signal layer having multiple differential via structures, and the trace direction can be the front-to-back direction of the multi-layer circuit board.

[0098] According to an embodiment of the present application, when the positive projection of the anti-pad of the first differential via structure or the second differential via structure is located on the second plane layer, the portion of the first trace extending along the second lateral direction is located outside the projection of the anti-pad in the first plane layer and the second plane layer adjacent to the first signal layer in the multi-layer plane layer in the normal direction of the second plane layer and away from the first differential via structure or the second differential via structure.

[0099] According to an embodiment of the present application, when the positive projection of the anti-pad of the first differential via structure or the second differential via structure is located on the first plane layer, the portion of the first trace extending along the second lateral direction is located outside the projection of the anti-pad in the first plane layer and the second plane layer adjacent to the first signal layer in the multi-layer plane layer in the normal direction of the first plane layer and away from the first differential via structure or the second differential via structure.

[0100] When via traces need to exit from the front and back (second lateral direction) of a multi-layer circuit board, they should be located as much as possible in the area between two ground layers. For example, taking the first signal layer as an example, with the z-axis as the reference direction, the plane layer (ground layer) above the first signal layer is considered the first plane layer, and the plane layer (ground layer) below the first signal layer is considered the second plane layer. Therefore, if the positive projection of the anti-pad of the differential via structure is located on the second plane layer, the differential via structure to be passed through can be used as a routing reference. The position of the anti-pad on the first plane layer can be used as the starting point, and a first normal projection on the second plane layer can be made. Based on the perpendicular line generated by the first projection, the traces arranged in the first signal layer are located on the other side of the perpendicular line generated by the first projection, away from the differential via structure. In the case where the positive projection of the anti-pad of the differential via structure is located on the first plane layer, the differential via structure that needs to be passed through can be used as a wiring reference. The position of the anti-pad located on the second plane layer can be used as the starting point, and a second normal projection located on the first plane layer can be made. Based on the vertical line generated by the second projection, the routing arranged in the first signal layer is located on the other side of the vertical line generated by the second projection away from the differential via structure.

[0101] According to the embodiments of the present application, for a multi-layer circuit board, the via routing of multiple differential via structures passing through the multi-layer circuit board can have an outlet layout in a first lateral direction and a second lateral direction. When the outlet layout of the via routing is performed in the first lateral direction, since the offset direction of the via routing at this time is completely consistent with or completely opposite to the drilling angle of the differential via structure, it is only necessary to consider whether the via routing between rows can be located in the same signal layer. When the via routing of multiple differential via structures is arranged along the second lateral direction, due to the influence of the anti-pads of the inclined differential via structure, it is necessary to make a comprehensive judgment based on the position of the anti-pads on the upper and lower plane layers of a certain signal layer, so that the routing is arranged as much as possible in the area facing the plane layer above and below, thereby reducing the impedance on the via routing and improving the quality of the transmitted signal.

[0102] Figure 8 A schematic diagram of via routing of a differential via structure according to yet another embodiment of the present application is shown.

[0103] like Figure 8 As shown, a plane layer is provided on the upper and lower sides of each signal layer, and the anti-pad 801 surrounds each differential via unit in each differential via structure. When the outlet direction of the first trace 802 is along the second lateral direction and the positive projection of the anti-pad 801 of the differential via structure is located on the second plane layer 805, the position of the anti-pad 801 located on the first plane layer 804 is used as the starting point, and a first normal projection is made on the second plane layer 805. Based on the vertical line 803 generated by the first projection, the first trace 802 arranged in the first signal layer 806 is located on the side away from the differential via structure, that is, on the right side of the vertical line 803.

[0104] According to an embodiment of the present application, an isolated ground hole may be further included in the multilayer circuit board.

[0105] According to an embodiment of the present application, an isolated ground via is drilled in the multilayer circuit board along a direction offset by a fifth drilling angle relative to the normal direction of the multilayer circuit board to electrically connect the multiple layers.

[0106] Isolation ground holes can be used to isolate adjacent differential via structures, further reducing crosstalk between them. For an isolation ground hole between two adjacent differential via structures in the same row, a fifth drilling angle is derived based on the drilling angles of the two adjacent differential via structures. This allows the isolation ground hole to be drilled into the multilayer PCB in the same offset direction as the differential via structure in that row, isolating the two adjacent differential via structures.

[0107] Furthermore, since the first differential via structure, the second differential via structure, the third differential via structure and the fourth differential via structure of the present application can all be drilled at an inclined angle in the multi-layer circuit board, the differential via structures in two adjacent rows with a predetermined spacing distance are arranged to intersect with each other in different planes, thereby reducing the coupling length between the differential via structures. As a result, there is no need to evenly arrange multiple isolation ground holes between two adjacent differential via structures in the same row or between areas in different rows but facing each other. Only one isolation ground hole can be arranged on each side of each differential via structure, thereby reducing the crosstalk of the differential via structure while precisely arranging the isolation ground holes, further reducing interference caused by factors such as crosstalk, saving the pin design space of the vias on the multi-layer circuit board, reducing the design size, and reducing the design cost and cycle.

[0108] For servers, the design of multi-layer circuit boards for high-speed and low-speed signals can refer to the above structure.

[0109] Figure 9 A schematic diagram showing the pin distribution of a multi-layer circuit board containing isolated ground holes according to an embodiment of the present application is shown.

[0110] like Figure 9 As shown, on the top layer of the multi-layer circuit board, there are multiple pins 901 of the first differential via structure, multiple pins 902 of the second differential via structure and multiple pins 903 of the isolation ground hole. The first differential via structure is offset to the first side of the first lateral direction, and the second differential via structure is offset to the second side of the first lateral direction. An isolation ground hole is provided on both sides of each differential via structure.

[0111] Figure 10 A schematic diagram showing an application scenario of a multi-layer circuit board according to an embodiment of the present application is shown.

[0112] like Figure 10As shown, the multi-layer circuit board of the present application can be applied to a 64-card intelligent computing all-in-one machine, which can support 8 8-card computing nodes and 6 51.2T switching nodes (SW, Switching Node). The 64 GPUs and the switching nodes have a non-blocking fully interconnected architecture, and a single switching node is 51.2T, including 8 computing nodes (Compute Chassis). The 6 switching nodes adopt a board-to-board orthogonal full connection method. Each switching node is interconnected with 64 open computing projects (OAM, OpenAccelerator Module) OAM to form a 6-track switching plane. The interconnection bandwidth between each open computing project and a single switching node is 800G. In the design of the switching node board, a switching chip can lead out 16 X16 112G signals. In the line-out area of ​​the ball grid array (BGA, Ball Grid Array), the crosstalk between the vias is very large, so the multi-layer circuit board of the present application can be set in the line-out area of ​​the ball grid array to offset the crosstalk through the inclined differential via structure.

[0113] Figure 11 A flow chart of a via structure optimization method according to an embodiment of the present application is shown.

[0114] like Figure 11 As shown, the via structure optimization method of this embodiment includes operations S1110 to S1130.

[0115] In operation S1110 , initial via structure parameters are determined for at least one first differential via structure and at least one second differential via structure.

[0116] If a third differential via structure and a fourth differential via structure are preset to exist in the multilayer circuit board, the initial via structure parameters may further include relevant structural parameters of the third differential via structure and the fourth differential via structure.

[0117] In operation S1120 , based on the initial via structure parameters, an electrical response of the multilayer circuit board under a test electrical signal is simulated to obtain a simulated response of the multilayer circuit board.

[0118] By performing electrical simulation on the established model of a multi-layer circuit board containing a differential via structure with tilted drilling, various losses and working conditions under actual conditions are simulated to facilitate adjustment of the initial via structure parameters.

[0119] In operation S1130, the initial via structure parameters are adjusted based on the simulation response, and simulation is performed based on the adjusted via structure parameters until the simulation response meets the performance requirements of the multi-layer circuit board, thereby obtaining target via structure parameters.

[0120] According to an embodiment of the present application, before producing a corresponding multi-layer circuit board, a simulation differential via structure model can be established to simulate parameters such as the drilling angle of the first differential via structure, the first differential via structure, the first differential via structure, and the first differential via structure, the predetermined spacing between rows and columns, the intersection angle between adjacent differential via structures, and the drilling angle of the isolation ground hole. By continuously adjusting the via structure parameters, the layout of the differential via structure and its via routing can achieve the best overall effect. In addition, by reducing the far-end crosstalk of the differential via structure, the crosstalk between each two intersecting vias can be adaptively offset by arbitrarily intersecting each other, thereby reducing the impact of crosstalk and improving the transmission integrity and accuracy of high-speed signals, especially the reliability of the multi-layer circuit board. Furthermore, by simulating the via structure parameters, the structural parameters can be flexibly adjusted according to different electrical design requirements, so that production personnel can generate the corresponding multi-layer circuit board based on the determined structural parameter information.

[0121] According to an embodiment of the present application, the initial via structure parameters may include the position, size, spacing distance, first drilling angle and second drilling angle of at least one first differential via structure and at least one second differential via structure, and the simulation includes: simulating via element interference, signal loss or far-end crosstalk of a multi-layer circuit board when transmitting high-speed signals.

[0122] The initial via structure parameters may further include the position, size, spacing distance, third drilling angle, and fourth drilling angle of at least one third differential via structure and at least one fourth differential via structure.

[0123] According to an embodiment of the present application, based on initial via structure parameters, the electrical response of the multilayer circuit board under a test electrical signal is simulated to obtain the simulated response of the multilayer circuit board, which includes the following operations.

[0124] According to an embodiment of the present application, a via component interference simulation is performed on a multi-layer circuit board to simulate the signal state of the multi-layer circuit board during the process of transmitting high-speed signals.

[0125] According to an embodiment of the present application, the capacitive impedance of the test via and the inductive impedance of the test via are calculated based on the initial via structural parameters, board structural parameters, and electrical parameters during the simulation of the multi-layer circuit board.

[0126] Via component interference includes via capacitance interference and via inductance interference. Via capacitance interference and via inductance interference can be calculated according to formula (1) and formula (2) respectively.

[0127] (1);

[0128] Among them, Cvia can be characterized as via capacitance interference. It can be represented as the relative dielectric constant, D1 can be represented as the pad diameter of the differential via structure, T can be represented as the thickness of the multi-layer circuit board, D2 can be represented as the anti-pad diameter, and pF can be represented as the unit of capacitance.

[0129] (2);

[0130] Among them, Lvia can be represented as via inductance interference, ln() can be represented as logarithmic calculation, h can be represented as the length of the differential via structure, d can be represented as the hole diameter of the differential via structure, and nH can be represented as the inductance unit.

[0131] According to the calculated via capacitance interference, via inductance interference and signal frequency, the test via capacitive impedance and the test via inductive impedance are calculated respectively.

[0132] According to an embodiment of the present application, when the inductive impedance of the test via is greater than or equal to the capacitive impedance of the test via, the initial via structure parameters of the multilayer circuit board are adjusted until the inductive impedance of the test via is less than the capacitive impedance of the test via, and the via component interference simulation test results are obtained.

[0133] In high-speed digital circuit design, the parasitic series inductance of the differential via structure weakens the bypass capacitor and the filtering effect of the entire system. Therefore, the harm caused by the parasitic inductance of the differential via structure is often greater than the impact of the parasitic capacitance. Therefore, if the inductive impedance of the test via is greater than or equal to the capacitive impedance of the test via, the initial via structure parameters need to be adjusted until the inductive impedance of the test via is less than the capacitive impedance of the test via.

[0134] When the inductive impedance of the test via is less than the capacitive impedance of the test via, the via structural parameters can be further adjusted according to a predetermined inductive impedance threshold and a predetermined capacitive impedance threshold to obtain target structural parameters.

[0135] According to an embodiment of the present application, based on the initial via structure parameters, the electrical response of the multilayer circuit board under the test electrical signal is simulated to obtain the simulated response of the multilayer circuit board, and the method further includes the following operations.

[0136] According to an embodiment of the present application, far-end crosstalk is simulated on a multi-layer circuit board, and test mutual inductance and test mutual capacitance are calculated based on initial via structure parameters, board structure parameters, and electrical parameters during the simulation of the multi-layer circuit board.

[0137] The test mutual capacitance for any differential via structure can be calculated based on the vacuum dielectric constant, relative dielectric constant, length of the differential via structure, hole radius of the differential via structure, and the hole spacing between the two differential via structures. The test mutual inductance for any differential via structure can be calculated based on the vacuum magnetic permeability, relative magnetic permeability, length of the differential via structure, and the hole spacing between the two differential via structures.

[0138] According to the embodiment of the present application, a crosstalk simulation test result is obtained based on the test mutual inductance and the test mutual capacitance.

[0139] According to the calculated test mutual inductance, test mutual capacitance of each differential via structure and the voltage, current and time during the simulation signal transmission, the time domain crosstalk simulation test results and the frequency domain crosstalk simulation test results are obtained.

[0140] At the same time, it is also necessary to simulate and calculate the via loss of the multi-layer circuit board to obtain the loss test results under the structure. Based on the loss test results and the predetermined loss threshold, when the loss test results are greater than or equal to the predetermined loss threshold, the initial via structure parameters are modulated until the loss test results are less than the predetermined loss threshold.

[0141] According to an embodiment of the present application, by simulating via component interference, signal loss or far-end crosstalk on a multi-layer circuit board, the structural parameters are repeatedly adjusted according to the results of multiple simulations to obtain differential via structural parameters with good anti-crosstalk effect.

[0142] Figure 12 A schematic diagram showing comparison of frequency domain crosstalk according to an embodiment of the present application is shown.

[0143] like Figure 12 As shown, the horizontal axis can be represented as frequency, and the vertical axis can be represented as crosstalk value. It can be seen from the figure that under the same simulation environment, the first frequency domain crosstalk test result 1201 obtained after simulating the multi-layer circuit board model of the present application containing the inclined first differential via structure, the second differential via structure, the third differential via structure and the fourth differential via structure is lower than the second frequency domain crosstalk test result 1202 obtained after simulating the prior art. At the same time, the first loss test result 1203 obtained after simulating the multi-layer circuit board model of the present application is also lower than the second loss test result 1204 obtained after simulating the prior art.

[0144] Figure 13 A schematic diagram showing a comparison of time domain crosstalk according to an embodiment of the present application is shown.

[0145] like Figure 13As shown, the horizontal axis can be represented by the signal transmission time, and the vertical axis can be represented by the crosstalk voltage amplitude. It can be seen from the figure that under the same simulation environment, the first time domain crosstalk test result 1301 obtained after simulating the multi-layer circuit board model of the present application including the inclined first differential via structure, the second differential via structure, the third differential via structure and the fourth differential via structure and the second time domain crosstalk test result 1302 obtained after simulating the prior art both maintained a crosstalk voltage amplitude of 0 for a period of time at the beginning, and then, as time went on, time domain crosstalk began to appear. During the stage of time domain crosstalk, the first time domain crosstalk test result 1301 obtained after simulating the multi-layer circuit board model of the present application including the inclined first differential via structure, the second differential via structure, the third differential via structure and the fourth differential via structure was lower than the crosstalk voltage amplitude of the second time domain crosstalk test result 1302 obtained after simulating the prior art, which can be explained that the crosstalk between the differential via structures in the multi-layer circuit board of the present application is lower.

[0146] According to an embodiment of the present application, the program code for executing the computer program provided by the embodiment of the present application can be written in any combination of one or more programming languages. Specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0147] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of the boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0148] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0149] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A multi-layer circuit board, characterized in that: The multi-layer circuit board comprises: at least one first differential via structure drilled in the multilayer circuit board in a direction offset by a first drilling angle relative to a normal direction of the multilayer circuit board, so as to electrically connect at least two signal layers among the multiple signal layers in the multilayer circuit board; and at least one second differential via structure drilled in the multilayer circuit board along a direction offset by a second drilling angle relative to a normal direction of the multilayer circuit board, so as to electrically connect the at least two signal layers in the multilayer circuit board to each other; Wherein, the first drilling angle and the second drilling angle are both acute angles, and the at least one first differential via structure and the at least one second differential via structure are arranged to intersect each other in different planes; The multilayer circuit board includes multiple layers of plane layers and multiple anti-pads, and a first routing line is arranged in the first signal layer among the multiple layers of signal layers, and the first routing line includes a portion extending along the second lateral direction; when the positive projection of the anti-pad of the first differential via structure or the second differential via structure is located on the second plane layer, the portion of the first routing line extending along the second lateral direction is located outside the projection of the anti-pad in the first plane layer and the second plane layer adjacent to the first signal layer in the multiple layers of plane layers in the normal direction of the second plane layer and away from the area of ​​the first differential via structure or the second differential via structure; and / or, when the positive projection of the anti-pad of the first differential via structure or the second differential via structure is located on the first plane layer, the portion of the first routing line extending along the second lateral direction is located outside the projection of the anti-pad in the first plane layer and the second plane layer adjacent to the first signal layer in the multiple layers of plane layers in the normal direction of the first plane layer and away from the area of ​​the first differential via structure or the second differential via structure.

2. The multilayer circuit board according to claim 1, wherein: The first drilling angle and the second drilling angle are offset toward opposite sides relative to a normal direction of the multilayer circuit board.

3. The multi-layer circuit board according to claim 2, wherein: The at least one first differential via structure is offset by the first drilling angle toward the first side in the first lateral direction relative to the normal of the multilayer circuit board, and the at least one second differential via structure is offset by the second drilling angle toward the second side opposite to the first side in the first lateral direction relative to the normal of the multilayer circuit board. The at least one first differential via structure and the at least one second differential via structure have a predetermined spacing distance in the second lateral direction intersecting the first lateral direction.

4. The multi-layer circuit board according to claim 3, wherein: The multi-layer circuit board further comprises: at least one third differential via structure, arranged with the at least one first differential via structure in the first lateral direction, the at least one third differential via structure being offset toward the first side in the first lateral direction and drilled in the multilayer circuit board in a direction offset by a third drilling angle relative to a normal direction of the multilayer circuit board, so as to electrically connect the at least two signal layers in the multilayer signal layers to each other, wherein the first drilling angle and the third drilling angle are different; and / or At least one fourth differential via structure is arranged in the first lateral direction with the at least one second differential via structure, and the at least one fourth differential via structure is offset toward the second side in the first lateral direction and drilled in the multilayer circuit board along a direction offset by a fourth drilling angle relative to the normal of the multilayer circuit board, so that the at least two signal layers in the multilayer signal layer are electrically connected to each other, wherein the second drilling angle and the fourth drilling angle are different.

5. The multi-layer circuit board according to claim 4, wherein: The multi-layer circuit board further comprises: a plurality of first via traces, respectively extending from the at least one first differential via structure and / or the at least one third differential via structure along the first transverse direction; when the at least one first differential via structure and / or the at least one third differential via structure are arranged in plurality in the first transverse direction, the plurality of first via traces are respectively arranged in the multi-layer signal layer; A plurality of second via routings are respectively led out from the at least one second differential via structure and / or the at least one fourth differential via structure along the first lateral direction. When the at least one second differential via structure and / or the at least one fourth differential via structure are arranged in plurality in the first lateral direction, the plurality of second via routings are respectively arranged in the multi-layer signal layer.

6. The multi-layer circuit board according to claim 5, wherein: The first via routing led out from the at least one first differential via structure and / or one differential via structure among the at least one third differential via structure and the second via routing led out from the at least one second differential via structure and / or one differential via structure among the at least one fourth differential via structure are arranged in the same signal layer among the multi-layer signal layers.

7. The multi-layer circuit board according to claim 3, wherein: The multi-layer circuit board further comprises: The multi-layer planar layers and the multi-layer signal layers are alternately stacked; The multiple anti-pads are respectively arranged in the multi-layer planar layer, surrounding the periphery of the at least one first differential via structure or the at least one second differential via structure, electrically isolating the at least one first differential via structure or the at least one second differential via structure from the multi-layer planar layer.

8. The multi-layer circuit board according to claim 1, wherein: The at least one first differential via structure and the at least one second differential via structure each include: a first differential via unit drilled in the multilayer circuit board along the first drilling angle or the second drilling angle to transmit a positive phase differential signal; The second differential via unit is arranged in parallel with the first differential via unit in the multi-layer circuit board to transmit an inverted differential signal.

9. The multi-layer circuit board according to claim 1, wherein: The multi-layer circuit board further comprises: multiple ground layers, alternately stacked with the multiple signal layers; and An isolation ground hole is drilled in the multilayer circuit board along a direction offset by a fifth drilling angle relative to a normal direction of the multilayer circuit board, so as to electrically connect the multilayer ground layers.

10. The multi-layer circuit board according to claim 1, wherein: The first drilling angle and the second drilling angle are complementary angles to each other, so that the at least one first differential via structure and the at least one second differential via structure are orthogonally arranged.

11. A method for optimizing the via structure of a multi-layer circuit board according to any one of claims 1 to 10, characterized in that: The via structure optimization method comprises: determining initial via structure parameters for at least one first differential via structure and at least one second differential via structure; Based on the initial via structure parameters, simulating the electrical response of the multilayer circuit board under the test electrical signal to obtain a simulated response of the multilayer circuit board; Based on the simulation response, the initial via structure parameters are adjusted, and simulation is performed based on the adjusted via structure parameters until the simulation response meets the performance requirements of the multi-layer circuit board, thereby obtaining target via structure parameters.

12. The via structure optimization method according to claim 11, characterized in that: The initial via structure parameters include the position, size, spacing distance, first drilling angle and second drilling angle of the at least one first differential via structure and the at least one second differential via structure, and the simulation includes: simulating via element interference, signal loss or far-end crosstalk of the multilayer circuit board when transmitting high-speed signals.

13. The via structure optimization method according to claim 11, characterized in that: The step of simulating the electrical response of the multilayer circuit board under a test electrical signal based on the initial via structure parameters to obtain a simulated response of the multilayer circuit board includes: Performing a via component interference simulation on the multi-layer circuit board to simulate a signal state of the multi-layer circuit board during high-speed signal transmission; Calculating the test via capacitive impedance and the test via inductive impedance according to the initial via structural parameters, board structural parameters, and electrical parameters during the simulation of the multilayer circuit board; When the inductive impedance of the test via is greater than or equal to the capacitive impedance of the test via, the initial via structure parameters of the multilayer circuit board are adjusted until the inductive impedance of the test via is less than the capacitive impedance of the test via, thereby obtaining the via component interference simulation test result.

14. The via structure optimization method according to claim 11, characterized in that: The step of simulating the electrical response of the multilayer circuit board under the test electrical signal based on the initial via structure parameters to obtain the simulated response of the multilayer circuit board further includes: Performing a far-end crosstalk simulation on the multi-layer circuit board, and calculating a test mutual inductance and a test mutual capacitance based on the initial via structure parameters, board structure parameters, and electrical parameters during the simulation of the multi-layer circuit board; The crosstalk simulation test result is obtained according to the test mutual inductance and the test mutual capacitance.

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