Transparent display device

Abstract

A transparent display device is disclosed. The transparent display device includes: a substrate including a display area provided with a transmissive area and a non-transmissive area, the non-transmissive area including a light emitting area provided with a light emitting element, and a non-display area provided at a periphery of the display area; at least one power line disposed on the substrate in the non-transmissive area of the display area and configured to extend in a first direction; a power shorting bar disposed in the non-display area on the substrate, electrically connected to the at least one power line, and extending in a second direction laterally intersecting the first direction; and at least one lower tangent line disposed in the display area and the non-display area on the substrate and extending in the first direction.

Description

Technical Field

[0001] The present disclosure relates to a transparent display device, and more particularly, for example but not limited to, to a transparent display device capable of reducing the occurrence of defects caused by moisture penetration. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images in various forms is increasing. Therefore, display devices such as liquid crystal display (LCD) devices, organic light emitting display (OLED) devices, micro light emitting diode (LED) devices, and quantum dot display (QD) devices are used.

[0003] Recently, research is actively underway on a transparent display device that not only displays an image to a user but also transmits light through the device, allowing the user to see objects or images behind the display device. The transparent display device includes a display area for displaying an image and a non-display area, wherein the display area may include a transmissive area that transmits external light and a non-transmissive area. The transmissive area can provide high light transmittance in the display area. The transparent display device can include multiple touch sensors and multiple touch lines to implement touch functionality.

[0004] Since images and backgrounds can be displayed simultaneously, transparent display devices have great application prospects in various fields. However, due to the diverse application fields and uses of transparent display devices, it is necessary to manufacture transparent display devices of various types (or sizes). However, when transparent display devices are manufactured in various types (or sizes), the number of processes increases, which increases the manufacturing cost and production energy.

[0005] The description provided in the description of the background technology section should not be assumed to be prior art simply because it is mentioned in the description of the background technology section or is associated with the description of the background technology section. The description of the background technology section may include information describing one or more aspects of the subject technology, and the description in this section does not limit the present invention. Summary of the Invention

[0006] The inventors have recognized that, in the background art, when transparent display devices are manufactured in various types (or various sizes), the manufacturing cost and production energy increase due to the increase in the number of processes, and the performance of the transparent display device decreases due to moisture penetration, etc. Therefore, one aspect of the present disclosure is to provide a transparent display device capable of reducing the occurrence of defects caused by moisture penetration.

[0007] Another aspect of the present disclosure is to provide a transparent display device capable of preventing deterioration of process reliability by forming a moisture penetration preventing structure.

[0008] Another aspect of the present disclosure is to provide a transparent display device that can be manufactured in various types (or various sizes).

[0009] The objects of the present disclosure are not limited to the above objects, but other objects not described herein will be clearly understood by those skilled in the art from the following description.

[0010] According to an exemplary embodiment of the present disclosure, a transparent display device may include: a substrate including a display area and a non-display area, wherein the display area is provided with a transmission area and a non-transmission area, the non-transmission area includes a light-emitting area provided with a light-emitting element, and the non-display area is provided on the periphery of the display area; at least one power line, which is provided in the non-transmission area of ​​the display area on the substrate and is configured to extend in a first direction; a power short-circuit bar, which is provided in the non-display area on the substrate, is electrically connected to the at least one power line, and extends in a second direction transversely intersecting the first direction; and at least one lower tangent line, which is provided in the display area and the non-display area on the substrate and extends in the first direction.

[0011] According to exemplary embodiments of the present disclosure, a transparent display device capable of reducing the occurrence of defects caused by moisture penetration may be provided.

[0012] According to the exemplary embodiments of the present disclosure, a transparent display device capable of preventing deterioration of process reliability by forming a moisture permeation preventing structure may be provided.

[0013] According to exemplary embodiments of the present disclosure, transparent display apparatuses manufactured in various types (or various sizes) may be provided.

[0014] The transparent display device according to one or more exemplary embodiments of the present disclosure can reduce the manufacturing process of producing various types of transparent display devices by cutting a large-size transparent display panel into various types (or various sizes) using a cutting process, thereby potentially reducing the generation of greenhouse gases that may be generated due to the manufacturing process, thereby achieving environmental / social / governance ESG.

[0015] Effects of the present disclosure are not limited to the above-described effects, but other effects that are not described herein will be clearly understood by those skilled in the art from the following description.

[0016] The details described in the technical problems, technical solutions, and advantageous effects of the present disclosure do not define essential features of the claims, and thus the scope of the claims is not limited by the details described in the detailed description of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application. They illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

[0018] Figure 1 A transparent display device according to an exemplary embodiment of the present disclosure is shown.

[0019] Figure 2 is a circuit diagram of a sub-pixel of a transparent display device according to an exemplary embodiment of the present disclosure.

[0020] Figure 3 An exemplary embodiment according to the present disclosure is shown. Figure 1 Area A shown in .

[0021] Figure 4 An exemplary embodiment of the present disclosure is shown. Figure 3 Region B shown in FIG.

[0022] Figure 5 According to an exemplary embodiment of the present disclosure, Figure 4 A cross-sectional view taken along line II' in FIG.

[0023] Figure 6 According to an exemplary embodiment of the present disclosure, Figure 4 A cross-sectional view taken along line II-II'.

[0024] Figure 7 A transparent display device according to another exemplary embodiment of the present disclosure is shown.

[0025] Figure 8 A transparent display device according to another exemplary embodiment of the present disclosure is shown.

[0026] Figure 9 Another exemplary embodiment of the present disclosure is shown. Figure 7 Region C shown in FIG.

[0027] Figure 10 According to another exemplary embodiment of the present disclosure, Figure 9 A cross-sectional view taken along line III-III'.

[0028] Figure 11 According to another exemplary embodiment of the present disclosure, Figure 9 A cross-sectional view taken along line IV-IV'.

[0029] Figure 12 Another exemplary embodiment of the present disclosure is shown. Figure 7Region C shown in FIG.

[0030] Figure 13 According to another exemplary embodiment of the present disclosure, Figure 12 A cross-sectional view taken along line V-V' in FIG.

[0031] Figure 14 Another exemplary embodiment of the present disclosure is shown. Figure 7 Region C shown in FIG.

[0032] Figure 15 According to another exemplary embodiment of the present disclosure, Figure 14 A cross-sectional view taken along line VI-VI'.

[0033] Figure 16 A transparent display device according to another exemplary embodiment of the present disclosure is shown.

[0034] Figure 17 A transparent display device according to another exemplary embodiment of the present disclosure is shown.

[0035] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The size, length, thickness, and depiction of layers, regions, and elements may be exaggerated for clarity, illustration, and / or convenience. DETAILED DESCRIPTION

[0036] The advantages and features of the present disclosure and their implementation methods are illustrated by referring to the exemplary embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be considered as limited to the exemplary embodiments described. On the contrary, these exemplary embodiments are examples and are provided so that the present disclosure can be comprehensive and complete, to help those skilled in the art understand the concept of the present invention without limiting the scope of protection of the present disclosure.

[0037] The shapes (e.g., size, length, width, height, thickness, position, radius, diameter, and area), dimensions, ratios, angles, quantities, etc. disclosed herein, including those shown in the accompanying drawings, are merely examples, and thus, the present disclosure is not limited to the details shown. Any implementation described herein as an "example" is not necessarily to be construed as superior or more advantageous than other implementations. However, it should be noted that the relative sizes of the components shown in the accompanying drawings are part of the present disclosure.

[0038] When the terms "comprising," "having," "including," "containing," "consisting of," "made of," "formed of," "composed of," etc. are used with respect to one or more elements, one or more other elements may be added unless a term such as "only" is used. The terms used in the present disclosure are only for describing exemplary embodiments and are not intended to limit the scope of the present disclosure. Terms in the singular may include plural forms unless the context clearly indicates otherwise.

[0039] The dimensions including size and thickness of the various components shown in the drawings are shown for ease of description, and the present disclosure is not limited to the size and thickness of the components shown, but it should be noted that the relative dimensions including relative size, position and thickness of the components shown in the various drawings submitted herein are part of the present disclosure.

[0040] When explaining an element, the element is interpreted as including an error area even though there is no explicit description of the element.

[0041] When describing a positional relationship, for example, when the positional order is described as "on," "over," "above," "under," "below," "beside," "under," "near," "near," "adjacent," "to the side of," or "close to," situations where there is no contact between them may be included unless "exactly" or "directly" is used.

[0042] Spatially relative terms may be used herein, such as "below," "beneath," "under," "lower," "above," "upper," etc., to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of elements in use or operation. For example, if the elements in the figures are inverted, elements described as being "below" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "below" may include both below and above orientations. Similarly, the exemplary terms "above" or "above" may include both above and below orientations.

[0043] If a first element is referred to as being positioned above a second element, this does not necessarily mean that the first element is positioned substantially above the second element in the drawings. The upper and lower portions of the relevant objects may vary depending on the orientation of the objects. Therefore, a case where a first element is positioned above a second element includes both cases where the first element is positioned "below" the second element in the drawings or in actual configuration, and cases where the first element is positioned "above" the second element.

[0044] When describing a temporal relationship, for example, when a temporal order is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "just" or "directly" is used.

[0045] It should be understood that although the terms "first," "second," "A," "B," "a," and "b," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0046] When describing elements of the present disclosure, terms such as "first," "second," "A," "B," "(a)," "(b)," etc. may be used. These terms are intended to identify corresponding elements from other elements and are not used to define the nature, basis, order, or quantity of the elements.

[0047] When an element is “connected,” “coupled,” “attached,” “bonded,” etc. to another element, the element may not only be directly connected, coupled, attached, bonded, etc. to the other element but also be indirectly connected, coupled, attached, bonded, etc. to the other element via one or more intermediate elements disposed or interposed between the elements, unless otherwise specified.

[0048] Regarding expressions that one element is “contacting,” “overlapping,” etc., with another element, unless otherwise specified, the one element may not only be directly in contact with, overlap with, etc., but may also be indirectly in contact with, overlap with, etc., with the other element via one or more intermediate elements disposed or interposed between the elements.

[0049] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, "at least one of a first element, a second element, and a third element" may include each of the first element, the second element, and the third element, as well as all combinations of two or more elements selected from the first element, the second element, and the third element.

[0050] The term "device" as used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting elements, etc. In addition, examples of devices may include laptop computers, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as complete electronic devices (or devices) or complete sets of devices (or devices) each including a light-emitting element as a complete product or final product, for example, mobile electronic devices such as smartphones or electronic tablets, but embodiments of the present disclosure are not limited thereto.

[0051] The features of the various exemplary embodiments of the present disclosure may be partially or entirely coupled or combined with each other, may be technically associated with each other, and may interoperate, link, or drive together in various ways. The exemplary embodiments of the present disclosure may be implemented or executed independently of each other, or may be implemented or executed together in a mutually dependent or related relationship. In one or more aspects, the components of each device according to the various exemplary embodiments of the present disclosure may be operably coupled and configured.

[0052] In the following description, various exemplary embodiments of the present disclosure are described in detail with reference to the accompanying drawings. With respect to the reference numerals of the elements of each drawing, the same elements may be shown in other drawings, and the same reference numerals may represent the same elements, unless otherwise stated. The same or similar elements may be represented by the same reference numerals, even if they are shown in different drawings. In addition, for ease of description, the proportions, dimensions, sizes, and thicknesses of each element shown in the drawings may be different from the actual proportions, dimensions, sizes, and thicknesses, and therefore, the exemplary embodiments of the present disclosure are not limited to the proportions, dimensions, sizes, and thicknesses shown in the drawings.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0054] In aspects of the present disclosure, for ease of description, source electrodes and drain electrodes are distinguished from each other. However, source electrodes and drain electrodes may be used interchangeably. A source electrode may be a drain electrode, and a drain electrode may be a source electrode. In addition, a source electrode in any aspect of the present disclosure may be a drain electrode in another aspect of the present disclosure, and a drain electrode in any aspect of the present disclosure may be a source electrode in another aspect of the present disclosure.

[0055] Figure 1 A transparent display device according to an exemplary embodiment of the present disclosure is shown. Figure 2 is a circuit diagram of a sub-pixel of a transparent display device according to an exemplary embodiment of the present disclosure.

[0056] Hereinafter, the X-axis represents a direction parallel to the scan lines, the Y-axis represents a direction parallel to the data lines, and the Z-axis represents a height direction of the transparent display device.

[0057] The transparent display device according to an exemplary embodiment of the present disclosure is implemented as an organic light emitting display (OLED). However, the transparent display device may be implemented as a liquid crystal display (LCD) device, a micro light emitting diode (MicroLED) display, a quantum dot display (QD), etc., and the present disclosure is not limited thereto.

[0058] Reference Figure 1 and Figure 2 According to an exemplary embodiment of the present disclosure, a transparent display device may include a transparent display panel 110 having a display area DA and a non-display area NDA, wherein the display area DA is provided with pixels for displaying an image, and an image is not displayed on the non-display area NDA. The non-display area NDA is configured to be adjacent to, partially, or completely surround the display area DA.

[0059] The display area DA of the transparent display panel 110 may include a first signal line SL1, a second signal line SL2, and pixels, and the non-display area NDA may include a pad area PA provided with pads and at least one gate driver 205. The exemplary embodiments of the present disclosure are not limited thereto. In addition, all components of each transparent display device according to all embodiments of the present disclosure are operably connected and configured.

[0060] The first signal line SL1 may extend in a first direction (or Y-axis direction) and may intersect the second signal line SL2 within the display area DA. The second signal line SL2 may extend in a second direction (or X-axis direction). Pixels are provided in an area where the first signal line SL1 and the second signal line SL2 intersect each other and may emit predetermined light to display an image.

[0061] The gate driver 205 may be connected to the scan line to supply a scan signal. The gate driver 205 may be implemented as a gate driver in panel (GIP) type or a tape automated bonding (TAB) type in the non-display area (NDA) on one or both sides of the display area DA of the transparent display panel 110. However, the present disclosure is not limited thereto.

[0062] A source driving circuit / source driving integrated circuit, a display controller, a circuit board, or a timing controller connected through a flexible circuit film may be electrically connected to the pad area PA of the transparent display panel 110 .

[0063] The display controller may control the source driving circuit and the gate driver 205. The display controller may control the source driving circuit and the gate driver 205 by providing various driving control signals DCS and GCS to the source driving circuit and the gate driver 205.

[0064] The display controller can start scanning according to the timing achieved in each frame, convert the external input image data into the data signal format used in the source drive circuit, output the converted image data Data, and control the data drive at the appropriate time according to the scan.

[0065] The display controller may receive various timing signals including, for example, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a clock signal, etc., and input image data from an external device (eg, a host system).

[0066] The display controller can not only convert the input image data input from the outside to suit the data signal format used in the source driving circuit and output the converted image data, but also control the source driving circuit and the gate driver 205, receive timing signals such as vertical synchronization signals, horizontal synchronization signals, input data enable signals or clock signals, and generate various drive control signals DCS and GCS and output them to the source driving circuit and the gate driver 205.

[0067] The source driving circuit may drive the plurality of data lines DL by receiving image data Data from the display controller and supplying data voltages to the plurality of data lines DL. The source driving circuit may be a data driving circuit, but exemplary embodiments of the present disclosure are not limited thereto.

[0068] The source driving circuit may be implemented by including at least one source driving integrated circuit, but exemplary embodiments of the present disclosure are not limited thereto.

[0069] The timing controller can control the source driver circuit and the gate driver 205. For example, the timing controller can realign the digital video data input from the outside to suit the resolution of the display panel and supply the video data to the source driver circuit. The timing controller can generate a gate control signal and a data control signal based on timing signals (such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) synchronized with the input image signal. Here, the horizontal synchronization signal is a signal representing the time taken for one horizontal line of the display screen, and the vertical synchronization signal is a signal representing the time taken for one frame of the display screen. The data enable signal can correspond to a signal indicating the period of supplying data voltage to the pixel. The timing controller can control the operation timing of the gate driver 205 and the source driver circuit by supplying the gate control signal to the gate driver 205 and the data control signal to the source driver circuit.

[0070] Reference Figure 2, each of the pixels includes a plurality of sub-pixels constituting a unit pixel. In each of the plurality of sub-pixels, there is a circuit element having 3T (transistor) 1C (capacitor), including a first switching transistor TR1, a second switching transistor TR2, a driving transistor DTR and a capacitor Cst, and a light-emitting element ED, but not limited thereto. Each sub-pixel may further include a compensation circuit. In this case, the sub-pixel may have various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0071] Each of the transistors DTR, TR1, and TR2 of each sub-pixel may include a gate electrode, a source electrode, and a drain electrode. Since the source electrode and the drain electrode may change depending on the voltage applied to the gate electrode and the direction of the current and are not fixed, any one of the source electrode and the drain electrode may be represented as a first electrode, and the other may be represented as a second electrode. The active layer of the transistors DTR, TR1, and TR2 of each sub-pixel may be formed of a semiconductor material, such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0072] Oxide semiconductor materials can have excellent effects in preventing leakage current and relatively cheap manufacturing costs. Oxide semiconductors can be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) or combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and their oxides. Specifically, oxide semiconductors can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO) and indium gallium oxide (IGO), but are not limited thereto.

[0073] Polycrystalline semiconductor materials have a fast moving speed of carriers such as electrons and holes, and thus have high mobility, low power consumption, and excellent reliability. Polycrystalline semiconductors may be made of polycrystalline silicon (poly-Si), but are not limited thereto.

[0074] The amorphous semiconductor material may be made of amorphous silicon (a-Si), but is not limited thereto.

[0075] The transistors DTR, TR1 and TR2 may be of P type or N type, or P type and N type may be used interchangeably.

[0076] The first switching transistor TR1 can be used to supply the data voltage Vdata supplied from the data line DL to the drive transistor DTR. For example, the first switching transistor TR1 can charge the data voltage Vdata supplied from the data line DL to the capacitor Cst. To this end, the gate electrode of the first switching transistor TR1 is connected to the scan line SCANL (or gate line), and its first electrode is connected to the data line DL. In addition, the second electrode of the first switching transistor TR1 can be connected to one end of the capacitor Cst and the gate electrode of the drive transistor DTR.

[0077] The first switching transistor TR1 may be turned on in response to a scan signal applied through a scan line SCANL (or a gate line). When the first switching transistor TR1 is turned on, a data voltage Vdata applied through a data line DL may be transmitted to one end of the capacitor Cst.

[0078] The second switching transistor TR2 can be used to supply a reference voltage Vref supplied from a reference line REFL to the driving transistor DTR. For example, the gate electrode of the second switching transistor TR2 is connected to a scan line (or a gate line), and the first electrode thereof is connected to the reference line. In addition, the second electrode of the second switching transistor TR2 can be connected to the first electrode of the driving transistor DTR and the other end of the capacitor Cst.

[0079] The second switching transistor TR2 can be turned on in response to a scan signal applied via a scan line (or gate line). When the second switching transistor TR2 is turned on, a reference voltage Vref applied via a reference line REFL can be transmitted to the other end of the capacitor Cst. In addition, the reference voltage Vref can also be applied to the source electrode of the drive transistor DTR.

[0080] Capacitor Cst maintains the data voltage Vdata supplied to the drive transistor DT for one frame. For example, a first electrode of capacitor Cst may be connected to the gate electrode of the drive transistor DTR, and a second electrode of capacitor Cst may be connected to the source electrode of the drive transistor DTR. Capacitor Cst may store a voltage corresponding to the data voltage Vdata transmitted by the first switching transistor TR1 and may use the stored voltage to turn on the drive transistor DTR.

[0081] The driving transistor DTR can generate a data current from the first power EVDD supplied by the pixel power line VDDL and can supply the data current to the anode electrode of the light-emitting element ED. For example, the gate electrode of the driving transistor DTR can be connected to one end of the capacitor Cst, and the first electrode of the driving transistor DTR can be connected to the pixel power line VDDL. In addition, the second electrode of the driving transistor DTR can be connected to the anode electrode of the light-emitting element ED.

[0082] The light-emitting element ED may include an anode electrode connected to the drive transistor DTR, a cathode electrode supplied with a second power EVSS by a common power line VSSL (or a second power line), and a light-emitting layer between the anode electrode and the cathode electrode. The anode electrode is an independent electrode of each light-emitting element, however, the cathode electrode may be a common electrode shared by all light-emitting elements. When a driving current is supplied from the drive transistor DTR to the light-emitting element ED, electrons from the cathode electrode are injected into the light-emitting layer of the light-emitting element ED, and holes from the anode electrode are injected into the light-emitting layer of the light-emitting element ED, whereby the fluorescent or phosphorescent material emits light by recombination of electrons and holes in the light-emitting layer, thereby generating light with a brightness proportional to the current value of the driving current.

[0083] The anode electrode of the light emitting element ED is connected to the second electrode of the driving transistor DTR, and the cathode electrode of the light emitting element ED is connected to the common power line VSSL. The light emitting element ED can emit light in response to the driving current generated by the driving transistor DTR.

[0084] Figure 3 An exemplary embodiment according to the present disclosure is shown. Figure 1 Area A shown in . Figure 4 An exemplary embodiment of the present disclosure is shown. Figure 3 Region B shown in FIG.

[0085] Combine Figure 1 and Figure 2 Reference Figure 3 and Figure 4 According to an exemplary embodiment of the present disclosure, the transparent display panel 110 may include a display area DA and a non-display area NDA. The display area DA may include a transmissive area TA and a non-transmissive area NTA. The transmissive area TA may be a region through which most of the light incident from the outside passes, and the non-transmissive area NTA may be a region that does not transmit most of the light incident from the outside. For example, the transmissive area TA may be a region with a light transmittance greater than a%, and the non-transmissive area NTA may be a region with a light transmittance less than b%. Here, "a" may be a value greater than "b". Due to the transmissive area TA, the transparent display panel 110 enables the user to see an object or background located on the rear surface of the transparent display panel 110.

[0086] A first non-transmission area NTA1, a second non-transmission area NTA2, and pixels P may be included in the non-transmission area NTA.

[0087] The first non-transmission area NTA1 may extend along the first direction (or Y-axis direction) on the display area DA and may be arranged to at least partially overlap with the light-emitting areas EA1, EA2, EA3, and EA4. There may be multiple first non-transmission areas NTA1. The multiple first non-transmission areas NTA1 may extend in the first direction (or Y-axis direction) and may be spaced apart from each other in the second direction (or X-axis direction). Two adjacent first non-transmission areas NTA1 may be arranged to be spaced apart from each other with the transmission area TA interposed therebetween. For example, the transmission area TA may be arranged between two adjacent first non-transmission areas NTA1. A first signal line SL1 extending in the first direction (or Y-axis direction) may be arranged in the first non-transmission area NTA1. For example, the first signal line SL1 may be arranged to overlap with the first non-transmission area NTA1.

[0088] The first signal line SL1 may include at least one of a pixel power line VDDL (or a first power line), a common power line VSSL (or a second power line), a reference line REFL, and data lines DL1, DL2, DL3, and DL4. For example, the first signal line SL1 may further include a touch sensor line TL, but exemplary embodiments of the present disclosure are not limited thereto.

[0089] The pixel power line VDDL can supply the first power EVDD to the driving transistor DTR of each of the sub-pixels SP1, SP2, SP3, and SP4 provided in the display area DA. The pixel power line VDDL can be provided on the right or left side of the emission areas EA1, EA2, EA3, and EA4. For example, the pixel power line VDDL can be provided on the right side of the emission areas EA1, EA2, EA3, and EA4. Alternatively, the pixel power line VDDL can be provided on the left side of the emission areas EA1, EA2, EA3, and EA4, but exemplary embodiments of the present disclosure are not limited thereto.

[0090] The common power line VSSL can supply the second power EVSS to the cathode electrodes of the sub-pixels SP1, SP2, SP3, and SP4 arranged in the display area DA. In this case, the second power EVSS can be a common power source commonly supplied to the sub-pixels SP1, SP2, SP3, and SP4. The common power line VSSL can be arranged on the right or left side of the emission areas EA1, EA2, EA3, and EA4. For example, the common power line VSSL can be arranged on the left side of the emission areas EA1, EA2, EA3, and EA4. Alternatively, the common power line VSSL can be arranged on the right side of the emission areas EA1, EA2, EA3, and EA4, but exemplary embodiments of the present disclosure are not limited thereto.

[0091] The reference line REFL can supply an initialization voltage (or reference voltage) to the driving transistor DTR of each sub-pixel SP1, SP2, SP3, and SP4 provided in the display area DA. For example, the reference line REFL can be provided between the plurality of data lines DL1, DL2, DL3, and DL4. For example, the reference line REFL can be provided in the middle of the plurality of data lines DL1, DL2, DL3, and DL4, but exemplary embodiments of the present disclosure are not limited thereto.

[0092] Each of the data lines DL1, DL2, DL3, and DL4 may provide a data voltage Vdata to the sub-pixels SP1, SP2, SP3, and SP4. For example, the first data line DL1 supplies a first data voltage to a first drive transistor of the first sub-pixel SP1, the second data line DL2 supplies a second data voltage to a second drive transistor of the second sub-pixel SP2, the third data line DL3 supplies a third data voltage to a third drive transistor of the third sub-pixel SP3, and the fourth data line DL4 supplies a fourth data voltage to a fourth drive transistor of the fourth sub-pixel SP4.

[0093] The second non-transmission area NTA2 may extend along the second direction (or X-axis direction) on the display area DA and may be arranged to at least partially overlap with the light-emitting areas EA1, EA2, EA3, and EA4. For example, the second non-transmission area NTA2 may extend along the second direction (or X-axis direction) between two adjacent first non-transmission areas NTA1. There may be multiple second non-transmission areas NTA2. The multiple second non-transmission areas NTA2 may extend in the second direction (or X-axis direction) and may be spaced apart from each other in the first direction (or Y-axis direction). Two adjacent second non-transmission areas NTA2 may be arranged to be spaced apart from each other with the transmission area TA interposed therebetween. For example, the transmission area TA may be arranged between two adjacent second non-transmission areas NTA2. A second signal line SL2 extending in the second direction (or X-axis direction) may be arranged in the second non-transmission area NTA2. For example, the second signal line SL2 may be arranged to overlap with the second non-transmission area NTA2.

[0094] The second signal line SL2 extends along the second direction (or the X-axis direction) and includes a scan line (or a gate line) that supplies a scan signal to the sub-pixels SP1, SP2, SP3, and SP4 of the pixel P.

[0095] The scan line SCANL may be connected to each pixel P corresponding to a horizontal line in which a plurality of pixels P are arranged in parallel in the second direction (or the X-axis direction). The scan line SCANL may be arranged at the center of the pixel P corresponding to the horizontal line. For example, the scan line SCANL may be arranged between the first subpixel SP1 and the third subpixel SP3 of each pixel P and the second subpixel SP2 and the fourth subpixel SP4 of each pixel P. Alternatively, the scan line SCANL may be arranged above or below the pixel P corresponding to the horizontal line. For example, the scan line SCANL may be arranged above the first subpixel SP1 and the third subpixel SP3 of the pixel P corresponding to the horizontal line, or may be arranged below the second subpixel SP2 and the fourth subpixel SP4 of the pixel P corresponding to the horizontal line, but exemplary embodiments of the present disclosure are not limited thereto.

[0096] Pixels P may be arranged within each intersection region where the first non-transmission area NTA1 and the second non-transmission area NTA2 intersect each other, and may emit light to display an image. Each pixel P is disposed between adjacent transmission areas TA, and the pixels P may include light-emitting areas EA1, EA2, EA3, and EA4, each of which includes a light-emitting element disposed therein to emit light. The light-emitting areas EA1, EA2, EA3, and EA4 may correspond to regions where light is emitted from the pixels P. Due to the small area of ​​the non-transmission area NTA, circuit elements may be disposed in the transparent display panel 110 so as to overlap with the light-emitting areas EA1, EA2, EA3, and EA4. For example, the light-emitting areas EA1, EA2, EA3, and EA4 may at least partially overlap with the circuit areas CA1, CA2, CA3, and CA4, in which the circuit elements are disposed. For example, the circuit areas CA1, CA2, CA3, and CA4 may include a first circuit area CA1 in which circuit elements connected to the first sub-pixel SP1 are provided, a second circuit area CA2 in which circuit elements connected to the second sub-pixel SP2 are provided, a third circuit area CA3 in which circuit elements connected to the third sub-pixel SP3 are provided, and a fourth circuit area CA4 in which circuit elements connected to the fourth sub-pixel SP4 are provided, but exemplary embodiments of the present disclosure are not limited thereto.

[0097] Each of the pixels P may be disposed in the first non-transmission area NTA1 and may emit light to display an image. Each of the pixels P may include a first subpixel SP1, a second subpixel SP2, a third subpixel SP3, and a fourth subpixel SP4. The first subpixel SP1 may include a first emission area EA1 for emitting a first color light, the second subpixel SP2 may include a second emission area EA2 for emitting a second color light, the third subpixel SP3 may include a third emission area EA3 for emitting a third color light, and the fourth subpixel SP4 may include a fourth emission area EA4 for emitting a fourth color light, but exemplary embodiments of the present disclosure are not limited thereto.

[0098] All of the first, second, third, and fourth light-emitting areas EA1, EA2, EA3, and EA4 can emit light of different colors. For example, the first light-emitting area EA1 can emit green light, the second light-emitting area EA2 can emit blue light, the third light-emitting area EA3 can emit white light, and the fourth light-emitting area EA4 can emit red light, but the present invention is not limited thereto. In addition, the arrangement order or arrangement of each of the sub-pixels SP1, SP2, SP3, and SP4 can vary to varying degrees.

[0099] The first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3 and the fourth sub-pixel SP4 can be arranged in a quadrilateral matrix along the first direction (or Y-axis direction) and the second direction (or X-axis direction). The first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3 and the fourth sub-pixel SP4 can be arranged to be adjacent to the pixel power line VDDL (or the first power line) or the common power line VSSL (or the second power line). For example, the first sub-pixel SP1 and the second sub-pixel SP2 can be arranged to be adjacent to the common power line VSSL, and the third sub-pixel SP3 and the fourth sub-pixel SP4 can be arranged to be adjacent to the pixel power line VDDL. Alternatively, the first sub-pixel SP1 and the second sub-pixel SP2 can be arranged to be adjacent to the pixel power line VDDL, and the third sub-pixel SP3 and the fourth sub-pixel SP4 can be arranged to be adjacent to the common power line VSSL, but exemplary embodiments of the present disclosure are not limited thereto.

[0100] Reference Figure 4According to an exemplary embodiment of the present disclosure, the transparent display panel 110 may include a light-emitting area formed by dividing the light-emitting area EA1, EA2, EA3, and EA4 included in each of the plurality of sub-pixels SP1, SP2, SP3, and SP4. For example, each of the plurality of sub-pixels SP1, SP2, SP3, and SP4 may include a first dividing electrode 121 and a second dividing electrode 122 formed by separating the first electrode 120 (or anode electrode) of the light-emitting element while being spaced apart from each other. Each of the first dividing electrode 121 and the second dividing electrode 122 may correspond to the divided light-emitting area. For example, the first light-emitting area EA1, EA2, EA3, and EA4 included in each of the sub-pixels SP1, SP2, SP3, and SP4 may include first divided light-emitting areas EA11, EA21, EA31, and EA41 and second divided light-emitting areas EA12, EA22, EA32, and EA42, respectively, corresponding to the first dividing electrode 121 and the second dividing electrode 122. When foreign matter is generated in any one of the first dividing electrode 121 and the second dividing electrode 122 according to the exemplary embodiment of the present disclosure, the dividing electrode containing the foreign matter is electrically separated or disconnected from the circuit areas CA1, CA2, CA3, and CA4, so that only the electrode containing the foreign matter may become dark, and the remaining dividing electrodes can be repaired to operate normally.

[0101] like Figure 2 As shown, the pixel circuit (circuit area) CA1, CA2, CA3, and CA4 of each of the multiple sub-pixels SP1, SP2, SP3, and SP4 may include a capacitor Cst, at least one thin-film transistor DRT, TR1, and TR2, and a light-emitting element ED. For example, the at least one thin-film transistor DRT, TR1, and TR2 may include a drive transistor DTR, a first switching transistor TR1, and a second switching transistor TR2. In addition, the light-emitting element ED may include a first electrode (or an anode electrode, a pixel electrode), a light-emitting layer (or an organic light-emitting layer), and a second electrode (or a cathode electrode, a common electrode). However, the pixel circuit CA1, CA2, CA3, and CA4 of each of the multiple sub-pixels SP1, SP2, SP3, and SP4 is not limited to this. Each of the multiple sub-pixels SP1, SP2, SP3, and SP4 may further include a compensation circuit. In this case, each of the multiple sub-pixels SP1, SP2, SP3, and SP4 may have various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0102] The transparent display panel 110 according to the exemplary embodiment of the present disclosure may further include at least one lower tangent line UCL extending in the first direction (or the Y-axis direction) in the transmission area TA.

[0103] At least one lower tangent line UCL may be provided on one side (or left side) of the transmission area TA, or on the other side (or right side) of the transmission area TA. For example, at least one lower tangent line UCL may be provided within the transmission area TA and may be arranged adjacent to the common power line VSSL (or second power line) provided in the non-transmission area NTA. Alternatively, at least one lower tangent line UCL may be provided in the transmission area TA and may be arranged adjacent to the pixel power line VDDL (or first power line) provided in the non-transmission area NTA, but exemplary embodiments of the present disclosure are not limited thereto. For example, at least two lower tangent lines UCL may be provided in the transmission area TA. At least one lower tangent line UCL may be provided on one side (or left side) of the transmission area TA, while the other lower tangent lines UCL may be provided on the other side (or right side) of the transmission area TA.

[0104] At least one undercut line UCL may be used to separate or disconnect the light-emitting layer (or organic light-emitting layer) disposed in the transmission area TA. The at least one undercut line UCL may be formed by at least a portion of an inorganic insulating layer (e.g., a passivation layer) and an organic insulating layer (e.g., a planarization layer). For example, the at least one undercut line UCL may be configured by removing at least a portion of the inorganic insulating layer (e.g., a passivation layer) and the organic insulating layer (e.g., a planarization layer), however, the present disclosure is not limited thereto.

[0105] The scan line (or gate line) crossing the transmissive area TA may be disposed below the at least one lower cut line UCL. The block pattern BP may be further included in a portion where the at least one lower cut line UCL and the scan line SCANL intersect. For example, during the formation of the at least one lower cut line UCL, the block pattern BP may prevent damage to the scan line SCANL intersecting the at least one lower cut line UCL disposed thereunder.

[0106] Figure 5 According to an exemplary embodiment of the present disclosure, Figure 4 A cross-sectional view taken along line II' in FIG. Figure 6 According to an exemplary embodiment of the present disclosure, Figure 4 A cross-sectional view taken along line II-II'.

[0107] Reference Figure 5 and Figure 6 And combined Figure 4 According to an exemplary embodiment of the present disclosure, a buffer layer BF may be disposed on the substrate 111 of the transparent display panel 110 , and at least one insulating layer, a thin film transistor, and at least one signal line may be disposed on the buffer layer BF.

[0108] The buffer layer BF may be made of an insulating material. For example, the buffer layer BF may be configured as a single layer or a multilayer made of at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). For example, the buffer layer BF may be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, depending on the structure or characteristics of the display device, the buffer layer BF may not be included.

[0109] For example, Figure 5 As shown, a scan line SCANL (GE) (or gate line) may be provided on the buffer layer BF. The scan line SCANL (GE) (or gate line) may be made of the same material as the gate electrode GE of the thin film transistor on the same layer. A gate insulating layer GI may be provided between the scan line SCANL (GE) (or gate line) and the buffer layer BF.

[0110] An interlayer insulating layer ILD may be provided on the buffer layer BF on which the scan line SCANL(GE) (or gate line) is provided. The interlayer insulating layer ILD may be formed to include a silicon oxide SiO X , silicon nitride SiN X , aluminum oxide Al2O3, or other inorganic insulating materials, such as a single-layer structure or a multi-layer structure. For example, the interlayer insulating layer ILD can be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film can be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0111] A first passivation layer PAS1 may be provided on the interlayer insulating layer ILD. A second passivation layer PAS2 may be provided on the first passivation layer PAS1. The first passivation layer PAS1 and the second passivation layer PAS2 may be formed as a single layer structure or a multi-layer structure including silicon oxide SiO X , silicon nitride SiN X, aluminum oxide Al2O3 and other inorganic insulating materials. For example, each of the first passivation layer PAS1 and the second passivation layer PAS2 can be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film can be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0112] A planarization layer PLN may be provided on the second passivation layer PAS2 to flatten the step difference caused by the thin-film transistors and multiple signal lines. The planarization layer PLN may be formed from an organic material such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. A first electrode of the light-emitting element, an organic light-emitting layer 130, and a second electrode 140 may be provided on the planarization layer PLN. The light-emitting element may be provided in the non-transmission area NTA on the substrate 111. An encapsulation layer EPAS may be provided on the light-emitting element on the substrate 111. The encapsulation layer EPAS may be provided on the second electrode 140 and may be configured to cover the second electrode 140. According to exemplary embodiments of the present disclosure, the transparency of the transmissive area TA on the substrate 111 is increased by removing most of the planarization layer PLN from the transmissive area TA and providing the planarization layer PLN only in a portion of the transmissive area TA on the substrate 111. For example, the organic light-emitting layer 130 and the second electrode 140 extending from the light-emitting element may be provided on the second passivation layer PAS2 in the transmissive area TA of the substrate 111.

[0113] According to an exemplary embodiment of the present disclosure, at least one undercut line UCL may be provided in the transmission area TA on the substrate 111. The at least one undercut line UCL may be arranged to extend along the first direction (or the Y-axis direction) in the transmission area TA. For example, the at least one undercut line UCL may be configured by using a planarization layer PLN and at least a portion of the first passivation layer PAS1 and the second passivation layer PAS2. The at least one undercut line UCL may be used to disconnect the organic light-emitting layer 130 from the transmission area TA. For example, the at least one undercut line UCL may separate or disconnect the organic light-emitting layer 130 extending from the non-transmission area NTA. Therefore, the at least one undercut line UCL may block a moisture penetration path relative to the boundary of the at least one undercut line UCL.

[0114] Reference Figure 5At least a portion of the at least one lower cut line UCL may be arranged to overlap with at least one scan line (or gate line) in the transmissive area TA. A block pattern BP may be provided at a portion where the at least one lower cut line UCL and the at least one scan line SCANL overlap. The block pattern BP may be provided on the first passivation layer PAS1. For example, the block pattern BP may prevent damage to the at least one scan line (or gate line) overlapping with the at least one lower cut line UCL during formation of the at least one lower cut line UCL.

[0115] At least one undercut line UCL may be configured by using a planarization layer PLN and a second passivation layer PAS2. For example, at least one undercut line UCL may be configured by removing at least a portion of the planarization layer PLN and the second passivation layer PAS2. At least one undercut line UCL may include a first pattern line UCL_P1 formed of the same material as the planarization layer PLN and a second pattern line UCL_P2 composed of the second passivation layer PAS2. For example, the first pattern line UCL_P1 of the at least one undercut line UCL may be formed by patterning the planarization layer PLN, and the second pattern line UCL_P2 of the at least one undercut line UCL may be formed by removing at least a portion of the second passivation layer PAS2 to have an undercut area UCA below the first pattern line UCL_P1.

[0116] Reference Figure 6 , at least a portion of at least one lower cut line UCL may be disposed so as not to overlap with other signal lines in the transmission area TA.

[0117] At least one undercut line UCL may be configured by using a planarization layer PLN and a first passivation layer PAS1 and a second passivation layer PAS2. For example, at least one undercut line UCL may be configured by removing at least a portion of the planarization layer PLN and the first passivation layer PAS1 and the second passivation layer PAS2. At least one undercut line UCL may include a first pattern line UCL_P1 formed of the same material as the planarization layer PLN and a second pattern line UCL_P2 composed of the first passivation layer PAS1 and the second passivation layer PAS2. For example, the first pattern line UCL_P1 of the at least one undercut line UCL may be formed by patterning the planarization layer PLN, and the second pattern line UCL_P2 of the at least one undercut line UCL may be formed by removing at least a portion of the first passivation layer PAS1 and the second passivation layer PAS2 to have an undercut area UCA below the first pattern line UCL_P1.

[0118] Figure 7 A transparent display device according to another exemplary embodiment of the present disclosure is shown. Figure 8 A transparent display device according to another exemplary embodiment of the present disclosure is shown.

[0119] Reference Figure 7 and Figure 8 According to another exemplary embodiment of the present disclosure, the transparent display panel 110 may include a display area DA in which pixels are configured to display an image and a non-display area NDA in which no image is displayed. For example, the non-display area NDA may be disposed at the periphery of the display area DA.

[0120] like Figure 3 and Figure 4 As shown, a plurality of pixels P including a plurality of sub-pixels SP1, SP2, SP3, and SP4 and a transmission area TA may be provided in the display area DA of the transparent display panel 110. The transparent display panel 110 may include at least one lower tangent line UCL extending in the first direction (or Y-axis direction) in the transmission area TA of the display area DA of the transparent display panel 110.

[0121] The non-display area NDA of the transparent display panel 110 may include a pad area PA having pads to which external signals are applied, and a plurality of gate drivers 205a and 205b. Furthermore, the transparent display panel 110 may include a non-pad area NPA disposed in the non-display area NDA, facing the pad area PA, with the display area DA interposed between the pad area PA and the non-pad area NPA. For example, the non-pad area NPA may be disposed in an area of ​​the non-display area NDA of the transparent display panel 110 that is opposite the pad area PA. The non-pad area NPA may be an area where no pads are disposed.

[0122] At least one lower cut line UCL according to another exemplary embodiment of the present disclosure may be provided in the non-display area NDA and the display area DA. For example, at least one lower cut line UCL may be arranged to extend in the non-display area NDA and the display area DA along a first direction (or Y-axis direction). For example, at least one lower cut line UCL may extend from the non-display area NDA to the display area DA. In at least a portion of the non-display area NDA, the organic light-emitting layer constituting the light-emitting element may be provided to extend from the display area DA, and at least one lower cut line UCL may extend from the portion of the organic light-emitting layer provided in the non-display area NDA to the display area DA. For example, at least one lower cut line UCL may extend from the pad area PA of the non-display area NDA to across the display area DA, and may extend to the non-pad area NPA of the non-display area NDA. For example, at least one lower cut line UCL may extend along the first direction (or Y-axis direction) from the pad area PA of the non-display area NDA to across the display area DA, and may extend to the non-pad area NPA of the non-display area NDA, however, the present disclosure is not limited thereto.

[0123] At least one power shorting bar may be provided in the non-display area NDA of the transparent display panel 110. The at least one power shorting bar is electrically connected to at least one power line provided in the display area DA and may be arranged to extend along the second direction (or the X-axis direction) in the non-display area NDA. At least one lower tangent line UCL according to another exemplary embodiment of the present disclosure may overlap with the at least one power shorting bar in the non-display area NDA. For example, in the non-display area NDA, the at least one lower tangent line UCL may intersect and overlap with the at least one power shorting bar.

[0124] The flexible film 220 can be connected to the pad area PA of the non-display area NDA of the transparent display panel 110 using a tape automated bonding (TAB) method, and the source driver integrated circuit 210 (hereinafter referred to as "IC"), the circuit board 230, and the timing controller 240 connected through the flexible film 220 can be electrically connected to the pad area PA.

[0125] Reference Figure 7 , at least one lower tangent line UCL may include a plurality of lower tangent lines UCL arranged in parallel with the first direction (or Y-axis direction) in the display area DA and spaced apart from each other in the second direction (or X-axis direction). Each of the plurality of lower tangent lines UCL may be arranged to be spaced apart from each other at predetermined intervals in the second direction (or X-axis direction). For example, the plurality of lower tangent lines UCL may be uniformly arranged on the entire surface of the non-display area NDA and the display area DA. For example, each of the plurality of lower tangent lines UCL may extend from the pad area PA of the non-display area NDA along the first direction (or Y-axis direction) to across the display area DA, and may extend to the non-pad area NPA of the non-display area NDA, however the present disclosure is not limited thereto.

[0126] Reference Figure 8 , the plurality of undercut lines UCL may be arranged to be concentrated on a portion of the display area DA and the non-display area NDA. For example, the plurality of undercut lines UCL may be arranged so as not to overlap with the flexible film 220 in the pad area PA of the non-display area NDA. The plurality of undercut lines UCL may be arranged so as not to overlap with a portion of the flexible film 220 connected by a tape automated bonding (TAB) method in the pad area PA of the non-display area NDA. For example, the plurality of undercut lines UCL may be arranged between adjacent flexible films 220 in the pad area PA of the non-display area NDA. The plurality of undercut lines UCL may be arranged to be spaced apart from each other at predetermined intervals in the second direction (or the X-axis direction) between adjacent flexible films 220.

[0127] Figure 9 Another exemplary embodiment of the present disclosure is shown. Figure 7 Region C shown in FIG. Figure 10According to another exemplary embodiment of the present disclosure, Figure 9 A cross-sectional view taken along line III-III'. Figure 11 According to another exemplary embodiment of the present disclosure, Figure 9 A cross-sectional view taken along line IV-IV'.

[0128] Reference Figures 9 to 11 In a transparent display panel 110 according to another exemplary embodiment of the present disclosure, at least one lower tangent line UCL may be provided in the non-display area NDA and the display area DA. The at least one lower tangent line UCL may be provided to extend along the first direction (or the Y-axis direction) in the transmission area TA of each pixel P provided in the display area DA. The at least one lower tangent line UCL may be provided on one side and the other side of the transmission area TA along the second direction (or the X-axis direction).

[0129] At least one lower tangent line UCL may have a portion disposed in the display area DA and a portion disposed in the non-display area NDA, wherein the portions disposed in the display area DA and the non-display area NDA, respectively, may be arranged on the same line along the first direction (or the Y-axis direction). For example, the at least one lower tangent line UCL may extend from the pad area PA of the non-display area NDA to the non-pad area NPA of the non-display area NDA, while crossing the transmissive area TA of the display area DA from the pad area PA of the non-display area NDA along the same line along the first direction (or the Y-axis direction).

[0130] At least one power shorting bar SB1 and SB2 may be provided in the non-display area NDA of the transparent display panel 110. The at least one power shorting bar SB1 and SB2 may be arranged to extend along the second direction (or the X-axis direction) in the non-display area NDA. For example, the at least one power shorting bar SB1 and SB2 may be electrically connected to the pixel power line VDDL (or the first power line) and the common power line VSSL (or the second power line) of each pixel P provided in the display area DA. For example, Figure 9As shown, at least one power shorting bar SB1 and SB2 can be connected to the pixel power line VDDL of each pixel P. The at least one power shorting bar SB1 and SB2 can include power line contact portions SBC1 and SBC2 connected to the pixel power line VDDL of each pixel P. For example, the at least one power shorting bar SB1 and SB2 can be formed of a different metal layer in a layer different from the layer of the power line contact portions SBC1 and SBC2. For example, the at least one power shorting bar SB1 and SB2 can be formed on the substrate 111, and the power line contact portions SBC1 and SBC2 are formed on an insulating layer above the at least one power shorting bar SB1 and SB2 and are electrically connected to the at least one power shorting bar SB1 and SB2 through contact holes in the insulating layer. However, the present disclosure is not limited thereto.

[0131] The non-display area NDA of the transparent display panel 110 may further include a dummy electrode pattern DP disposed around at least one lower cut line UCL. For example, the dummy electrode pattern DP may be disposed around one side or the other side of the at least one lower cut line UCL. Alternatively, the dummy electrode pattern DP may be disposed between a plurality of adjacent lower cut lines UCL, but exemplary embodiments of the present disclosure are not limited thereto.

[0132] In the process of forming the undercut area UCA extending from the non-display area NDA to the display area DA, the dummy electrode pattern DP can prevent etching deviation caused by the etchant from occurring between the display area DA where the first electrode (or pixel electrode) constituting the light-emitting element is patterned and the non-display area NDA where the first electrode is not patterned. For example, the dummy electrode pattern DP can be made of the same material as the first electrode (or pixel electrode) constituting the light-emitting element, and can prevent over-etching in the non-display area NDA when forming the undercut line UCL, thereby improving the uniformity of the undercut line UC formed in the non-display area NDA and the display area DA.

[0133] Reference Figure 10 At least one power shorting bar SB1 may be disposed in the pad area PA of the non-display area NDA on the substrate 111. The at least one power shorting bar SB1 may extend along the second direction (or the X-axis direction) within the pad area PA. The at least one power shorting bar SB1 may be disposed to intersect and overlap with at least one lower tangent line UCL in the pad area PA.

[0134] At least one power shorting bar SB1 may be provided in the pad area PA on the substrate 111. For example, at least one power shorting bar SB1 may be a pixel power shorting bar SB1 connected to a pixel power line VDDL (or first power line) extending in a first direction (or Y-axis direction) within the display area DA and configured to supply a first power. In addition, a light shielding layer may be provided on the substrate 111. For example, the light shielding layer may be used to block external light incident on the active layer of the thin film transistor. The light shielding layer may be formed as a single-layer structure or a multi-layer structure of molybdenum Mo, aluminum Al, chromium Cr, gold Au, titanium Ti, nickel Ni, neodymium Nd, copper Cu, or an alloy thereof. At least one power shorting bar SB1 may be formed of the same material on the same layer as the light shielding layer, but exemplary embodiments of the present disclosure are not limited thereto. For example, at least one power shorting bar SB1 may also be formed of a different material from the light shielding layer.

[0135] At least one power shorting bar SB1 in the pad area PA on the substrate 111 may be partially spaced apart so as to be connected to another component in certain portions. At least one power shorting bar SB1 may include portions having different shapes on the substrate 111. For example, at least one power shorting bar SB1 may be configured to have multiple slit structures to reduce electrical effects with other signal lines. For example, at least one power shorting bar SB1 may be configured to have multiple slit structures in portions overlapping with the data line DL, the reference line REFL, and the common power line VSSL. At least one power shorting bar SB1 may include a contact portion electrically connected to the pixel power line VDDL extending along the first direction (or Y-axis direction) in the display area DA.

[0136] A buffer layer BF may be provided on the substrate 111 on which at least one power shorting bar SB1 and a light shielding layer are provided. The buffer layer BF protects the thin film transistor from moisture penetrating the substrate 111 which is susceptible to moisture penetration. The buffer layer BF may be formed to include a silicon oxide SiO X , silicon nitride SiN X , aluminum oxide Al2O3 and other inorganic insulating materials. For example, the buffer layer BF can be formed by a single layer or a multilayer inorganic film. For example, the single layer inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film can be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, depending on the structure or characteristics of the display device, the buffer layer BF may not be included.

[0137] At least one insulating layer, a thin film transistor, and at least one signal line may be provided on the buffer layer BF. For example, an interlayer insulating layer ILD may be provided on the buffer layer BF. The interlayer insulating layer ILD may be formed to include a silicon oxide SiO X , silicon nitride SiN X , aluminum oxide Al2O3, or other inorganic insulating materials. For example, the interlayer insulating layer ILD may be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0138] The power line contact portion SBC1 can be disposed on the interlayer insulating layer ILD and can be electrically connected to at least one power shorting bar SB1. For example, the power line contact portion SBC1 can be formed of the same material on the same layer as the source / drain electrodes of the thin film transistor. The buffer layer BF and the interlayer insulating layer ILD can be disposed between the power line contact portion SBC1 and the at least one power shorting bar SB1. The at least one power shorting bar SB1 and the power line contact portion SB1 can be electrically connected to each other via a contact hole that penetrates the buffer layer BF and the interlayer insulating layer ILD. For example, the power line contact portion SBC1 can be electrically connected to at least one power shorting bar SB1 that is spaced apart from each other in certain portions. In addition, the power line contact portion SBC1 can be electrically connected to a pixel power line VDDL extending along the first direction (or Y-axis direction) in the display area DA.

[0139] A first passivation layer PAS1 may be disposed on the interlayer insulating layer ILD on which the power line contact portion SBC1 is disposed. A second passivation layer PAS2 may be disposed on the first passivation layer PAS1. The first passivation layer PAS1 and the second passivation layer PAS2 may be formed to include a silicon oxide SiO X , silicon nitride SiN X , aluminum oxide Al2O3, or other inorganic insulating materials. For example, each of the first passivation layer PAS1 and the second passivation layer PAS2 may be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0140] A block pattern BP may be provided on the first passivation layer PAS1. For example, the block pattern BP may be provided at the intersection of at least one power shorting bar SB1 and the lower cut line UCL. For example, the block pattern BP may be provided between at least one lower cut line UCL and at least one power shorting bar SB1. Furthermore, the block pattern BP may be provided between at least one lower cut line UCL and the power line contact portion SBC1. The block pattern BP prevents damage to the power line contact portion SBC1 and the at least one power shorting bar SB1 by the etchant used to form the lower cut line UCL. For example, the block pattern BP may be formed of the same material as another signal line provided on the first passivation layer PAS1.

[0141] A planarization layer PLN for planarizing the step difference caused by the thin film transistor and the plurality of signal lines may be provided on the second passivation layer PAS2. The planarization layer PLN may be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first electrode, the organic light-emitting layer, and the second electrode of the light-emitting element, as well as the bank layer BA, may be provided on the planarization layer PLN. For example, the bank layer BA may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0142] At least one undercut line UCL in the pad area PA of the non-display area NDA on the substrate 111 may be configured using the planarization layer PLN and the second passivation layer PAS2. For example, the at least one undercut line UCL may be configured by removing at least a portion of the planarization layer PLN and the second passivation layer PAS2. The at least one undercut line UCL may include a first pattern line UCL_P1 formed of the same material as the planarization layer PLN, and a second pattern line UCL_P2 configured to support the first pattern line UCL_P1 and formed by removing at least a portion of the second passivation layer PAS2 to have an undercut area UCA below the first pattern line UCL_P1.

[0143] According to another exemplary embodiment of the present disclosure, the transparent display panel 110 may further include an organic pattern OP disposed on the substrate 111 around at least one lower cut line UCL that overlaps with at least one power shorting bar SB1 in the pad area PA of the non-display area NDA. For example, the organic pattern OP may be disposed on one side or the other side of the at least one lower cut line UCL. Alternatively, the organic pattern OP may be disposed between a plurality of adjacent lower cut lines UCL, but exemplary embodiments of the present disclosure are not limited thereto.

[0144] The organic pattern OP can reduce variations in voltage or current supplied through at least one power shorting bar SB1 disposed in the pad area PA of the non-display area NDA. For example, the organic pattern OP may include a first organic pattern OP_P1 formed from the same material as the planarization layer PLN and a second organic pattern OP_P2 formed from the same material as the bank layer BA. The organic pattern OP covers the upper portion of the at least one shorting bar SB1 having a predetermined thickness, thereby preventing noise caused by the voltage or current supplied through the at least one shorting bar SB1 from propagating to other signal lines.

[0145] Reference Figure 11 At least one power shorting bar SB2 may be disposed in the non-pad area NPA of the non-display area NDA on the substrate 111. The at least one power shorting bar SB2 may extend along the second direction (or the X-axis direction) in the non-pad area NPA. The at least one power shorting bar SB2 may be disposed to intersect and overlap with at least one lower tangent line UCL in the non-pad area NPA.

[0146] At least one power shorting bar SB2 may be disposed in the non-pad area NPA on the substrate 111. For example, the at least one power shorting bar SB2 may be a pixel power shorting bar SB2 connected to a pixel power line VDDL (or first power line) extending in the first direction (or Y-axis direction) in the display area DA and configured to provide a first power. The at least one power shorting bar SB2 disposed in the non-pad area NPA may be formed of the same material and on the same layer as the gate electrode of the thin film transistor, but exemplary embodiments of the present disclosure are not limited thereto. A gate insulating layer GI may be disposed between the at least one power shorting bar SB2 and the buffer layer BF.

[0147] At least one power shorting bar SB2 in the non-pad area NPA on the substrate 111 may be partially spaced apart to connect to other configurations in certain portions. The at least one power shorting bar SB2 may include a contact portion to be electrically connected to the pixel power line VDDL extending in the first direction (or Y-axis direction) in the display area DA.

[0148] An interlayer insulating layer ILD may be provided on the buffer layer BF on which at least one power shorting bar SB2 and the gate electrode of the thin film transistor are provided. The interlayer insulating layer ILD may be formed to include silicon oxide SiO X , silicon nitride SiN X, aluminum oxide Al2O3, or other inorganic insulating materials. For example, the interlayer insulating layer ILD may be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0149] The interlayer insulating layer ILD may include a power line contact portion SBC2 electrically connected to at least one power shorting bar SB2 .

[0150] For example, the power line contact portion SBC2 can be formed on the same layer as the source / drain electrodes of the thin film transistor from the same material. An interlayer insulating layer ILD can be provided between the power line contact portion SBC2 and the at least one power shorting bar SB2. The power line contact portion SBC2 and the at least one power shorting bar SB2 can be electrically connected to each other via a contact hole passing through the interlayer insulating layer ILD. For example, the power line contact portion SBC2 can be electrically connected to the power shorting bars SB2 that are spaced apart from each other in certain portions. In addition, the power line contact portion SBC2 can be electrically connected to the pixel power line VDDL extending along the first direction (or the Y-axis direction) in the display area DA.

[0151] A first passivation layer PAS1 may be provided on the interlayer insulating layer ILD on which the power line contact portion SBC2 is provided. A second passivation layer PAS2 may be provided on the first passivation layer PAS1. The first passivation layer PAS1 and the second passivation layer PAS2 may be formed to include a silicon oxide SiO X , silicon nitride SiN X , aluminum oxide Al2O3, or other inorganic insulating materials. For example, each of the first passivation layer PAS1 and the second passivation layer PAS2 may be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0152] The block pattern BP may be disposed on the first passivation layer PAS1. For example, the block pattern BP may be disposed at a portion where at least one power shorting bar SB2 and the lower cut line UCL intersect. For example, the block pattern BP may be disposed between at least one lower cut line UCL and at least one power shorting bar SB2. Furthermore, the block pattern BP may be disposed between at least one lower cut line UCL and the power line contact portion SBC2. The block pattern BP may prevent the etchant used when forming the lower cut line UCL from damaging the at least one power shorting bar SB2 and the power line contact portion SBC2. For example, the block pattern BP may be formed of the same material as another signal line formed on the first passivation layer PAS1.

[0153] A planarization layer PLN for planarizing the step difference caused by the thin film transistor and the plurality of signal lines may be provided on the second passivation layer PAS2. The planarization layer PLN may be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first electrode, the organic light-emitting layer, and the second electrode of the light-emitting element, as well as the bank layer BA, may be provided on the planarization layer PLN. For example, the bank layer BA may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0154] At least one undercut line UCL in the non-pad area NPA of the non-display area NDA on the substrate 111 can be configured using the planarization layer PLN and the second passivation layer PAS2. For example, the at least one undercut line UCL can be configured by removing at least a portion of the planarization layer PLN and the second passivation layer PAS2. The at least one undercut line UCL may include a first pattern line UCL_P1 formed of the same material as the planarization layer PLN, and a second pattern line UCL_P2 configured to support the first pattern line UCL_P1 and formed by removing at least a portion of the second passivation layer PAS2 to have an undercut area UCA below the first pattern line UCL_P1.

[0155] According to another exemplary embodiment of the present disclosure, the transparent display panel 110 may further include an organic pattern OP disposed on the substrate 111 around at least one lower cut line UCL that overlaps with at least one power shorting bar SB1 in the non-pad area NPA of the non-display area NDA. For example, the organic pattern OP may be disposed on one side or the other side of the at least one lower cut line UCL. Alternatively, the organic pattern OP may be disposed between a plurality of adjacent lower cut lines UCL, but exemplary embodiments of the present disclosure are not limited thereto.

[0156] The organic pattern OP can reduce variations in voltage or current supplied through at least one power shorting bar SB2 disposed in the non-pad area NPA of the non-display area NDA. For example, the organic pattern OP can include a first organic pattern OP_P1 formed from the same material as the planarization layer PLN and a second organic pattern OP_P2 formed from the same material as the bank layer BA. The organic pattern OP covers the upper portion of the at least one shorting bar SB2 having a predetermined thickness, thereby preventing noise caused by the voltage or current supplied through the at least one shorting bar SB2 from propagating to another signal line.

[0157] Figure 12 Another exemplary embodiment of the present disclosure is shown. Figure 7 Region C shown in FIG. Figure 13 According to another exemplary embodiment of the present disclosure, Figure 12 A cross-sectional view taken along line V-V' in FIG.

[0158] Figure 12 and Figure 13 By changing the reference Figures 1 to 11 The transparent display panel 110 is configured to be configured according to the configuration of at least one lower tangent line in the described transparent display panel 110. Therefore, in the following description, the same reference numerals are assigned to the same elements except for the changed configuration, and redundant descriptions thereof will be omitted or briefly described.

[0159] Reference Figure 12 and Figure 13 In the transparent display panel 110 according to another exemplary embodiment of the present disclosure, at least one lower tangent line UCL may be provided in the non-display area NDA and the display area DA. The at least one lower tangent line UCL may include at least one first lower tangent line UCL1 provided in the non-display area NDA and at least one second lower tangent line UCL2 provided in the display area DA. The at least one first lower tangent line UCL1 may be provided in parallel with the at least one second lower tangent line UCL2 in the first direction (or Y-axis direction) to extend to another line. The at least one second lower tangent line UCL2 may be provided to extend along the first direction (or Y-axis direction) in the transmission area TA of each pixel P provided in the display area DA. The at least one second lower tangent line UCL2 may be provided on one side and the other side in the second direction (or X-axis direction) in the transmission area TA.

[0160] At least one first lower tangent line UCL1 is set in the non-display area NDA, at least one second lower tangent line UCL2 is set in the display area DA, and the at least one first lower tangent line UCL1 and the at least one second lower tangent line UCL2 can be set on different lines parallel to the first direction (or Y-axis direction). At least one first lower tangent line UCL1 can be bent at least twice in the non-display area NDA and can be connected to at least one second lower tangent line UCL2. For example, at least one first lower tangent line UCL1 extends along the first direction (or Y-axis direction) in the non-display area NDA, then extends in a third direction (or diagonal direction) between the first direction (or Y-axis direction) and the second direction (or X-axis direction), and then bends along the first direction (or Y-axis direction) around the display area DA, whereby at least one first lower tangent line UCL1 can be set to extend on the same line as at least one second lower tangent line UCL2. For example, at least one first undercut line UCL1 may be arranged at a predetermined interval without overlapping the power line contact portions SBC1 and SBC2 in the non-display area NDA, and may be configured to extend along the same line as at least one second undercut line UCL2 arranged in the display area DA after bypassing the power line contact portions SBC1 and SBC2. For example, at least one first undercut line UCL1 may include an undercut connection pattern UCL1c extending in a third direction (or diagonal direction) in a portion adjacent to the at least one second undercut line UCL2. For example, the undercut connection pattern UCL1c may be arranged between the first undercut line UCL1 and the second undercut line UCL2.

[0161] The at least one first lower cut line UCL1 may be disposed symmetrically with each other in the pad area PA of the non-display area NDA and the non-pad area NPA of the non-display area NDA. For example, a portion of the at least one first lower cut line UCL1 disposed in the pad area PA and a portion of the at least one first lower cut line UCL1 disposed in the non-pad area NPA may be disposed on the same line as the display area DA interposed therebetween, but exemplary embodiments of the present disclosure are not limited thereto.

[0162] The at least one second lower cut line UCL2 may include a plurality of second lower cut lines UCL2 spaced apart from each other along the second direction (or X-axis direction) in the transmissive area TA of the display area DA. For example, the plurality of second lower cut lines UCL2 may be spaced apart from each other to have a first width W1 in the second direction (or X-axis direction).

[0163] The at least one first undercut line UCL1 may include a plurality of first undercut lines UCL1 spaced apart from one another along the second direction (or the X-axis direction) in the non-display area NDA. For example, the plurality of first undercut lines UCL1 may be spaced apart from one another to have a second width W2 in the second direction (or the X-axis direction). The second width W2 of the plurality of first undercut lines UCL1 may be equal to or less than the first width W1 of the plurality of second undercut lines UCL2. For example, the first width W1 of the plurality of second undercut lines UCL2 may be less than the width of the transmissive area TA of the display area DA in the second direction (or the X-axis direction), and the second width W2 of the plurality of first undercut lines UCL1 may be less than the first width W1 of the plurality of second undercut lines UCL2, but exemplary embodiments of the present disclosure are not limited thereto.

[0164] Reference Figure 13 In the pad area PA on the substrate 111 , at least one first undercut line UCL1 may be disposed to overlap with at least one power shorting bar SB1 and may be disposed not to overlap with a power line contact portion SB1 connected to the at least one power shorting bar SB1 .

[0165] At least one first undercut line UCL1 is disposed so as not to overlap with the power line contact portion SBC1, and a first passivation layer PAS1 is interposed therebetween, thereby preventing damage to the power line contact portion SBC1 during the formation of the at least one first undercut line UCL1. Therefore, the transparent display panel 110 according to another exemplary embodiment of the present disclosure prevents degradation of process reliability due to the formation of the at least one undercut line UCL1.

[0166] Figure 14 Another exemplary embodiment of the present disclosure is shown. Figure 7 Region C shown in FIG. Figure 15 According to another exemplary embodiment of the present disclosure, Figure 14 A cross-sectional view taken along line VI-VI'. Figure 14 and Figure 15 By changing the reference Figures 1 to 13 The transparent display panel 110 is configured to be configured according to the configuration of at least one lower tangent line in the described transparent display panel 110. Therefore, in the following description, the same reference numerals are assigned to the same elements except for the changed configuration, and redundant descriptions thereof will be omitted or briefly described.

[0167] Reference Figure 14 and Figure 15, a transparent display panel 110 according to another exemplary embodiment of the present disclosure may be provided in a non-display area NDA and a display area DA. The at least one lower tangent line UCL may include at least one first lower tangent line UCL1 provided in the non-display area NDA and at least one second lower tangent line UCL2 provided in the display area DA. The at least one second lower tangent line UCL2 may be provided to extend along the first direction (or Y-axis direction) in the transmission area TA of each pixel P provided in the display area DA. The at least one second lower tangent line UCL2 may be provided on one side and the other side along the second direction (or X-axis direction) in the transmission area TA. The at least one second lower tangent line UCL2 may include a plurality of second lower tangent lines UCL2 spaced apart from each other along the second direction (or X-axis direction) in the transmission area TA.

[0168] At least one first lower cut line UCL1 may be provided in the non-display area NDA and may be configured to be the same as or less than the number of the plurality of second lower cut lines UCL2. For example, the at least one first lower cut line UCL1 may be configured to be smaller in number than the plurality of second lower cut lines UCL2. The at least one first lower cut line UCL1 may be provided on the same line as any one of the plurality of second lower cut lines UCL2 along the first direction (or the Y-axis direction). For example, the at least one first lower cut line UCL1 may extend along the first direction (or the Y-axis direction) in the non-display area NDA and may be connected to one of the plurality of second lower cut lines UCL2 provided in the display area DA. For example, the at least one first lower cut line UCL1 may be configured to bypass the power line contact portions SBC1 and SBC2 of at least one power shorting bar SB1 and SB2 in the non-display area NDA. For example, at least one first lower cut line UCL1 may extend in a line that does not overlap with the power line contact portions SBC1 and SBC2 in the non-display area NDA, and may be configured to be connected to an lower cut line UCL2 among a plurality of second lower cut lines UCL2 that is disposed on a line that does not overlap with the power line contact portions SBC1 and SBC2.

[0169] For example, at least one first undercut line UCL1 may include an undercut connection pattern UCL1c that protrudes to connect to another undercut line UCL2 located on a portion adjacent to the plurality of second undercut lines UCL2. For example, the undercut connection pattern UCL1c may protrude from the at least one first undercut line UCL1 along the second direction (or the X-axis direction). The undercut connection pattern UCL1c may be disposed between the second undercut line UCL2 located on another line of the plurality of second undercut lines UCL2 and the first undercut line UCL1.

[0170] At least one first lower cut line UCL1 may be provided to extend along the same line on the pad area PA of the non-display area NDA and the non-pad area NPA of the non-display area NDA. For example, a portion of at least one first lower cut line UCL1 provided in the pad area PA and a portion of at least one first lower cut line UCL1 provided in the non-pad area NPA may be provided to extend along the same line with the display area DA interposed therebetween, but exemplary embodiments of the present disclosure are not limited thereto.

[0171] Reference Figure 15 In the pad area PA on the substrate 111 , at least one first undercut line UCL1 may be disposed to overlap with at least one power shorting bar SB1 and may be disposed not to overlap with a power line contact portion SB1 connected to the at least one power shorting bar SB1 .

[0172] At least one first undercut line UCL1 is disposed so as not to overlap with the power line contact portion SBC1, wherein the first passivation layer PAS1 is interposed between the at least one first undercut line UCL1 and the power line contact portion SBC1, thereby preventing damage to the power line contact portion SBC1 during the process of forming the at least one first undercut line UCL1. Therefore, the transparent display panel 110 according to another exemplary embodiment of the present disclosure prevents degradation of process reliability caused by forming the at least one undercut line UCL1.

[0173] Figure 16 A transparent display device according to another exemplary embodiment of the present disclosure is shown.

[0174] Reference Figure 16 According to another exemplary embodiment of the present disclosure, the transparent display panel 110 may include a display area DA in which pixels are configured to display an image and a non-display area NDA in which no image is displayed. For example, the non-display area NDA may be disposed at the periphery of the display area DA.

[0175] According to another exemplary embodiment of the present disclosure, the transparent display panel 110 may include at least one lower cut line extending to the non-display area NDA and the display area DA. For example, the at least one lower cut line UCL may be arranged to extend along the first direction (or Y-axis direction) in the non-display area NDA and the display area DA. For example, the at least one lower cut line UCL may extend from the non-display area NDA to the display area DA. In at least a portion of the non-display area NDA, the organic light-emitting layer constituting the light-emitting element may extend from the display area DA, and the at least one lower cut line UCL may extend from the portion of the organic light-emitting layer provided in the non-display area NDA to the display area DA. For example, the at least one lower cut line UCL may extend from the pad area PA of the non-display area NDA to pass through the display area DA, and may extend to the non-pad area NPA of the non-display area NDA.

[0176] The transparent display panel 110 may include a dam pattern DAM surrounding the display area DA in a plan view. The dam pattern DAM may be configured in a closed loop around the non-display area NDA at the periphery of the display area DA in a plan view. For example, the closed loop shape of the dam pattern DAM may be configured in a rectangular shape.

[0177] The transparent display panel 110 may include a plurality of gate drivers 205 a and 205 b , a source driver integrated circuit IC 210 , a flexible film 220 , a circuit board 230 , and a timing controller 240 .

[0178] Figure 17 A transparent display device according to another exemplary embodiment of the present disclosure is shown.

[0179] Reference Figure 17 According to another exemplary embodiment of the present disclosure, a transparent display panel 110 may include dam patterns DAM1 and DAM2 for dividing a display area DA into at least two or more areas. The dam patterns DAM1 and DAM2 may be configured in the form of a closed loop surrounding at least a portion of the non-display area NDA and the display area DA, such that the display area DA can be divided into the two or more areas DA. For example, the dam patterns DAM1 and DAM2 may include a first dam pattern DAM1 and a second dam pattern DAM2.

[0180] The first dam pattern DAM1 may be configured to surround the display area DA on the left side in the second direction (or X-axis direction), and the second dam pattern DAM2 may be configured to surround the display area DA on the right side in the second direction (or X-axis direction).

[0181] The first and second dam patterns DAM1 and DAM2 may be spaced apart from each other in the second direction (or X-axis direction). Alternatively, at least a portion of adjacent portions of the first and second dam patterns DAM1 and DAM2 may overlap each other.

[0182] The transparent display panel 110 may include a plurality of gate drivers 205a and 205b. For example, the plurality of gate drivers 205a and 205b may include a first gate driver 205a and a second gate driver 205b. The first gate driver 205a is arranged in the non-display area NDA located on the left side along the second direction (or the X-axis direction), and the second gate driver 205b is arranged in the non-display area NDA located on the right side along the second direction (or the X-axis direction). For example, the first dam pattern DAM1 may be provided to surround the first gate driver 205a and a portion on the left side of the display area DA, and the second dam pattern DAM2 may be provided to surround the second gate driver 205b and a portion on the right side of the display area DA.

[0183] The transparent display panel 110 may include first and second source driver integrated circuits IC 210a and 210b, first and second flexible films 220a and 220b, first and second circuit boards 230a and 230b, and first and second timing controllers 240a and 240b.

[0184] The first source driver IC 210a, the first flexible film 220a, the first circuit board 230a, and the first timing controller 240a may be connected to the left display area DA defined by the first dam pattern DAM1, and the second source driver IC 210b, the second flexible film 220b, the second circuit board 230b, and the second timing controller 240b may be connected to the left display area DA defined by the second dam pattern DAM2.

[0185] At least a portion of the first and second dam patterns DAM1 and DAM2 may be disposed parallel to at least one lower cut line UCL disposed in the non-display area NDA and the display area DA. For example, at least one lower cut line UCL may be disposed to overlap the first and second dam patterns DAM1 and DAM2.

[0186] A cutting portion CP may be provided between the first dam pattern DAM1 and the second dam pattern DAM2. The cutting portion CP may be a portion of the transparent display panel 110 that can be separated or cut using a cutting device such as a laser or a grinding wheel. Even if the cutting portion CP is cut, the transparent display panel 110 can ensure moisture penetration reliability due to at least one lower cut line UCL arranged parallel to the first and second dam patterns DAM1 and DAM2. Each of the first display area DA1 and the second display area DA2 surrounded by the first and second dam patterns DAM1 and DAM2 may be provided with a moisture penetration prevention structure via at least one lower cut line UCL. Each of the first and second display areas DA1 and DA2 may be independently provided as the first and second transparent display panels 110a and 110b by separation or cutting of the cutting portion CP.

[0187] The first dam pattern DAM1 and the second dam pattern DAM2 may be non-display areas NDA (or border areas) of the first and second transparent display panels 110a and 110b that are separated from each other. For example, the center portion of the display area DA where the first dam pattern DAM1 and the second dam pattern DAM2 intersect in the first direction (or Y-axis direction) may be the display area DA before the cutting process, but may also be the non-display area NDA (or border area) after the cutting process.

[0188] A transparent display apparatus according to one or more exemplary embodiments of the present disclosure will be described below.

[0189] According to one or more exemplary embodiments of the present disclosure, a transparent display device may include: a substrate including a display area and a non-display area, the display area being provided with a transmission area and a non-transmission area, the non-transmission area including a light-emitting area in which a light-emitting element is provided, and the non-display area being provided on the periphery of the display area; at least one power line, the at least one power line being provided in the non-transmission area of ​​the display area on the substrate and being configured to extend in a first direction; a power shorting bar, the power shorting bar being provided in the non-display area on the substrate, being electrically connected to the at least one power line, and extending in a second direction transversely intersecting the first direction; and at least one lower tangent line, the at least one lower tangent line being provided in the display area and the non-display area on the substrate and extending in the first direction.

[0190] According to one or more exemplary embodiments of the present disclosure, the transparent display device may further include: a passivation layer disposed above the substrate; and a planarization layer disposed on the passivation layer, wherein at least one undercut line includes a first pattern line and a second pattern line, the first pattern line is formed by patterning the planarization layer, and the second pattern line is formed by removing at least a portion of the passivation layer to have an undercut area below the first pattern line.

[0191] According to one or more exemplary embodiments of the present disclosure, a power shorting bar may include a plurality of slit structures.

[0192] According to one or more exemplary embodiments of the present disclosure, a power shorting bar may be configured to have a plurality of slit structures in a portion overlapping at least one power line.

[0193] According to one or more exemplary embodiments of the present disclosure, the transparent display apparatus may further include a block pattern provided at a portion where the at least one lower cut line and the at least one power line overlap each other.

[0194] According to one or more exemplary embodiments of the present disclosure, the transparent display device may further include an organic pattern covering an upper portion of the power shorting bar.

[0195] According to one or more exemplary embodiments of the present disclosure, the transparent display device may further include a planarization layer disposed above the substrate, and a dam layer disposed on the planarization layer, wherein the organic pattern includes a first organic pattern formed of the same material as the planarization layer and a second organic pattern formed of the same material as the dam layer.

[0196] According to one or more exemplary embodiments of the present disclosure, the at least one lower cut line may extend from the non-display area to the display area.

[0197] According to one or more exemplary embodiments of the present disclosure, the at least one lower cut line may be provided in the transmissive region of the display region.

[0198] According to one or more exemplary embodiments of the present disclosure, the organic light emitting element may include an organic light emitting layer, the organic light emitting element is configured to extend from the display area to at least a portion of the non-display area, and the at least one lower cut line may extend from the non-display area where the organic light emitting layer is provided to the display area.

[0199] According to one or more exemplary embodiments of the present disclosure, at least a portion of the at least one lower cut line may overlap with the power shorting bar in the non-display area.

[0200] According to one or more exemplary embodiments of the present disclosure, the at least one lower tangent line may include at least one first lower tangent line disposed in the non-display area and at least one second lower tangent line disposed in the transmissive area of ​​the display area.

[0201] According to one or more exemplary embodiments of the present disclosure, the at least one first lower tangent line may be arranged on the same line as the at least one second lower tangent line in the first direction.

[0202] According to one or more exemplary embodiments of the present disclosure, the at least one first lower tangent line may be provided on another line parallel to the at least one second lower tangent line along the first direction.

[0203] According to one or more exemplary embodiments of the present disclosure, the at least one first lower cut line may be bent at least twice in the non-display area and may be connected to the at least one second lower cut line.

[0204] According to one or more exemplary embodiments of the present disclosure, the at least one first lower cut line may be configured to detour a contact portion of the at least one power line and the power shorting bar in the non-display area.

[0205] According to one or more exemplary embodiments of the present disclosure, the at least one first lower cut line may not overlap with a contact portion of at least one power line and a power shorting bar in the non-display area and may be disposed adjacent to the at least one power line.

[0206] According to one or more exemplary embodiments of the present disclosure, the at least one second lower tangent line may be arranged on one side in the second direction in the transmission region, or may be arranged on the other side in the second direction.

[0207] According to one or more exemplary embodiments of the present disclosure, the at least one second lower tangent line may include a plurality of second lower tangent lines spaced apart from each other along the second direction in the transmission area, and the plurality of second lower tangent lines may be respectively disposed on one side and the other side along the second direction.

[0208] According to one or more exemplary embodiments of the present disclosure, the number of the at least one first lower tangent line may be equal to or smaller than the number of the plurality of second lower tangent lines.

[0209] According to one or more exemplary embodiments of the present disclosure, the at least one first lower tangent line may be disposed on the same line as any one of the plurality of second lower tangent lines along the first direction.

[0210] According to one or more exemplary embodiments of the present disclosure, the at least one first lower cut line may include a connection pattern protruding in the second direction, and the connection pattern may be connected to another one of the plurality of second lower cut lines and the at least one first lower cut line.

[0211] According to one or more exemplary embodiments of the present disclosure, the at least one first lower cut line may be provided to detour a contact portion of the at least one power line and the power shorting bar in the non-display area.

[0212] According to one or more exemplary embodiments of the present disclosure, it may further include at least one organic insulating layer on the substrate, and at least one inorganic insulating layer between the substrate and the at least one organic insulating layer, and at least one undercut line may be formed by removing at least a portion of the at least one inorganic insulating layer and the at least one organic insulating layer.

[0213] According to one or more exemplary embodiments of the present disclosure, the at least one undercut line may separate or disconnect the organic light emitting layer constituting the light emitting element.

[0214] According to one or more exemplary embodiments of the present disclosure, a block pattern provided at a portion where the at least one lower cut line and the power shorting bar overlap each other may be further included.

[0215] According to one or more exemplary embodiments of the present disclosure, a block pattern may be provided on at least one inorganic insulating layer between the at least one lower cut line and the power shorting bar.

[0216] According to one or more exemplary embodiments of the present disclosure, an organic pattern provided in a periphery of the at least one lower cut line overlapping the power shorting bar may be further included.

[0217] According to one or more exemplary embodiments of the present disclosure, the organic pattern may include at least a portion of the at least one organic insulating layer.

[0218] According to one or more exemplary embodiments of the present disclosure, a dummy electrode pattern provided in a periphery of the at least one lower cut line in the non-display area may be further included.

[0219] According to one or more exemplary embodiments of the present disclosure, the dummy electrode pattern may include the same material as the first electrode constituting the light emitting element.

[0220] According to one or more exemplary embodiments of the present disclosure, a dam pattern provided in a non-display area on the substrate may be further included.

[0221] According to one or more exemplary embodiments of the present disclosure, the dam pattern on the substrate may include a closed loop shape surrounding the non-display area in a plan view.

[0222] According to one or more exemplary embodiments of the present disclosure, at least a portion of the dam pattern may be disposed parallel to the at least one lower cut line.

[0223] According to one or more exemplary embodiments of the present disclosure, the at least one lower cut line may overlap with the dam pattern.

[0224] It is obvious to those skilled in the art that various modifications and variations can be made to the device of the present disclosure without departing from the scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the appended claims and their equivalents.

[0225] CROSS-REFERENCE TO RELATED APPLICATIONS

[0226] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0030283 filed in Korea on February 29, 2024, which is hereby expressly incorporated herein in its entirety for all purposes.

Claims

1. A transparent display device, comprising: a substrate comprising a display area and a non-display area, wherein the display area is provided with a transmissive area and a non-transmissive area, the non-transmissive area includes a light-emitting area provided with a light-emitting element, and the non-display area is provided at the periphery of the display area; at least one electric force line, the at least one electric force line being disposed on the substrate in the non-transmissive region of the display region, the at least one electric force line being configured to extend in a first direction; a power shorting bar, the power shorting bar being disposed in the non-display area on the substrate, the power shorting bar being electrically connected to the at least one power line, and the power shorting bar extending in a second direction transversely intersecting the first direction; and At least one lower cut line is provided on the substrate in the display area and the non-display area, and the at least one lower cut line extends in the first direction.

2. The transparent display device according to claim 1, further comprising: a passivation layer disposed above the substrate; as well as A planarization layer is provided on the passivation layer, The at least one undercut line includes a first pattern line and a second pattern line, the first pattern line is formed by patterning the planarization layer, and the second pattern line is formed by removing at least a portion of the passivation layer to have an undercut area below the first pattern line.

3. The transparent display device according to claim 1, wherein: The power shorting bar includes a plurality of slot structures. 4 . The transparent display device according to claim 3 , wherein the power shorting bar is configured to have the plurality of slit structures in a portion overlapping with the at least one power line. 5 . The transparent display apparatus according to claim 1 , further comprising a block pattern provided at a portion where the at least one lower cut line and the at least one electric power line overlap each other. 6 . The transparent display device according to claim 1 , further comprising an organic pattern covering an upper portion of the power shorting bar.

7. The transparent display device according to claim 6, further comprising: a planarization layer disposed above the substrate; as well as a bank layer provided on the planarization layer, The organic pattern includes a first organic pattern formed of the same material as the planarization layer and a second organic pattern formed of the same material as the bank layer.

8. The transparent display device according to claim 1, wherein: The at least one lower cut line extends from the non-display area to the display area.

9. The transparent display device according to claim 1, wherein: The at least one lower tangent line is provided in the transmission area in the display area.

10. The transparent display device according to claim 1, in, The light emitting element includes an organic light emitting layer, and the organic light emitting layer is arranged to extend from the display area to at least a portion of the non-display area, and The at least one lower cutting line extends from the non-display area where the organic light-emitting layer is provided to the display area.

11. The transparent display device according to claim 1, wherein: At least a portion of the at least one lower cut line overlaps the power shorting bar in the non-display area.

12. The transparent display device according to claim 1, in, The at least one lower tangent line comprises: at least one first lower tangent line, the at least one first lower tangent line being disposed in the non-display area; and At least one second lower tangent line is provided in the transmission area of ​​the display area.

13. The transparent display device according to claim 12, wherein: The at least one first lower tangent line is arranged along the same line as the at least one second lower tangent line in the first direction.

14. The transparent display device according to claim 12, wherein: The at least one first lower tangent line is disposed on another line parallel to the at least one second lower tangent line along the first direction.

15. The transparent display device according to claim 14, wherein: The at least one first lower tangent line is bent at least twice in the non-display area and is connected to the at least one second lower tangent line.

16. The transparent display device according to claim 15, in, The at least one first lower cut line is configured to bypass a contact portion between the at least one power line and the power shorting bar in the non-display area.

17. The transparent display device according to claim 12, wherein: The at least one first lower cut line does not overlap with a contact portion of the power shorting bar and the at least one power line in the non-display area and is disposed adjacent to the at least one power line.

18. The transparent display device according to claim 12, wherein: The at least one second lower tangent line is arranged on one side of the transmission region along the second direction, or on the other side along the second direction.

19. The transparent display device according to claim 12, wherein: The at least one second lower tangent line includes a plurality of second lower tangent lines spaced apart from each other along the second direction in the transmission area, and the plurality of second lower tangent lines are respectively disposed on one side and the other side in the second direction.

20. The transparent display device according to claim 19, wherein: The number of the at least one first lower tangent line is equal to or smaller than the number of the plurality of second lower tangent lines.

21. The transparent display device according to claim 20, wherein: The at least one first lower tangent line and any one of the plurality of second lower tangent lines are arranged on the same line along the first direction.

22. The transparent display device according to claim 21, in, The at least one first lower cut line includes a connection pattern protruding in the second direction, and The connection pattern is connected to the plurality of second undercut lines and another one of the at least one first undercut line.

23. The transparent display device according to claim 22, wherein: The at least one first lower cut line is arranged to bypass a contact portion between the at least one power line and the power shorting bar in the non-display area.

24. The transparent display device according to claim 1, further comprising: at least one organic insulating layer, the at least one organic insulating layer being located on the substrate; as well as at least one inorganic insulating layer, the at least one inorganic insulating layer being located between the substrate and the at least one organic insulating layer, The at least one undercut line is formed by removing at least a portion of the at least one inorganic insulating layer and the at least one organic insulating layer.

25. The transparent display device according to claim 24, wherein: The at least one undercut line separates or breaks the organic light emitting layer constituting the light emitting element. 26 . The transparent display apparatus of claim 24 , further comprising a block pattern provided at a portion where the at least one lower cut line and the power shorting bar overlap each other.

27. The transparent display device according to claim 26, wherein: The block pattern is disposed on the at least one inorganic insulating layer between the at least one lower cut line and the power shorting bar. 28 . The transparent display device of claim 26 , further comprising an organic pattern provided in a periphery of the at least one lower cut line overlapping the power shorting bar.

29. The transparent display device according to claim 28, wherein: The organic pattern includes at least a portion of the at least one organic insulating layer. 30 . The transparent display device of claim 1 , further comprising a dummy electrode pattern disposed in a periphery of the at least one lower cut line disposed in the non-display area.

31. The transparent display device according to claim 30, wherein: The dummy electrode pattern includes the same material as that of the first electrode constituting the light emitting element. 32 . The transparent display device of claim 1 , further comprising a dam pattern provided in the non-display area on the substrate. 33 . The transparent display device of claim 32 , wherein the dam pattern on the substrate comprises a closed loop shape surrounding the non-display area in a plan view.

34. The transparent display device according to claim 33, wherein: At least a portion of the dam pattern is disposed parallel to the at least one lower cut line.

35. The transparent display device according to claim 34, wherein: The at least one lower cut line overlaps the dam pattern.

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