Chip thermal resistance and over-temperature protection temperature testing system, method, device and medium

Abstract

The present disclosure relates to the technical field of chip testing, and particularly relates to a chip thermal resistance and over-temperature protection temperature testing system, method, device and medium, the testing system comprising: a direct current power supply for supplying power to a chip to be tested; an electronic load for providing a load for the chip to be tested; a controllable thermostat for providing an environmental temperature for the chip to be tested to work; a computing device for obtaining a chip power consumption of the chip to be tested at a time point before over-temperature protection occurs under a predetermined environmental temperature after the controllable thermostat is at the predetermined environmental temperature and the electronic load is gradually increased from 0 until over-temperature protection occurs in the chip to be tested; and after obtaining n corresponding chip power consumptions under n predetermined environmental temperatures from a data acquisition module, calculating a chip thermal resistance and a final over-temperature protection temperature based on the n predetermined environmental temperatures and the n corresponding chip power consumptions. The technical scheme has high testing precision, simple, stable, reliable and low-cost testing lines, and is mainly used for testing chip thermal resistance and over-temperature protection temperature.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing technology, specifically to a chip thermal resistance and over-temperature protection temperature testing system, method, apparatus and medium. Background Technology

[0002] Temperature is a crucial factor affecting chip performance. In practical applications, the internal temperature of a chip is influenced by parameters such as its power consumption, ambient temperature, and thermal resistance. Chip thermal resistance is an important parameter characterizing chip thermal performance. Over-temperature protection temperature ensures the safe operation of the chip under extreme temperatures. Generally, chips are designed with internal temperature protection circuits that automatically activate over-temperature protection when the internal temperature exceeds the over-temperature protection temperature. Therefore, chip thermal resistance and over-temperature protection temperature are two important test indicators for chip testing.

[0003] Chip thermal resistance is generally estimated by chip packaging companies based on simulations of package type, material, volume, etc., which deviates significantly from the actual value. Currently, a more accurate method for testing thermal resistance is to measure it using professional instruments such as thermal resistance testers. These testers can utilize the characteristics of the chip's diodes and take into account factors such as ambient temperature and power consumption to obtain the chip's thermal resistance. However, this method is complex and costly.

[0004] The over-temperature protection temperature of a chip is typically determined by applying ambient temperature to an incubator and measuring the temperature at which the chip requires over-temperature protection. However, this testing method is limited by the temperature range of the incubator; laboratory incubators usually operate at a maximum temperature between 150°C and 180°C. Therefore, it is not suitable for measuring over-temperature protection at higher temperatures. Summary of the Invention

[0005] To address the problems in the related technologies, this disclosure provides a testing system, method, apparatus, and medium for chip thermal resistance and over-temperature protection temperature.

[0006] In a first aspect, this disclosure provides a chip thermal resistance and over-temperature protection temperature testing system, comprising:

[0007] The chip under test is equipped with an over-temperature protection circuit, which activates over-temperature protection when it detects that the temperature of the chip under test reaches the initial over-temperature protection temperature.

[0008] A test board is connected to the chip under test and is used to put the chip under test into a normal working state.

[0009] A DC power supply, connected to the test board, is used to power the chip under test;

[0010] An electronic load, connected to the test board, is used to provide a load for the chip under test;

[0011] A controllable temperature chamber is used to provide the ambient temperature for the chip under test to operate, and the test board connected to the chip under test is placed inside the controllable temperature chamber;

[0012] A computing device is configured to: ...

[0013] The computing device is specifically used for:

[0014] The chip's thermal resistance Rjc and final over-temperature protection temperature T are calculated using the following formulas:

[0015] P = (T-TA) / Rjc;

[0016] Where TA is the predetermined ambient temperature and P is the chip power consumption.

[0017] In one possible implementation, the computing device is specifically used for:

[0018] The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted using the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0019] In one possible implementation, the computing device is specifically used for:

[0020] The input voltage, input current, output voltage, and output current of the chip under test are obtained at the moment before the over-temperature protection occurs; based on the input voltage, input current, output voltage, and output current, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs is calculated.

[0021] In one possible implementation, both the power input terminal and the ground terminal of the test board support Kelvin connection. When the DC power supply also supports Kelvin connection, the voltage output by the DC power supply is used as the input voltage of the chip under test.

[0022] When the DC power supply does not support Kelvin connection, the test system further includes a first voltage measuring instrument, which is connected to the chip under test and is used to measure the input voltage of the chip under test.

[0023] In one possible implementation, when the DC power supply supports current measurement, the current output by the DC power supply measured by the DC power supply is used as the input current of the chip under test.

[0024] When the DC power supply does not support current measurement, the test system further includes a first current measuring instrument, which is connected to the chip under test and is used to measure the input current of the chip under test.

[0025] In one possible implementation, when the electronic load supports current measurement, the current input to the electronic load measured by the electronic load is used as the output current of the chip under test.

[0026] When the electronic load does not support current measurement, the test system further includes a second current meter, which is connected to the chip under test and is used to measure the output current of the chip under test.

[0027] In one possible implementation, the test system further includes a second voltage measuring instrument;

[0028] The second voltage measuring instrument is connected to the chip under test and is used to measure the output voltage of the chip under test.

[0029] In one possible implementation, if the controllable constant temperature chamber has a temperature measurement function, the controllable constant temperature chamber controls the temperature inside the controllable constant temperature chamber to be at a predetermined ambient temperature based on the temperature measurement function of the controllable constant temperature chamber.

[0030] If the controllable constant temperature chamber does not have a temperature measurement function, the test system further includes a temperature measurement module located inside the controllable constant temperature chamber for measuring the temperature inside the chamber. The controllable constant temperature chamber is connected to the temperature measurement module and is used to control the temperature inside the controllable constant temperature chamber to a predetermined ambient temperature based on the temperature measured by the temperature measurement module.

[0031] In one possible implementation, the chip under test includes a power supply chip.

[0032] Secondly, embodiments of this disclosure provide a method for testing the thermal resistance and over-temperature protection temperature of a chip, including:

[0033] Obtain the chip power consumption of the chip under test at the moment before the over-temperature protection occurs at the predetermined ambient temperature;

[0034] After obtaining the chip power consumption corresponding to n predetermined ambient temperatures, the chip thermal resistance and the final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

[0035] In one possible implementation, the step of calculating the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions includes:

[0036] The chip's thermal resistance Rjc and final over-temperature protection temperature T are calculated using the formula P = (T-TA) / Rjc, where TA is the predetermined ambient temperature and P is the chip's power consumption.

[0037] In one possible implementation, the calculation of the chip thermal resistance Rjc and the final over-temperature protection temperature T according to the formula P = (T-TA) / Rjc includes:

[0038] The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted using the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0039] In one possible implementation, obtaining the chip power consumption of the chip under test at the moment before over-temperature protection occurs at a predetermined ambient temperature includes:

[0040] Obtain the input voltage, input current, output voltage, and output current of the chip under test at the moment before the over-temperature protection occurs;

[0041] Based on the input voltage, input current, output voltage, and output current, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs is calculated.

[0042] Thirdly, embodiments of this disclosure provide a testing apparatus for chip thermal resistance and over-temperature protection temperature, comprising:

[0043] The acquisition module is configured to acquire the chip power consumption of the chip under test at the moment before the over-temperature protection occurs at a predetermined ambient temperature.

[0044] The parameter calculation module is configured to, after obtaining the chip power consumption corresponding to n predetermined ambient temperatures, calculate the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

[0045] In one possible implementation, the parameter calculation module is configured as follows:

[0046] The chip's thermal resistance Rjc and final over-temperature protection temperature T are calculated using the formula P = (T-TA) / Rjc, where TA is the predetermined ambient temperature and P is the chip's power consumption.

[0047] In one possible implementation, the parameter calculation module is configured as follows:

[0048] The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted using the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0049] In one possible implementation, the acquisition module is configured as follows:

[0050] Obtain the input voltage, input current, output voltage, and output current of the chip under test at the moment before the over-temperature protection occurs;

[0051] Based on the input voltage, input current, output voltage, and output current, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs is calculated.

[0052] Fourthly, this disclosure provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the method as described in any one of the second aspects.

[0053] According to the technical solution provided in this disclosure, the chip under test (DUT) has an over-temperature protection function. A test board is connected to the DUT to ensure it is in normal working condition. A DC power supply is connected to the test board to power the DUT. An electronic load is connected to the test board to provide a load to the DUT. A controllable temperature chamber provides the ambient temperature for the DUT's operation, and the test board connected to the DUT is placed inside the controllable temperature chamber. A computing device is used to acquire the chip power consumption of the DUT at the moment before the over-temperature protection occurs at the predetermined ambient temperature, while the electronic load gradually increases from 0 until the DUT experiences over-temperature protection. After acquiring the chip power consumption corresponding to n predetermined ambient temperatures from the data acquisition module, the device... The chip thermal resistance and final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and their corresponding n chip power consumptions. By utilizing the characteristic that the power consumption of the chip under test increases with the increase of electronic load and the over-temperature protection function of the chip under test itself, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs under different predetermined ambient temperatures and different loads is tested. The chip thermal resistance and final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and their corresponding n chip power consumptions. The chip thermal resistance and final over-temperature protection temperature obtained by this test system are highly accurate, highly operable, and have low testing costs. Moreover, by calculating the chip thermal resistance and final over-temperature protection temperature using multiple n predetermined ambient temperatures and their corresponding n chip power consumptions, it is possible to measure the chip under test whose operating temperature exceeds the temperature chamber temperature, without being limited by the temperature chamber temperature range.

[0054] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0055] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. The following is a description of the accompanying drawings.

[0056] Figure 1 This diagram illustrates a structural block diagram of a chip thermal resistance and over-temperature protection temperature testing system according to an embodiment of the present disclosure.

[0057] Figure 2 This diagram illustrates a structural block diagram of another chip thermal resistance and over-temperature protection temperature testing system provided according to an embodiment of the present disclosure.

[0058] Figure 3 The flowchart illustrates a method for testing chip thermal resistance and over-temperature protection temperature according to an embodiment of this disclosure.

[0059] Figure 4 This diagram illustrates a structural block diagram of a chip thermal resistance and over-temperature protection temperature testing apparatus according to an embodiment of the present disclosure.

[0060] Figure 5 A schematic diagram of the structure of a computer system suitable for implementing the methods of the embodiments of this disclosure is shown. Detailed Implementation

[0061] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of exemplary embodiments have been omitted from the drawings.

[0062] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0063] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0064] Figure 1 This diagram illustrates a structural block diagram of a chip thermal resistance and over-temperature protection temperature testing system according to an embodiment of the present disclosure. Figure 1As shown, the testing system includes: a chip under test 101, a test board 102, a DC power supply 103, an electronic load 104, a controllable constant temperature chamber 105, and a computing device 100.

[0065] In one possible implementation, the chip under test 101 has an over-temperature protection function. The initial over-temperature protection temperature of the chip under test 101 can be pre-simulated and tested. A temperature protection circuit is installed within the chip under test 101. When the internal temperature of the chip is detected to be higher than the initial over-temperature protection temperature, the temperature protection circuit automatically activates the over-temperature protection, thus realizing the over-temperature protection function of the chip under test 101. In this embodiment, the chip under test 101 is mainly a power supply chip.

[0066] In one possible implementation, the test board 102 is connected to the chip under test 101, which can be placed on the test board 102 and electrically connected to the test board 102. The test board 102 can enable the chip under test 101 to be in normal working condition.

[0067] In one possible implementation, both the DC power supply 103 and the electronic load 104 are connected to the test board 102. The DC power supply 103 can supply power to the chip under test 101 through the circuit on the test board 102, and the electronic load 104 can provide a load to the chip under test 101 through the circuit on the test board 102.

[0068] In one possible implementation, the controllable temperature chamber 105 can provide the ambient temperature for the chip under test 101 to operate. During testing, the test board 102 connected to the chip under test 101 is placed inside the controllable temperature chamber 105, which provides a constant ambient temperature.

[0069] In one possible implementation, the specific testing process may involve controlling the controllable constant temperature chamber 105 to be at a predetermined ambient temperature, and controlling the electronic load 104 to gradually increase from 0 until the chip under test 101 experiences over-temperature protection, so as to obtain the chip power consumption of the chip under test 101 at the moment before the over-temperature protection occurs.

[0070] It should be noted that the temperature control within the controllable thermostat 105 and the electronic load 104 can be manually controlled by the tester. For example, the controllable thermostat 105 can be equipped with a temperature selection button, which the tester can operate to control the controllable thermostat 105 to maintain a predetermined ambient temperature; the electronic load 104 can be equipped with an operation button, which the tester can operate to control the electronic load 104 to gradually increase from 0. Alternatively, the temperature control within the controllable thermostat 105 and the electronic load 104 can be controlled by a control device. When controlled by a control device, the control device can be connected to the controllable thermostat 105 and the electronic load 104 through corresponding ports. In this way, the control device can send control commands to the controllable thermostat 105 and the electronic load 104 through the corresponding ports to control the controllable thermostat 105 to maintain a predetermined ambient temperature and to control the electronic load 104 to gradually increase from 0.

[0071] In one possible implementation, assuming that no over-temperature protection occurs at time t under a predetermined ambient temperature, but over-temperature protection occurs at time t1, the chip power consumption of the chip under test 101 at time t is obtained as the chip power consumption corresponding to that predetermined ambient temperature. This allows obtaining the chip power consumption corresponding to n predetermined ambient temperatures. After obtaining the chip power consumption corresponding to n predetermined ambient temperatures, the chip thermal resistance and the final over-temperature protection temperature can be calculated based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

[0072] In one possible implementation, the predetermined ambient temperature can be determined based on the chip's operating temperature range and the temperature range of the controllable temperature chamber 105. This can result in n predetermined ambient temperatures TA1, TA2, TA3, ..., TAN (n being an integer greater than or equal to 2). Preferably, these n predetermined ambient temperatures TA1, TA2, TA3, ..., TAN can be an arithmetic sequence. It should be noted that if the chip's operating temperature exceeds the temperature range of the controllable temperature chamber 105, then n temperature values ​​within the higher temperature range of the controllable temperature chamber 105 can be selected as the predetermined ambient temperature.

[0073] In one possible implementation, the electronic load 104 can be controlled to gradually increase from 0 at each of the n predetermined ambient temperatures TA1, TA2, TA3, ..., TAn, until the chip under test 101 experiences over-temperature protection, so that the computing device 100 can obtain the chip power consumption P1, P2, P3, ..., Pn of the chip under test 101 at the moment before the over-temperature protection occurs.

[0074] In one possible implementation, the computing device 100 can calculate the chip's thermal resistance Rjc and the final over-temperature protection temperature T based on the relationship between the chip's thermal resistance Rjc and the final over-temperature protection temperature T, the ambient temperature TA, and the power consumption P of multiple chips corresponding to the ambient temperature TA. It can substitute n predetermined ambient temperatures TA1, TA2, TA3, ..., TAn and n chip power consumption P1, P2, P3, ..., Pn into the relationship between TA and P in the relationship to calculate the chip's thermal resistance Rjc and the final over-temperature protection temperature T.

[0075] In this embodiment, the chip under test (DUT) 101 has an over-temperature protection function. A test board 102 is connected to the DUT 101 to ensure the DUT 101 is in normal working condition. A DC power supply 103 is connected to the test board 102 to power the DUT 101. An electronic load 104 is connected to the test board 102 to provide a load to the DUT 101. A controllable temperature chamber 105 provides the ambient temperature for the DUT 101 to operate at, and the test board 102 connected to the DUT 101 is placed inside the controllable temperature chamber 105. A computing device 100 is used to obtain the chip power consumption of the DUT 101 at the moment before the over-temperature protection occurs at the predetermined ambient temperature, while the electronic load 104 gradually increases from 0 until the DUT 101 experiences over-temperature protection. The device then calculates the power consumption of the DUT 101 at the data... After acquiring the chip power consumption corresponding to n predetermined ambient temperatures, the acquisition module calculates the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions. By utilizing the characteristic that the power consumption of the chip under test increases with the increase of electronic load and the over-temperature protection function of the chip under test itself, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs under different predetermined ambient temperatures and different loads is tested. The chip thermal resistance and the final over-temperature protection temperature are calculated using the n predetermined ambient temperatures and their corresponding n chip power consumptions. This test system provides high accuracy in obtaining the chip thermal resistance and the final over-temperature protection temperature, is highly operable, and has low testing costs. Moreover, by calculating the chip thermal resistance and the final over-temperature protection temperature using multiple n predetermined ambient temperatures and their corresponding n chip power consumptions, it can also measure the chip under test whose operating temperature exceeds the temperature chamber temperature, without being limited by the temperature chamber temperature range.

[0076] In one possible implementation, the computing device 100 calculates the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, including:

[0077] The chip's thermal resistance Rjc and final over-temperature protection temperature T are calculated using the following formulas:

[0078] P = (T-TA) / Rjc;

[0079] Where TA is the predetermined ambient temperature and P is the chip power consumption.

[0080] In this embodiment, in P = (T-TA) / Rjc, TA is the predetermined ambient temperature, which is the independent variable, and P is the chip power consumption, which is the dependent variable. n=2 predetermined ambient temperatures and their corresponding n=2 chip power consumptions P can be obtained by testing. Substituting these two predetermined ambient temperatures TA and their corresponding two chip power consumptions P into the formula P = (T-TA) / Rjc, the two linear equations can be solved to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0081] In one possible implementation, the computing device 100 calculates the chip thermal resistance Rjc and the final over-temperature protection temperature T according to the following formula: P = (T-TA) / Rjc, including:

[0082] The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted using the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0083] In this embodiment, when n is greater than 2, the independent variable TA and the dependent variable P in the formula P = (T-TA) / Rjc may not satisfy a linear relationship due to measurement errors or other reasons. In this case, in order to more accurately calculate the chip thermal resistance Rjc and the final over-temperature protection temperature T, the independent variable TA and the dependent variable P can be fitted with a straight line to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T in P = (T-TA) / Rjc. Optionally, the least squares method can be used for straight line fitting. Of course, other algorithms can also be used for fitting, and there are no restrictions here.

[0084] In one possible implementation, the chip power consumption of the chip under test 101 at the moment before the computing device 100 experiences over-temperature protection at a predetermined ambient temperature includes:

[0085] The input voltage, input current, output voltage, and output current of the chip under test 101 at the moment before the over-temperature protection occurred are obtained; based on the input voltage, input current, output voltage, and output current, the chip power consumption of the chip under test 101 at the moment before the over-temperature protection occurred is calculated.

[0086] In this embodiment, during the test, the input voltage, input current, output voltage, and output current of the chip under test 101 can be continuously collected. Thus, after the chip under test 101 experiences over-temperature protection, the computing device 100 can obtain the input voltage V of the chip under test 101 at the moment preceding the over-temperature protection event. IN Input current I IN Output voltage V OUTand output current I OUT And according to the formula P= V IN× I IN -V OUT× I OUT The chip power consumption P of the chip under test 101 at the moment before the over-temperature protection occurs is calculated.

[0087] In one possible implementation, the input voltage of the chip under test 101 can be measured in the following two ways:

[0088] The first method is: when both the power input terminal and the ground terminal of the test board 102 support Kelvin connection, and the DC power supply 103 also supports Kelvin connection, the voltage output by the DC power supply 103 is used as the input voltage of the chip under test 101.

[0089] Here, Kelvin connection is a four-wire connection method for highly accurate measurement of parameters such as resistance and voltage. In chip testing, Kelvin connection is a method to improve measurement accuracy by reducing the resistance of the test system. In this embodiment, the DC power supply 103 needs to be connected to the chip under test 101 through wires on the test board 102 to supply power to the chip under test 101. Due to the existence of DC impedance of the wires, the supply voltage of the DC power supply 103 will drop. To avoid this situation, in this embodiment, both the power input terminal and the ground terminal of the test board 102 support Kelvin connection, and the DC power supply 103 also supports Kelvin connection. This eliminates the influence of voltage drop generated on the wires in the circuit, and allows the voltage provided by the DC power supply 103 to be output to the chip under test 101 without a significant voltage drop. Therefore, in this embodiment, the voltage output by the DC power supply 103 can be directly used as the input voltage of the chip under test 101. The voltage output by the DC power supply 103 is a fixed value that can be manually input to the computing device 100 by the tester.

[0090] The second method is: when the DC power supply 103 does not support Kelvin connection, such as Figure 2 As shown, the test system also includes a first voltage measuring instrument 106, which is connected to the chip under test 101 and is used to measure the input voltage of the chip under test 101.

[0091] Here, if the DC power supply 103 does not support Kelvin connection, the supply voltage of the DC power supply 103 will drop due to the DC impedance of the wires. The input voltage obtained by the chip under test 101 will be lower than the output voltage of the DC power supply. At this time, a first voltage measuring instrument 106 can be connected to the chip under test 101 (such as connected to the voltage input terminal and ground terminal of the chip under test 101) to measure the input voltage of the chip under test 101. The first voltage measuring instrument 106 can be a multimeter, voltmeter or other instrument that can measure voltage.

[0092] It should be noted that the input voltage of the chip under test 101 measured by the first voltage measuring instrument 106 can be manually input to the computing device 100 by the tester, or the computing device 100 can be connected to the first voltage measuring instrument 106 and the first voltage measuring instrument 106 can send the voltage to the computing device 100.

[0093] In one possible implementation, the input current of the chip under test 101 can be measured in the following two ways:

[0094] The first measurement method is: when the DC power supply 103 supports current measurement, the current output by the DC power supply 103 is measured by the DC power supply 103 as the input current of the chip under test 101.

[0095] The second measurement method is: when the DC power supply 103 does not support current measurement, the test system further includes a first current measuring instrument 107, which is connected to the chip under test 101 and is used to measure the input current of the chip under test 101.

[0096] Here, some DC power supplies 103 support current measurement, allowing the measurement of the output current of the DC power supply 103. This measured output current can be used as the input current of the chip under test 101. It should be noted that the DC power supply 103 can measure and display the input current of the chip under test 101. This input current can be manually input to the computing device 100 by the tester, or the computing device 100 can be connected to the DC power supply 103, with the DC power supply 103 sending the input current to the computing device 100.

[0097] Here, some DC power supplies 103 do not support current measurement. The test system also includes a first current measuring instrument 107, which can be connected to the chip under test 101 (e.g., connected to any point between the chip under test 101 and the DC power supply 103) to measure the input current of the chip under test 101. The first current measuring instrument 107 can be a multimeter, current sensor, or other instrument capable of measuring current. It should be noted that the input current of the chip under test 101 measured by the first current measuring instrument 107 can be manually input to the computing device 100 by the tester, or the computing device 100 can be connected to the first current measuring instrument 107, and the first current measuring instrument 107 can send the data to the computing device 100.

[0098] In one possible implementation, the output current of the chip under test 101 can be measured in the following two ways:

[0099] The first measurement method is as follows: when the electronic load 104 supports current measurement, the current input to the electronic load 104 measured by the electronic load 104 is used as the output current of the chip under test 101.

[0100] The second measurement method is as follows: when the electronic load 104 does not support current measurement, the test system further includes a second current measuring instrument 108, which is connected to the chip under test 101 and is used to measure the output current of the chip under test 101.

[0101] Here, some electronic loads 104 support current measurement, which can measure the current input to the electronic load 104. The current measured by the electronic load 104 can be used as the output current of the chip under test 101. It should be noted that the electronic load 104 can measure and display the output current of the chip under test 101. The tester can manually input the output current to the computing device 100, or the computing device 100 can be connected to the electronic load 104, and the DC power supply 103 can send the output current to the computing device 100.

[0102] Here, some electronic loads 104 do not support current measurement. The test system also includes a second current meter 108, which can be connected to the chip under test 101 (e.g., connected to any point between the chip under test 101 and the load) to measure the output current of the chip under test 101. The second current meter 108 can be a multimeter, current sensor, or other instrument capable of measuring current. It should be noted that the output current of the chip under test 101 measured by the second current meter 108 can be manually input to the computing device 100 by the tester, or the computing device 100 can be connected to the second current meter 108, and the second current meter 108 can send the data to the computing device 100.

[0103] In one possible implementation, the output voltage of the chip under test 101 can be measured using a second voltage measuring instrument 109. The test system also includes a second voltage measuring instrument 109; the second voltage measuring instrument 109 is connected to the chip under test 101 and is used to measure the output voltage of the chip under test 101.

[0104] Here, a second voltage measuring instrument 109 can be connected to the chip under test 101 (e.g., connected to the voltage output terminal and ground terminal of the chip under test 101) to measure the output voltage of the chip under test 101. The second voltage measuring instrument 109 can be a multimeter, voltmeter, or other instrument capable of measuring voltage. It should be noted that the output voltage of the chip under test 101 measured by the second voltage measuring instrument 109 can be manually input to the computing device 100 by the tester, or the computing device 100 can be connected to the second voltage measuring instrument 109, and the second voltage measuring instrument 109 can send the data to the computing device 100.

[0105] In one possible implementation, if the controllable constant temperature chamber 105 has a temperature measurement function, the temperature inside the controllable constant temperature chamber 105 is adjusted based on the temperature measurement function of the controllable constant temperature chamber 105.

[0106] If the controllable constant temperature chamber 105 does not have a temperature measurement function, the test system further includes a temperature measurement module 110, which is located inside the controllable constant temperature chamber 105 and is used to measure the temperature inside the controllable constant temperature chamber 105.

[0107] Here, some controllable temperature chambers 105 have temperature measurement functions, while others do not. If the controllable temperature chamber 105 is equipped with a temperature sensor or other temperature measurement module 110, and thus has a temperature measurement function, the controllable temperature chamber 105 can regulate its internal temperature based on this function to maintain a predetermined ambient temperature. If the controllable temperature chamber 105 does not have a temperature measurement function, the testing system further includes a temperature measurement module 110, which is placed inside the controllable temperature chamber 105 to measure its internal temperature. The controllable temperature chamber 105 is connected to the temperature measurement module 110, and can control its internal temperature to maintain a predetermined ambient temperature based on the temperature measured by the module. For example, the controllable temperature chamber 105 can raise its temperature if the measured temperature is below the predetermined ambient temperature, or lower its temperature if the measured temperature is above the predetermined ambient temperature.

[0108] This disclosure provides a method for testing the thermal resistance and over-temperature protection temperature of a chip. Figure 3 This diagram illustrates a flowchart of a method for testing chip thermal resistance and over-temperature protection temperature according to an embodiment of this disclosure. Figure 3 As shown, the test method for the chip's thermal resistance and over-temperature protection temperature includes the following steps S301-S302:

[0109] In step S301, the chip power consumption of the chip under test is obtained at the moment before the over-temperature protection occurs at the predetermined ambient temperature.

[0110] In step S302, after obtaining the chip power consumption corresponding to n predetermined ambient temperatures, the chip thermal resistance and the final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

[0111] In one possible implementation, the method for testing chip thermal resistance and over-temperature protection temperature is applicable to electronic devices such as computers and computing devices that can perform chip thermal resistance and over-temperature protection temperature tests.

[0112] In one possible implementation, the predetermined ambient temperature can be determined based on the chip's operating temperature range and the temperature range of the controllable temperature chamber. This can result in n predetermined ambient temperatures TA1, TA2, TA3, ..., TAN (n being an integer greater than or equal to 2). Preferably, these n predetermined ambient temperatures TA1, TA2, TA3, ..., TAN can be an arithmetic sequence. It should be noted that if the chip's operating temperature exceeds the temperature range of the controllable temperature chamber, then n temperature values ​​within the higher temperature range of the controllable temperature chamber can be selected as the predetermined ambient temperature.

[0113] In one possible implementation, the above-described test system is used to control the electronic load to gradually increase from 0 at each of the n predetermined ambient temperatures TA1, TA2, TA3, ..., TAn, until the chip under test experiences over-temperature protection, so that the computing device can obtain the chip power consumption P1, P2, P3, ..., Pn of the chip under test at the moment before the over-temperature protection occurs.

[0114] In one possible implementation, the computing device can calculate the chip's thermal resistance Rjc and the final over-temperature protection temperature T by substituting n predetermined ambient temperatures TA1, TA2, TA3, ..., TAn and n chip power consumptions P1, P2, P3, ..., Pn into the relationship between the chip's thermal resistance Rjc and the final over-temperature protection temperature T, the ambient temperature TA, and the power consumption of multiple chips corresponding to the ambient temperature TA.

[0115] This embodiment utilizes the characteristic that the power consumption of the chip under test (DUT) increases with the increase of electronic load and the DUT's own over-temperature protection function to obtain the chip power consumption at the moment before the DUT triggers over-temperature protection under different predetermined ambient temperatures and different loads. By using n predetermined ambient temperatures and their corresponding n chip power consumptions, the chip thermal resistance and the final over-temperature protection temperature are calculated. This test system provides high accuracy in obtaining chip thermal resistance and the final over-temperature protection temperature, is highly operable, and has low testing costs. Moreover, by calculating the chip thermal resistance and the final over-temperature protection temperature using multiple n predetermined ambient temperatures and their corresponding n chip power consumptions, it can also measure DUTs whose operating temperature exceeds the temperature chamber temperature, without being limited by the temperature chamber temperature range.

[0116] In one possible implementation, the step of calculating the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions includes:

[0117] The chip's thermal resistance Rjc and final over-temperature protection temperature T are calculated using the formula P = (T-TA) / Rjc, where TA is the predetermined ambient temperature and P is the chip's power consumption.

[0118] In this embodiment, in P = (T-TA) / Rjc, TA is the predetermined ambient temperature, which is the independent variable, and P is the chip power consumption, which is the dependent variable. n=2 predetermined ambient temperatures and their corresponding n=2 chip power consumptions P can be obtained by testing. Substituting these two predetermined ambient temperatures and their corresponding two chip power consumptions P into the formula P = (T-TA) / Rjc, the two-variable linear equation can be solved to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0119] In one possible implementation, the calculation of the chip thermal resistance Rjc and the final over-temperature protection temperature T according to the formula P = (T-TA) / Rjc includes:

[0120] The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted using the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0121] In this embodiment, when n is greater than 2, the independent variable TA and the dependent variable P in the formula P = (T-TA) / Rjc may not satisfy a linear relationship due to measurement errors or other reasons. In this case, in order to more accurately calculate the chip thermal resistance Rjc and the final over-temperature protection temperature T, the independent variable TA and the dependent variable P can be fitted with a straight line to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T in P = (T-TA) / Rjc. Optionally, the least squares method can be used for straight line fitting. Of course, other algorithms can also be used for fitting, and there are no restrictions here.

[0122] In one possible implementation, obtaining the chip power consumption of the chip under test at the moment before over-temperature protection occurs at a predetermined ambient temperature includes:

[0123] Obtain the input voltage, input current, output voltage, and output current of the chip under test at the moment before the over-temperature protection occurs;

[0124] Based on the input voltage, input current, output voltage, and output current, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs is calculated.

[0125] In this embodiment, during the test, the input voltage, input current, output voltage, and output current of the chip under test can be continuously collected. Thus, after the chip under test triggers over-temperature protection, the computing device can obtain the input voltage V of the chip under test at the moment preceding the over-temperature protection event. IN Input current I IN Output voltage V OUT and output current I OUT And according to the formula P= V IN× I IN -V OUT× I OUT The chip power consumption P of the chip under test is calculated at the moment before the over-temperature protection occurs.

[0126] This disclosure also provides a testing device for chip thermal resistance and over-temperature protection temperature. Figure 4 This diagram illustrates a structural block diagram of a chip thermal resistance and over-temperature protection temperature testing device according to an embodiment of the present disclosure. This device can be implemented as part or all of an electronic device through software, hardware, or a combination of both. Figure 4 As shown, the testing apparatus includes:

[0127] The acquisition module 401 is configured to acquire the chip power consumption of the chip under test at the moment before the over-temperature protection occurs at a predetermined ambient temperature.

[0128] The parameter calculation module 402 is configured to, after obtaining the chip power consumption corresponding to n predetermined ambient temperatures, calculate the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2.

[0129] In one possible implementation, the chip thermal resistance and over-temperature protection temperature testing device is suitable for electronic devices such as computers and computing equipment that can perform chip thermal resistance and over-temperature protection temperature testing.

[0130] In one possible implementation, the predetermined ambient temperature can be determined based on the chip's operating temperature range and the temperature range of the controllable temperature chamber. This can result in n predetermined ambient temperatures TA1, TA2, TA3, ..., TAN (n being an integer greater than or equal to 2). Preferably, these n predetermined ambient temperatures TA1, TA2, TA3, ..., TAN can be an arithmetic sequence. It should be noted that if the chip's operating temperature exceeds the temperature range of the controllable temperature chamber, then n temperature values ​​within the higher temperature range of the controllable temperature chamber can be selected as the predetermined ambient temperature.

[0131] In one possible implementation, using the above-described test system, the electronic load is controlled to gradually increase from 0 at each of the n predetermined ambient temperatures TA1, TA2, TA3, ..., TAn, until the chip under test experiences over-temperature protection, so that the acquisition module 401 acquires the chip power consumption P1, P2, P3, ..., Pn of the chip under test at the moment before the over-temperature protection occurs.

[0132] In one possible implementation, the parameter calculation module 402 can calculate the chip's thermal resistance Rjc and the final over-temperature protection temperature T based on the relationship between the chip's thermal resistance Rjc and the final over-temperature protection temperature T, the ambient temperature TA, and the power consumption of multiple chips corresponding to the ambient temperature TA. It can substitute n predetermined ambient temperatures TA1, TA2, TA3, ..., TAn and n chip power consumptions P1, P2, P3, ..., Pn into the relationship to calculate the chip's thermal resistance Rjc and the final over-temperature protection temperature T.

[0133] This embodiment utilizes the characteristic that the power consumption of the chip under test (DUT) increases with the increase of electronic load and the DUT's own over-temperature protection function to obtain the chip power consumption at the moment before the DUT triggers over-temperature protection under different predetermined ambient temperatures and different loads. By using n predetermined ambient temperatures and their corresponding n chip power consumptions, the chip thermal resistance and the final over-temperature protection temperature are calculated. This test system provides high accuracy in obtaining chip thermal resistance and the final over-temperature protection temperature, is highly operable, and has low testing costs. Moreover, by calculating the chip thermal resistance and the final over-temperature protection temperature using multiple n predetermined ambient temperatures and their corresponding n chip power consumptions, it can also measure DUTs whose operating temperature exceeds the temperature chamber temperature, without being limited by the temperature chamber temperature range.

[0134] In one possible implementation, the parameter calculation module is configured as follows:

[0135] The chip's thermal resistance Rjc and final over-temperature protection temperature T are calculated using the formula P = (T-TA) / Rjc, where TA is the predetermined ambient temperature and P is the chip's power consumption.

[0136] In this embodiment, in P = (T-TA) / Rjc, TA is the predetermined ambient temperature, which is the independent variable, and P is the chip power consumption, which is the dependent variable. n=2 predetermined ambient temperatures and their corresponding n=2 chip power consumptions P can be obtained by testing. Substituting these two predetermined ambient temperatures and their corresponding two chip power consumptions P into the formula P = (T-TA) / Rjc, the two-variable linear equation can be solved to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0137] In one possible implementation, the parameter calculation module is configured as follows:

[0138] The n predetermined ambient temperatures and their corresponding n chip power consumptions are fitted using the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T.

[0139] In this embodiment, when n is greater than 2, the independent variable TA and the dependent variable P in the formula P = (T-TA) / Rjc may not satisfy a linear relationship due to measurement errors or other reasons. In this case, in order to more accurately calculate the chip thermal resistance Rjc and the final over-temperature protection temperature T, the independent variable TA and the dependent variable P can be fitted with a straight line to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T in P = (T-TA) / Rjc. Optionally, the least squares method can be used for straight line fitting. Of course, other algorithms can also be used for fitting, and there are no restrictions here.

[0140] In one possible implementation, the acquisition module is configured as follows:

[0141] Obtain the input voltage, input current, output voltage, and output current of the chip under test at the moment before the over-temperature protection occurs;

[0142] Based on the input voltage, input current, output voltage, and output current, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs is calculated.

[0143] In this embodiment, during the test, the input voltage, input current, output voltage, and output current of the chip under test can be continuously collected. Thus, after the chip under test triggers over-temperature protection, the acquisition module can obtain the input voltage V of the chip under test at the moment immediately preceding the over-temperature protection event. IN Input current I IN Output voltage V OUT and output current I OUT And according to the formula P= V IN× I IN -V OUT× I OUT The chip power consumption P of the chip under test is calculated at the moment before the over-temperature protection occurs.

[0144] The technical terms and features mentioned in the above method and device implementations are the same as or similar to those mentioned in the above test system implementations. For explanations and descriptions of the technical terms and features involved in the method and device implementations, please refer to the explanations of the above test system implementations. They will not be repeated here.

[0145] Figure 5 A schematic diagram of the structure of a computer system suitable for implementing the methods of the embodiments of this disclosure is shown.

[0146] like Figure 5 As shown, the computer system 500 includes a processing unit 501, which can execute various processes described in the above embodiments according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage section 508 into a random access memory (RAM) 503. The RAM 503 also stores various programs and data required for the operation of the computer system 500. The processing unit 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0147] The following components are connected to I / O interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to I / O interface 505 as needed. A removable medium 511, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 510 as needed so that computer programs read from it can be installed into storage section 508 as needed. The processing unit 501 can be implemented as a CPU, GPU, TPU, FPGA, NPU, etc.

[0148] In particular, according to embodiments of this disclosure, the methods described above can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising computer instructions that, when executed by a processor, implement the steps of the methods described above. In such embodiments, the computer program product can be downloaded and installed from a network via communication section 509, and / or installed from removable media 511.

[0149] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0150] The units or modules described in the embodiments of this disclosure can be implemented in software or programmable hardware. The described units or modules can also be located in a processor, and the names of these units or modules do not necessarily constitute a limitation on the unit or module itself.

[0151] In another aspect, this disclosure also provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system described above; or it may be a standalone computer-readable storage medium not assembled into a device. The computer-readable storage medium stores one or more programs, which are used by one or more processors to perform the methods described in this disclosure.

[0152] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A testing system for chip thermal resistance and over-temperature protection temperature, characterized in that, include: The chip under test is equipped with an over-temperature protection circuit, which activates over-temperature protection when it detects that the temperature of the chip under test reaches the initial over-temperature protection temperature. A test board is connected to the chip under test and is used to put the chip under test into a normal working state. A DC power supply, connected to the test board, is used to power the chip under test; An electronic load, connected to the test board, is used to provide a load for the chip under test; A controllable temperature chamber is used to provide the ambient temperature for the chip under test to operate, and the test board connected to the chip under test is placed inside the controllable temperature chamber; A computing device is configured to: a controllable constant temperature chamber is at a predetermined ambient temperature, and the electronic load gradually increases from 0 until the chip under test (TBT) experiences over-temperature protection; acquire the chip power consumption of the TBT at the moment before the over-temperature protection occurs at the predetermined ambient temperature; and, after acquiring the chip power consumption corresponding to n predetermined ambient temperatures, calculate the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2. Specifically, the computing device is used for: The n predetermined ambient temperatures and their corresponding n chip power consumptions are linearly fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T, where TA is the predetermined ambient temperature and P is the chip power consumption.

2. The testing system according to claim 1, characterized in that, The computing device is specifically used for: The input voltage, input current, output voltage, and output current of the chip under test are obtained at the moment before the over-temperature protection occurs; based on the input voltage, input current, output voltage, and output current, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs is calculated.

3. The testing system according to claim 2, characterized in that, The power input terminal and ground terminal of the test board both support Kelvin connection. When the DC power supply also supports Kelvin connection, the voltage output by the DC power supply is used as the input voltage of the chip under test. When the DC power supply does not support Kelvin connection, the test system further includes a first voltage measuring instrument; the first voltage measuring instrument is connected to the chip under test and is used to measure the input voltage of the chip under test.

4. The testing system according to claim 2, characterized in that, When the DC power supply supports current measurement, the current output by the DC power supply measured by the DC power supply is used as the input current of the chip under test. When the DC power supply does not support current measurement, the test system further includes a first current measuring instrument; The first current measuring instrument is connected to the chip under test and is used to measure the input current of the chip under test.

5. The testing system according to claim 2, characterized in that, When the electronic load supports current measurement, the current input to the electronic load measured by the electronic load is used as the output current of the chip under test; When the electronic load does not support current measurement, the test system further includes a second current meter, which is connected to the chip under test and is used to measure the output current of the chip under test.

6. The testing system according to claim 2, characterized in that, The testing system also includes a second voltage measuring instrument; The second voltage measuring instrument is connected to the chip under test and is used to measure the output voltage of the chip under test.

7. The testing system according to claim 1, characterized in that, If the controllable constant temperature chamber has a temperature measurement function, the controllable constant temperature chamber controls the temperature inside the controllable constant temperature chamber to be at a predetermined ambient temperature based on the temperature measurement function of the controllable constant temperature chamber. If the controllable constant temperature chamber does not have a temperature measurement function, the test system further includes a temperature measurement module located inside the controllable constant temperature chamber for measuring the temperature inside the chamber. The controllable constant temperature chamber is connected to the temperature measurement module and is used to control the temperature inside the controllable constant temperature chamber to a predetermined ambient temperature based on the temperature measured by the temperature measurement module.

8. The testing system according to claim 1, characterized in that, The chip under test includes a power supply chip.

9. A method for testing the thermal resistance and over-temperature protection temperature of a chip, characterized in that, include: Obtain the chip power consumption of the chip under test at the moment before the over-temperature protection occurs at the predetermined ambient temperature; After obtaining the chip power consumption corresponding to n predetermined ambient temperatures, the chip thermal resistance and the final over-temperature protection temperature are calculated based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2. The step of calculating the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions includes: performing a linear fit on the n predetermined ambient temperatures and their corresponding n chip power consumptions according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T, where TA is the predetermined ambient temperature and P is the chip power consumption.

10. The test method according to claim 9, characterized in that, The process of obtaining the chip power consumption of the chip under test at the moment before the over-temperature protection occurs at the predetermined ambient temperature includes: Obtain the input voltage, input current, output voltage, and output current of the chip under test at the moment before the over-temperature protection occurs; Based on the input voltage, input current, output voltage, and output current, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs is calculated.

11. A testing device for chip thermal resistance and over-temperature protection temperature, characterized in that, include: The acquisition module is configured to acquire the chip power consumption of the chip under test at the moment before the over-temperature protection occurs at a predetermined ambient temperature. The parameter calculation module is configured to, after obtaining the chip power consumption corresponding to n predetermined ambient temperatures, calculate the chip thermal resistance and the final over-temperature protection temperature based on the n predetermined ambient temperatures and their corresponding n chip power consumptions, where n is an integer greater than or equal to 2; The parameter calculation module is configured as follows: The n predetermined ambient temperatures and their corresponding n chip power consumptions are linearly fitted according to the formula P = (T-TA) / Rjc to obtain the chip thermal resistance Rjc and the final over-temperature protection temperature T, where TA is the predetermined ambient temperature and P is the chip power consumption.

12. The testing apparatus according to claim 11, characterized in that, The acquisition module is configured as follows: Obtain the input voltage, input current, output voltage, and output current of the chip under test at the moment before the over-temperature protection occurs; Based on the input voltage, input current, output voltage, and output current, the chip power consumption of the chip under test at the moment before the over-temperature protection occurs is calculated.

13. A readable storage medium, characterized in that, It stores computer instructions that, when executed by a processor, implement the method described in any one of claims 9 to 10.

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