Frequency multiplication delay-locked loop device and control method

Abstract

The present disclosure relates to the technical field of electronic circuit, including a frequency multiplication delay-locked loop device and a control method. By extending the strobe on the basis of the traditional MDLL circuit, at least two strobes are set, and after the loop enters the locked state, the first strobe end of k strobes in the at least two strobes is opened and the second strobe end is closed in the time window signal generated by the window generation circuit, the first strobe end of other strobes is closed and the second strobe end is opened, so that the reference clock signal and the output clock signal are input into the voltage-controlled delay line at the same time, and the edges of the reference clock signal and the output clock signal are subjected to interpolation processing. Compared with the single MDLL circuit, since the edge of the output clock signal participates, the pulse in the output clock signal is not completely lost, the problem of unstable frequency of the output clock signal can be avoided, and the stability and linearity of the loop clock are ensured.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and in particular to a frequency-multiplying delay-locked loop device and a control method. Background Art

[0002] In chip design, phase-locked loop (PLL) technology is often used to generate and recover clock signals. Existing PLL technologies are categorized into two types, PLL (Phase Locked Loop) and DLL (Delay-Locked Loop), based on their loop characteristics.

[0003] Commonly used phase-locked loop circuits are generally implemented as charge pump phase-locked loops. Figure 1 As shown in the figure, the phase-locked loop circuit includes: Phase Frequency Detector (PFD), Charge Pump (CP), Low Pass Filter (LPF) and Voltage-Controlled Oscillator (VCO). The basic working principle is: PFD generates a phase frequency detector (PFD) according to the input signal f r and the output clock signal f o The phase difference between them controls CP to charge and discharge the LPF, thereby controlling the output voltage of the loop filter and changing the oscillation frequency of the VCO so that the input signal f r and the output clock signal f o The phase difference between the two signals decreases until the phases of the two signals are aligned and the loop enters the locked state. In the locked state, f r and f o The phase-locked loop circuit can also realize the frequency multiplication function, which can be achieved by adding an N-frequency divider in the phase-locked loop circuit. At this time, the output clock signal after N frequency division is the same as the input reference clock signal f r The frequencies are equal, so f o The frequency is f r N times.

[0004] The structure of the delay line phase-locked loop circuit is similar to that of the phase-locked loop circuit. Figure 2 As shown in Figure 1, the main difference between the delay-locked loop circuit and the phase-locked loop circuit is that a voltage-controlled delay line (VCDL) is used instead of a voltage-controlled oscillator (VCO). Figure 2Let's take the example of replacing the PFD in a phase-locked loop circuit with a phase detector (PD). Unlike a phase-locked loop circuit, a delay-line phase-locked loop circuit does not have an oscillating clock signal. Instead, it aligns the output clock signal with the input signal by adjusting the delay from input to output to exactly equal the period of the input reference clock signal. The delay-line phase-locked loop circuit can achieve more precise phase alignment, but it cannot accurately determine the phase of the input signal f. r Complete frequency doubling.

[0005] In order to make the phase-locked loop have both frequency multiplication capability and precise phase alignment capability, a multiplying delay-locked loop (MDLL) circuit is proposed. Figure 3 As shown in Figure 1, the MDLL circuit includes a phase detector, a charge pump, a loop filter, a frequency divider, a voltage-controlled delay line, a multiplexer (MUX), and a logic selector. Its operating principle involves splitting a reference clock signal into two paths: one input to the multiplexer and the other to the phase detector. The logic selector periodically controls the multiplexer to select either the output clock signal of the voltage-controlled delay line or the reference clock signal as the input to the voltage-controlled delay line. When the output clock signal is selected to be input into the voltage-controlled delay line, the loop formed by the voltage-controlled delay line, frequency divider, phase detector, charge pump and loop filter operates according to the PLL operating mechanism to form a VCO path. The voltage-controlled delay line delays each edge of the VCO to generate a high-frequency output clock signal. The output clock signal is divided by the frequency divider to generate a low-frequency clock signal. The phase detector compares the phase difference between the low-frequency clock signal and the reference clock signal. The charge pump generates a current pulse based on the phase difference. The loop filter integrates the current pulse into a control voltage to adjust the frequency of the VCO so that it tends to N times the frequency of the reference clock signal, and adjusts the delay of the voltage-controlled delay line so that it tends to one oscillation period of the VCO. When the reference clock signal is selected to be input into the voltage-controlled delay line, the loop operates according to the DLL working mechanism. The voltage-controlled delay line delays the edge of the reference clock signal to generate an output clock signal. After the frequency is divided by the divider, the input phase detector compares the phase difference between the reference clock signal and the low-frequency clock signal. The charge pump generates a current pulse based on the phase difference and controls the loop filter to fine-tune the control voltage so that the delay of the voltage-controlled delay line is exactly equal to one oscillation period of the VCO. Under the DLL working mechanism, the phase information of the reference clock signal can be directly added to the output clock signal to ensure phase accuracy and consistency.

[0006] According to the operating principle of the MDLL, within the time window signal generated by the logic selector, the edge of the reference clock is input into the voltage-controlled delay line. At this time, if the reference clock signal is "0," the output clock signal may be pulled low prematurely, resulting in an output clock signal with only N pulses, which originally had N pulses, ultimately having only N-1 pulses. This means that one of the pulses, due to the premature low input of the reference clock signal, causes a frequency jump in the output clock signal, resulting in unstable output clock frequency. Summary of the Invention

[0007] In view of this, the present disclosure proposes a frequency-multiplying delay-locked loop device and a control method, which can solve the problem of unstable output clock signal frequency of a traditional MDLL circuit.

[0008] According to one aspect of the present disclosure, a frequency-doubling delay-locked loop device is provided, the device comprising:

[0009] Phase and frequency detector;

[0010] At least two gates, each gate comprising a first gate terminal for receiving a reference clock signal, a second gate terminal for receiving an output clock signal, and an output terminal for outputting a gate result;

[0011] Charge pump;

[0012] Loop filter;

[0013] voltage-controlled delay line;

[0014] a window generation circuit; and,

[0015] A control component connected to the output terminal of the window generation circuit and the control terminals of the at least two gates, respectively, for:

[0016] After the frequency multiplication delay phase-locked loop is started, the first gate end of each gate is controlled to be closed and the second gate end is controlled to be open, so that the output clock signal is input into the voltage-controlled delay line and the output clock signal is frequency modulated;

[0017] When the frequency of the output clock signal reaches N times that of the reference clock signal, within the time window signal generated by the window generation circuit, the first gate ends of k of the at least two gates are controlled to be turned on and the second gate ends are turned off, and the first gate ends of the other gates are kept turned off and the second gate ends are turned on, so that the reference clock signal and the output clock signal are simultaneously input into the voltage-controlled delay line, and k and N are both positive integers.

[0018] In a possible implementation, the frequency and phase detector includes a first input terminal for receiving a reference clock signal, a second input terminal for receiving a frequency-divided output clock signal, and an output terminal for outputting a frequency and phase detection result;

[0019] The charge pump and the loop filter are connected to the output end of the phase frequency detector in sequence;

[0020] The voltage-controlled delay line is connected to the output end of the loop filter and the output end of each gate respectively;

[0021] The output end of the voltage-controlled delay line is respectively connected to each second selection end, the input end of the window generation circuit, and the frequency divider. The output end of the frequency divider is connected to the second input end of the frequency and phase detector.

[0022] In a possible implementation, the control component is further configured to:

[0023] After controlling the first gate ends of k of the at least two gates to be turned on and the second gate ends to be turned off within the time window signal, if the window generating circuit is not detected to generate a valid time window signal within the preset time length, the first gate ends of each gate are controlled to be turned off and the second gate ends to be turned on.

[0024] In a possible implementation, the control component is further configured to:

[0025] Monitoring whether the window generation circuit generates a time window signal within a preset time period, and whether the time period of the time window signal satisfies a preset condition;

[0026] If the window generation circuit does not generate a time window signal, or the duration of the time window signal generated by the window generation circuit does not meet a preset condition, the first gate end of each gate is controlled to be closed and the second gate end is controlled to be open.

[0027] In a possible implementation, the control component includes: a sampling circuit and a detection circuit respectively connected to the output end of the window generation circuit,

[0028] The detection circuit is used to detect whether the window generation circuit has a time window signal;

[0029] The sampling circuit is used to detect whether the duration of the time window signal generated by the window generation circuit meets a preset condition.

[0030] In one possible implementation, the control component includes:

[0031] The gate configuration circuit includes a first configuration terminal for configuring a first mode, a second configuration terminal for configuring a second mode, and a configuration output terminal; the first mode refers to an operating mode in which the first gate terminals of each gate are closed and the second gate terminals are opened; the second mode refers to an operating mode in which the first gate terminals of k gates are opened and the second gate terminals are closed within a time window signal, while the first gate terminals of the other gates are closed and the second gate terminals are opened; when the frequency of the output clock signal does not reach N times the reference clock signal or the window generation circuit is not detected to generate a valid time window signal, the configuration output terminal is used to output the configuration of the first configuration terminal; when the frequency of the output clock signal reaches N times the reference clock signal and the window generation circuit is detected to generate a valid time window signal, the configuration output terminal is used to output the configuration of the second configuration terminal;

[0032] An AND gate includes a first signal terminal connected to the configuration output terminal, a second signal terminal connected to the output terminal of the window generation circuit, and an output terminal connected to the control terminal of the gate; the output terminal of the AND gate is used to output the time window signal generated by the window generation circuit to k gates when the configuration output terminal outputs the configuration of the second configuration terminal, so that the k gates turn on the first gate terminal and turn off the second gate terminal within the time window signal.

[0033] In a possible implementation, the control component further includes: a register connected to the second configuration terminal, the register is used to store configuration information of the second mode, and the configuration information is used to indicate a value of k.

[0034] In a possible implementation, the control component is further configured to:

[0035] If the frequency of the output clock signal still does not reach N times of the reference clock signal within the preset state monitoring time, the step of controlling the first gate end of each gate to be closed and the second gate end to be opened and subsequent steps are triggered.

[0036] According to another aspect of the present disclosure, a control method based on a frequency multiplication delay phase locked loop device is provided, which is used in the above-mentioned frequency multiplication delay phase locked loop device, and the method includes:

[0037] After the frequency multiplication delay phase-locked loop is started, the first gate end of each gate is controlled to be closed and the second gate end is controlled to be open, so that the output clock signal is input into the voltage-controlled delay line and the output clock signal is frequency modulated;

[0038] When the frequency of the output clock signal reaches N times that of the reference clock signal, within the time window signal generated by the window generation circuit, the first gate ends of k of the at least two gates are controlled to be turned on and the second gate ends are turned off, and the first gate ends of the other gates are kept turned off and the second gate ends are turned on, so that the reference clock signal and the output clock signal are simultaneously input into the voltage-controlled delay line, and k and N are both positive integers.

[0039] According to another aspect of the present disclosure, a timing controller chip is provided, wherein the timing controller chip includes the above-mentioned frequency multiplication delay locked loop device.

[0040] According to another aspect of the present disclosure, a display device is provided, comprising a plurality of display units and the above-mentioned timing controller chip.

[0041] According to another aspect of the present disclosure, an electronic device is provided, comprising the above display device.

[0042] By setting at least two gates, and after the loop enters the locked state, within the time window signal generated by the window generation circuit, the first gate ends of k gates out of the at least two gates are controlled to be open and the second gate ends are closed, and the first gate ends of the other gates are kept closed and the second gate ends are opened, so that the reference clock signal and the output clock signal are input into the voltage-controlled delay line at the same time, so as to perform interpolation processing on the edges of the reference clock signal and the output clock signal. Compared with a separate MDLL circuit, due to the participation of the output clock signal edge, the pulses in the output clock signal will not be completely lost, the problem of unstable frequency of the output clock signal can be avoided, and the stability and linearity of the loop clock can be guaranteed.

[0043] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0045] Figure 1 A schematic diagram showing a charge pump phase-locked loop circuit of the background art;

[0046] Figure 2 A schematic diagram showing a delay locked loop circuit of the background art;

[0047] Figure 3 A schematic diagram showing a frequency multiplication delay phase locked loop of background technology;

[0048] Figure 4FIG. 1 shows a timing diagram of an MDLL circuit according to an embodiment of the present disclosure;

[0049] Figure 5 A schematic diagram showing a compressed time window signal according to an embodiment of the present disclosure;

[0050] Figure 6 A schematic diagram illustrating outputting a clock signal when a reset delay occurs in a time window signal according to an embodiment of the present disclosure;

[0051] Figure 7 A schematic diagram showing a frequency multiplication delay phase locked loop device according to an embodiment of the present disclosure is shown;

[0052] Figure 8 A timing diagram showing a frequency multiplication delay phase locked loop from power-on to locking according to an embodiment of the present disclosure is shown;

[0053] Figure 9 A timing diagram showing a reference clock signal and an output clock signal simultaneously input into a voltage-controlled delay line according to an embodiment of the present disclosure;

[0054] Figure 10 A schematic diagram illustrating a control component according to an embodiment of the present disclosure is shown;

[0055] Figure 11 A control flow chart of a control component according to an embodiment of the present disclosure is shown;

[0056] Figure 12 A schematic diagram illustrating switching of the working mode of a loop according to an embodiment of the present disclosure is shown;

[0057] Figure 13 A flow chart of a control method based on a frequency multiplication delay locked loop device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0058] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0059] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0061] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0062] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0063] The present application provides a frequency-multiplying delay phase-locked loop device, which, based on a traditional MDLL, is provided with at least two gates. One part of the gates receives an output clock signal, so that the loop corresponding to the gate operates in PLL mode, and the other part of the gates periodically (the period of a time window signal) receives a reference clock signal, so that the loop in which the gate is located operates in MDLL mode. At this time, the reference clock signal and the output clock signal can be simultaneously input into a voltage-controlled delay line, and the edges of the reference clock signal and the output clock signal are interpolated. Compared with a separate MDLL circuit, due to the participation of the output clock signal edge, the pulses in the output clock signal will not be completely lost, thereby ensuring the stability and linearity of the loop clock.

[0064] Below, the technical solution of this application is introduced in detail.

[0065] Figure 7 FIG. 1 is a schematic diagram showing a frequency multiplication delay phase locked loop device according to an embodiment of the present disclosure. Figure 7As shown, the device includes: a frequency detector and phase detector 710, a multiplexer (MUX) 720, a charge pump and loop filter 730, a voltage-controlled delay line 740, a frequency divider 750, a window generation circuit 760 and a control component 770.

[0066] The frequency and phase detector 710 includes a first input terminal for receiving a reference clock signal, a second input terminal for receiving a frequency-divided output clock signal, and an output terminal for outputting a frequency and phase detection result.

[0067] The phase and frequency detector 710 is used to perform phase and frequency comparison on the reference clock signal received at the first input terminal and the divided output clock signal received at the second input terminal, and output the obtained phase and frequency detection results to the charge pump through the output terminal.

[0068] The output of phase frequency detector 710 is connected to a charge pump and a loop filter in sequence. In other words, the charge pump's input is connected to the output of phase frequency detector 710, and its output is connected to the input of the loop filter. The charge pump is used to charge and discharge the loop filter based on the phase frequency detection result output by phase frequency detector 710, thereby controlling the output voltage of the loop filter. The output of the loop filter is connected to the control terminal of voltage-controlled delay line 740 to adjust the delay of voltage-controlled delay line 740.

[0069] In the present application, there are at least two gates 720, each of which includes a first gate terminal for receiving a reference clock signal, a second gate terminal for receiving an output clock signal, and an output terminal for outputting a gated result. The output terminal of each gate 720 is connected to the input terminal of the same voltage-controlled delay line 740, thereby inputting the gated results of different gates 720 into the same voltage-controlled delay line 740. The voltage-controlled delay line 740 is used to delay the received reference clock signal or the output clock signal to obtain an output clock signal, which is then outputted through the output terminal. The output terminal of the voltage-controlled delay line 740 can serve as the output terminal of a frequency-multiplying delay-locked loop device, i.e., the output clock signal is the output of the frequency-multiplying delay-locked loop device.

[0070] The frequency divider 750 is used to divide the frequency of the output clock signal by N, or to perform a frequency division process on the output clock signal by N, to obtain a divided output clock signal. N is a positive integer.

[0071] The output end of the voltage-controlled delay line 740 is respectively connected to each second selection end, the input end of the window generation circuit 760, and the frequency divider 750. The output end of the frequency divider 750 is connected to the second input end of the frequency detector 710. In this way, the second input end of the frequency detector 710 can obtain the divided output clock signal to compare the divided output clock signal with the reference clock signal; when the second selection end is turned on, the output clock signal can be input into the voltage-controlled delay line 740; the window generation circuit 760 can determine the setting and resetting timing of the time window signal based on the output clock signal, thereby generating a time window signal. Figure 4 , the time window signal (i.e. Figure 4 The control signal of the logic selector in the logic selector) needs to be set after the rising edge of the output clock signal before the Nth frequency division (that is, the Nth frequency division input signal) and before the rising edge of the output clock signal before the N+1th frequency division. For details, refer to Figure 4 The control signal of the logic selector indicated by the arrow on the Nth frequency division input signal is set at the timing, and is reset after the rising edge of the reference clock signal and before the falling edge of the output clock signal before the N+1th frequency division (i.e., the N+1th frequency division input signal). For details, refer to Figure 4 The dot on the rising edge of the reference clock signal indicates the reset timing of the control signal of the logic selector through the dotted arrow. In this application, "within the time window signal" means the duration of the time window signal being set. Wherein, N represents the frequency division multiple and is a positive integer.

[0072] The control component 770 is connected to the output terminal of the window generation circuit 760 and the control terminals of at least two gates 720. In this embodiment, the control component 770 is used to monitor whether the frequency multiplication delay locked loop device is in a locked state and switch the operating mode of the loop in which each gate 720 is located.

[0073] Specifically, the control component 770 is used to: after the frequency multiplication delay locked loop is started, control the first gate terminal of each gate 720 to be closed and the second gate terminal to be opened, so that the output clock signal is input into the voltage controlled delay line 740 to perform frequency modulation on the output clock signal;

[0074] When the frequency of the output clock signal reaches N times that of the reference clock signal, within the time window signal generated by the window generation circuit 760, the first gate terminals of k of the at least two gates 720 are controlled to be open and the second gate terminals are closed, while the first gate terminals of the other gates 720 are kept closed and the second gate terminals are kept open, so that the reference clock signal and the output clock signal are simultaneously input into the voltage-controlled delay line 740, and the phase of the output clock signal is correlated with the phase of the reference clock signal. Here, k and N are both positive integers.

[0075] For example, in order to ensure the loop locking speed, at the beginning of power-on, the control component 770 controls the loops where each gate is located to operate in PLL mode, that is, the first gate end of all gates 720 is closed and the second gate end is opened. At this time, the output clock signal is input into the voltage-controlled delay line 740, which can ensure the locking speed. The ratio of PLL mode to MDLL mode is 1:0, that is, if there are K gates, the loops where the K gates are located all operate in PLL mode, and the loops where the 0 gates are located operate in MDLL mode.

[0076] The loop where the gate is located refers to the loop formed by the processing path of the clock signal selected by the gate, and the processing path includes: the clock signal selected by the gate (i.e., the reference clock signal or the output clock signal) is input into the voltage-controlled delay line, and the output clock signal obtained after delay by the voltage-controlled delay line is output to the frequency divider 750, and the frequency divider 750 is input into the frequency detector and phase detector after frequency division, and the frequency detection result output by the frequency detector and phase detector is processed by the charge pump and the loop filter to control the voltage-controlled delay line.

[0077] The control component 770 includes a loop lock detection circuit, which is connected to the output end of the frequency detector and detects whether the frequency of the output clock signal reaches N times the reference clock signal. If so, it is determined that the loop is locked; if it does not reach N times the reference clock signal, it is determined that the loop is not locked.

[0078] In one example, the lock detection circuit detects whether the frequency of the output clock signal reaches N times that of the reference clock signal in the following manner: determining whether the frequency of the output clock signal continues to be N times that of the reference clock signal within a preset detection time period; if so, determining that the frequency of the output clock signal reaches N times that of the reference clock signal; if not, determining that the frequency of the output clock signal does not reach N times that of the reference clock signal.

[0079] When the frequency of the output clock signal reaches N times that of the reference clock signal (i.e., the loop is locked), the control component controls the k gates to have their first gate terminals open and their second gate terminals closed within the time window signal generated by the window generation circuit. Outside the time window signal, the first gate terminals are closed and the second gate terminals are open. In other words, the loop containing the k gates operates in MDLL mode. The number k is pre-stored in the control component and can be fixed or dynamically changed.

[0080] Optionally, the k gates may be pre-designated gates, or the gates numbered first k, or randomly selected gates. This embodiment does not limit the method for determining the k gates.

[0081] Optionally, if the frequency of the output clock signal still does not reach N times the reference clock signal within the preset state monitoring time, the steps of controlling the first gate end of each gate to close and the second gate end to open and subsequent steps are triggered, that is, the loop is reset.

[0082] For example: Reference Figure 8 The timing diagram of the frequency multiplication delay phase-locked loop from power-up to lock is shown. After power-up, the loops where each gate 720 is located are initialized to operate in PLL mode. At this time, the control voltage output by the charge pump and loop filter 730 to the voltage-controlled delay line 740 is in a gradually increasing stage, and the lock status signal indicates that the loop is not locked (i.e., it is not a continuous high level within the preset detection time). After the loop is locked, the lock status signal is continuously high, and the control signal output by the charge pump and loop filter 730 to the voltage-controlled delay line 740 tends to be stable. At this time, the mode switching signal generated by the control component (e.g. Figure 10 The output of the middle selection configuration circuit 773) is switched from a low level to a high level to instruct the k gates to switch the selection results according to the time window signal. Accordingly, the gates periodically (specifically, the period of the time window signal) change from a low level to a high level according to the instruction of the mode switching signal to generate a window selection signal (i.e., the selection result of the gate), thereby periodically inputting the reference clock signal to the voltage-controlled delay line, so that the loop where the k gates are located operates in the MDLL mode.

[0083] refer to Figure 9 In a traditional MDLL, if a gate opens its first gate terminal and closes its second gate terminal within the time window signal to receive the reference clock signal (i.e., receives the reference clock signal within the time range indicated by the red vertical line), the final output clock signal should be 0. However, in this embodiment, by setting the loop containing k gates to operate in MDLL mode, while the loop containing the remaining gates still operates in PLL mode, the reference clock signal is interpolated with the output clock signals received by the remaining gates. As a result, the final output clock signal does not become 0, but is pulled down by half a level. This avoids the problem of lost pulses in the output clock signal and the resulting frequency jump, ensuring the stability and linearity of the loop clock.

[0084] Furthermore, in traditional MDLLs, the logic selector needs to select the reference clock signal input at a specific time point, "inputting" a reference clock signal edge into the voltage-controlled delay line. To accurately capture the reference clock signal edge and prevent false triggering, a time window signal (time interval) is generally calculated. Within this time window signal, the logic selector selects the reference clock signal, and outside this time window signal, the output clock signal of the voltage-controlled delay line is selected. However, the process of generating the time window signal involves delays, such as the delay in detecting the current state of the PLL operating mechanism and the switching delay of the logic selector itself. When the frequency of the reference clock signal is too high, causing the delay in generating the time window signal to exceed one reference clock signal period, the following problems may arise:

[0085] 1. Unable to generate a valid time window signal. Specifically, the frequency of the output clock signal is too high, causing the loop state to change too quickly. Before the window generation circuit in the logic selector has time to calculate the position of the next valid time window signal based on the current state, the loop state has already changed, resulting in the inability to generate a valid time window signal.

[0086] 2. Missing the reference clock edge. Even if the time window signal is barely generated, its position may lag significantly behind its intended time point due to delays in the generation process. By the time the window signal reaches the logic selector, the reference clock edge it is expected to capture has already passed, causing the input timing to be missed. Alternatively, the time window signal may appear too late, overlapping the next reference edge or interfering signal that it should not have covered.

[0087] When this problem occurs, the DLL loop fails, and the logic selector may be forced to remain in the VCO path or perform an incorrect switching operation. In this case, the MDLL lacks a reference clock signal edge input to reset the phase. The output clock signal can only be output after reaching the voltage-controlled delay line delay. However, the voltage-controlled delay line delay is greater than the VCO's oscillation period. As a result, the output clock signal delay is prolonged, and the hysteresis of the clock signal edges gradually accumulates. This ultimately leads to unstable output clock signal periods, large deterministic jitter, and phase errors.

[0088] When the frequency of the reference clock signal is too high (or too fast or with a short period), the gate time window of the gate may be compressed or disappear due to the delay in the time window signal generated by the logic selector, causing the output clock signal of the MDLL circuit to be deformed near the time window signal. Figure 5As the frequency of the reference clock signal becomes faster, the gate time window of the gate shown in the circle is compressed, and its corresponding output clock signal (the part selected by the red rectangle) is deformed.

[0089] If the time window signal generated by the window generation circuit is reset late, the reference clock signal will continue to be fed into the oscillator loop, resulting in a loss of oscillator loop output, which is equivalent to a frequency reduction and clock failure. At this time, the PLL lock signal will be pulled low. For example: Reference Figure 6 In a normal time window signal, the reset occurs before the rising edge of the reference clock signal (the time indicated by the black line). However, if the reset delay occurs in the time window signal, the reset is not completed before the rising edge of the reference clock signal (the time indicated by the red line). At this time, the oscillator loop output is missing, that is, the frequency of oscillator signal a and oscillator signal b decreases after the red line, the clock fails, and the PLL lock signal is pulled low.

[0090] In summary, there is a delay in the time window generated by the window generation circuit, and this delay needs to be within one cycle of the reference clock signal. When the reference clock signal is too fast, the window generation circuit may fail and the MDLL mode loop will fail. This will cause the overall input phase error of the loop to accumulate over time, increasing the deterministic disturbance of the output clock signal.

[0091] In order to avoid the above technical problems, in this embodiment, the control component detects the time window generated by the window generation circuit to determine whether the time window is invalid, and when it fails, sets the working mode of the loop where each selector is located to PLL mode again, which can avoid disturbing the input and output clock signals.

[0092] Specifically, the control component is used to: after controlling the first gate end of k gates out of at least two gates to open and the second gate end to close within the time window signal, if the window generation circuit is not detected to generate a valid time window signal within a preset time length, control the first gate end of each gate to close and the second gate end to open.

[0093] Exemplarily, after the control component controls the loop containing k gates to operate in MDLL mode, the window generation circuit periodically generates a time window signal to periodically input a reference clock signal to the voltage-controlled delay line. If the window generation circuit fails to generate a valid time window signal, the loop containing all gates is controlled to operate in PLL mode. This prevents disturbances from being input into the output clock signal, ensuring the accuracy of the output clock signal.

[0094] A valid time window signal refers to the presence of a time window signal (i.e., the time window signal is set), and the duration of the time window signal being set meets a preset condition, which is less than the period of the reference clock signal. For example, if the period of the reference clock signal is 0.16 nanoseconds, the preset condition can be 0.04 nanoseconds, 0.05 nanoseconds, etc. This embodiment does not limit the duration of the preset condition. In other words, an invalid time window refers to the absence of a time window signal, or the duration of the time window signal does not meet the preset condition.

[0095] For example, refer to Figure 10 The control component includes a sampling circuit 771 and a detection circuit 772, each connected to the output of the window generation circuit. Detection circuit 772 is used to detect whether the window generation circuit has a time window signal; sampling circuit 771 is used to detect whether the duration of the time window signal generated by the window generation circuit meets preset conditions. Sampling circuit 771 and detection circuit 772 work together to monitor the time window signal.

[0096] The outputs of the sampling circuit 771, the detection circuit 772 and the lock detection circuit are connected to the three-input gate. At this time, the output of the three-input gate is determined based on the outputs of the sampling circuit 771, the detection circuit 772 and the lock detection circuit. Figure 10 As shown, when the lock detection circuit detects loop lock, the sampling circuit 771 detects that the duration of the time window signal meets a preset condition, and the detection circuit 772 detects the time window signal, the three-input gate outputs 1 to instruct the control component to switch the operating mode of the frequency multiplication delay phase-locked loop device. In other cases, the three-input gate outputs 0. The control component also includes a gating configuration circuit 773 and an AND gate 774.

[0097] The gate configuration circuit 773 includes a first configuration terminal for configuring a first mode, a second configuration terminal for configuring a second mode, and a configuration output terminal; the first mode refers to an operating mode in which the first gate terminal of each gate is closed and the second gate terminal is opened (i.e., a mode in which the loops of all gates operate in PLL mode); the second mode refers to an operating mode in which the first gate terminal of k gates is opened and the second gate terminal is closed within a time window signal, while the first gate terminal of other gates is closed and the second gate terminal is opened (i.e., k gates operate in MDLL mode and the other gates operate in MDLL mode). a mode in which the gate operates in PLL mode); when the frequency of the output clock signal does not reach N times the reference clock signal, or the window generation circuit is not detected to generate a valid time window signal, the configuration output end is used to output the configuration of the first configuration end, so that the loop in which all gates are located operates in PLL mode; when the frequency of the output clock signal reaches N times the reference clock signal and the window generation circuit is detected to generate a valid time window signal, the configuration output end is used to output the configuration of the second configuration end, so that k gates operate in MDLL mode and the other gates operate in PLL mode.

[0098] AND gate 774 includes a first signal terminal connected to the configuration output terminal, a second signal terminal connected to the output terminal of the window generation circuit, and an output terminal connected to the control terminal of the gate; the output terminal of the AND gate is used to output the time window signal generated by the window generation circuit to k gates when the configuration output terminal outputs the configuration of the second configuration terminal, so that the k gates turn on the first gate terminal and turn off the second gate terminal within the time window signal.

[0099] The gating configuration circuit 773, AND gate 774, and lock detection circuit work together to determine whether to generate an indication signal for switching operating modes. Specifically, the gating configuration circuit 773 initially selects the first mode indicated by "0." If the lock detection circuit detects that the loop is not locked, the gating configuration circuit 773 continues to select the first mode indicated by "0" and outputs 0. At this time, all gates 720 select 0, that is, the input and output clock signals are continuously input and output, and the circuit operates in PLL mode.

[0100] If the lock detection circuit detects loop lock, the detection circuit detects the presence of a time window signal, and the sampling circuit samples a time window signal that meets preset requirements, the gating configuration circuit 773 selects the second mode indicated by "1" and outputs 1. At this time, the k gates 720 indicated by the second mode select 1 within the time window signal and select 0 outside the time window signal, operating in MDLL mode.

[0101] If the lock detection circuit detects that the loop is locked, the detection circuit detects that the time window signal does not exist, or the sampling circuit does not sample the time window signal that meets the preset requirements, then the selection configuration circuit 773 selects the first mode indicated by "0" and outputs 0. At this time, all the selectors 720 select 0, that is, the input and output clock signals are continuously input and output, and work in PLL mode.

[0102] Optionally, the control component also includes a register connected to the second configuration end, the register is used to store configuration information of the second mode, the configuration information is used to indicate the value of k, for example: the register is used to store the ratio between the gate working in MDLL mode and the gate working in PLL mode (such as 1:1), and the value of k can be indicated based on the ratio and the total number of gates.

[0103] By setting a register connected to the second configuration terminal and storing configuration information in the register, the gate operating in the MDLL mode can be made dynamically variable, thereby improving the operating flexibility of the frequency multiplication delay locked loop device.

[0104] In order to more clearly understand the control process of the control component in this application, the following example is used to illustrate the process. Figure 11 , the process includes the following steps:

[0105] Step 1101, the frequency multiplication delay phase locked loop is started (i.e., the loop is powered on);

[0106] Step 1102, controlling the first gate terminal of each gate to be closed and the second gate terminal to be opened, so that the loop where each gate is located operates in the PLL mode;

[0107] Step 1103: The lock detection circuit detects whether the loop is locked within a preset state monitoring time; if so, step 1103 is executed; if not, the loop is reset and step 1102 is executed again;

[0108] Step 1104: During the time window signal generated by the window generation circuit, the first gate terminals of k gates among the at least two gates are controlled to be turned on and the second gate terminals are controlled to be turned off. Outside the time window signal, the first gate terminals of the k gates are controlled to be turned off and the second gate terminals are controlled to be turned on, so that the loops in which the k gates are located operate in the MDLL mode; the loops in which the other gates are located continue to operate in the PLL mode.

[0109] Step 1105, determine whether a valid time window signal is generated; if so, execute step 1104; if not, execute step 1102, and the process ends when the frequency multiplication delay locked loop is closed.

[0110] In this embodiment, by monitoring whether the time window signal fails, and after monitoring the failure of the time window signal, controlling the loops where all selectors are located to operate in PLL mode, the problem of deterministic disturbance of the output clock signal input caused by the failure of the time window signal in the MDLL mode can be avoided, thereby ensuring the accuracy of the clock signal generated by the circuit.

[0111] For example: Reference Figure 12 The schematic diagram of the loop working mode switching is shown in FIG. Figure 12 In this case, the control component will output an indication signal indicating that the time window has failed, that is, the indication signal changes from a low level to a high level. At this time, all loops where the gates are located work in PLL mode.

[0112] Figure 13 FIG. 1 is a flow chart showing a control method based on a frequency multiplication delay phase locked loop device according to an embodiment of the present disclosure. Figure 13 As shown, the method is used in the frequency multiplication delay phase locked loop device described in the above embodiment, and the method includes:

[0113] Step 1301, after the frequency multiplication delay locked loop is started, controlling the first gate terminal of each gate to be closed and the second gate terminal to be opened, so that the output clock signal is input into the voltage controlled delay line, and the output clock signal is frequency modulated;

[0114] Step 1302, when the frequency of the output clock signal reaches N times of the reference clock signal, within the time window signal generated by the window generation circuit, control the first gate ends of k of the at least two gates to be turned on and the second gate ends to be turned off, and maintain the first gate ends of other gates to be turned off and the second gate ends to be turned on, so that the reference clock signal and the output clock signal are simultaneously input into the voltage-controlled delay line, and k and N are both positive integers.

[0115] The relevant description of this embodiment is detailed in the above embodiment, and this embodiment will not be repeated here.

[0116] To summarize, after the loop enters the locked state, within the time window signal generated by the window generation circuit, the first gate ends of k of the at least two gates are controlled to be open and the second gate ends are closed, and the first gate ends of the other gates are kept closed and the second gate ends are opened, so that the reference clock signal and the output clock signal are simultaneously input into the voltage-controlled delay line to interpolate the edges of the reference clock signal and the output clock signal. Compared with a separate MDLL circuit, due to the participation of the output clock signal edge, the pulses in the output clock signal will not be completely lost, the problem of unstable frequency of the output clock signal can be avoided, and the stability and linearity of the loop clock can be guaranteed.

[0117] The present application also provides a timing controller (TCON) chip, comprising a receiver RX, the RX including a frequency-multiplying delay-locked loop (DDPLL) device, the frequency-multiplying DDPLL device configured to recover an input clock in the RX and monitor and regulate the recovered clock. The frequency-multiplying DDPLL device includes the frequency-multiplying DDPLL device described in the above-described embodiment.

[0118] The present application also provides a display device, which includes multiple display units and a timing controller chip.

[0119] Optionally, the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel and a small-pitch display panel.

[0120] Optionally, the above chip and display device can be applied to electronic devices. Accordingly, the present application also provides an electronic device, which includes the above display device. For example, the electronic devices in this embodiment include but are not limited to desktop computers, televisions, mobile devices with large screens such as mobile phones, tablet computers, and other common electronic devices that require multiple chips to be cascaded to achieve driving.

[0121] Exemplarily, the electronic device may also be user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device or vehicle-mounted device, etc. Exemplarily, some examples of terminals include: display, smart phone or portable device, mobile phone, tablet computer, laptop computer, PDA, mobile Internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control (Industrial Control), wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid (Smart Grid), wireless terminal in transportation safety (Transportation Safety), wireless terminal in smart city (Smart City), wireless terminal in smart home (Smart Home), wireless terminal in Internet of Vehicles, etc. For example, the server may be a local server or a cloud server.

[0122] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention. The scope of protection of the present invention is determined by the appended claims.

[0123] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0124] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0125] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0126] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A frequency-multiplying delay-locked loop device, characterized in that: The device comprises: Phase and frequency detector; At least two gates, each gate comprising a first gate terminal for receiving a reference clock signal, a second gate terminal for receiving an output clock signal, and an output terminal for outputting a gate result; Charge pump; Loop filter; voltage-controlled delay line; a window generation circuit; and, A control component connected to the output terminal of the window generation circuit and the control terminals of the at least two gates, respectively, for: After the frequency multiplication delay phase-locked loop is started, the first gate end of each gate is controlled to be closed and the second gate end is controlled to be open, so that the output clock signal is input into the voltage-controlled delay line and the output clock signal is frequency modulated; When the frequency of the output clock signal reaches N times that of the reference clock signal, within the time window signal generated by the window generation circuit, the first gate ends of k of the at least two gates are controlled to be turned on and the second gate ends are turned off, and the first gate ends of the other gates are kept turned off and the second gate ends are turned on, so that the reference clock signal and the output clock signal are simultaneously input into the voltage-controlled delay line, and k and N are both positive integers.

2. The device according to claim 1, characterized in that The frequency and phase detector comprises a first input terminal for receiving a reference clock signal, a second input terminal for receiving a frequency-divided output clock signal, and an output terminal for outputting a frequency and phase detection result; The charge pump and the loop filter are connected to the output end of the phase frequency detector in sequence; The voltage-controlled delay line is connected to the output end of the loop filter and the output end of each gate respectively; The output end of the voltage-controlled delay line is respectively connected to each second selection end, the input end of the window generation circuit, and the frequency divider. The output end of the frequency divider is connected to the second input end of the frequency and phase detector.

3. The device according to claim 1, characterized in that The control component is further used to: After controlling the first gate ends of k of the at least two gates to be turned on and the second gate ends to be turned off within the time window signal, if the window generating circuit is not detected to generate a valid time window signal within the preset time length, the first gate ends of each gate are controlled to be turned off and the second gate ends to be turned on.

4. The device according to claim 3, characterized in that The control component is further used to: Monitoring whether the window generation circuit generates a time window signal within a preset time period, and whether the time period of the time window signal satisfies a preset condition; If the window generation circuit does not generate a time window signal, or the duration of the time window signal generated by the window generation circuit does not meet a preset condition, the first gate end of each gate is controlled to be closed and the second gate end is controlled to be open.

5. The device according to claim 4, characterized in that The control component includes: a sampling circuit and a detection circuit respectively connected to the output end of the window generation circuit, The detection circuit is used to detect whether the window generation circuit has a time window signal; The sampling circuit is used to detect whether the duration of the time window signal generated by the window generation circuit meets a preset condition.

6. The device according to claim 3, characterized in that The control component includes: A gate configuration circuit, comprising a first configuration terminal for configuring a first mode, a second configuration terminal for configuring a second mode, and a configuration output terminal; the first mode refers to an operating mode in which the first gate terminals of each gate are closed and the second gate terminals are opened; the second mode refers to an operating mode in which the first gate terminals of k gates are opened and the second gate terminals are closed within a time window signal, while the first gate terminals of the other gates are closed and the second gate terminals are opened; the configuration output terminal is used to output the configuration of the first configuration terminal when the frequency of the output clock signal does not reach N times the reference clock signal or the window generation circuit is not detected to generate a valid time window signal; the configuration output terminal is used to output the configuration of the second configuration terminal when the frequency of the output clock signal reaches N times the reference clock signal and the window generation circuit is detected to generate a valid time window signal; An AND gate includes a first signal terminal connected to the configuration output terminal, a second signal terminal connected to the output terminal of the window generation circuit, and an output terminal connected to the control terminal of the gate; the output terminal of the AND gate is used to output the time window signal generated by the window generation circuit to k gates when the configuration output terminal outputs the configuration of the second configuration terminal, so that the k gates turn on the first gate terminal and turn off the second gate terminal within the time window signal.

7. The device according to claim 6, characterized in that The control component further includes: a register connected to the second configuration terminal, the register is used to store configuration information of the second mode, and the configuration information is used to indicate the value of k.

8. The device according to any one of claims 1 to 7, characterized in that The control component is further used to: If the frequency of the output clock signal still does not reach N times of the reference clock signal within the preset state monitoring time, the step of controlling the first gate end of each gate to be closed and the second gate end to be opened and subsequent steps are triggered.

9. A control method based on a frequency multiplication delay phase locked loop device, characterized in that: Used in the frequency-doubling delay-locked loop device according to any one of claims 1 to 8, the method comprises: After the frequency multiplication delay phase-locked loop is started, the first gate end of each gate is controlled to be closed and the second gate end is controlled to be open, so that the output clock signal is input into the voltage-controlled delay line and the output clock signal is frequency modulated; When the frequency of the output clock signal reaches N times that of the reference clock signal, within the time window signal generated by the window generation circuit, the first gate ends of k of the at least two gates are controlled to be turned on and the second gate ends are turned off, and the first gate ends of the other gates are kept turned off and the second gate ends are turned on, so that the reference clock signal and the output clock signal are simultaneously input into the voltage-controlled delay line, and k and N are both positive integers.

10. A timing controller chip, characterized in that: The timing controller chip includes the frequency multiplication delay phase locked loop device according to any one of claims 1 to 8.

11. A display device, characterized in that: The device comprises a plurality of display units and the timing controller chip according to claim 10.

12. An electronic device, characterized in that: Comprising the display device according to claim 11.

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