A concurrency control and traffic scheduling system for card data interaction

Abstract

This invention discloses a concurrency control and traffic scheduling system for card data interaction, relating to the fields of Internet of Things communications and distributed data processing technology. By adding a semantic addressing intent field (PIF) to the IPv6 extension header, the system enables switches to complete parsing and direct traffic to SmartNICs within 16ns. The SmartNIC generates a time-slot micro-ledger with a 500µs cycle and pre-allocates transaction locks using the Edge-Lock Weaving algorithm. Backend nodes complete strongly consistent transaction submissions using a single round of RDMA using a fast two-phase commit protocol. Dynamic congestion management is achieved through a dual-layer token bucket combined with flight windows. This solution achieves nanosecond read and write speeds, sub-millisecond submissions, and highly available decentralized scalability, significantly improving latency, throughput, and fault tolerance.

Description

Technical Field

[0001] The present invention relates to the technical field of Internet of Things communications and distributed data processing, and in particular to a concurrency control and flow scheduling system for card data interaction. Background Art

[0002] Existing card data services usually use traditional five-tuple routing and static hash scheduling. Messages lack business semantic identification at the network layer and can only rely on upper-layer applications for secondary classification, resulting in the switch being unable to divert hot traffic on the first hop; concurrency control mostly uses software-based two-phase commit or centralized lock management, and write conflicts require multiple rounds of handshakes, which easily form single-point bottlenecks, and transaction completion delays are often above milliseconds; the network speed limit mechanism is mainly based on a single-layer token bucket, which can only coarse-grained packet loss or overall speed limit for instantaneous burst traffic, and cannot identify and protect high-priority services; hardware such as SmartNIC is generally only responsible for message offloading, lacks transaction-level collaboration, and cannot sink highly correlated metadata such as lock tables and ledgers to the data plane; once local congestion or node failure occurs, centralized scheduling needs to re-converge routes, resulting in long recovery time and large service jitter, making it difficult to meet high concurrency and high consistency scenarios. Summary of the Invention

[0003] To overcome the deficiencies of the above-mentioned prior art, the present invention provides the following technical solutions: a concurrency control and traffic scheduling system for card data interaction, which sets a semantic-addressing intent field (PIF) in the IP layer header of the message to carry the card service category, service priority and security level; the programmed switch parses the PIF field at the first hop into the network and distributes the traffic to the corresponding hardware acceleration unit; the hardware acceleration unit is a SmartNIC deployed on a network card or FPGA, which generates a time slot micro-ledger (T-MSL) within a fixed time slot period and pre-allocates transaction locks using the Edge-Lock Weaving algorithm; the back-end distributed nodes submit transactions according to the micro-ledger using the fast two-phase commit (F2SC) protocol to achieve strong consistency; the system dynamically limits the traffic and manages congestion through a double-layer token bucket combined with a flight window mechanism.

[0004] Preferably, the PIF field is located in the IPv6 extension message header, has a length of 16 bits, and is encoded according to 6 bits for service category, 6 bits for priority, and 4 bits for security level.

[0005] Preferably, the programming switch uses the P4 language to define the parsing pipeline, completes PIF parsing and flow table matching within 16ns, and directs the message to different SmartNIC queues according to the PIF-Class.

[0006] Preferably, the time slot micro-ledger generation period can be configured to be 100µs to 1ms, preferably 500µs, and the synchronization accuracy is better than ±100ns.

[0007] Preferably, the micro-ledger contains the transaction sequence number, read-write set bitmap and vector clock, and the order between the ledgers is globally sorted by the vector clock.

[0008] Preferably, the Edge-Lock Weaving algorithm maps the lock address of each card to a fixed slot in the SmartNIC's local SRAM, and uses a dual-Bank-Swap approach for non-blocking migration when the lock is saturated.

[0009] Preferably, the lock slot address is obtained by taking the modulus of the hash function SHA-1 (activation timestamp | ICCID last 8 bits), and the lock migration threshold is 85% of the single bank usage rate.

[0010] Preferably, the fast two-phase commit protocol combines the write-ahead log, replication broadcast, and commit confirmation into a single-round RDMAWrite+Fence operation, using the ledger sequence number as the commit version number without the need for additional ACK messages.

[0011] Preferably, the first layer of the double-layer token bucket is speed-limited according to the PIF-Class dimension, and the second layer is speed-limited according to the card ID dimension. The flight window counter is used to monitor in-transit requests in real time to trigger margin retraction control.

[0012] Preferably, when the flight window count exceeds a set threshold, the SmartNIC pauses sending new requests to the backend with a backoff time of the cube root of the exceedance rate µs and returns a rate suggestion frame to the upstream switch.

[0013] Compared with the prior art, the present invention has the following advantages: (1) The present invention introduces the PIF field in the IPv6 extension header, encodes the service category, priority and security level at one time and completes the parsing at the first hop, so that the switch can determine the message ownership within 16ns and accurately allocate it to the corresponding SmartNIC hard queue, realizing network diversion, avoiding the extra round trip of secondary classification on the traditional application side, shortening the overall end-to-end delay compared with centralized soft load balancing, and completely eliminating the risk of hot services being overwhelmed by low-priority traffic; (2) The present invention uses the time-slot micro-ledger (T-MSL) and Edge-Lock Weaving lock weaving algorithm generated by SmartNIC regularly, pre-arranges the lock address and read-write set in the hardware SRAM dual bank, completes the write conflict detection at the network card level, and automatically Bank-Swaps the lock migration at the 85% saturation threshold. The entire process is zero-blocking and zero-software intervention, which further compresses the average lock waiting time in high-concurrency scenarios from microseconds to sub-microseconds, improves transaction throughput and eliminates the bottleneck of single-point lock table; (3) The fast two-phase commit (F2SC) protocol of the present invention utilizes single-round RDMA Write+Fence combines pre-write logs, replication, and confirmation. The ledger sequence number is the version number, and no ACK is required. Therefore, the number of network round trips for a transaction is reduced from the traditional 4-way handshake to 1. Combined with ±50ns global clock synchronization, it can achieve strict serializable consistency while maintaining sub-millisecond submission performance, getting rid of the practice of sacrificing consistency for performance. (4) The double-layer token bucket of the present invention is combined with the congestion management mechanism of flight window counting, so that the speed limit granularity covers the three dimensions of business level, card level, and in-transit request. When a certain type of business breaks out, only the token of the PIF-Class is retracted without affecting other businesses. If a single card ID is overloaded, the excess packet is locally discarded and a rate recommendation frame is sent. When the FlightWindow exceeds the limit, the SmartNIC backs off at the cubic root excess rate µs, and the upstream knows the margin in real time. This refined flow control reduces the traditional link-level packet loss rate from 10⁻³ to 10⁻ 5 , ensuring continuous low latency for critical queries; (5) The present invention's fully decentralized architecture splits traffic scheduling, lock management, and transaction sorting among switches, SmartNICs, and backend nodes, forming a distributed autonomous system with hardware-software collaboration. When any node fails, the remaining nodes seamlessly catch up based on the ledger vector clock, avoiding global downtime caused by a centralized arbitrator crash. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the overall flow of the system of the present invention.

[0015] In the figure: Terminal-side messages carry PIFs; the gateway only performs security and rate marking; the switch accurately directs traffic to the corresponding SmartNIC based on business semantics; the SmartNIC completes time-slot micro-ledger, lock weaving, and double-layer token buckets within the hardware; transaction nodes execute sequentially based on the ledger and commit in a single round using F2SC; the distributed database achieves persistence and maintains strong consistency; and the results are returned by the original path. DETAILED DESCRIPTION

[0016] The technical solution of the present invention will be further described below with reference to the accompanying drawings and through specific implementation methods.

[0017] The present invention provides a concurrency control and traffic scheduling system for card data interaction. A semantic-addressing intent field (PIF) is set in the IP layer header of the message to carry the card service category, service priority and security level. The programmed switch parses the PIF field at the first hop of network access and distributes the traffic to the corresponding hardware acceleration unit. The hardware acceleration unit is a SmartNIC deployed on a network card or FPGA. The SmartNIC generates a time-slot micro-ledger (T-MSL) within a fixed time slot period and pre-allocates transaction locks using the Edge-Lock Weaving algorithm. The back-end distributed nodes submit transactions according to the micro-ledger using the fast two-phase commit (F2SC) protocol to achieve strong consistency. The system dynamically limits the traffic and manages congestion through a double-layer token bucket combined with a flight window mechanism.

[0018] The PIF field, located in the IPv6 extension header, is 16 bits long and encodes a 6-bit service class, a 6-bit priority, and a 4-bit security level. The programmable switch uses the P4 language to define a parsing pipeline, completing PIF parsing and flow table matching in less than 16ns. Packets are then directed to different SmartNIC queues based on the PIF class. The time-slot micro-ledger generation cycle can be configured from 100µs to 1ms, with 500µs being preferred, and synchronization accuracy better than ±100ns. The micro-ledger contains transaction sequence numbers, read / write set bitmaps, and a vector clock. The order between ledgers is globally sorted using the vector clock. The Edge-Lock Weaving algorithm maps each card's lock address to a fixed slot in the SmartNIC's local SRAM. A dual-bank swap approach is used to enable non-blocking migration when the lock is saturated. The lock slot address is calculated modulo the SHA-1 hash function (activation timestamp / last 8 bits of the ICCID). The lock migration threshold is 85% single-bank utilization. The fast two-phase commit protocol combines write-ahead logging, replication broadcast, and commit confirmation into a single-round RDMAWrite+Fence operation, using the ledger sequence number as the commit version number, eliminating the need for additional ACK messages. The first layer of the two-tier token bucket limits the rate based on the PIF-Class dimension, while the second layer limits the rate based on the card ID dimension. A flight window counter monitors in-flight requests in real time, triggering margin retraction control. When the flight window count exceeds the set threshold, the SmartNIC suspends new requests to the backend with a backoff period of the cubic root of the limit-exceeding rate (µs) and returns a rate recommendation frame to the upstream switch.

[0019] Network access and PIF field injection: During the activation process, the terminal firmware writes the PIF field to the SIM / eSIM terminal. The message then enters the programmable switch SW-1 via the gateway. SW-1 uses the P4 pipeline to parse the PIF with a latency of <16ns and query the flow table: PIF-Class = "Balance Inquiry" is forwarded to SmartNIC-A queue 0; PIF-Class = "Agent Inquiry" is forwarded to SmartNIC-B queue 2.

[0020] SmartNIC-side time slot synchronization and micro-ledger construction: All SmartNICs maintain ±50ns synchronization with the IEEE-1588v2 link using a high-precision oscillator. At each 500µs time slot boundary, all transactions in the time slot queue are read; the micro-ledger header is constructed based on the card ID; the local read / write set bitmap is calculated; and the ledger is pushed to the backend transaction node.

[0021] ELW lock weaving and hot migration: lock address = SHA-1 (activation timestamp | ICCID [23:30]) mod 2 64The SmartNIC has built-in dual-bank SRAM: When the usage rate of Bank-0 exceeds 85%, the hardware automatically migrates the next transaction to Bank-1 and writes back the update mark; the old bank is regularly cleaned up in the background to ensure unblocked migration.

[0022] Backend node transaction execution: After receiving the ledger, the transaction node sorts it according to the vector clock: 1. Execute read-only transactions (snapshot reads) first; 2. Then execute update transactions (latest version of MVCC); 3. Write operations are completed in one round by F2SC:

[0023] RDMA Write → replica memory;

[0024] RDMA Fence → ensures durability;

[0025] Node local submission → returns TxID;

[0026] The failed node is automatically compensated by the remaining replicas according to the ledger sequence number, and the multi-replica Paxos log is asynchronously balanced.

[0027] Flow control and congestion management: The SmartNIC maintains two-level token buckets (ClassToken and CardToken) and FlightWindow counters. When a traffic surge triggers: if ClassTokens are exhausted, rate limiting is applied to the CL-PIF queue at the switch layer; if CardTokens are exhausted, excess packets are discarded and the recommended rate is returned; if the FlightWindow exceeds the limit, packet transmission is suspended (the excess rate is calculated in µs under the square root of the third order).

[0028] System Architecture: Access Layer (Card Gateway): Responsible for aggregating IoT device requests and carrying out primary access and authentication functions. It uses a multi-active gateway cluster and load balancer to support batch concurrent access.

[0029] Network Scheduling Layer: Deploy programmable switches / SmartNICs to implement custom traffic scheduling protocols. This layer performs fine-grained classification and distribution of requests, intelligently dividing different types of traffic (such as balance inquiries and package display requests) and routing them in parallel to different backend modules. Network devices dynamically adjust routing through mechanisms such as flow tables and time wheels, achieving multi-path adaptive scheduling.

[0030] Service Processing Layer: This layer is composed of several microservice nodes, with a core consisting of a concurrency control engine and business logic processing modules. The concurrency control engine performs global transaction scheduling, lock management, and multi-version data access. The business module performs functions such as card balance query and package allocation. Each service node is elastically scalable and maintains strict consistency through a distributed transaction protocol.

[0031] The storage layer (distributed database) utilizes a NewSQL in-memory database, with data placed in shards. Non-volatile memory (NVM) and multiple replicas ensure durability and fault tolerance. Data access is achieved through a high-speed RDMA network, supporting nanosecond read and write speeds. The underlying physical architecture consists of a CPU, high-speed memory, and SSD / NVM, supplemented by GPU / FPGA acceleration for specialized computations when necessary. The architecture is clearly layered, with networking, computing, and storage collaborating to form a fully integrated, highly concurrent processing system.

[0032] Core Module: The Global Scheduling Center: The brain of the system, receiving traffic statistics and node load information from the network layer, running a revolutionary scheduling protocol, and dynamically optimizing resource allocation. This protocol breaks away from traditional static allocation and introduces clock synchronization and priority queues, similar to Hedera's centralized scheduling concept, but with greater granularity and lower latency.

[0033] Hardware acceleration units (SmartNIC / FPGA): Deployed in key nodes and switches, they offload protocol stacks and concurrency control logic. For example, they offload some lock management and transaction verification logic to the FPGA, enabling fast conflict detection at the network card level. These hardware units also feature built-in custom pipelines for real-time monitoring of network congestion and feedback to the dispatch center.

[0034] Deterministic Transaction Engine: Utilizing a sequenced transaction mechanism, transactions entering the system are prioritized to ensure that parallel execution does not violate global order. The engine maintains a read-write set for each transaction and incorporates multi-version concurrency control to avoid lock conflicts and prolonged blocking. By implementing write-before-execution logging (WAL) and globally consistent clock synchronization, distributed transaction submission is achieved with cross-machine fault tolerance.

[0035] Multi-version data management: Data operations utilize MVCC technology. Read operations can be executed lock-free under snapshots, while write operations only require updating the latest version and broadcasting it asynchronously, significantly improving concurrency. Hot data and hot indexes can be cached or replicated to local nodes, and hardware transactional memory (HTM) optimizations can be used to reduce conflict overhead.

[0036] Adaptive Load Balancer: A real-time load balancing module exists between the service processing and storage layers. It performs weighted scheduling based on traffic type and service priority, ensuring sufficient resources are always allocated to core query interfaces (such as card balance and package inquiries). This module also automatically migrates sessions based on fault detection to ensure high availability.

[0037] Concurrency Control Mechanism: Deterministic Transaction Scheduling: Global transaction pre-ordering eliminates the non-deterministic overhead of traditional 2PC and 2PL. The system assigns a globally unique sequence number upon request acceptance. Each node only needs to maintain this sequence during parallel execution, eliminating most transaction coordination and significantly reducing lock hold times and conflict probability. Hardware-Accelerated Concurrency Management: Porting some concurrency control logic to hardware, such as implementing lock table caching and HTM transaction detection within a network interface card or FPGA. For example, leveraging hardware transactional memory technologies like Intel RTM allows for rapid tracking of cached read and write sets and conflict detection, achieving significantly higher efficiency than pure software implementations. Hotspot locks can be cached on the NIC, implementing a first-come, first-served lock strategy, significantly reducing cross-core / cross-node communication in multi-core and multi-node environments. Multi-Version Read / Write and Transaction Merging: For frequently read interfaces (such as balance inquiries and package display), the system employs snapshot reads or weak consistency strategies to ensure that most read operations do not require locks. When transactions involve cross-database writes, flexible commit strategies (such as asynchronous geo-replication followed by confirmation) and multi-version parallel commit are introduced to further reduce conflict retry rates. For updates requiring strong consistency, the minority direct write principle is adopted, and dedicated hardware is used to accelerate atomic broadcasts to ensure serializable isolation. No assumptions about architectural redundancy: The design does not rely on a single clock, a single arbitrator, or pre-defined storage. All resources (compute, storage, and network) can be dynamically added or failovered. Because the concurrency protocol is tightly coupled with the replication mechanism, even if some nodes or links fail, other nodes can seamlessly take over transaction execution, eliminating the need for complex recovery processes and fundamentally improving the system's fault tolerance.

[0038] Traffic Scheduling: A custom scheduling protocol replaces traditional static hash scheduling. The network control plane aggregates the status of each switch / node in real time and intelligently distributes traffic based on traffic characteristics (such as query type, latency sensitivity, and service priority). Unlike standard ECMP, this system proactively detects large flows and selects dedicated paths for them, while reserving low-latency paths for small flows, ensuring that most requests are completed quickly. Distributed Scheduling at the Hardware Logic Layer: Programmable logic (such as P4 programs and FPGAs) is deployed in physical switches and network interface cards (NICs) to implement multi-level scheduling decisions. Switches maintain traffic statistics through hardware tables, supporting sub-second flow migration and instantly shifting overloaded traffic to backup links. NICs run lightweight scheduling algorithms that directly adjust forwarding priorities at the packet level based on queue length and packet loss rate. This transforms the network layer into an autonomous distributed scheduling system, enabling unprecedented routing flexibility. Fine-grained traffic routing policies: The system divides traffic into extremely fine-grained granularity, no longer routing based on traditional five-tuples, but instead assigns paths based on higher-level semantics such as service intent and data freshness. For example, balance query requests with extremely strict real-time requirements can use dedicated low-latency paths; report requests that can tolerate short delays use high-throughput backup links. Mechanisms such as time wheels and token buckets are also introduced to centrally schedule bursty traffic, preventing local congestion from causing global performance crashes. Multi-dimensional resource scheduling: This not only schedules network traffic but also considers the unified scheduling of computing and storage resources. The scheduling center monitors node CPU / GPU load and storage I / O in real time. Through horizontal switching (such as migrating a task from a congested node to an idle node) and parallel execution of task sharding, each request is guaranteed resource protection at the end-to-end level.

[0039] Compared to traditional architectures, this approach eliminates centralized bottlenecks. Traditional systems often rely on centralized coordinators (such as central lock management and single-point timestamp servers), which can easily become scaling bottlenecks. Distributed programmable hardware and global pre-scheduling enable decentralized concurrency and routing control. Each node and switch can directly participate in scheduling decisions, avoiding centralized lock / clock contention and enabling linear performance scalability. Strong consistency and high performance are both achieved: Conventional high-concurrency designs often sacrifice consistency for performance (such as weak consistency in NO-SQL). Deterministic concurrency control and multi-replica synchronization technologies achieve millisecond-level response times with strong consistency (strict serializability). Hardware co-optimization: Previously, software-driven architectures struggled to leverage hardware advantages. By integrating hardware capabilities into the core architecture, FPGAs, RTM hardware, and programmable network cards are introduced to achieve a hardware-software-integrated concurrent processing system. Increased traffic control granularity: Traditional architectures often rely on general-purpose load balancing and software queue scheduling, lacking deep link state awareness. This system implements multi-layered flow sorting and fine-grained control at the network edge and within the network, ensuring that different service flows do not interfere with each other and are isolated during congestion. This strategy can avoid the Spring Festival travel rush effect in high-concurrency scenarios and, compared with the traditional single traffic model, can adapt to extreme load fluctuations more flexibly and in real time.

Claims

1. A concurrency control and traffic scheduling system for card data interaction, including a hardware acceleration unit, characterized by: Set the semantic-addressing intent field PIF in the IP layer header of the message to carry the card service category, service priority and security level; Programming the switch to parse the semantic-addressing intent field PIF at the first hop of network access and distribute the traffic to the corresponding hardware acceleration unit; The hardware acceleration unit is a SmartNIC deployed on a network card or FPGA. The SmartNIC generates a time-slot micro-ledger T-MSL within a fixed time slot period and pre-allocates transaction locks using the Edge-Lock Weaving algorithm. The back-end distributed nodes use the fast two-phase submission F2SC protocol to submit transactions based on the micro-ledger to achieve strong consistency; The system uses a double-layer token bucket combined with a flight window mechanism to dynamically limit traffic and manage congestion. The micro-ledger contains the transaction sequence number, read-write set bitmap and vector clock. The order between the ledgers is globally sorted by the vector clock. The Edge-Lock Weaving algorithm maps each card's lock address to a fixed slot in the SmartNIC's local SRAM and uses a dual-bank-swap approach for non-blocking migration when the lock is saturated. The fast two-phase commit protocol combines write-ahead logging, replication broadcast, and commit confirmation into a single-round RDMA Write+Fence operation, using the ledger sequence number as the commit version number without the need for additional ACK messages. The first layer of the double-layer token bucket limits the speed according to the PIF-Class dimension, and the second layer limits the speed according to the card ID dimension. The flight window counter is used to monitor in-transit requests in real time and trigger margin retraction control.

2. A concurrency control and traffic scheduling system for card data interaction according to claim 1, characterized in that: The semantic-addressing intent field PIF is located in the IPv6 extension message header, has a length of 16 bits, and is encoded according to the service category (6 bits), priority (6 bits), and security level (4 bits).

3. The concurrency control and traffic scheduling system for card data interaction according to claim 2, characterized in that: The programming switch uses the P4 language to define the parsing pipeline, completes PIF parsing and flow table matching within 16ns, and directs packets to different SmartNIC queues based on the PIF-Class.

4. A concurrency control and traffic scheduling system for card data interaction according to claim 3, characterized in that: The time slot micro-ledger generation period is configurable from 100µs to 1ms, with a synchronization accuracy of ±100ns.

5. The concurrency control and traffic scheduling system for card data interaction according to claim 4, characterized in that: The lock address is obtained by taking the modulus of the hash function SHA-1, and the lock migration threshold is 85% of the single bank usage rate.

6. A concurrency control and traffic scheduling system for card data interaction according to claim 5, characterized in that: When the flight window count exceeds the set threshold, the SmartNIC pauses sending new requests to the backend with a backoff time of the cube root of the exceedance rate µs and returns a rate suggestion frame to the upstream switch.

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