Residual voltage detection method and residual voltage detection circuit

Abstract

The invention discloses a residual voltage detection method and a residual voltage detection circuit, relates to the technical field of residual voltage detection, and solves the technical problem that the residual voltage detection method is easy to cause misjudgment or missing detection under complex working conditions. The detection method comprises the following steps: carrying out continuous sampling through an analog-to-digital converter to obtain N voltage sampling points of an alternating current period; based on the N voltage sampling points, square calculation, calculation of a total average value Aversion after square calculation and calculation of an arithmetic square root S of the total average value Aversion are carried out, and the arithmetic square root S is multiplied by a voltage conversion coefficient Vr to obtain a voltage effective value RMS; performing null drift dynamic calibration and real-time smooth filtering processing on the voltage effective value RMS to obtain an output voltage value Vrms; and detecting whether the output voltage value Vrms is a residual voltage based on the output voltage value Vrms, obtaining a residual voltage detection result and storing the residual voltage detection result. The DC bias error introduced by the hardware operational amplifier is eliminated, the output stability is improved, and the stability and high efficiency of residual voltage detection are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of residual voltage detection, and in particular to a residual voltage detection method and a residual voltage detection circuit. Background Art

[0002] FTU (Feeder Terminal Unit) is an important remote control, telemetry, telesignaling and fault detection device in the power grid. It can communicate with the distribution network automation master station and provide important operating status information of the distribution system and the necessary information required for various parameter measurements, including power parameters, circuit breaker switch status, three-phase fault conditions, ground fault conditions and parameters at the time of fault.

[0003] Continuous improvements in feeder automation technology, particularly the application of reclosing functions, have significantly shortened outage durations, rapidly identified fault locations, and reduced outage coverage. However, when reclosing on a permanent fault, the line will trip again, resulting in a short-term fault voltage cycle, or residual voltage, on the faulty line. In distribution automation, when reclosing a switch after a fault trip, the FTU (Failed Switch Unit) is typically required to detect the residual voltage on both sides of the switch even when the device loses power. This state is then stored and can be detected upon powering up the FTU. This allows the FTU to make logical decisions based on this information to avoid reclosing the switch on the faulty line.

[0004] Current residual pressure detection methods primarily rely on traditional, simple software algorithms. However, these methods perform poorly under complex operating conditions (such as high and low temperatures, strong electromagnetic interference, etc.), and are prone to misjudgments or missed detections. For example, in high-temperature environments, the detection accuracy of existing technologies decreases, and in certain scenarios with rapidly changing residual pressure signals, recognition may even be completely impossible. Therefore, a method that can stably and efficiently detect residual pressure under various extreme conditions is urgently needed. Summary of the Invention

[0005] The present invention aims to provide a residual voltage detection method and circuit to address the technical problem that existing residual voltage detection methods are prone to misjudgment or missed detection under complex operating conditions. The various technical effects achieved by the preferred technical solutions provided by the present invention are detailed below.

[0006] To achieve the above objectives, the present invention provides the following technical solutions:

[0007] The present invention provides a residual voltage detection method, comprising the following steps: S100: performing signal conversion and processing on alternating current, performing continuous sampling at intervals through an analog-to-digital converter and converting the sampled voltage signals into digital voltage signals, obtaining multiple groups of sampled voltage queue arrays, and obtaining N voltage sampling points of one alternating current cycle based on the data of one alternating current cycle in the sampled voltage queue array; S200: performing square calculation, total average value Average after calculating the square, and arithmetic square root S of the total average value Average in sequence based on each numerical value corresponding to the N voltage sampling points, and multiplying the arithmetic square root S by a voltage conversion coefficient Vr to obtain a voltage effective value RMS; S300: performing zero-drift dynamic calibration and real-time smoothing filtering on the voltage effective value RMS to obtain an output voltage value Vrms; S400: detecting whether the output voltage value Vrms is residual voltage based on the output voltage value Vrms, obtaining and storing a residual voltage detection result, and recording the current residual voltage status in the previous status page when storing the residual voltage detection result, and erasing the current status page.

[0008] Preferably, in step S100, the collected AC signals are two AC signals with a sampling rate of 8kHz, and the analog-to-digital converter is turned on by a timer and the interrupt of the analog-to-digital converter is triggered for continuous sampling. The number of data points in the voltage queue array is 160.

[0009] Preferably, in step S300, the zero drift dynamic calibration and real-time smoothing filtering processing process obtains the output voltage value Vrms through the following calculation formula: Vrms = Vcofe*RMS*100-V0, Vcoef = (Vset+V0) / Vaverage, wherein Vcoef is the calibration coefficient, Vset is the calibration setting value, Vaverage is the smoothing filter return value of the voltage sampling data within 1s, and V0 is the circuit zero drift value.

[0010] Preferably, in step S400, the judgment condition for residual voltage detection is: if the output voltage value Vrms collected within an AC power cycle is greater than the residual voltage threshold, and the output voltage value Vrms within a preset time is less than the no-pressure set value, it is judged as residual voltage.

[0011] Preferably, in step S400, when power is turned on, it is first detected whether there is a remote signal in the previous residual voltage status record page, and if there is a remote signal, the current residual voltage record page status is directly erased.

[0012] A residual voltage detection circuit is used to run a residual voltage detection method described in Example 1, including a processor module, a voltage sampling detection module and a power supply module. The processor module is used to calculate the effective value of the voltage and perform residual voltage judgment; the voltage sampling detection module is used to sample the voltage signal of the alternating current and convert it into a digital signal for input to the processor module. The power supply module converts the alternating current into direct current and provides power to the processor module and the voltage sampling detection module.

[0013] Preferably, the processor chip model of the processor module is HC32L110B6PA, and the processor chip is connected to the indicator light circuit through the RUN pin, and is connected to the crystal oscillator circuit through the XTLI pin and the XTLO pin.

[0014] Preferably, the voltage sampling module includes a first voltage sampling circuit and a second voltage sampling circuit. The first sampling circuit and the second voltage sampling circuit perform voltage sampling through a first amplifier and a second amplifier respectively. The models of the first amplifier and the second amplifier are both CBM8539AS8_2; the non-inverting input terminal of the first amplifier collects the Uab AC voltage signal, the inverting input terminal is grounded, and the output terminal is connected to the Pab_C pin of the processor; the non-inverting input terminal of the second amplifier collects the Ucb AC voltage signal, the inverting input terminal is grounded, and the output terminal is connected to the Pcb_C pin of the processor.

[0015] Preferably, the power supply module includes a rectifier circuit and a DC-DC conversion circuit. The rectifier circuit converts AC power into DC power through a transformer and a KBP206 rectifier bridge. The DC-DC conversion circuit converts the rectified DC power into +3.3V DC power through an SCT2632 chip.

[0016] Implementing one of the above technical solutions of the present invention has the following advantages or beneficial effects:

[0017] In this invention, the calibration coefficient is calculated using the sample mean value, achieving dynamic zero-drift calibration and eliminating DC offset errors introduced by hardware op amps. Real-time smoothing filtering is also performed to improve output stability. Efficient root mean square (RMS) calculation ensures high accuracy and noise immunity, thus ensuring stable and efficient residual voltage detection. Furthermore, the residual voltage detection result storage method reduces the detection time to 50ms, compared to the 60ms detection time of the existing technology, while also reducing the false positive rate to near zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work. In the drawings:

[0019] Figure 1 This is a flow chart of a residual voltage detection method according to embodiment 1 of the present invention;

[0020] Figure 2 This is a power-on waveform diagram of a residual voltage detection method according to embodiment 1 of the present invention;

[0021] Figure 3 1 is a schematic diagram of residual voltage storage in a residual voltage detection method according to embodiment 1 of the present invention;

[0022] Figure 4 This is a residual pressure storage flow chart of a residual pressure detection method according to a second embodiment of the present invention;

[0023] Figure 5 1 is a circuit diagram of a processing module of a residual voltage detection circuit according to a second embodiment of the present invention;

[0024] Figure 6 1 is a circuit diagram of a first voltage sampling circuit of a residual voltage detection circuit according to a second embodiment of the present invention;

[0025] Figure 7 1 is a circuit diagram of a first voltage sampling circuit of a residual voltage detection circuit according to a second embodiment of the present invention;

[0026] Figure 8 This is a circuit diagram of a power supply module of a residual voltage detection circuit according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the objects, technical solutions and advantages of the present invention clearer, the various exemplary embodiments to be described below will refer to the corresponding drawings, which constitute a part of the exemplary embodiments, in which various exemplary embodiments that may be used to implement the present invention are described. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present disclosure. It should be understood that they are only examples of processes, methods and devices that are consistent with some aspects of the present disclosure as detailed in the appended claims, and other embodiments may also be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and essence of the present invention.

[0028] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse" and the like indicate the orientation or positional relationship based on the figures, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the elements referred to must have a specific orientation, be constructed and operated in a specific orientation. The terms "first", "second" and the like are only used for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "multiple" means two or more. The terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0029] In order to illustrate the technical solution of the present invention, a specific embodiment is provided below, in which only the parts related to the embodiment of the present invention are shown.

[0030] Example 1:

[0031] like Figure 1 As shown, the present invention provides a residual voltage detection method, comprising the following steps. S100: Convert and process the AC signal, adjusting the original AC signal to specifications suitable for sampling and ADC (analog-to-digital converter) input, to achieve the purposes of protecting the ADC, adapting the ADC input range, improving the signal-to-noise ratio, and filtering. Specifically, the method can be implemented using existing technologies, with the analog-to-digital converter performing continuous sampling at intervals and converting the sampled data into a digital voltage signal. The interval facilitates periodic calculation and storage of the sampled data, improving operational flexibility. For example, sampling is performed every 1ms for residual voltage detection. Continuous sampling ensures the integrity of the sampled data within an AC cycle, resulting in multiple groups of sampled voltage queue arrays, each group of sampled voltage queue arrays corresponding to an AC cycle of 20ms, thereby facilitating subsequent calculation and processing of each sampled voltage value. Based on the data of an AC cycle in the sampled voltage queue array, N voltage sampling points of the AC cycle are obtained. In this embodiment, N is 160, namely V1, V2, ..., V160. S200: Based on each value corresponding to the N voltage sampling points, that is, 160 voltage sampling values, squares are calculated in sequence (i.e., V1^2, V2^2, ..., V160^2), and the total average value after square calculation is calculated. Calculate the square root of the total average value The calculation of the arithmetic root mean square (S) can also be combined with a Kalman filter (optimized sample data processing) operation. The arithmetic square root (S) is multiplied by the voltage conversion coefficient (Vr) (RMS = S × Vr) to obtain the voltage effective value (RMS). The voltage conversion coefficient (Vr) refers to the conversion ratio between the input voltage and the output voltage measured after conversion by the analog-to-digital converter in this embodiment. The voltage effective value (RMS) is a core parameter for measuring the magnitude of an AC voltage. It represents the DC voltage equivalent to this AC voltage in terms of work capacity. Obtaining this voltage value facilitates further determination of the residual voltage condition. S300: The voltage effective value (RMS) is subjected to dynamic zero-drift calibration (using the 2S sampling average to calculate the calibration coefficient) and real-time smoothing filtering (a low-pass filter can also be used to suppress rapid fluctuations) to obtain the output voltage value (Vrms). S400: Based on the output voltage value (Vrms), the output voltage value (Vrms) is tested to determine whether it represents residual voltage. The test result is obtained and stored, allowing the FTU test equipment to read the residual voltage signal detected by the residual voltage detection circuit. When the residual pressure test result is stored, the current residual pressure status is recorded in the previous status page and the current status page is erased. Figure 2 As shown, after the residual voltage detection MCU is powered on, it needs to wait for the clock to stabilize. It is measured that it takes about 15ms to run to the main function. Because the detection standard is to detect a residual voltage of not less than 110V for 60ms (50ms-55ms in this embodiment), but the detection chip has lost 15ms of detection time when it starts running; the time for the MCU to erase a page of flash is 5ms, and the time for detecting a cycle is 20ms. And no interrupt is generated during erasing, so in some extreme cases, sampling the traditional erasing method will miss the residual voltage information due to the long initialization time, resulting in no detection. Therefore, in this embodiment, Figure 3 As shown, when the residual voltage detection result is stored, the current residual voltage status is recorded in the last status page, and the current status page is erased. Therefore, the Flash storage page has the current residual voltage status and the last residual voltage status. Since the last residual voltage status is sent during residual voltage communication, the current residual voltage status will be recorded in the last status page when powered on for the second time, and the current status will be erased to prepare for the next residual voltage record. When powered on, it will first detect whether there is a telesignal (data communication for recording changes in the status of power equipment) on the last residual voltage status record page. If there is a telesignal, it means that the FTU has not actively erased the residual voltage detection telesignal status. At this time, the current residual voltage record page status can be directly erased to prepare for the next residual voltage record. In this embodiment, the calibration coefficient is calculated using the sampling mean value to achieve zero drift dynamic calibration, eliminate the DC bias error introduced by the hardware operational amplifier, and perform real-time smoothing filtering to improve output stability. High precision and noise resistance are also ensured through efficient root mean square calculation, thereby ensuring stable and efficient residual voltage detection. The residual voltage detection result storage method of this embodiment shortens the detection time to 50ms compared with the 60ms detection time in the prior art, and the false positive rate is close to 0.

[0032] As an optional implementation, in step S100, the collected AC signal is two-way AC, that is, this embodiment is used to detect the residual voltage of two-phase AC, and the sampling rate is 8kHz, that is, a voltage data is sampled every 0.125ms, and the timer is used to start the analog-to-digital converter and trigger the analog-to-digital converter interrupt for continuous sampling. By starting the analog-to-digital converter and interrupting the analog-to-digital converter, sampling at intervals is achieved. The interval time can be set as needed, such as 1ms, so that real-time residual voltage detection can be achieved. There are 160 data points in the voltage queue array, and the period corresponding to 50Hz AC is 20ms. The sampling rate is 8kHz, that is, a voltage data can be sampled every 0.125ms, so that there are 160 data points in each voltage queue array.

[0033] As an optional implementation, in step S300, the calibration filter processing process obtains the output voltage value Vrms through the following calculation formula: Vrms = Vcofe*RMS*100-V0, Vcoef = (Vset+V0) / Vaverage, where Vcoef is the calibration coefficient (due to the presence of capacitors and inductors in the residual voltage measurement circuit, if no calibration is performed, there will be a certain deviation between the measured value and the actual value, which will lead to inaccurate final calculation results. For example, if the actual input voltage is 220V, the uncalibrated measured value may be 221.8V. The calibration coefficient can be obtained by comparing the two values, so that the value of each sampling * this calibration coefficient can obtain the actual accurate value. In this embodiment, the calibration coefficient is calculated using the average value of 2S voltage sampling), and Vset is the calibration setting Fixed value (the calibration setting value is the actual voltage given when calculating the calibration coefficient. For example, if the actual voltage is 200V, the calibration setting value is 200. This is the voltage value to be finally obtained, and only one calibration is required), Vaverage is the return value of the smoothing filter of the voltage sampling data within 1s (smoothing filtering can suppress noise and improve signal stability, thereby obtaining a more stable and accurate voltage sampling value), V0 is the circuit zero drift value (the circuit zero drift value exists in general analog-to-digital conversion circuits, that is, when no voltage is input, a voltage of 1-2V can still be measured. This is due to the voltage division of some capacitors and resistors in the circuit, which will be amplified by multiplying the conversion coefficient. However, this error is constant, and this error must be subtracted for each calculation. During calibration, the error must be added to obtain a more accurate voltage value).

[0034] As an optional implementation, in step S400, the judgment condition for residual voltage detection is: if the output voltage value Vrms collected within an AC power cycle is greater than the residual voltage threshold, the residual voltage threshold is set according to the user's test needs, and the output voltage value Vrms within the preset time is less than the no-voltage set value, it is judged as residual voltage. The no-voltage set value is a protection setting value set for the power system in a no-voltage state, mainly used for low-voltage protection or undervoltage locking devices. When the line or equipment detects that the voltage disappears or is lower than the threshold (such as a power outage or short-circuit fault), the protection device triggers the action according to the preset "no-voltage set value". Performing residual voltage detection and judgment in this way facilitates improving the accuracy and efficiency of residual voltage detection.

[0035] As an optional implementation, in step S400, when power is turned on (all modules of the residual voltage detection circuit are powered on and running), first check whether there is telesignaling (i.e. remote status signal acquisition and transmission, mainly used for real-time monitoring of the operating status of power equipment) on the last residual voltage status record page. If there is telesignaling (if there is telesignaling, it means that the FTU has not actively erased the telesignaling status of the residual voltage module), then directly erase the status of the current residual voltage record page. Erasing the recording area first each time power is turned on and synchronizing the information to a certain area according to the corresponding processing can avoid the time discontinuity and long delay caused by flash erasure. While reducing the detection time, it avoids the impact of discontinuous data of the analog-to-digital converter caused by no interruption, thereby reducing the detection error and improving the accuracy. The specific implementation process is as follows: Figure 4 shown.

[0036] The embodiment is only a special example and does not represent only one way of implementing the present invention.

[0037] Example 2:

[0038] A residual voltage detection circuit is used to run a residual voltage detection method in Example 1, including a processor module, a voltage sampling detection module and a power supply module. The processor module is used to calculate the effective value of the voltage and perform residual voltage judgment; the voltage sampling detection module is used to sample the voltage signal of the alternating current and convert it into a digital signal to input into the processor module; the power supply module converts the alternating current into direct current and supplies power to the processor module and the voltage sampling detection module. In this embodiment, the residual voltage detection circuit uses the sampling mean value to calculate the calibration coefficient to achieve zero-drift dynamic calibration, eliminate the DC bias error introduced by the residual voltage detection circuit op amp, and perform real-time smoothing and filtering to improve output stability. It also ensures high precision and noise resistance through efficient root mean square calculation, thereby ensuring stable and efficient residual voltage detection.

[0039] As an optional implementation, Figure 5As shown, the processor module's processor chip is the HC32L110B6PA. The processor chip is connected to the indicator circuit via the RUN pin. When the RUN pin is low, the indicator light in the indicator circuit turns on, indicating whether the residual voltage detection circuit is operating. The processor chip is connected to the crystal oscillator circuit via the XTLI and XTLO pins. The specific specifications of the crystal X1 in the crystal oscillator circuit can be selected based on needs. The HC32L110B6PA is an ultra-low-power microcontroller chip based on the ARM Cortex-M0+ core, launched by Huada Semiconductor. It is widely used in battery-powered and power-sensitive applications such as the Internet of Things, consumer electronics, and industrial control. Its low cost, low power consumption, and minimalist design make it suitable for cost- and power-sensitive applications. The M0 core chip will prohibit interrupts when reading and writing flash, and erasing takes a long time, which will extend the power-on time. However, through the storage method in the embodiment, that is, erasing the recording area first when powering on and synchronizing the information to a certain area according to the corresponding processing, the time discontinuity and long delay caused by flash erasing can be avoided, thereby reducing the detection time, and at the same time avoiding the impact of discontinuous data on the analog-to-digital converter caused by no interruption, which can reduce detection errors and improve accuracy.

[0040] As an optional implementation, Figure 6-Figure 7 As shown, the voltage sampling module includes a first voltage sampling circuit and a second voltage sampling circuit. The first and second voltage sampling circuits sample voltages through a first and second amplifier, respectively. Both amplifiers are CBM8539AS8_2 models, generating a DC voltage with a peak value of 1.587V, facilitating sampling calculations. The CBM8539AS8_2 amplifier uses auto-zeroing technology to simultaneously provide extremely low offset voltage, achieving near-zero drift over temperature and overtime. It also features ultra-low noise, offset, and power, achieving unity-gain stability, and thus outputting stable sampled voltage information to the processor chip. The first amplifier's non-inverting input samples the Uab AC voltage signal, while its inverting input is grounded. Its output is connected to the processor's Pab_C pin. The second amplifier's non-inverting input samples the Ucb AC voltage signal, while its inverting input is grounded. Its output is connected to the processor's Pcb_C pin. In other words, the non-inverting inputs of the first and second amplifiers receive the converted AC signal, while their outputs provide reliable sampled voltage information to the processor chip.

[0041] As an optional implementation, Figure 8As shown, the power supply module includes a rectifier circuit and a DC-DC converter circuit. The rectifier circuit converts AC power to DC power via a transformer and a KBP206 rectifier bridge. The KBP206 is a widely used 2A / 600V universal rectifier bridge. It uses a 4-pin plug-in package for easy installation and has advantages such as high reliability and low power consumption. Specifically, in this embodiment, the two AC sources pass through transformer T1 and rectifier bridge BR1, and transformer T2 and rectifier bridge BR2, respectively, to obtain a DC voltage. The DC-DC converter circuit converts the rectified DC power to +3.3V DC power via the SCT2632 chip. The SCT2632 is a high-efficiency, wide-input voltage range synchronous step-down DC-DC converter chip launched by Core Island Technology. It is widely used in industrial control, automotive electronics, and portable devices. It has an output voltage of 0.8V-50V and features overvoltage protection, overtemperature protection, output overvoltage protection, and input undervoltage protection. This facilitates the generation of a stable and reliable +3.3V DC power, ensuring the continuous and stable operation of the processor module and voltage sampling and detection module.

[0042] The foregoing is merely a preferred embodiment of the present invention. Those skilled in the art will appreciate that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the guidance of the present invention, these features and embodiments may be modified to suit specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be within the scope of the present invention.

Claims

1. A residual pressure detection method, characterized in that: The following steps are involved: S100: Performing signal conversion and processing on the AC power, performing continuous sampling at intervals through an analog-to-digital converter and converting the sampled voltage signals into digital voltage signals, obtaining multiple groups of sampled voltage queue arrays, and obtaining N voltage sampling points of one AC power cycle based on the data of one AC power cycle in the sampled voltage queue arrays; S200: Based on each value corresponding to the N voltage sampling points, calculate the square, calculate the total average value Average after the square, calculate the arithmetic square root S of the total average value Average, and multiply the arithmetic square root S by the voltage conversion coefficient Vr to obtain the voltage effective value RMS; S300: Performing zero-drift dynamic calibration and real-time smoothing filtering on the voltage RMS to obtain an output voltage value Vrms; S400: Based on the output voltage value Vrms, whether the output voltage value Vrms is residual voltage is detected, and the residual voltage detection result is obtained and stored. When storing the residual voltage detection result, the current residual voltage status is recorded in the previous status page, and the current status page is erased.

2. A residual voltage detection method according to claim 1, characterized in that: In step S100, the collected AC signals are two AC signals with a sampling rate of 8kHz. The analog-to-digital converter is started by a timer and the interrupt of the analog-to-digital converter is triggered for continuous sampling. The number of data points in the voltage queue array is 160.

3. The residual voltage detection method according to claim 1, wherein: In step S300, the zero drift dynamic calibration and real-time smoothing filtering process obtains the output voltage value Vrms through the following calculation formula: Vrms=Vcofe*RMS*100-V0, Vcoef=(Vset+V0) / Vaverage, Where Vcoef is the calibration coefficient, Vset is the calibration setting value, Vaverage is the smoothing filter return value of the voltage sampling data within 1s, and V0 is the circuit zero drift value.

4. The residual voltage detection method according to claim 1, wherein: In step S400, the residual voltage detection condition is: if the output voltage value Vrms collected within an AC power cycle is greater than the residual voltage threshold, and the output voltage value Vrms within a preset time is less than the no-pressure set value, it is judged as residual voltage.

5. The residual voltage detection method according to claim 1, characterized in that: In step S400, when power is turned on, it is first detected whether there is a remote signal on the previous residual voltage status record page. If there is a remote signal, the current residual voltage record page status is directly erased.

6. A residual voltage detection circuit, characterized in that: A residual voltage detection method for running any one of claims 1-6, comprising a processor module, a voltage sampling detection module and a power supply module, wherein the processor module is used to calculate the effective value of the voltage and perform residual voltage judgment; the voltage sampling detection module is used to sample the voltage signal of the alternating current and convert it into a digital signal input into the processor module, and the power supply module converts the alternating current into direct current and supplies power to the processor module and the voltage sampling detection module.

7. The residual voltage detection circuit according to claim 7, characterized in that: The processor chip model of the processor module is HC32L110B6PA. The processor chip is connected to the indicator light circuit through the RUN pin and is connected to the crystal oscillator circuit through the XTLI pin and the XTLO pin.

8. The residual voltage detection circuit according to claim 7, characterized in that: The voltage sampling module includes a first voltage sampling circuit and a second voltage sampling circuit. The first sampling circuit and the second voltage sampling circuit perform voltage sampling through a first amplifier and a second amplifier respectively. The models of the first amplifier and the second amplifier are both CBM8539AS8_2; the non-inverting input terminal of the first amplifier collects the Uab AC voltage signal, the inverting input terminal is grounded, and the output terminal is connected to the Pab_C pin of the processor; the non-inverting input terminal of the second amplifier collects the Ucb AC voltage signal, the inverting input terminal is grounded, and the output terminal is connected to the Pcb_C pin of the processor.

9. The residual voltage detection circuit according to claim 7, characterized in that: The power supply module includes a rectifier circuit and a DC-DC conversion circuit. The rectifier circuit converts AC power into DC power through a transformer and a KBP206 rectifier bridge. The DC-DC conversion circuit converts the rectified DC power into +3.3V DC power through an SCT2632 chip.

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