Input / output circuit and chip

Abstract

The application is suitable for the chip design technical field, and provides an input and output circuit and a chip. The input and output circuit comprises a first driving module, a first switching module, a first voltage-resistant module, a second switching module, a pull-up module, a second voltage-resistant module and a second driving module. The first switching module is electrically connected with the first driving module and the first voltage-resistant module respectively. The second voltage-resistant module is electrically connected with the first voltage-resistant module, the second driving module and the pull-up module respectively. The second switching module is electrically connected with the pull-up module. The first voltage-resistant module and the second voltage-resistant module are electrically connected with a burning foot of the chip. The first driving module and the second driving module are electrically connected with a core module of the chip. The input and output circuit of the application completes data burning and data reading by using a single burning foot, without the need of additionally setting independent burning feet and data transmission feet, thereby significantly saving the chip foot resources and improving the economy and integration of the chip design.

Description

Technical Field

[0001] The present application belongs to the field of chip design technology, and in particular relates to an input and output circuit and a chip. Background Art

[0002] To program the chip's internal Flash memory, a dedicated VPP pin is typically required. This pin is directly connected to the Flash memory cell and is specifically used to provide a programming voltage higher than the chip's normal operating voltage during the programming process. Because other internal chip circuits cannot withstand this high voltage, the VPP pin must be physically isolated from the regular IO (Input / Output) pins, preventing functional reuse. Furthermore, data input (programming data) and output (reading data) must rely on separate IO pins for transmission. This requires at least two dedicated pins, resulting in a waste of pin resources. Summary of the Invention

[0003] The embodiments of the present application provide an input-output circuit and chip, which can solve the problem that the existing IO circuit requires at least two dedicated pins, resulting in a waste of pin resources.

[0004] In a first aspect, an embodiment of the present application provides an input-output circuit, including a first driver module, a first switch module, a first voltage-resistant module, a second switch module, a pull-up module, a second voltage-resistant module, and a second driver module, wherein the first switch module is electrically connected to the first driver module and the first voltage-resistant module, respectively, the second voltage-resistant module is electrically connected to the first voltage-resistant module, the second driver module, and the pull-up module, respectively, the second switch module is electrically connected to the pull-up module, the first voltage-resistant module and the second voltage-resistant module are both electrically connected to the burning pins of a chip, and the first driver module and the second driver module are both used to be electrically connected to the core module of the chip;

[0005] During data transmission to the chip via the programming pin, the first voltage-withstand module is configured to clamp a first node voltage to a first preset voltage when the voltage of the programming pin is greater than the power supply voltage of the chip, where the first node voltage is the voltage at a common terminal of the first voltage-withstand module and the first switch module; the second voltage-withstand module is configured to clamp a second node voltage to a second preset voltage when the voltage of the programming pin is greater than the power supply voltage of the chip, where the second node voltage is the voltage at a common terminal of the second voltage-withstand module and the second driver module; and the second driver module is configured to output a target voltage to the core module and the second switch module according to the second node voltage.

[0006] During the process of the chip outputting data through the burning pin, the first driving module is used to output a driving signal to the first switching module according to the control signal output by the core module; the first switching module is used to be turned on or off according to the driving signal to adjust the first node voltage; the second switching module is used to be turned on according to the target voltage; and the pull-up module is used to pull up the second node voltage when the first switching module is turned off and the second switching module is turned on.

[0007] In a possible implementation of the first aspect, the first driving module includes a first driver, an input end of the first driver is used to receive the control signal, and an output end of the first driver is electrically connected to the first switch module.

[0008] In a possible implementation of the first aspect, the first switch module includes a first switch tube, a control end of the first switch tube is electrically connected to the first driving module, a first conduction end of the first switch tube is electrically connected to the first voltage-resistant module, and a second conduction end of the first switch tube is grounded.

[0009] In a possible implementation of the first aspect, the first voltage-resistant module includes a first MOS transistor, a control end of the first MOS transistor is used to receive a first gate drive signal, a first conductive end of the first MOS transistor is electrically connected to the burning pin, and a second conductive end of the first MOS transistor is electrically connected to the first switch module.

[0010] In a possible implementation of the first aspect, the second switch module includes a second switch tube, a control end of the second switch tube is electrically connected to the second driving module, a first conduction end of the second switch tube is used to be electrically connected to the first power supply, and a second conduction end of the second switch tube is electrically connected to the pull-up module.

[0011] In a possible implementation of the first aspect, the pull-up module includes a first resistor, a first end of the first resistor is electrically connected to the second switch module, and a second end of the first resistor is electrically connected to the second voltage-resistant module and the second driving module respectively.

[0012] In a possible implementation of the first aspect, the second voltage-resistant module includes a second MOS transistor, a control end of the second MOS transistor is used to receive a second gate drive signal, a first conductive end of the second MOS transistor is electrically connected to the burning pin, and a second conductive end of the second MOS transistor is electrically connected to the pull-up module and the second drive module, respectively.

[0013] In a possible implementation of the first aspect, the first voltage-resistant module includes a first voltage-stabilizing diode connected between the programming pin and the first switch module;

[0014] The second voltage-resistant module includes a second voltage-stabilizing tube, and the second voltage-stabilizing tube is connected between the programming pin and the second driving module.

[0015] In a possible implementation of the first aspect, the second driving module includes a second driver, an input end of the second driver is electrically connected to the second voltage-resistant module and the pull-up module respectively, and an output end of the second driver is used to output the target voltage.

[0016] In the second aspect, an embodiment of the present application provides a chip, comprising a core module, a burning pin and an input-output circuit as described in any one of the first aspects, wherein the core module is electrically connected to the first driving module and the second driving module in the input-output circuit, respectively, and the burning pin is electrically connected to the first voltage-resistant module and the second voltage-resistant module in the input-output circuit, respectively.

[0017] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0018] The input and output circuit provided in the embodiments of the present application comprises a first driving module, a first switching module, a first voltage-resistant module, a second switching module, a pull-up module, a second voltage-resistant module and a second driving module. In the burning process, that is, in the process of transmitting data from an external device to a chip through a burning pin, input data is transmitted to the second driving module through the burning pin and the second voltage-resistant module, and a target voltage is output from the second driving module to the core module and temporarily stored by the core module. At this time, the external device drives the burning pin to a high voltage higher than the power voltage of the chip and keeps it, and the core module writes the temporarily stored data into the Flash storage module of the chip. In this process, the first voltage-resistant module and the second voltage-resistant module can monitor the voltage of the burning pin in real time, and when the voltage of the burning pin is greater than the power voltage of the chip, the first node voltage and the second node voltage are clamped respectively, thereby effectively avoiding damage to the second driving module, the core module and other elements in the chip caused by high voltage in the burning process, and ensuring the safety of the burning process. In the reading process, that is, in the process of transmitting data from the chip to the external device through the burning pin, the first driving module outputs a driving signal to the first switching module according to the control signal output from the core module, so that the first switching module is turned on or turned off according to the driving signal, thereby adjusting the first node voltage. At the same time, the second switching module is turned on according to the target voltage. The pull-up module can pull up the second node voltage when the first switching module is turned off and the second switching module is turned on. Since the first voltage-resistant module and the second voltage-resistant module are equivalent to wires when the voltage of the burning pin is less than or equal to the power voltage of the chip, the first node voltage, the second node voltage and the voltage of the burning pin remain the same. Therefore, through the coordinated action of the first switching module, the second switching module and the pull-up module, the transmission of data from the burning pin to the external device can be stably realized. As can be seen, the input and output circuit provided in the embodiments of the present application realizes high voltage clamping protection by adding the first voltage-resistant module and the second voltage-resistant module, and successfully makes a single burning pin have three functions of "receiving data, loading burning high voltage and outputting reading data" through the coordinated work of the first driving module, the second driving module, the first switching module, the second switching module and the pull-up module, so that data burning and data reading are completed by using a single burning pin, without the need of additionally setting independent burning pins and data transmission pins, thereby significantly saving the chip pin resources and improving the economy and integration of chip design. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1is a circuit schematic diagram of an existing input / output circuit;

[0021] Figure 2 is a principle block diagram of an input / output circuit provided by an embodiment of the present application;

[0022] Figure 3 is a circuit connection schematic diagram of an input / output circuit provided by an embodiment of the present application;

[0023] Figure 4 is a circuit connection schematic diagram of an input / output system provided by an embodiment of the present application.

[0024] In the figure, 10, input / output circuit; 101, first driving module; 102, first switch module; 103, first voltage-resistant module; 104, second switch module; 105, pull-up module; 106, second voltage-resistant module; 107, second driving module. DETAILED DESCRIPTION

[0025] In the following description, for the purpose of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

[0026] It should be understood that the term "comprises" when used in this specification and the appended claims indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] It should also be understood that the term "and / or" when used in this specification and the appended claims, such as in the phrases "A and / or B" and "A and / or B and / or C", means any combination of one or more of the associated listed items, and that includes one or more of the associated listed items by itself, as well as any combination of one or more of the associated listed items with one or more of the other associated listed items.

[0028] As used in this specification and the appended claims, the term "if' can be construed to mean "when" or "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be construed to mean "upon determining" or "in response to determining" or "upon detecting [the described condition or event]" or "in response to detecting [the described condition or event]", depending on the context.

[0029] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0030] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0031] like Figure 1 As shown in the figure, to program the internal Flash memory of a chip, a dedicated VPP pin is typically required. This pin is directly connected to the Flash memory cell and is specifically used to provide a programming voltage higher than the chip's normal operating voltage during the programming process. Because other circuits within the chip cannot withstand this high voltage, the VPP pin must be physically isolated from the normal IO pins, making functional reuse impossible. Furthermore, data input (programming data) and output (reading data) must rely on separate IO pins for transmission. This requires at least two dedicated pins, resulting in a waste of pin resources.

[0032] Based on the above problems, the input-output circuit provided in the embodiment of the present application is arranged in the chip, and the input-output circuit includes a first driving module, a first switching module, a first voltage-resistant module, a second switching module, a pull-up module, a second voltage-resistant module and a second driving module.

[0033] During the programming process—that is, when an external device transmits data to the chip via the programming pins—the input data is transmitted via the programming pins and the second voltage-withstand module to the second driver module. The second driver module then outputs the target voltage to the core module, which then temporarily stores the data. At this point, the external device drives the programming pins to a voltage exceeding the chip's power supply voltage and maintains it there. The core module then writes the temporarily stored data to the chip's Flash memory module. During this process, the first and second voltage-withstand modules monitor the programming pin voltage in real time. When the programming pin voltage exceeds the chip's power supply voltage, they clamp the voltage at the first and second nodes, respectively. This effectively prevents high voltage damage to the second driver module, the core module, and other components within the chip during programming, ensuring the safety of the programming process.

[0034] During the reading process—that is, when the chip transmits data to an external device via the programming pin—the first driver module outputs a drive signal to the first switch module based on the control signal output by the core module. This turns the first switch module on or off according to the drive signal, thereby adjusting the voltage at the first node. Simultaneously, the second switch module turns on according to the target voltage. The pull-up module pulls up the voltage at the second node when the first switch module is off and the second switch module is on. Since the voltage at the programming pin is less than or equal to the chip's power supply voltage, the first and second voltage-resistant modules act as conductors, ensuring that the voltages at the first and second nodes are consistent with the voltage at the programming pin. Therefore, the coordinated action of the first and second switch modules and the pull-up module ensures stable data transmission to an external device via the programming pin.

[0035] It can be seen from this that the input and output circuit provided in the embodiment of the present application realizes high-voltage clamping protection by adding a first voltage-resistant module and a second voltage-resistant module, and combines the coordinated work of the first driving module, the second driving module, the first switch module, the second switch module and the pull-up module to successfully enable a single burning pin to have the three functions of "receiving data, loading burning high voltage, and outputting read data". Data burning and data reading are completed using a single burning pin, and there is no need to set up independent burning pins and data transmission pins, which significantly saves chip pin resources and improves the economy and integration of chip design.

[0036] In order to illustrate the technical solution described in this application, specific embodiments are provided below.

[0037] Figure 2 FIG1 shows a block diagram of the principle of the input and output circuit 10 provided in one embodiment of the present application. Figure 2 As shown, the input-output circuit 10 includes a first driving module 101, a first switch module 102, a first voltage-resistant module 103, a second switch module 104, a pull-up module 105, a second voltage-resistant module 106 and a second driving module 107. The first switch module 102 is electrically connected to the first driving module 101 and the first voltage-resistant module 103, respectively. The second voltage-resistant module 106 is electrically connected to the first voltage-resistant module 103, the second driving module 107 and the pull-up module 105, respectively. The second switch module 104 is electrically connected to the pull-up module 105. The first voltage-resistant module 103 and the second voltage-resistant module 106 are both electrically connected to the programming pin (i.e., the VPP pin) of the chip and an external device. The first driving module 101 and the second driving module 107 are both used to be electrically connected to the core module of the chip.

[0038] Specifically, during the programming process—that is, when an external device transmits data to the chip via the programming pins—the input data is transmitted to the second driver module 107 via the programming pins and the second voltage-withstand module 106. The second driver module 107 then outputs a target voltage to the core module and the second switch module 104 based on the second node voltage. The core module then temporarily stores the target voltage. At this point, the external device drives the programming pins to a voltage exceeding the chip's power supply voltage and maintains this voltage. The core module then writes the temporarily stored data to the chip's Flash memory module. During this process, the first voltage-withstand module 103 and the second voltage-withstand module 106 monitor the programming pin voltage in real time. When the programming pin voltage exceeds the chip's power supply voltage, they clamp the first node voltage (i.e., the voltage at node N1) and the second node voltage (i.e., the voltage at node N2), respectively. This effectively prevents high voltage damage to the second driver module 107, the core module, and other components within the chip during the programming process, ensuring the safety of the programming process.

[0039] During the reading process—that is, when the chip transmits data to an external device via the programming pin—the first driver module 101 outputs a drive signal to the first switch module 102 based on the control signal output by the core module. This turns the first switch module 102 on or off according to the drive signal, thereby adjusting the voltage at the first node. Simultaneously, the second switch module 104 turns on according to the target voltage. The pull-up module 105 pulls up the voltage at the second node when the first switch module 102 is off and the second switch module 104 is on. Since the voltage at the programming pin is less than or equal to the chip's power supply voltage, the first and second voltage-resistant modules 103 and 106 act as conductors, ensuring that the voltages at the first and second nodes are consistent with the voltage at the programming pin. Therefore, the coordinated action of the first and second switch modules 102, 104, and pull-up module 105 enables stable data transmission to an external device via the programming pin.

[0040] It can be seen that the input-output circuit 10 provided in the embodiment of the present application realizes high-voltage clamping protection by adding a first voltage-resistant module 103 and a second voltage-resistant module 106, and combines the coordinated work of the first driving module 101, the second driving module 107, the first switch module 102, the second switch module 104 and the pull-up module 105, so that a single burning pin can successfully have the three functions of "receiving data, loading burning high voltage, and outputting read data". A single burning pin is used to complete data burning and data reading, without the need to set up independent burning pins and data transmission pins, which significantly saves chip pin resources and improves the economy and integration of chip design.

[0041] It should be noted that during the programming process, when the programming pin is high, the voltage at the second node is also high, and node Y is high. When the programming pin is low, the voltage at the second node is also low, and node Y is low. During this process, the voltage at the second node follows the high and low levels of the programming pin, and the turning on or off of the second switch module 104 does not affect the voltage level signal at the second node. Specifically, when the target voltage is high, the second switch module 104 is turned off, and when the target voltage is low, the second switch module 104 is turned on. When the second switch module 104 is turned off according to the target voltage, the pull-up module 105 has no conductive path and therefore does not affect the voltage at the second node. When the second switch module 104 is turned on according to the target voltage, due to the sufficient driving capability of the external device and the large resistance of the pull-up module 105, the external device's driving capability is sufficient to pull the voltage at the second node down to a low level, while the pull-up module 105 is insufficient to pull the voltage at the second node up to a high-level threshold.

[0042] For example, the programming voltage required during a programming operation is typically 9.3V, while the chip's normal power supply voltage generally does not exceed 5.5V (a significant voltage difference exists between the two). During the programming process, after an external device transmits the data to be programmed (input data) to the programming pin and the core module temporarily stores it, the programming pin is driven to a high voltage of 9.3V by the external device and maintained at this voltage. It is during this high-voltage hold phase that the core module writes the temporarily stored data to the Flash storage module. To address the compatibility issues between "high-voltage programming" and "low-voltage signal transmission," this application adds a first voltage-resistant module 103 and a second voltage-resistant module 106. When the programming pin is at a high voltage of 9.3V, the two voltage-resistant modules clamp the internal node voltages within the chip's power supply voltage range (≤5.5V), ensuring that the driver module and core module are not damaged by the high voltage. During normal reading or data transmission (programming pin voltage ≤5.5V), the first and second voltage-resistant modules 103 and 106 act as conductive wires, allowing high and low-level signals to pass normally. This design enables a single programming pin to withstand the 9.3V programming high voltage to complete data writing, and also to achieve normal signal reception (programming data input) and transmission (reading data output) at low voltage, ultimately realizing the multiplexing of programming and reading functions on a single pin.

[0043] It should be noted that the first driver module 101, the first switch module 102, the first voltage-resistant module 103, the second switch module 104, and the pull-up module 105 can form an open-drain output driver circuit, and the second voltage-resistant module 106 and the second driver module 107 can form an input circuit. During the programming process, the open-drain output driver circuit is disabled and the input circuit is enabled. During the reading process, the open-drain output driver circuit is enabled and the input circuit is disabled.

[0044] It should be noted that traditional IO designs separate the programming and reading functions, requiring additional circuit switching, which increases design complexity and power consumption. The present application integrates a dual voltage-resistant module, a switch module, and a pull-up module 105 within the input / output circuit 10, enabling a single programming pin to multiplex both programming and reading functions without the need for additional function switching circuitry. This design not only eliminates the function switching circuitry found in traditional solutions, reducing design complexity, but also reduces redundant power consumption during circuit switching. Furthermore, single-pin multiplexing reduces the number of connections between the chip and external devices, further reducing overall system power consumption. This improves circuit integration while also meeting low power requirements. Furthermore, traditional solutions cannot achieve single-wire bidirectional communication, limiting the application scenarios of low-pin-count MCUs (Microcontroller Units). The single programming pin in the present application has bidirectional communication capabilities, meaning it can both receive programming data transmitted from an external device and output read data to the external device. This single-wire bidirectional communication feature overcomes the limitations of traditional solutions, enabling low-pin-count MCUs to fully support programming and data exchange functions while maintaining pin resources, significantly broadening their application scenarios.

[0045] In one embodiment of the present application, Figure 3 and Figure 4 As shown, the first driving module 101 includes a first driver I1 , an input end of the first driver I1 is used to receive a control signal, and an output end of the first driver I1 is electrically connected to the first switch module 102 .

[0046] Specifically, the first driver I1 converts the weak control signal output by the core module (i.e., the control signal at node A) into a signal with sufficient drive capability, ensuring reliable switching on and off of the first switch module 102. If the output level of the core module does not match the control terminal requirements of the first switch module 102, the first driver I1 performs level conversion to ensure signal compatibility. The first driver I1 can also optimize the switching speed of the first switch module 102 by adjusting the rise and fall time of the drive signal, reducing signal distortion and power consumption, and ensuring stable data transmission.

[0047] In one embodiment of the present application, Figure 3 and Figure 4 As shown, the first switch module 102 includes a first switch tube M1, a control end of the first switch tube M1 is electrically connected to the first driving module 101, a first conduction end of the first switch tube M1 is electrically connected to the first voltage-resistant module 103, and a second conduction end of the first switch tube M1 is grounded.

[0048] Specifically, the gate of the first switch tube M1 is used as a control end, the drain of the first switch tube M1 is used as a first conduction end, and the source of the first switch tube M1 is used as a second conduction end. The first switch tube M1 is used as a switching device, and can be turned on or turned off according to a driving signal received by the gate. When the first switch tube M1 is turned on, the first node voltage can be pulled low, and when the first switch tube M1 is turned off, the up pull module 105 can pull up the second node voltage if the second switch module 104 is turned on. Therefore, the first node voltage, that is, the voltage transmitted to the burning pin, can be adjusted according to the turn-on or turn-off of the first switch tube M1.

[0049] For example, the designer can select the type of the first switch tube M1 according to actual conditions, that is, a full-controlled power device such as a metal oxide field effect transistor or an insulated gate bipolar transistor can be used. For example, the first switch tube M1 can be an NMOS tube.

[0050] It should be noted that only one circuit structure of the first switch module 102 is shown in the embodiments provided in the present application, and this circuit structure does not mean that only this circuit structure can realize the function of the first switch module 102. Other circuit structures that can realize the function can also be replaced, and are not limited to this.

[0051] In one embodiment of the present application, the first voltage-resistant module 103 includes a first MOS tube, a control end of the first MOS tube is used for receiving a first gate driving signal, a first conduction end of the first MOS tube is electrically connected with the burning pin, and a second conduction end of the first MOS tube is electrically connected with the first switch module 102.

[0052] Specifically, when the voltage at the programming pin is a high voltage greater than the chip's power supply voltage, the control terminal of the first MOS transistor is biased to a safe voltage (e.g., the chip's power supply voltage of 5.5V) via a first gate drive signal, placing it in a linear or saturation region rather than a fully conductive state. At this point, the on-resistance of the first MOS transistor and the parasitic resistance in the circuit jointly divide the voltage, clamping the first node voltage (i.e., the voltage at the second conductive terminal of the first MOS transistor) within the chip's tolerable range (e.g., ≤5.5V), thus preventing high voltage breakdown of subsequent circuits. In normal operating mode (e.g., reading or data transmission), the voltage at the programming pin is less than or equal to the chip's power supply voltage, and the control terminal of the first MOS transistor is fully conductive (entering a deep conduction state) via the first gate drive signal. At this point, the on-resistance of the first MOS transistor is extremely low (typically in the milliohm range), acting like a conductor, allowing low-voltage signals (e.g., 0-5V) to be transmitted between the programming pin and the first switch module 102 without attenuation, ensuring the integrity of data transmission. In addition, the first gate drive signal of the first MOS tube can be precisely controlled according to the system timing, for example, it can be turned off in advance before the high voltage is loaded, or the conduction speed can be optimized during data transmission, thereby reducing signal distortion and switching loss and improving the anti-interference ability of the circuit.

[0053] For example, designers can select the type of the first MOS transistor based on actual conditions, i.e., a fully controlled power device such as a metal oxide field effect transistor or an insulated gate bipolar transistor can be used. For example, the first MOS transistor can be a common 5V NMOS transistor or a common 5V PMOS transistor. Furthermore, the first voltage-resistant module 103 can also use a voltage regulator, a Zener diode, or a high-voltage MOS transistor. The voltage regulator, Zener diode, or high-voltage MOS transistor is connected between the programming pin and the first switch module 102. Using a common 5V MOS transistor can effectively reduce circuit design costs.

[0054] It should be noted that the embodiments provided herein only illustrate the above circuit structure as the first voltage-resistant module 103, which does not mean that only the above circuit structure can realize the function of the first voltage-resistant module 103. Other circuit structures that can realize this function can also be replaced, and are not limited to this.

[0055] In one embodiment of the present application, Figure 3 and Figure 4 As shown, the second switch module 104 includes a second switch tube M2, the control end of the second switch tube M2 is electrically connected to the second driving module 107, the first conduction end of the second switch tube M2 is used to be electrically connected to the first power supply, and the second conduction end of the second switch tube M2 is electrically connected to the pull-up module 105.

[0056] Specifically, the gate of the second switch tube M2 serves as the control terminal, the source of the second switch tube M2 serves as the first conduction terminal, and the drain of the second switch tube M2 serves as the second conduction terminal. The second switch tube M2 acts as a switching device and can be turned on or off according to the target voltage received by the gate. During the programming process, the turning on or off of the second switch module 104 does not affect the second node voltage. During the reading process, since the second driver module 107 is turned off by default, the target voltage defaults to a low level. At this time, the second switch tube M2 is turned on. If the first switch tube M1 is turned off, the pull-up module 105 can pull up the second node voltage.

[0057] For example, designers can select the type of the second switch tube M2 according to actual conditions, that is, a fully controlled power device such as a metal oxide field effect transistor or an insulated gate bipolar transistor can be used. For example, the second switch tube M2 can be selected as a PMOS tube.

[0058] Exemplarily, the supply voltage of the first power supply generally ranges from 2V to 5.5V, and is usually set to 3.3V and 5V.

[0059] It should be noted that the embodiment provided in this application only shows one circuit structure as the second switch module 104, which does not mean that only this circuit structure can realize the function of the second switch module 104. Other circuit structures that can realize this function can also be replaced, and are not limited to this.

[0060] In one embodiment of the present application, Figure 3 and Figure 4 As shown, the pull-up module 105 includes a first resistor R1 , a first end of the first resistor R1 is electrically connected to the second switch module 104 , and a second end of the first resistor R1 is electrically connected to the second voltage-resistant module 106 and the second driving module 107 .

[0061] Specifically, during a read operation, when the first switch M1 is turned off and the second switch M2 is turned on according to the target voltage, the first resistor R1 is connected in parallel with the second resistor R2 in the external device to jointly pull up the voltage at the second node to a high level, ensuring that the programming pin outputs a logic "1" signal. During the programming process, when a high voltage is applied to the programming pin, the first resistor R1 works in conjunction with the second voltage-withstand module 106 to limit the current flowing into the second driver module 107, preventing it from being damaged by the high voltage. Furthermore, when the circuit state switches (e.g., from programming mode to reading mode), the first resistor R1 can optimize the signal rise time by adjusting the pull-up strength, reducing signal jitter and transmission delay, and improving data transmission reliability. Therefore, the presence of the first resistor R1 ensures both circuit safety in high-voltage environments and signal stability during low-voltage communications.

[0062] It should be noted that the embodiments provided herein only illustrate one circuit structure as the pull-up module 105, and do not mean that only this circuit structure can implement the function of the pull-up module 105. Other circuit structures that can implement this function can also be substituted, and are not limited to this.

[0063] In one embodiment of the present application, the second voltage-resistant module 106 includes a second MOS transistor, the control end of the second MOS transistor is used to receive the second gate drive signal, the first conduction end of the second MOS transistor is electrically connected to the burning pin, and the second conduction end of the second MOS transistor is electrically connected to the pull-up module 105 and the second drive module 107 respectively.

[0064] Specifically, when the voltage at the programming pin is a high voltage greater than the chip's power supply voltage, the control terminal of the second MOS transistor is biased to a safe voltage (e.g., the chip's power supply voltage of 5.5V) via a second gate drive signal, placing it in a linear or saturation region rather than a fully conductive state. At this point, the on-resistance of the second MOS transistor and the parasitic resistance in the circuit jointly divide the voltage, clamping the second node voltage (i.e., the voltage at the second on-terminal of the second MOS transistor) within the chip's tolerable range (e.g., ≤5.5V), thus preventing high voltage breakdown of subsequent circuits. In normal operating mode (e.g., reading or data transmission), the voltage at the programming pin is less than or equal to the chip's power supply voltage, and the control terminal of the second MOS transistor is fully turned on (entering a deep conduction state) via the second gate drive signal. At this point, the on-resistance of the second MOS transistor is extremely low (typically in the milliohm range), acting like a conductor, allowing low-voltage signals (e.g., 0-5V) to be transmitted from the programming pin to the second driver module 107 without attenuation, ensuring the integrity of data transmission. In addition, the second gate drive signal of the second MOS tube can be precisely controlled according to the system timing, such as shutting down in advance before burning high voltage loading, or optimizing the conduction speed during data transmission, thereby reducing signal distortion and switching loss and improving the circuit's anti-interference ability.

[0065] For example, designers can select the type of the second MOS transistor based on actual conditions, namely, fully controlled power devices such as metal oxide field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs). For example, the second MOS transistor can be a common 5V NMOS transistor or a common 5V PMOS transistor. Furthermore, the second voltage-resistant module 106 can also use a voltage regulator, a Zener diode, or a high-voltage MOS transistor. The voltage regulator, Zener diode, or high-voltage MOS transistor is connected between the programming pin and the second driver module 107. Using a common 5V MOS transistor can effectively reduce circuit design costs.

[0066] It should be noted that the embodiment provided in this application only shows the above circuit structure as the second voltage-resistant module 106, which does not mean that only the above circuit structure can realize the function of the second voltage-resistant module 106. Other circuit structures that can realize this function can also be replaced, and are not limited to this.

[0067] In one embodiment of the present application, Figure 3 and Figure 4 As shown, the second driving module 107 includes a second driver I2, the input end of the second driver I2 is electrically connected to the second voltage-resistant module 106 and the pull-up module 105 respectively, and the output end of the second driver I2 is used to output the target voltage.

[0068] Specifically, during the programming process, when high voltage is applied to the programming pin, the second driver I2 receives the clamped safety voltage signal through the second voltage-resistant module 106 and converts it into a logic level recognizable by the core module (e.g., converting the signal corresponding to a 9.3V high voltage into a digital signal ≤5.5V), while preventing high voltage interference with the core module. During the reading process, the second driver I2 is in the off state, and the target voltage output by the second driver I2 defaults to a low-level signal. Furthermore, the second driver I2 also features signal amplification and shaping, enhancing signal strength, optimizing waveforms, and improving the anti-interference capability and reliability of data transmission. By processing and isolating signals, the second driver I2 effectively protects the core module and ensures proper signal transmission in both high-voltage programming and low-voltage communication modes.

[0069] The present application also discloses a chip, including a core module, a burning pin (i.e., a VPP pin) and the above-mentioned input and output circuit 10, wherein the core module is electrically connected to the first driving module 101 and the second driving module 107 in the input and output circuit 10, respectively, and the burning pin is electrically connected to the first voltage-resistant module 103 and the second voltage-resistant module 106 in the input and output circuit 10, respectively.

[0070] Specifically, the chip employing the aforementioned input / output circuit 10 eliminates the need for separate VPP and data transmission pins. Instead, a single programming pin can be used to complete the three operations of "receiving programming data, carrying programming high voltage, and outputting read data." This significantly conserves chip pin resources (compared to traditional multi-line solutions, saving over 50% of pins), lowering chip packaging costs, power consumption, and chip area. Furthermore, the protective effect of the voltage-resistant module improves chip reliability in high-voltage programming scenarios, making it particularly suitable for miniaturized chip designs where pin count and cost are critical.

[0071] like Figure 4As shown, this application also discloses an input / output system, including an external device and the aforementioned chip. The input / output system eliminates the need for separate pins for programming and data transmission, simplifying the connection complexity between the external device and the chip, reducing PCB (Printed Circuit Board) wiring area, and lowering system costs. Furthermore, the input / output system effectively isolates the impact of high-voltage programming environments on the chip's internal circuitry, significantly improving system reliability and stability. This system is particularly suitable for applications such as IoT devices and wearable devices, which have stringent requirements on size and power consumption.

[0072] Since the processing and functions implemented by the chip and input / output system in this embodiment basically correspond to the embodiments, principles and examples of the aforementioned input / output circuits, any details not fully described in this embodiment can be referred to the relevant descriptions in the aforementioned embodiments and will not be repeated here.

[0073] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. An input-output circuit, characterized in that: The device comprises a first driving module, a first switch module, a first voltage-resistant module, a second switch module, a pull-up module, a second voltage-resistant module, and a second driving module, wherein the first switch module is electrically connected to the first driving module and the first voltage-resistant module respectively, the second voltage-resistant module is electrically connected to the first voltage-resistant module, the second driving module, and the pull-up module respectively, the second switch module is electrically connected to the pull-up module, the first voltage-resistant module and the second voltage-resistant module are both electrically connected to the programming pins of the chip, and the first driving module and the second driving module are both used to be electrically connected to the core module of the chip; During data transmission to the chip via the programming pin, the first voltage-withstand module is configured to clamp a first node voltage to a first preset voltage when the voltage of the programming pin is greater than the power supply voltage of the chip, where the first node voltage is the voltage at a common terminal of the first voltage-withstand module and the first switch module; the second voltage-withstand module is configured to clamp a second node voltage to a second preset voltage when the voltage of the programming pin is greater than the power supply voltage of the chip, where the second node voltage is the voltage at a common terminal of the second voltage-withstand module and the second driver module; and the second driver module is configured to output a target voltage to the core module and the second switch module according to the second node voltage. In the process of the chip outputting data through the programming pin, the first driving module is used to output a driving signal to the first switch module according to the control signal output by the core module; The first switch module is used to be turned on or off according to the driving signal to adjust the first node voltage; the second switch module is used to be turned on according to the target voltage; and the pull-up module is used to pull up the second node voltage when the first switch module is turned off and the second switch module is turned on.

2. The input-output circuit according to claim 1, wherein: The first driving module includes a first driver, an input end of the first driver is used to receive the control signal, and an output end of the first driver is electrically connected to the first switch module.

3. The input-output circuit according to claim 1, wherein: The first switch module includes a first switch tube, a control end of the first switch tube is electrically connected to the first driving module, a first conduction end of the first switch tube is electrically connected to the first voltage-resistant module, and a second conduction end of the first switch tube is grounded.

4. The input-output circuit according to claim 1, wherein: The first voltage-resistant module includes a first MOS transistor, a control end of the first MOS transistor is used to receive a first gate drive signal, a first conduction end of the first MOS transistor is electrically connected to the burning pin, and a second conduction end of the first MOS transistor is electrically connected to the first switch module.

5. The input-output circuit according to claim 1, wherein: The second switch module includes a second switch tube, a control end of the second switch tube is electrically connected to the second driving module, a first conduction end of the second switch tube is used to be electrically connected to the first power supply, and a second conduction end of the second switch tube is electrically connected to the pull-up module.

6. The input-output circuit according to claim 1, wherein: The pull-up module includes a first resistor, a first end of the first resistor is electrically connected to the second switch module, and a second end of the first resistor is electrically connected to the second voltage-resistant module and the second driving module respectively.

7. The input-output circuit according to claim 1, wherein: The second voltage-resistant module includes a second MOS transistor, a control end of the second MOS transistor is used to receive a second gate drive signal, a first conduction end of the second MOS transistor is electrically connected to the burning pin, and a second conduction end of the second MOS transistor is electrically connected to the pull-up module and the second drive module respectively.

8. The input-output circuit according to claim 1, wherein: The first voltage-resistant module includes a first voltage-stabilizing diode connected between the programming pin and the first switch module; The second voltage-resistant module includes a second voltage-stabilizing tube, and the second voltage-stabilizing tube is connected between the programming pin and the second driving module.

9. The input-output circuit according to claim 1, wherein: The second driving module includes a second driver, the input end of the second driver is electrically connected to the second voltage-resistant module and the pull-up module respectively, and the output end of the second driver is used to output the target voltage.

10. A chip, characterized in that: The device comprises a core module, a burning pin and the input-output circuit according to any one of claims 1 to 9, wherein the core module is electrically connected to the first driving module and the second driving module in the input-output circuit respectively, and the burning pin is electrically connected to the first voltage-resistant module and the second voltage-resistant module in the input-output circuit respectively.

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