Silicon wafer chamfer grain residue control method

Abstract

The invention discloses a silicon wafer chamfering grain residue control method, which comprises the following steps of: firstly, carrying out substrate chamfering pretreatment, and chamfering step by step by using a resin grinding wheel of which the granularity is less than or equal to 5 microns so as to reduce edge damage; carrying out an X1 region LTO selective removal step, protecting a non-X1 region through a mask, and locally removing an LTO layer at the X1 position by adopting dry etching or a low-concentration HF solution; and finally, edge polishing is conducted, the chemical mechanical polishing technology is used, and the surface roughness Ra of the X1 area is controlled to be smaller than or equal to 0.1 micrometer. According to the silicon wafer chamfer grain residue control method, the non-X1 area is protected through the mask, and the LTO layer at the X1 position is accurately removed through dry etching or the low-concentration HF solution, so that the problem that the LTO layer structure is loose due to high chamfer surface roughness in the traditional process is fundamentally solved, the grain adhesion phenomenon caused by the looseness of the LTO layer is effectively avoided, and the quality of the product is improved. Defects in the epitaxial process are significantly reduced, and the quality and performance of the epitaxial layer are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon wafer chamfering, and in particular to a method for controlling residual grains during silicon wafer chamfering. Background Art

[0002] In semiconductor manufacturing, chamfering of silicon wafers is a key front-end process. This process uses mechanical or chemical means to trim the edges of silicon wafers into an arc shape. The main purpose is to eliminate stress concentration at the edges of the silicon wafers and prevent problems such as edge collapse and corner chipping during subsequent processing and use, thereby improving the mechanical strength and durability of the silicon wafers. At the same time, chamfering can also effectively reduce particle contamination at the edges, which is crucial to improving the yield and reliability of chip manufacturing.

[0003] Traditional chamfering processes mostly use grinding wheels. However, this method can easily lead to high chamfer surface roughness, which in turn causes a series of subsequent problems. For example, after covering the low-temperature silicon oxide (LTO) layer, defects such as residual grains appear due to the loose structure of the LTO layer, affecting the quality of the epitaxial layer. Therefore, advanced chamfering processes are constantly emerging, such as using resin-bonded grinding wheels for high-precision step-by-step chamfering, combined with chemical mechanical polishing technology to fine-tune specific areas to achieve low-roughness, high-cleanliness chamfered surfaces, meeting the stringent quality requirements of silicon wafers in high-performance semiconductor device manufacturing.

[0004] The existing technology has the following defects: loose LTO layer structure: when the chamfer surface roughness is high, the LTO layer is prone to form a loose structure, resulting in residual grains in the subsequent epitaxial process; full area coverage defects: traditional processes do not differentiate the chamfer areas (such as X1, X2 and other positions); among them, the X1 area is the point where the curvature of the silicon wafer edge is the largest, and mechanical stress is concentrated, making it more likely to have residual grains than other areas; cleaning and drying risks: residual grains are prone to fall off during the drying process, which in turn causes particle contamination and affects the quality of the epitaxial layer. Summary of the Invention

[0005] The main purpose of the present invention is to provide a method for controlling residual grains in chamfered silicon wafers, which can effectively solve the problems of loose LTO layer structure, undifferentiated treatment of chamfered areas resulting in full-area coverage defects, and residual grains during cleaning and drying that easily cause particle contamination and affect the quality of the epitaxial layer.

[0006] To achieve the above object, the present invention adopts a technical solution: a method for controlling grain residue during chamfering of a silicon wafer, the method comprising the following steps:

[0007] S1. Substrate chamfer pretreatment: Use a resin grinding wheel with a particle size of ≤5μm to perform step-by-step chamfering to reduce edge damage;

[0008] S2, X1 area LTO selective removal: Use a mask to protect the non-X1 area, and use dry etching or low-concentration HF solution to locally remove the LTO layer at X1;

[0009] S3, edge polishing: Use chemical mechanical polishing technology to control the surface roughness of the X1 area to Ra ≤ 0.1μm.

[0010] Preferably, in the substrate chamfering pretreatment step, the particle size of the resin grinding wheel is 1 μm to 5 μm.

[0011] Preferably, in the X1 region LTO selective removal step, the concentration of the low-concentration HF solution is 1% to 10%.

[0012] Preferably, in the X1 edge polishing step, chemical mechanical polishing technology is adopted, and the chemical mechanical polishing technology parameters include polishing pressure: 10kPa to 50kPa, polishing time: 1 minute to 10 minutes and polishing liquid flow rate: 100mL / min to 500mL / min.

[0013] Preferably, after the X1 edge polishing step, the method further includes cleaning and drying the silicon wafer to remove polishing residues and prevent particle contamination.

[0014] Preferably, the method further comprises the step of retaining the LTO layer in the non-X1 region to maintain the overall mechanical strength of the silicon wafer.

[0015] Preferably, the method is applicable to the chamfering process of 8-inch or 12-inch silicon wafers.

[0016] Preferably, before the substrate chamfering pretreatment step, the method further includes a step of performing preliminary cleaning on the edge of the silicon wafer to remove surface contaminants.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. In the present invention, the method protects the non-X1 area by using a mask, and then uses dry etching or low-concentration HF solution to accurately remove the LTO layer at X1. This fundamentally solves the problem of loose LTO layer structure caused by high chamfer surface roughness in traditional processes, effectively avoids the grain adhesion phenomenon caused by loose LTO layer, significantly reduces defects in the epitaxial process, improves the quality and performance of the epitaxial layer, and lays a good foundation for subsequent semiconductor device manufacturing.

[0019] 2. In this method, chemical mechanical polishing (CMP) is used to finely treat the X1 region, strictly controlling the surface roughness of the X1 region to Ra ≤ 0.1 μm. This process not only significantly improves the surface smoothness of the X1 region but also effectively reduces mechanical stress concentration in this region, minimizing the risk of residual grains caused by stress concentration. It also reduces the possibility of particles falling off during the cleaning and drying process and causing contamination, thereby improving the cleanliness and overall quality of the silicon wafer and enhancing the reliability and stability of the semiconductor device.

[0020] 3. In this invention, the method removes the LTO layer in the X1 region while retaining the LTO layer in non-X1 regions. This design maintains the overall mechanical strength of the silicon wafer, avoiding the problems of reduced strength and damage caused by removing the LTO layer from the entire region. This ensures the structural integrity and stability of the silicon wafer during subsequent processing, transportation, and use, providing a safer and more reliable solution for silicon wafer handling in semiconductor manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a process framework diagram of the present invention;

[0022] Figure 2 Schematic diagram of chamfering of the present invention. DETAILED DESCRIPTION

[0023] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention will be described in detail below in conjunction with specific implementation methods.

[0024] Example 1: Control of chamfered grain residue on an 8-inch silicon wafer.

[0025] During implementation, S1, substrate chamfer pretreatment, uses a resin grinding wheel with a grit size of 3μm for step-by-step chamfering. The silicon wafer is fixed to the fixture of the chamfering equipment, and the grinding wheel speed is set to 2800rpm and the feed rate is set to 8mm / s. The silicon wafer edge is gradually trimmed in two steps according to the preset chamfer angle, the first trimming angle is 2°, and the second trimming angle is 5°. This process effectively reduces edge damage, and the edge morphology of the silicon wafer after preliminary chamfering treatment is obtained, with edge roughness reduced by 30%. During the trimming process, the uniformity and consistency of the chamfer are ensured by precisely controlling the feed speed and rotation speed of the grinding wheel, laying a good foundation for subsequent processing.

[0026] Selective removal of LTO in S2 and X1 areas

[0027] The non-X1 area is protected by a mask. The silicon wafer is placed in a photolithography machine and exposed and developed using a mask matching the shape of the X1 area, covering the non-X1 area with the mask material. The wafer is then placed in a dry etching machine with an etching power of 350W, an etching gas flow rate of 12sccm, and an etching time of 65 seconds to remove the LTO layer at the X1 location. After etching, the wafer surface residue is rinsed with deionized water. After drying, the surface flatness of the LTO layer in the X1 area is measured using an ellipsometer. The results show that the surface flatness of the X1 area has increased by 40%. During the dry etching process, precise control of etching parameters ensures the complete removal of the LTO layer while avoiding damage to the underlying silicon wafer surface.

[0028] S3, Edge polishing

[0029] Using chemical mechanical polishing (CMP) technology, the polishing pressure was set to 25kPa, the polishing time was set to 5 minutes, and the polishing liquid flow rate was set to 250mL / min. The X1 area was brought into contact with the polishing pad. Under the action of the polishing liquid, the mechanical friction of the polishing pad and the chemical action of the polishing liquid were utilized to control the surface roughness of the X1 area to Ra≤0.1μm. After testing, the surface roughness of the X1 area reached Ra=0.08μm, which met the control requirements and significantly reduced the risk of grain residue. During the polishing process, by optimizing the formula of the polishing liquid and the polishing process parameters, an efficient polishing effect was achieved while maintaining the chemical stability and mechanical integrity of the silicon wafer surface.

[0030] This embodiment uses a resin-bonded grinding wheel of appropriate grit for step-by-step chamfering, effectively reducing edge damage. Dry etching precisely removes the LTO layer in the X1 region, improving surface flatness. CMP polishing further minimizes surface roughness in the X1 region through extremely low levels. The overall process significantly reduces grain residue in the chamfered area of ​​8-inch silicon wafers, lowering the risk of particle contamination during subsequent epitaxial growth and improving the quality of the epitaxial layer. The process is highly compatible with existing silicon wafer chamfering and epitaxial processes, eliminating the need for major equipment modifications. Actual production verification shows that silicon wafers treated using this embodiment experience a 45% reduction in grain residue defects and a 38% reduction in epitaxial layer surface roughness during epitaxial layer growth, effectively improving the electrical performance and reliability of semiconductor devices.

[0031] Example 2: Control of chamfered grain residue on a 12-inch silicon wafer.

[0032] During implementation, S1, substrate chamfer pretreatment, was performed using a resin-bonded grinding wheel with a grit size of 1μm for step-by-step chamfering. The silicon wafer was mounted on the chamfering equipment, with the grinding wheel speed set to 3200rpm and the feed rate set to 6mm / s. The silicon wafer edge was trimmed in three steps according to the required chamfer angle, with trimming angles of 1°, 3°, and 5° respectively. After this treatment, damage to the silicon wafer edge was significantly reduced, and edge roughness was reduced by 35%. The use of a finer-grained resin-bonded grinding wheel further improved chamfer quality, providing a higher-quality foundation for subsequent high-precision processing.

[0033] The LTO layer in the S2 and X1 areas is selectively removed, and a mask is also used to protect the non-X1 area. The silicon wafer is photolithographically processed so that the mask material accurately covers the non-X1 area. Then, the X1 area is immersed in a low-concentration HF solution (concentration is 3%) for 25 seconds, and then rinsed with deionized water for 10 seconds. After drying, the surface flatness of the X1 area is measured using an ellipsometer to obtain the LTO layer removal effect data of the X1 area. The results show that the surface flatness of the X1 area is improved by 35%. The use of low-concentration HF solution, combined with precise mask technology, achieves efficient removal of the LTO layer in the X1 area, while avoiding accidental etching of the non-X1 area, ensuring the overall performance of the silicon wafer.

[0034] S3: Edge polishing. Chemical mechanical polishing (CMP) was performed using a polishing pressure of 15 kPa, a polishing time of 8 minutes, and a polishing fluid flow rate of 150 mL / min. Area X1 was polished, ultimately achieving a surface roughness of Ra = 0.07 μm, effectively reducing the possibility of residual grains. Precise control of polishing pressure and time ensured consistent and stable polishing results. Optimized polishing fluid flow helped to remove heat and particles generated during polishing, further improving surface quality.

[0035] This embodiment uses a finer-grained resin grinding wheel for 12-inch silicon wafers to further reduce edge damage; a low-concentration HF solution combined with masking technology is used to accurately remove the LTO layer in the X1 area, thereby improving surface flatness; by optimizing the CMP polishing process parameters, the surface roughness of the X1 area is controlled at an extremely low level, significantly reducing the grain residue in the chamfered area of ​​the 12-inch silicon wafer, effectively reducing the risk of particle contamination, and improving the quality of the epitaxial layer. At the same time, the LTO layer in the non-X1 area is retained to maintain the overall mechanical strength of the silicon wafer, ensuring the stability of the silicon wafer in subsequent processing. After treatment, the grain residue defect rate of the 12-inch silicon wafer is reduced by 50% during the epitaxial growth process, and the uniformity and crystallization quality of the epitaxial layer are significantly improved, providing reliable material guarantee for the manufacture of high-end semiconductor devices. The entire process flow is highly compatible with the existing 12-inch production line, without the need for additional equipment investment, and has significant economic benefits and application value.

[0036] Example 3: Further processing and optimization of 12-inch silicon wafers.

[0037] First, after step S3 of Example 2, the silicon wafer was cleaned and dried. Deionized water was rinsed at a pressure of 0.55 MPa for 35 seconds to remove polishing residue. The wafer was then dried in a drying chamber at 100°C for 12 minutes to prevent particle contamination. This reduced particle contamination on the wafer surface by 60%. During the cleaning process, optimized water pressure and rinsing time ensured effective removal of polishing residue while preventing secondary contamination of the wafer surface. During the drying process, precise temperature and time control ensured effective drying of the wafer and prevented reattachment of particles.

[0038] Secondly, the LTO layer is retained in the non-X1 area of ​​the silicon wafer to maintain the overall mechanical strength. The overall mechanical strength of the silicon wafer is measured by testing equipment. The results show that the mechanical strength of the silicon wafer is equivalent to that before treatment, which verifies the effectiveness of retaining the LTO layer in the non-X1 area. Through advanced testing technology, a comprehensive assessment of the overall mechanical strength of the silicon wafer is carried out to ensure that the retention of the LTO layer in the non-X1 area will not affect the mechanical properties of the silicon wafer, while providing necessary protection for subsequent processing and use.

[0039] This embodiment, based on the previous processing, effectively removes polishing residues through cleaning and drying steps, further reducing the risk of particle contamination. At the same time, the LTO layer in the non-X1 area is retained, ensuring that the overall mechanical strength of the silicon wafer is not reduced, and guaranteeing the structural stability of the silicon wafer during subsequent processing, transportation, and use. This series of optimization measures has significantly reduced the grain retention rate in the chamfered area of ​​the silicon wafer to below 5%, significantly improving the quality of the epitaxial layer, and providing a reliable material foundation for the manufacture of high-performance semiconductor devices. The entire process is highly compatible with existing silicon wafer chamfering and epitaxial processes, showing good scalability and application prospects. After comprehensive evaluation, silicon wafers treated with the method of this embodiment have increased the chip yield by 32% and production efficiency by 28% in the subsequent chip manufacturing process, bringing significant economic benefits and market competitiveness to enterprises.

[0040] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for controlling residual grains during chamfering of silicon wafers, characterized in that: The method comprises the following steps: S1. Substrate chamfer pretreatment: Use a resin grinding wheel with a particle size of ≤5μm to perform step-by-step chamfering to reduce edge damage; S2, X1 area LTO selective removal: Use a mask to protect the non-X1 area, and use dry etching or low-concentration HF solution to locally remove the LTO layer at X1; S3, edge polishing: Use chemical mechanical polishing technology to control the surface roughness of the X1 area to Ra ≤ 0.1μm.

2. The method for controlling residual grains during chamfering of a silicon wafer according to claim 1, wherein: In the substrate chamfering pretreatment step, the particle size of the resin grinding wheel is 1 μm to 5 μm.

3. The method for controlling residual grains during chamfering of a silicon wafer according to claim 1, wherein: In the X1 region LTO selective removal step, the concentration of the low-concentration HF solution is 1% to 10%.

4. The method for controlling residual grains during chamfering of a silicon wafer according to claim 1, wherein: In the X1 edge polishing step, chemical mechanical polishing technology is adopted, and the chemical mechanical polishing technology parameters include polishing pressure: 10kPa to 50kPa, polishing time: 1 minute to 10 minutes and polishing liquid flow rate: 100mL / min to 500mL / min.

5. The method for controlling residual grains during chamfering of a silicon wafer according to claim 1, wherein: After the X1 edge polishing step, the silicon wafer is further cleaned and dried to remove polishing residues and prevent particle contamination.

6. The method for controlling residual grains during chamfering of a silicon wafer according to claim 1, wherein: The method further comprises the step of retaining the LTO layer in the non-X1 region to maintain the overall mechanical strength of the silicon wafer.

7. The method for controlling residual grains during chamfering of a silicon wafer according to claim 1, wherein: The method is applicable to the chamfering process of 8-inch or 12-inch silicon wafers.

8. The method for controlling residual grains during chamfering of a silicon wafer according to claim 1, wherein: Before the substrate chamfering pretreatment step, the method further includes a step of performing preliminary cleaning on the edge of the silicon wafer to remove surface dirt.

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