Wafer, wafer die and method of manufacturing wafer die

Abstract

A wafer, a wafer die, and a method of manufacturing a wafer die are provided. The wafer comprises a wafer substrate; the epitaxial thin film is arranged on the wafer substrate and comprises a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer; and a plurality of marks formed on the epitaxial thin film and indicating crystal orientation.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2024-0030554 filed on March 4, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments relate to a wafer, a wafer die, and a method of manufacturing a wafer die. Background Art

[0003] With the development of multimedia, the importance of display devices is gradually increasing. In response, various display devices are being developed, such as liquid crystal display devices that require backlight sources and light-emitting display devices that directly emit light. Among these display devices, light-emitting display devices include display panels containing light-emitting elements and are used in various types of electronic devices, including portable electronic devices and televisions, as well as virtual reality (VR) and augmented reality (AR) devices.

[0004] When manufacturing epitaxial wafers for such display devices, multiple semiconductor layers are grown. Because defects in these layers can cause abnormalities in the light-emitting elements formed in subsequent processes, the wafers are inspected or analyzed before subsequent processes. This inspection or analysis can be considered an essential process.

[0005] To describe these analysis and verification steps, first, a specimen is prepared by cutting a predetermined size from a wafer, and then the specimen is inspected or analyzed by a device such as a transmission electron microscope (TEM). Summary of the Invention

[0006] However, the aspects of the disclosure are not limited to the contents set forth herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0007] According to an embodiment, a wafer may include: a wafer substrate; an epitaxial thin film disposed on the wafer substrate and including a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer; and a plurality of marks formed on the epitaxial thin film and indicating a crystal orientation.

[0008] The markings may be made from photosensitive polymers.

[0009] Each of the plurality of marks may be disposed on the surface of the epitaxial thin film and spaced apart from an adjacent mark by a first distance.

[0010] The first distance may be in the range of about 50 μm to about 300 μm.

[0011] Tens to hundreds of marks can be arranged per unit area of ​​approximately 1 cm×1 cm of the epitaxial thin film.

[0012] Each of the plurality of marks may have a thickness of about 500 nm to about 1 μm.

[0013] Each of the plurality of marks may indicate a crystal orientation through a plurality of strokes and contact points of the plurality of strokes.

[0014] The length of each of the plurality of strokes may be in the range of about 500 nm to about 1 μm.

[0015] Multiple markers can have the same shape.

[0016] The wafer substrate may include at least one of a flat area and a notch, wherein a crystal orientation indicated by the flat area or the notch may be consistent with a crystal orientation indicated by the mark.

[0017] The wafer may include: a wafer substrate; an epitaxial thin film disposed on the wafer substrate and including a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer; and a plurality of marks formed between the wafer substrate and the epitaxial thin film and indicating crystal orientation.

[0018] The wafer die may include: a wafer substrate cut into a predetermined size; an epitaxial thin film disposed on the wafer substrate and including a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer; and a plurality of marks formed on the epitaxial thin film and indicating a crystal orientation.

[0019] The predetermined size may be approximately 1 cm x 1 cm in width x length.

[0020] Tens to hundreds of marks can be provided on the surface of the epitaxial thin film.

[0021] Each of the plurality of marks may indicate a crystal orientation through a plurality of strokes and contact points of the plurality of strokes.

[0022] According to an embodiment, a wafer die may include: a wafer substrate, which is cut into a predetermined size; an epitaxial thin film, which is arranged on the wafer substrate and includes a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer; and a plurality of marks, which are formed between the wafer substrate and the epitaxial thin film and indicate the crystal orientation.

[0023] According to an embodiment, a method for manufacturing wafer grains may include the following steps: growing an epitaxial thin film including a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer on a wafer substrate to form an epitaxial wafer; forming a mark indicating a crystal orientation on the epitaxial thin film; and dividing the epitaxial wafer into a plurality of wafer grains, wherein each of the plurality of wafer grains may include a plurality of marks.

[0024] The step of forming the mark indicating the crystal orientation may include forming a photoresist layer by uniformly applying a photosensitive polymer throughout the epitaxial thin film and forming the mark by selectively etching the photoresist layer using a mask pattern.

[0025] The step of dividing the epitaxial wafer into a plurality of wafer dies may include dicing the epitaxial wafer so that the epitaxial wafer is divided into a plurality of wafer dies each having a predetermined size.

[0026] The predetermined size may be approximately 1 cm x 1 cm in width x length.

[0027] Aspects and features of the embodiments are to provide a wafer, a wafer die, and a method of manufacturing a wafer die that can confirm the crystal orientation on a cut wafer.

[0028] According to an embodiment, the crystal orientation on the cut wafer die may be confirmed by forming a plurality of marks indicating the crystal orientation on the epitaxial thin film.

[0029] However, the effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic perspective view showing an epitaxial wafer.

[0031] Figure 2 is a schematic plan view showing an epitaxial wafer.

[0032] Figure 3 is an enlarged schematic cross-sectional view showing a portion of an epitaxial wafer.

[0033] Figures 4 to 6 is a schematic plan view showing an example of a marker.

[0034] Figure 7 is an enlarged schematic cross-sectional view showing a portion of an epitaxial wafer according to another embodiment.

[0035] Figure 8 is a schematic perspective view of the schematic shape of a wafer die.

[0036] Figure 9 yes Figure 8 An enlarged schematic plan view of region A.

[0037] Figure 10 According to the embodiment Figure 9 Schematic cross-sectional view of .

[0038] Figure 11 According to another embodiment Figure 9 Schematic cross-sectional view of .

[0039] Figure 12 is a schematic flow chart illustrating a method of manufacturing a wafer die according to an embodiment.

[0040] Figures 13 to 17 is a schematic diagram illustrating a method of manufacturing a wafer die according to an embodiment.

[0041] Figure 18 is an example of a structural analysis image obtained from a specimen fabricated in a crystal orientation.

[0042] Figure 19 is an example of a structural analysis image obtained from a specimen fabricated in an amorphous orientation.

[0043] Figures 20 to 24 is a schematic diagram illustrating a method of manufacturing a light-emitting element. DETAILED DESCRIPTION

[0044] Embodiments will now be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout the disclosure, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0045] For the purpose of describing the disclosed embodiments, some of the components that are not relevant to the description may not be provided.

[0046] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0047] In addition, the phrase "in a plan view" means when the object portion is viewed from above, while the phrase "in a schematic cross-sectional view" means when a schematic cross-section obtained by vertically cutting the object portion is viewed from the side. The term "superimposed" or its variations mean that the first object can be above the second object or below the second object or to the side of the second object, and vice versa. In addition, the term "superimposed" can include stacking, stacking, facing or facing, extending over..., covering or partially covering or any other suitable term as those of ordinary skill in the art will understand and appreciate. The expression "not superimposed" can include meanings such as "separated from..." or "deviating from..." or "offset from..." and any other suitable equivalents as those of ordinary skill in the art will understand and appreciate. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is placed between the first and second objects, although still facing each other, the first and second objects can be understood to be indirectly opposite to each other.

[0048] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," or "upper" may be used herein to describe the relationship between one element or component and another element or component as shown in the figures. It will be understood that spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, where the device shown in the figures is flipped, a device positioned "below" or "beneath" another device may be placed "above" another device. Thus, the illustrative term "below" may include both a lower position and an upper position. The device may also be oriented in other directions, so spatially relative terms may be interpreted differently depending on the orientation.

[0049] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms “comprises,” “having,” “includes,” and / or variations thereof are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0050] It will be understood that although the terms "first," "second," or "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element or to facilitate description and explanation thereof. For example, when discussing a "first element" in the description, it may be named "second element" or "third element" without departing from the teachings herein, and the "second element" and "third element" may be named in a similar manner.

[0051] As used herein, the term "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0052] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for the purposes of its meaning and interpretation. For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or a disjunction sense and may be understood to be equivalent to "and / or". In the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." for the purposes of its meaning and interpretation. For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0053] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined in the specification.

[0054] In this specification, crystal orientation (or direction) refers to the arrangement of a crystal structure. Materials with a crystal structure, such as sapphire, can exhibit different properties depending on their orientation. These properties can be one or more of electrical, optical, or mechanical. For example, crystal orientation refers to the arrangement of the crystal axes of a wafer material relative to the wafer surface and edges. Furthermore, a crystal plane refers to a flat, two-dimensional surface defined by the periodic arrangement of atoms within the wafer material's crystal structure.

[0055] Therefore, crystal orientation plays an important role in the process of manufacturing and processing devices. In the case of manufacturing devices, the characteristics of the device can be optimized by considering the crystal orientation, and in the case of processing devices, different treatments can be performed according to the crystal orientation.

[0056] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0057] Figure 1 is a schematic perspective view showing an epitaxial wafer. Figure 2 is a schematic plan view showing an epitaxial wafer. Figure 3 is an enlarged schematic cross-sectional view showing a portion of an epitaxial wafer.

[0058] Reference Figures 1 to 3 The epitaxial wafer EWF may include a wafer substrate WAF, an epitaxial thin film EPIL disposed on the wafer substrate WAF, and a mark AK.

[0059] The wafer substrate WAF may be a semiconductor substrate suitable for epitaxial growth of semiconductors. For example, the wafer substrate WAF may be a substrate containing a material such as silicon (Si), sapphire, SiC, GaN, GaAs, or ZnO. Figure 23 In the case of epitaxial growth of LE in the wafer substrate, the type, material and shape of the wafer substrate WAF are not restricted.

[0060] The wafer base WAF may include at least one of a flat zone FZ indicating a crystal orientation of the wafer and a notch NC.

[0061] The flat zone FZ may be a region where the crystal plane of the wafer is flat. The notch NC may be a triangular groove indicating the crystal orientation of the wafer. In another example, an alignment mark may be used instead of the flat zone FZ or the notch NC.

[0062] In an embodiment, the diameter of the wafer substrate WAF may be approximately 8 inches, approximately 10 inches, or approximately 12 inches. The wafer substrate WAF may be several micrometers (μm) to several hundred micrometers (μm). Each height (or thickness) of the wafer substrate WAF in the third direction DR3 may be approximately 100 μm or less. The third direction DR3 may intersect each of the first direction DR1 and the second direction DR2, and a normal direction of a surface (e.g., an upper surface or a lower surface) of the wafer substrate WAF may be substantially parallel to the third direction DR3.

[0063] The epitaxial thin film EPIL may include a third semiconductor layer USEM, a second semiconductor layer SEM2 , an active layer MQW, and a first semiconductor layer SEM1 sequentially disposed and / or stacked on the wafer substrate WAF along the third direction DR3 .

[0064] According to embodiments, the epitaxial thin film EPIL may further include additional layers, such as a superlattice layer disposed between the active layer MQW and the second semiconductor layer SEM2 and / or an electron blocking layer disposed between the first semiconductor layer SEM1 and the active layer MQW.

[0065] A third semiconductor layer USEM may be provided to reduce the difference in lattice constant between the second semiconductor layer SEM2 and the wafer substrate WAF. In an example, the third semiconductor layer USEM may include an undoped semiconductor that is an n-type or p-type undoped material. In an embodiment, the third semiconductor layer USEM may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the third semiconductor layer USEM may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The third semiconductor layer USEM may include a material other than silver.

[0066] The second semiconductor layer SEM2 may be disposed on the third semiconductor layer USEM. In embodiments, the second semiconductor layer SEM2 may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the second semiconductor layer SEM2 may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The second semiconductor layer SEM2 may include other materials.

[0067] The second semiconductor layer SEM2 may include a semiconductor material doped with a second conductive type dopant. For example, the second semiconductor layer SEM2 may be made of GaN (eg, n-GaN) doped with a second conductive type dopant (eg, n-type dopant) such as Si, Ge, Se, or Sn.

[0068] The active layer MQW may be disposed on the second semiconductor layer SEM2. The active layer MQW may emit light by recombination of electron-hole pairs in response to an electrical signal applied through the first and second semiconductor layers SEM1 and SEM2. For example, the active layer MQW may be a light emitting layer of the light emitting element LE.

[0069] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW may have a structure in which well layers and barrier layers are alternately stacked. The active layer MQW may include other III-V semiconductor materials depending on the wavelength of the emitted light.

[0070] In embodiments, the active layer MQW may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the active layer MQW may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, InGaAlN, AlN, InN, and AlInN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. For example, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but embodiments are not limited thereto. When the active layer MQW includes InGaN, the color of light emitted from the light-emitting element LE can be controlled by adjusting the indium (In) content. The active layer MQW may also include other materials.

[0071] The first semiconductor layer SEM1 may be disposed on the active layer MQW. The first semiconductor layer SEM1 may include a nitride-based semiconductor material or a phosphide-based semiconductor material. For example, the first semiconductor layer SEM1 may include a nitride-based semiconductor material including at least one of GaN, AlGaN, InGaN, AlInGaN, AlN, and InN, or a phosphide-based semiconductor material including at least one of GaP, GaInP, AlGaP, AlGaInP, AlP, and InP. The first semiconductor layer SEM1 may also include other materials.

[0072] The first semiconductor layer SEM1 may include a semiconductor material doped with a first conductive type dopant. For example, the first semiconductor layer SEM1 may include GaN (eg, p-GaN) doped with a first conductive dopant (eg, p-type dopant) such as Mg, Zn, Ca, Sr, or Ba.

[0073] In an embodiment, the first semiconductor layer SEM1 and the second semiconductor layer SEM2 may have different thicknesses in a thickness direction (eg, third direction DR3 ) of the epitaxial thin film EPIL. For example, the second semiconductor layer SEM2 may be thicker than the first semiconductor layer SEM1 in the thickness direction of the epitaxial thin film EPIL.

[0074] Marks AK may be provided on the epitaxial thin film EPIL to indicate crystal orientation.

[0075] Marks AK having a first size can be arranged at a first distance d1 across the entire surface of the epitaxial thin film EPIL. For example, the first distance d1 can range from approximately 50µm to approximately 300µm. In embodiments, the marks AK can be arranged at intervals of approximately 100µm (or spaced apart by approximately 100µm). Therefore, tens to hundreds of marks AK can be provided per unit area (or predetermined size) of approximately 1cm×1cm (width×length) on the epitaxial thin film EPIL. The first size can be approximately 1µm×1µm (width×length), but embodiments are not limited thereto. While the marks AK are preferably smaller, they should not be smaller than the minimum size that can be confirmed using an electron microscope.

[0076] The thickness Th1 of the mark AK may be equal to or smaller than the horizontal length (eg, length in the first direction DR1) and vertical length (eg, length in the second direction DR2) of the mark AK. For example, the thickness Th1 of the mark AK may be in the range of about 500 nm to about 1 μm.

[0077] The marks AK may be made of a photosensitive polymer (eg photoresist).The marks AK may all have the same shape and point to the crystal orientation.

[0078] Next, we will refer to Figures 4 to 6 Describes the shape of the marker AK.

[0079] Figures 4 to 6 AK is a schematic plan view showing an example of a marker AK.

[0080] Reference Figure 4 , the mark AK in the area defined by P1, P2, P3, and P4 may be formed by two or more strokes, and the length of each of the plurality of strokes may be in the range of about 500 nm to about 1 μm. For example, the mark AK may include a first stroke AK-1 and a second stroke AK-2, the first stroke AK-1 may be arranged horizontally relative to the crystal plane, and the second stroke AK-2 may be arranged perpendicular to the first stroke AK-1, but the position of the contact point K of the second stroke AK-2 and the first stroke AK-1 may indicate the crystal plane. For example, in Figure 4 In the case where P1 is a crystal plane, if only the first stroke AK-1 is placed horizontally relative to the crystal plane, it is difficult to determine whether the crystal plane is P1 or P3. Therefore, by placing the second stroke AK-2 in perpendicular contact with the first stroke AK-1, the direction along which the second stroke AK-2 points to the contact point can be the direction of the crystal plane. For example, the mark AK can clearly indicate the crystal orientation through the second stroke AK-2 and the first stroke AK-1.

[0081] Reference Figure 5The first stroke AK-1 can be arranged to be longer than the second stroke AK-2. With this arrangement, the plane defined by the second stroke AK-2 along its direction toward the contact point K, among the two horizontal planes relative to the longer first stroke AK-1, can be a crystal plane.

[0082] Reference Figure 6 , the first stroke AK-1 and the second stroke AK-2 contact each other at a single point and may be arranged similarly to the notch NC.

[0083] The first stroke AK-1, the second stroke AK-2, and the contact point K may be formed to point in the same direction as the notch NC, and may point in the direction of the same crystal plane as the notch NC.

[0084] exist Figure 4 and Figure 6 In the embodiment, the mark AK can be made of at least two tangentially adjacent parts and can accurately indicate the direction of the crystal plane by each stroke and contact point.

[0085] Figure 7 is an enlarged schematic cross-sectional view showing a portion of an epitaxial wafer according to another embodiment.

[0086] Reference Figure 7 , and Figure 3 The difference may be that the mark AK is provided between the wafer substrate WAF and the epitaxial thin film EPIL.

[0087] The mark AK may be provided on the wafer substrate WAF, and the epitaxial thin film EPIL may be provided on the mark AK. For example, the mark AK may be provided (e.g., directly) on the wafer substrate WAF, and the third semiconductor layer USEM may be provided (e.g., directly) on the mark AK. The third semiconductor layer USEM may be formed with a groove corresponding to the mark AK. For example, the mark AK may be surrounded by the third semiconductor layer USEM on both the side surface and the top surface.

[0088] In the case where the mark AK is provided between the wafer substrate WAF and the epitaxial thin film EPIL, there is a disadvantage of poor visibility. However, advantageously, the mark AK can be removed together with the removal of the third semiconductor layer USEM by a method such as sliding.

[0089] For example, the epitaxial wafer EWF may be divided into small sizes through a dicing process, and each of the divided pieces may be referred to as a wafer die.

[0090] Figure 8 is a schematic perspective view of the schematic shape of a wafer die. Figure 9 yes Figure 8 An enlarged schematic plan view of region A. Figure 10According to the embodiment Figure 9 Schematic cross-sectional view of .

[0091] Reference Figure 8 and Figure 10 , wafer die EWFD can be from epitaxial wafer ( Figure 1 The EWF in the wafer is divided into smaller blocks, and its cross-sectional structure (or shape) is substantially the same as the cross-sectional structure (or shape) of the epitaxial wafer EWF. For example, each of the wafer die EWFD may include a wafer substrate (e.g., Figure 3 A piece of wafer substrate WAF in the middle), divided into smaller-sized epitaxial thin films EPIL and marked AK.

[0092] In an embodiment, each of the wafer-die EWFDs may have a size corresponding to each unit region of a backplane substrate including unit regions for forming a display panel (e.g., a backplane mother substrate to be divided into backplane substrates for each display panel) (e.g., an area corresponding to the area of ​​each unit region). For example, by dividing the epitaxial wafer EWF into a size corresponding to the area of ​​each unit region of the backplane substrate including the unit regions, wafer-die EWFDs having a size corresponding to the area of ​​each unit region may be manufactured. In an embodiment, each of the wafer-die EWFDs may have a size greater than or equal to the area of ​​a display region positioned in each unit region.

[0093] In an embodiment, each of the wafer-die EWFDs may be rectangular or square.The wafer-die EWFDs may have a size of approximately 1 cm×1 cm, but the embodiment is not limited thereto.

[0094] Although the marks AK are invisible to the naked eye, dozens to hundreds of them may be provided on each of the wafer die EWFDs. The marks AK may be arranged in rows and columns at a first distance (or first pitch) d1. The distance between adjacent marks AK may be the first distance d1. For example, the first distance d1 may range from 50µm to 300µm, and in an embodiment, the first distance d1 may be approximately 100µm.

[0095] exist Figures 8 to 10 In the embodiment, each of the separated wafer-die EWFDs may include a mark AK. Therefore, the crystal orientation can be independently confirmed by the mark AK without requiring the crystal orientation information of the epitaxial wafer EWF used as a ledger of the wafer-die EWFDs.

[0096] Figure 11 According to another embodiment Figure 9 Schematic cross-sectional view of .

[0097] Reference Figure 11 , and Figure 10 The difference may be that the mark AK is provided between the wafer substrate WAF and the epitaxial thin film EPIL.

[0098] The mark AK may be provided on the wafer substrate WAF, and the epitaxial thin film EPIL may be provided on the mark AK. For example, the mark AK may be provided (eg, directly provided) on the wafer substrate WAF, and the third semiconductor layer USEM may be provided (eg, directly provided) on the mark AK.

[0099] Figure 12 is a flow chart illustrating a method of manufacturing a wafer die according to an embodiment. Figures 13 to 17 is a schematic diagram illustrating a method of manufacturing a wafer die according to an embodiment.

[0100] For example, Figures 13 to 17 Specific steps for forming the wafer die EWFD are shown in the form of schematic perspective views, schematic cross-sectional views or schematic plan views.

[0101] Reference Figure 12 and Figure 13 , can manufacture epitaxial wafer EWF including epitaxial thin film EPIL ( Figure 12 S110 in the ).

[0102] For example, Figure 13 As shown in , a wafer substrate WAF (or another type of substrate suitable for epitaxial growth) may be prepared, and an epitaxial thin film EPIL may be formed on the wafer substrate WAF. Figure 13 A schematic cross-sectional view of a portion of an epitaxial wafer EWF according to an embodiment is shown.

[0103] In the case of performing a subsequent dicing process, etc., the wafer base WAF may include a region (or unit region) CELA corresponding to the wafer die EWFD.

[0104] For example, on the wafer substrate WAF, the third semiconductor layer USEM, the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1 may be sequentially formed by epitaxial growth. In an embodiment, the third semiconductor layer USEM, the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1 may be formed by epitaxial growth using a process technology such as metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or vapor phase epitaxy (VPE).

[0105] The third semiconductor layer USEM may be formed from the materials previously described for the third semiconductor layer USEM. For example, the third semiconductor layer USEM may be formed from at least one nitride-based semiconductor material or at least one phosphide-based semiconductor material, and may be formed from a single semiconductor layer or multiple semiconductor layers. The third semiconductor layer USEM may be doped to include a second conductivity type dopant (e.g., an n-type dopant).

[0106] The third semiconductor layer USEM may include an undoped semiconductor that is an n-type undoped material or a p-type undoped material.

[0107] The second semiconductor layer SEM2 may be formed from the materials previously described for the second semiconductor layer SEM2. For example, the second semiconductor layer SEM2 may be formed from at least one nitride-based semiconductor material or at least one phosphide-based semiconductor material, and may be formed as a single semiconductor layer or multiple semiconductor layers. The second semiconductor layer SEM2 may be doped to include a second conductivity-type dopant (e.g., an n-type dopant).

[0108] The active layer MQW may be formed of the materials previously described for the active layer MQW. For example, the active layer MQW may be formed of at least one nitride-based semiconductor material or at least one phosphide-based semiconductor material. In embodiments, barrier layers and quantum well layers may be alternately and / or repeatedly formed on the second semiconductor layer SEM2 to form the active layer MQW having a multi-quantum well structure.

[0109] The first semiconductor layer SEM1 may be formed from the materials of the first semiconductor layer SEM1 previously described. For example, the first semiconductor layer SEM1 may be formed from at least one nitride-based semiconductor material or at least one phosphide-based semiconductor material, and may be formed from a single semiconductor layer or multiple semiconductor layers. The first semiconductor layer SEM1 may be doped to include a first conductivity-type dopant (e.g., a p-type dopant).

[0110] Reference Figure 12 and Figures 14 to 16 , a mark AK can be formed on the epitaxial film EPIL ( Figure 12 S120 in the . Figure 16 yes Figure 15 Schematic diagram of an enlarged portion of the cross section shown in FIG.

[0111] For example, refer to Figure 14 The photoresist layer PRL may be formed by uniformly applying a photosensitive polymer (eg, photoresist) to the entire surface of the epitaxial thin film EPIL. The thickness of the photoresist layer PRL may be about 500 nm to about 1 μm.

[0112] Reference Figure 14 and Figure 15 , the photoresist layer PRL can be selectively etched to form the mark AK.

[0113] For example, if the photosensitive polymer (e.g., photoresist) is negative-tone, a mask containing a marking pattern can be placed on the photoresist layer PRL, and an optical process can be performed to selectively etch the portions not exposed by the mask. The photoresist in the exposed portions becomes the marking AK. In another example, if the photosensitive polymer (e.g., photoresist) is positive-tone, a mask containing a marking pattern can be placed on the photoresist layer PRL, and an optical process can be performed to selectively etch the portions exposed by the mask. For example, the unexposed photoresist can become the marking AK. The marking pattern can have a pattern that repeats at a first distance d1. Thus, the marking AK can be formed at the first distance d1. The first distance d1 can range from approximately 50µm to approximately 300µm, and in an embodiment, can be approximately 100µm. The dimensions of the marking AK can be approximately 1µm × 1µm (width × length), but embodiments are not limited thereto.

[0114] Reference Figure 12 and Figure 17 , the epitaxial wafer EWF can be divided into wafer dies EWFD ( Figure 12 In an example, the wafer die EWFD may be manufactured by cutting the epitaxial wafer EWF into a size corresponding to the area of ​​the region (or unit region) CELA corresponding to the wafer die EWFD.

[0115] The size of the wafer die EWFD may be larger than the first distance d1, which is the separation distance between the marks AK, and the size of the wafer die EWFD may be formed so that dozens or hundreds of marks AK are arranged within the wafer die EWFD. For example, the size of the wafer die EWFD may be approximately 1 cm×1 cm.

[0116] Reference Figures 12 to 17 The wafer die EWFD manufactured can be compared with the reference Figures 8 to 10 The wafer die EWFD described above corresponds to the wafer die EWFD. For example, the wafer die EWFD may include a wafer substrate WAF, an epitaxial thin film EPIL, and a mark AK. The mark AK may be provided on the lower surface or the upper surface of the epitaxial thin film EPIL.

[0117] In an embodiment, after the epitaxial wafer EWF is divided into wafer dies EWFD, an evaluation (e.g., quality test) may be performed on each wafer die EWFD to select high-quality products. The wafer dies EWFD selected as high-quality products may be used to form light-emitting elements LE in each unit area CELA through subsequent processes.

[0118] In an embodiment, a destructive analysis may be performed on the wafer die EWFD for evaluation. Destructive analysis may require the production of a sample. For example, to produce the sample, the crystal orientation of the wafer die EWFD must first be confirmed.

[0119] Since the wafer die EWFD according to the embodiment includes the mark AK indicating the crystal orientation, it is easy to check the crystal orientation of the wafer die EWFD in the case of manufacturing a sample.

[0120] Figure 18 is an example of a structural analysis image obtained from a specimen fabricated in a crystal orientation. Figure 19 is an example of a structural analysis image obtained from a specimen fabricated in an amorphous orientation.

[0121] For example, structural analysis images can be acquired by transmission electron microscopy (TEM).

[0122] Reference Figure 18 and Figure 19 The quality of structural analysis images obtained from samples manufactured with a crystalline orientation can be higher than that of structural analysis images obtained from samples manufactured with an amorphous orientation. Structural analysis images obtained from samples manufactured with a crystalline orientation enable thickness measurements at the atomic level, and due to the clear images, measurement errors can be relatively small. On the other hand, structural analysis images obtained from samples with an amorphous orientation have low atomic resolution, which makes it difficult to measure atomic thickness, and when measuring atomic thickness, measurement errors can be relatively large. When measuring thickness in atomic units, measurement errors can be relatively large.

[0123] When it is difficult to confirm the crystal orientation of the wafer die EWFD, the sample may be produced with an amorphous orientation. When the sample is produced with an amorphous orientation, the analysis quality will deteriorate.

[0124] In the case where the wafer die EWFD has the mark AK, as in the embodiment, the crystal orientation can be easily identified, which helps to manufacture a specimen with the crystal orientation.

[0125] In the following, reference is made to Figures 20 to 24 , a method of manufacturing a light emitting element LE using the wafer die EWFD through subsequent processes will be described.

[0126] Figures 20 to 24 Schematic diagram showing a method for manufacturing a light emitting element. Figures 20 to 24 The wafer-to-die EWFD described can be compared with the reference Figures 12 to 17 The wafer described corresponds to the die EWFD.

[0127] For example, refer to Figure 20, the mark formed by the photoresist can be removed by methods such as stripping or ashing ( Figure 17 AK in ), and a bonding material is applied on the epitaxial thin film EPIL.

[0128] For example, the conductive bonding layer BDL can be formed by applying (e.g., entirely applying) a conductive bonding material on the epitaxial thin film EPIL. For example, gold (Au), copper (Cu), aluminum (Al), tin (Sn), or other bonding metals can be applied (e.g., deposited) on the top surface of the epitaxial thin film EPIL to form the conductive bonding layer BDL.

[0129] Reference Figure 21 , a backplane substrate 110 including a conductive bonding layer BDL may be prepared.

[0130] For example, the backplane substrate 110 may include light-emitting areas EA (e.g., EA1, EA2, and EA3) in which the light-emitting elements LE are to be formed. The backplane substrate 110 may include pixel electrodes PXE disposed in the light-emitting areas EA. For example, the backplane substrate 110 may include pixel electrodes PXE disposed in the light-emitting areas EA of each unit area CELA, pixel circuits PXC connected to each pixel electrode PXE, a first insulating layer INS1 disposed around the periphery of the pixel electrode PXE, and a conductive bonding layer BDL disposed on the pixel electrode PXE and the first insulating layer INS1.

[0131] Reference Figure 22 , the wafer die ( Figure 20 The EWFD in the backplane is bonded to the backplane substrate 110.

[0132] For example, the conductive bonding layer BDL of the backplane substrate 110 and the conductive bonding layer BDL of the wafer die EWFD may be arranged to face each other, and the conductive bonding layer BDL may be bonded by a thermocompression (TC) bonding method. The conductive bonding layer BDL of the backplane substrate 110 and the conductive bonding layer BDL of the wafer die EWFD may be welded to form an integrated conductive bonding layer BDL.

[0133] Thus, the backplane substrate 110 and the wafer die EWFD may be bonded. Subsequently, the wafer substrate WAF of the wafer die EWFD may be removed.

[0134] The wafer substrate WAF may be removed through a laser lift off (LLO) method, but the embodiment is not limited thereto.

[0135] Reference Figure 23 , a light emitting element LE can be formed.

[0136] For example, the epitaxial thin film EPIL may be etched to form each light emitting element LE in the light emitting area EA. The light emitting element LE may be formed on the pixel electrode PXE positioned in each light emitting area EA.

[0137] For example, the conductive bonding layer BDL may be etched to form a bonding electrode BOE. In an embodiment, the light-emitting element LE and the bonding electrode BOE may be formed in a size and / or shape corresponding to the pixel electrode PXE. For example, the light-emitting element LE and the bonding electrode BOE may be formed to have an area corresponding to the area of ​​the pixel electrode PXE and a planar shape that follows the planar shape of the pixel electrode PXE. However, the embodiment is not limited thereto, and the size and shape of the light-emitting element LE and the bonding electrode BOE may vary in different embodiments.

[0138] Reference Figure 24 , a subsequent process for forming the light emitting element layer 120 may be performed, the subsequent process including a process of forming the common electrode CE.

[0139] For example, Figure 24 As shown in FIG, an organic layer ORL may be formed between the light emitting elements LE. Thereafter, a common electrode CE may be sequentially formed on the light emitting elements LE.

[0140] In an embodiment, when manufacturing a display panel including a light conversion layer and / or a color filter layer, a process of forming a light conversion layer and / or a color filter layer on the top (or upper surface) of the light emitting element layer 120 or inside the light emitting element layer 120 may be further performed.

[0141] In an embodiment, in the case of manufacturing a display panel including a lens-type optical structure, a process of attaching and / or forming the lens-type optical structure on the light emitting element layer 120 or the like may be further performed.

[0142] Then, a modularization process or the like may be further performed to manufacture a display device including each display panel.

[0143] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles of the disclosure. Therefore, the disclosed embodiments disclosed are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A wafer, comprising: Wafer substrate; an epitaxial thin film, disposed on the wafer substrate and comprising a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer; as well as A plurality of marks are formed on the epitaxial thin film and indicate crystal orientation.

2. The wafer according to claim 1, wherein The markers are made of photosensitive polymer.

3. The wafer according to claim 1, wherein: Each of the plurality of marks is disposed on the surface of the epitaxial thin film and is spaced apart from an adjacent mark by a first distance.

4. The wafer according to claim 3, wherein: The first distance is in the range of 50 μm to 300 μm.

5. The wafer according to claim 1, wherein Tens to hundreds of marks are arranged per unit area of ​​1 cm×1 cm of the epitaxial thin film.

6. The wafer according to claim 1, wherein Each of the plurality of marks has a thickness of 500 nm to 1 μm.

7. The wafer according to claim 1, wherein: Each of the plurality of marks indicates a crystal orientation through a plurality of strokes and contact points of the plurality of strokes.

8. The wafer according to claim 7, wherein: A length of each of the plurality of strokes is in a range of 500 nm to 1 μm.

9. The wafer according to claim 7, wherein: The plurality of marks have the same shape.

10. The wafer according to claim 7, wherein: The wafer base includes at least one of a flat area and a notch, and The crystal orientation indicated by the flat area or the notch is consistent with the crystal orientation indicated by the mark.

11. A wafer, comprising: Wafer substrate; an epitaxial thin film, disposed on the wafer substrate and comprising a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer; as well as A plurality of marks are formed between the wafer substrate and the epitaxial thin film and indicate crystal orientation.

12. A wafer die, comprising: The wafer substrate is cut into predetermined sizes; an epitaxial thin film, disposed on the wafer substrate and comprising a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer; as well as A plurality of marks are formed on the epitaxial thin film and indicate crystal orientation.

13. The wafer die according to claim 12, wherein: The predetermined size is 1 cm×1 cm in width×length.

14. The wafer die according to claim 12, wherein: Dozens to hundreds of marks are provided on the surface of the epitaxial thin film.

15. The wafer die according to claim 12, wherein: Each of the plurality of marks indicates a crystal orientation through a plurality of strokes and contact points of the plurality of strokes.

16. A wafer die, comprising: The wafer substrate is cut into predetermined sizes; an epitaxial thin film, disposed on the wafer substrate and comprising a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer; as well as A plurality of marks are formed between the wafer substrate and the epitaxial thin film and indicate crystal orientation.

17. A method for manufacturing a wafer die, the method comprising the following steps: Growing an epitaxial thin film including a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer on a wafer substrate to form an epitaxial wafer; forming a mark indicating crystal orientation on the epitaxial thin film; as well as dividing the epitaxial wafer into a plurality of wafer dies, Each of the plurality of wafer dies includes a plurality of markings.

18. The method for manufacturing a wafer die according to claim 17, wherein: The step of forming a mark indicating the crystal orientation includes forming a photoresist layer by uniformly applying a photosensitive polymer throughout the epitaxial thin film and forming the mark by selectively etching the photoresist layer using a mask pattern.

19. The method for manufacturing a wafer die according to claim 17, wherein: The step of dividing the epitaxial wafer into the plurality of wafer dies includes: cutting the epitaxial wafer so that the epitaxial wafer is divided into a plurality of wafer dies each having a predetermined size.

20. The method for manufacturing a wafer die according to claim 19, wherein: The predetermined size is 1 cm×1 cm in width×length.

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