Semiconductor device and forming method thereof

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an electronic fuse, and a switching transistor. The electronic fuse is on the substrate. The switching transistor is arranged on the substrate and beside the electronic fuse. A first doped region of the substrate below the electronic fuse has a first conductivity type, a second doped region of the substrate below the switching transistor has a second conductivity type, and the first conductivity type is the same as the second conductivity type. The first doped region of the substrate is disposed between a plurality of third doped regions of the substrate, and a plurality of third conductivity types of the third doped regions are different from the first conductivity type. The semiconductor device avoids diffusion of dopants to avoid contamination of doped regions under the electronic fuses and the switching transistors. In addition, the size of the semiconductor device can be reduced, and no dopant contaminates the electronic fuse and a doped region below the switching transistor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for forming the same. Background Art

[0002] Electronic fuses are designed as sacrificial components and can be used in semiconductor devices to protect them from damage and / or improve their performance and efficiency. For example, electronic fuses are designed to blow when excessive current flows through them, thereby protecting the semiconductor from high voltage damage. Furthermore, by blowing the electronic fuse in a semiconductor device, the current in the semiconductor device can be varied as needed, thereby providing various circuit loops. In some cases, when a component in a semiconductor device is not functioning properly, the electronic fuse connected to that component may be blown to avoid reducing the performance and efficiency of the semiconductor device. However, as the size of semiconductor devices decreases, the distance between the electronic fuse and other components may also decrease. If the electronic fuse is too close to surrounding components and the dopant type implanted under the electronic fuse is different from the dopant type implanted under the surrounding components, the dopant may diffuse and cause contamination, thereby disrupting the function of the electronic fuse and / or surrounding components. Therefore, there is a need to develop a new semiconductor device including an electronic fuse and a method for forming the same to meet various needs. Summary of the Invention

[0003] The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an electronic fuse, and a switching transistor. The electronic fuse is on the substrate. The switching transistor is on the substrate and adjacent to the electronic fuse. A first doped region of the substrate below the electronic fuse has a first conductivity type, a second doped region of the substrate below the switching transistor has a second conductivity type, and the first conductivity type and the second conductivity type are the same. The first doped region of the substrate is disposed between a plurality of third doped regions of the substrate, and the plurality of third doped regions have a third conductivity type different from the first conductivity type.

[0004] In some embodiments, the first doped region and the third doped region are disposed between a plurality of source / drain doped regions of the substrate.

[0005] In some embodiments, depths of the source / drain doped regions in the substrate are greater than depths of the third doped regions in the substrate.

[0006] In some embodiments, the dopant concentrations of the source / drain doped regions are greater than the dopant concentrations of the third doped regions.

[0007] In some embodiments, the fourth conductivity type of the source / drain doped regions is the same as the third conductivity type.

[0008] In some embodiments, the second doped region of the substrate is disposed between a plurality of fourth doped regions of the substrate, the plurality of fourth conductivity types of these fourth doped regions are different from the second conductivity type, and one of these source / drain doped regions extends continuously from one of these third doped regions to one of these fourth doped regions.

[0009] In some embodiments, the first doped region is in direct contact with the third doped region.

[0010] In some embodiments, an electronic fuse includes a gate structure, a plurality of first spacers on a plurality of sidewalls of the gate structure, and a plurality of second spacers on the first spacers.

[0011] In some embodiments, the first doped region is disposed below the gate structure and the first spacer, and the third doped region is disposed below the second spacer.

[0012] In some embodiments, the first conductivity type is P-type, the second conductivity type is P-type, and the third conductivity types are N-type, or the first conductivity type is N-type, the second conductivity type is N-type, and the third conductivity types are P-type.

[0013] In some embodiments, a minimum distance between the gate structure of the electronic fuse and the gate structure of the switching transistor is less than 100 nm.

[0014] The present disclosure also provides a method for forming a semiconductor device. The method includes the following operations. Performing a first ion implantation process to form a first implantation region in a substrate. Forming a gate structure of an electronic fuse and a gate structure of a switching transistor on the first implantation region. Forming a plurality of first spacers on a plurality of sidewalls of the gate structure of the electronic fuse. Performing a second ion implantation process near the first spacers to convert a plurality of first portions of the first implantation region into a plurality of second implantation regions in the substrate, wherein the plurality of conductivity types of these second implantation regions are different from the conductivity type of the first implantation region. Forming a plurality of second spacers on the first spacers. Performing a third ion implantation process near the second spacers to convert a plurality of first portions of these second implantation regions into a plurality of third implantation regions in the substrate, wherein the plurality of conductivity types of these third implantation regions are the same as the conductivity type of the second implantation region.

[0015] In some embodiments, after performing the third ion implantation process, the second portion of the first implanted region remains under the gate structure of the electronic fuse and the first spacer, multiple second portions of the second implanted regions remain under the second spacers, and the second portion of the first implanted region and the second portions of the second implanted regions are located between the third implanted region.

[0016] In some embodiments, the ion implantation energy used in the third ion implantation process is greater than the ion implantation energy used in the second ion implantation process.

[0017] In some embodiments, the dopant concentration used in the second ion implantation process is 1×10 13 atoms / cm 3 Up to 1x10 15 atoms / cm 3 , and the dopant concentration used in the third ion implantation process is 1x10 14 atoms / cm 3 Up to 1x10 16 atoms / cm 3 .

[0018] In some embodiments, forming the first spacers further includes forming the first spacers on sidewalls of the gate structure of the switching transistor. After performing the third ion implantation process, the second portions of the second implanted regions remain and are located adjacent to the gate structure of the electronic fuse, the third portions of the second implanted regions remain and are located adjacent to the gate structure of the switching transistor, and one of the third implanted regions continuously extends from one of the second portions of the second implanted regions to one of the third portions of the second implanted regions.

[0019] In some embodiments, a P-type dopant is used in the first ion implantation process, and a plurality of N-type dopants are used in the second and third ion implantation processes. Alternatively, an N-type dopant is used in the first ion implantation process, and a plurality of P-type dopants are used in the second and third ion implantation processes.

[0020] In some embodiments, the dopant concentration used in the first ion implantation process is 1×10 11 atoms / cm 3 Up to 1x10 14 atoms / cm 3 . BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present disclosure may be better understood upon reading the following detailed description of embodiments with reference to the following drawings.

[0022] Figure 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0023] Figure 2 is a top view of a semiconductor device according to some embodiments of the present disclosure.

[0024] Figure 3 is a flow chart of a method of forming a semiconductor device according to some embodiments of the present disclosure.

[0025] Figures 4 to 10 is a cross-sectional view of a structure during formation of a semiconductor device using the method of the present disclosure according to some embodiments. DETAILED DESCRIPTION

[0026] To provide a detailed and complete description of the present disclosure, the following provides illustrative descriptions of various aspects of the embodiments. This is not intended to limit the embodiments of the present disclosure to a single form. The embodiments of the present disclosure may be combined or substituted with each other where beneficial, and other embodiments may be added without further description.

[0027] In addition, spatially relative terms, such as above and below, may be used in this disclosure to describe the relationship of one element (or feature) to another element (or feature) in a figure. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device when in use or operation. For example, the device may be oriented in other ways (e.g., rotated 90 degrees), and spatially relative terms may be interpreted accordingly. In this disclosure, unless otherwise indicated, the same element numbers in different figures refer to the same or similar elements formed from the same or similar materials by the same or similar methods.

[0028] The terms "about," "approximately," "close to," "substantially," "substantially," and the like used in this disclosure include values ​​(or features) that are understood by those skilled in the art to have a range of deviations from the stated value (or feature). For example, these terms may indicate values ​​within one or more standard deviations (e.g., values ​​within ±30%, ±20%, ±15%, ±10%, or ±5%), taking into account the error of the value (or feature), or may indicate that the feature includes deviations in practical operation (e.g., "substantially parallel" may mean close to parallel in practical operation rather than perfectly parallel in ideal operation). In addition, an acceptable range of deviations may be selected based on the nature of the measurement or other properties, rather than applying a single range of deviations to all values ​​(or features).

[0029] The present disclosure provides a semiconductor device 10, such as Figure 1 and Figure 2 As shown, Figure 1 yes Figure 2 Cross-sectional view taken along line AA. Semiconductor device 10 includes a substrate 101, an electronic fuse 102, and a switching transistor 103. Electronic fuse 102 is disposed above substrate 101. Switching transistor 103 is disposed above substrate 101 and adjacent to electronic fuse 102. A first doped region D1 of substrate 101 is disposed below electronic fuse 102 and has a first conductivity type, and a second doped region D2 of substrate 101 is disposed below each switching transistor 103 and has a second conductivity type, wherein the first conductivity type and the second conductivity type are the same. The first doped region D1 of substrate 101 is disposed between a plurality of third doped regions D3 of substrate 101, and the third doped regions D3 have a third conductivity type different from the first conductivity type. Because the first conductivity type of the first doped region D1 and the second conductivity type of the second doped region D2 disposed below the electronic fuse 102 and the switching transistor 103 are the same, the dopant in the first doped region D1 and the dopant in the second doped region D2 do not contaminate each other during the formation of the semiconductor device 10, given that dopants may diffuse between regions, and particularly when the distance between the electronic fuse 102 and the switching transistor 103 (e.g., the minimum distance W1 described below) is very small (e.g., less than 100 nm). The formation of the semiconductor device 10 can also be simplified by forming the first doped region D1 and the second doped region D2 together in a single implantation process (e.g., the first ion implantation process 201 described below). Moreover, as the distance between the electronic fuse 102 and the switching transistor 103 decreases, the single implantation process can more advantageously implant the first doped region D1 and the second doped region D2 with a large area (e.g., a small area) during the manufacturing process, compared to separately implanting the first doped region D1 and the second doped region D2 with a small area. Figure 2 In the illustrated embodiment, the doped region D1 is formed by a third doped region D3 adjacent to the first doped region D1, which facilitates current flow through the first doped region D1 when a voltage is applied to the gate structure 102G of the electronic fuse 102. The semiconductor device 10 of the present disclosure is described in detail below using the following embodiments.

[0030] The substrate 101 may be any suitable substrate. In some embodiments, the substrate 101 may be a semiconductor substrate and include a semiconductor material, wherein the semiconductor material includes an elemental semiconductor material, such as carbon, single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, tin, sulfur, selenium, tellurium, etc.; a compound semiconductor material, such as silicon carbide, boron nitride, aluminum nitride, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, etc.; an alloy semiconductor material, such as SiGe, AlGaAs, InGaAs, InGaP, AlInAs, GaAsP, AlGaN, InGaN, AlGaInP, etc.; or a combination thereof.

[0031] The substrate 101 includes different doped regions. For example, the first doped region D1 is located below the electronic fuse 102 to provide a path for current flowing below the electronic fuse 102. For example, the second doped region D2 is located below the switching transistor 103 to provide a path for current flowing below the switching transistor 103. For example, the third doped region D3 located next to the first doped region D1 makes it easier for current to flow in the first doped region D1 when a voltage is applied to the gate structure 102G of the electronic fuse 102. In some embodiments, the substrate 101 also includes a plurality of fourth doped regions D4, and the second doped region D2 is disposed between the fourth doped regions D4. In some embodiments, the first doped region D1 and the third doped region D3 are disposed between a plurality of source / drain doped regions D5, and the second doped region D2 and the fourth doped region D4 are disposed between a plurality of source / drain doped regions D5.

[0032] In some embodiments, the first doped region D1 is disposed below the gate structure 102G of the electronic fuse 102 and below the plurality of first spacers S1 on the gate structure 102G of the electronic fuse 102. In some embodiments, the second doped region D2 is disposed below the gate structure 103G of the switching transistor 103 and below the plurality of first spacers S1 on the gate structure 103G of the switching transistor 103. In some embodiments, the third doped region D3 is disposed below the plurality of second spacers S2 on the first spacer S1 on the gate structure 102G of the electronic fuse 102. In some embodiments, the fourth doped region D4 is disposed below the plurality of second spacers S2 on the first spacer S1 on the gate structure 103G of the switching transistor 103. In some embodiments, in a portion of the substrate 101 located below the space or region between the gate structure 102G of the electronic fuse 102 and the gate structure 103G of the switching transistor 103, one of the source / drain doped regions D5 extends continuously from one of the third doped regions D3 to one of the fourth doped regions D4, such that the source / drain doped region D5 can be shared by adjacent electronic fuses 102 and switching transistors 103. In some embodiments, the first doped region D1 is in direct contact with the third doped region D3. In some embodiments, the second doped region D2 is in direct contact with the fourth doped region D4. In some embodiments, the depth D5' of the source / drain doped region D5 in the substrate 101 (e.g., along a third direction Z perpendicular to the first direction X and the second direction Y) is greater than the depth D3' of the third doped region D3 in the substrate 101 (e.g., along the third direction Z). In some embodiments, the ratio of the depth D5' of any source / drain doping region D5 to the depth D3' of any third doping region D3 is preferably 1.5 to 7.5, for example, 1.5, 2.5, 3.5, 4.5, 5.5, 6.5 or 7.5, so as to have sufficient doping amounts of the source / drain doping region D5 and the third doping region D3, have a clear boundary between the working areas of the source / drain doping region D5 and the third doping region D3, and avoid excessive spending of manufacturing resources without significant improvement.

[0033] The first doped region D1 has a first conductivity type, the second doped region D2 has a second conductivity type, the third doped region D3 has a third conductivity type, the fourth doped region D4 has a fourth conductivity type, and the source / drain doped region D5 has a fifth conductivity type. The first conductivity type and the second conductivity type are the same. The third conductivity type, the fourth conductivity type, and the fifth conductivity type are different from the first conductivity type and the second conductivity type. In some embodiments, the first doped region D1 and the second doped region D2 each include a P-type dopant, such as boron or gallium, so that the first conductivity type and the second conductivity type are P-type, and the third doped region D3, the fourth doped region D4, and the source / drain doped region D5 each include an N-type dopant, such as phosphorus, antimony, or arsenic, so that the third conductivity type, the fourth conductivity type, and the fifth conductivity type are N-type. In some embodiments, the first doped region D1 and the second doped region D2 each include an N-type dopant, such as phosphorus, antimony, or arsenic, so that the first conductivity type and the second conductivity type are N-type, and the third doped region D3, the fourth doped region D4, and the source / drain doped region D5 each include a P-type dopant, such as boron or gallium, so that the third conductivity type, the fourth conductivity type, and the fifth conductivity type are P-type. In some embodiments, the dopant concentration of either the first doped region D1 or the second doped region D2 is preferably 1×10 11 atoms / cm 3 Up to 1x10 14 atoms / cm 3 , for example 1x10 11 atoms / cm 3 , 1x10 12 atoms / cm 3 , 1x10 13 atoms / cm 3 or 1x10 14 atoms / cm 3 In some embodiments, the dopant concentration of the source / drain doped region D5 is greater than the dopant concentration of the third doped region D3 and the dopant concentration of the fourth doped region D4. In some embodiments, the dopant concentration of either the third doped region D3 or the fourth doped region D4 is preferably 1×10 13 atoms / cm 3 Up to 1x10 15 atoms / cm 3 , for example, 1x10 13 atoms / cm 3 , 5x10 13 atoms / cm 3 , 1x10 14 atoms / cm 3 , 5x10 14 atoms / cm3 or 1x10 15 atoms / cm 3 In some embodiments, the dopant concentration of any one of the source / drain doped regions D5 is preferably 1×10 14 atoms / cm 3 Up to 1x10 16 atoms / cm 3 , for example, 1x10 14 atoms / cm 3 , 5x10 14 atoms / cm 3 , 1x10 15 atoms / cm 3 , 5x10 15 atoms / cm 3 or 1x10 16 atoms / cm 3 .

[0034] In some embodiments, because the first conductivity type of the first doped region D1 and the second conductivity type of the second doped region D2 disposed below the electronic fuse 102 and the switching transistor 103 are the same, the minimum distance W1 between the gate structure 102G of the electronic fuse 102 and the gate structure 103G of the switching transistor 103 can be reduced without causing cross-contamination between dopants in the first doped region D1 and dopants in the second doped region D2. In some embodiments, the minimum distance W1 is preferably 10 nm to 100 nm, such as 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, or 90 nm, to effectively reduce the size of the semiconductor device 10 and avoid significant interference between the gate structure 102G of the electronic fuse 102 and the gate structure 103G of the switching transistor 103.

[0035] In some embodiments, the gate structure 102G of the electronic fuse 102 is disposed between a source structure (not shown) and a drain structure (not shown), and the source structure and the drain structure are disposed on the source / drain doped region D5 of an adjacent electronic fuse 102. In some embodiments, the gate structure 103G of the switch transistor 103 is disposed between a source structure (not shown) and a drain structure (not shown), and the source structure and the drain structure are disposed on the source / drain doped region D5 of an adjacent switch transistor 103.

[0036] In some embodiments, insulating layer 104 is disposed on substrate 101, between substrate 101 and gate structure 102G of electronic fuse 102, and between substrate 101 and gate structure 103G of switch transistor 103. In some embodiments, insulating layer 104 comprises any suitable material, such as silicon oxide.

[0037] In some embodiments, the first electrode 105 is disposed on the source / drain doped region D5 and is located adjacent to a side of the switching transistor 103 opposite the side facing the electronic fuse 102. The first electrode 105 can serve as an electrical ground when the electronic fuse 102 is blown and can be used to measure resistance when confirming whether the electronic fuse 102 is blown. In some embodiments, the first electrode 105 includes any suitable material, such as a metal.

[0038] When a high voltage is applied to the gate structure 102G of the electronic fuse 102, the electronic fuse 102 may be blown. For example, when a high voltage is applied to the gate structure 102G of the electronic fuse 102, portions P1 and P2 of the insulating layer 104 adjacent to the gate structure 102G of the electronic fuse 102 may each have a probability of blowing. When portions P1, P2, or a combination thereof blow, an electrical short circuit occurs beneath the electronic fuse 102. To confirm whether an electrical short circuit has occurred beneath the electronic fuse 102, a voltage less than the voltage required to blow the electronic fuse 102 and greater than the minimum voltage required to overcome the pn junction beneath the electronic fuse 102 may be applied to the gate structure 102G of the electronic fuse 102. The resistance of the first electrode 105 is then measured. If the measured resistance is sufficiently low, it is determined that an electrical short circuit has occurred beneath the electronic fuse 102.

[0039] Switching transistor 103 is configured to open or close a channel beneath switching transistor 103, thereby controlling whether a blow operation is performed on electronic fuse 102 and whether resistance beneath electronic fuse 102 is measured. For example, when the channel beneath switching transistor 103 is open during a blow operation, a high-voltage current can flow from the channel beneath electronic fuse 102 to the channel beneath switching transistor 103, thereby flowing to electrical ground, thereby increasing the probability that electronic fuse 102 will blow. However, when the channel beneath switching transistor 103 is closed during a blow operation, the high-voltage current is blocked from flowing to electrical ground, preventing electronic fuse 102 from blowing. For example, when the channel beneath switching transistor 103 is open during resistance measurement, current beneath electronic fuse 102 can flow to first electrode 105 and be measured. However, when the channel under the switch transistor 103 is closed during resistance measurement, the current under the electronic fuse 102 cannot flow to the first electrode 105 and be measured.

[0040] In some embodiments, the semiconductor device 10 may include a cell 100, and the cell 100 includes an electronic fuse 102, two switching transistors 103 (e.g., switching transistor 103A and switching transistor 103B), and two first electrodes 105 (e.g., first electrode 105A and first electrode 105B), as shown in FIG. Figure 1 Therefore, the first side of the electronic fuse 102 (eg Figure 1 Whether the portion P1 of the insulating layer 104 next to the left side of the electronic fuse 102 is blown can be determined by the switch transistor 103A and the first electrode 105A next to the first side of the electronic fuse 102, and the second side of the electronic fuse 102 (for example, Figure 1 Whether portion P2 of insulating layer 104 on the right side (in FIG. 1 ) is blown can be determined by switching transistor 103B and first electrode 105B on the second side. The first and second sides are substantially opposite each other. Because the two switching transistors 103 can operate independently by opening or closing their respective channels, whether portions P1 and P2 are blown can be independently measured.

[0041] The number of units 100 is not limited. In some embodiments, the number of units 100 is preferably an integer from 1 to 20, such as 1, 4, 8, 12, 16 or 20 (e.g., Figure 2 16). In some embodiments, the cells 100 are arranged along a first direction X, and the electronic fuse 102, the switching transistor 103, and the first electrode 105 in each cell 100 are arranged along a second direction Y perpendicular to the first direction X. In some embodiments, the electronic fuse 102, the switching transistor 103, and the first electrode 105 in one cell 100 are aligned with the electronic fuse 102, the switching transistor 103, and the first electrode 105 in another cell 100, respectively. In some embodiments, the switching transistor 103A and the switching transistor 103B in the same cell 100 are physically connected in a top view, as shown in FIG. Figure 2 In some embodiments, the electronic fuses 102 in different units 100 are physically connected in a top view, and the switching transistors 103 in different units 100 are physically connected in a top view, as shown in FIG. Figure 2As shown. In some embodiments, the second electrode 106 can be a common electrode of the physically connected electronic fuses 102, so that a voltage can be applied simultaneously to multiple electronic fuses 102 to blow them and / or a voltage can be applied simultaneously to read the resistance of multiple electronic fuses 102. In some embodiments, multiple second electrodes 106 disposed on the physical connections of the electronic fuses 102 are arranged along the first direction X, and the physically connected electronic fuses 102 are disposed between these second electrodes 106. In some embodiments, the third electrode 107 can be a common electrode of the physically connected switching transistors 103, so that the switching transistors 103 in different cells 100 can be turned on and / or off simultaneously. In some embodiments, the multiple third electrodes 107 disposed on the physical connections of the switching transistors 103 include multiple third electrodes 107A and multiple third electrodes 107B, wherein the switching transistor 103A is disposed between these third electrodes 107A, and the switching transistor 103B is disposed between these third electrodes 107B. It should be noted that since each unit 100 includes the first electrode 105A and the first electrode 105B, each unit 100 can be operated independently, for example, selectively electrically grounding certain first electrodes 105 and / or selectively reading the resistance of certain first electrodes 105 .

[0042] In some embodiments, each cell 100 is disposed on a corresponding active region 101A in a substrate 101, and different active regions 101A are separated from each other by isolation regions of the substrate 101. In some embodiments, in each cell, a width W2 of the active region 101A below the electronic fuse 102 is smaller than a width W3 of the active region 101A below the switching transistor 103. This allows the channel below the switching transistor 103 to be larger than the channel below the electronic fuse 102. This allows the electronic fuse 102 to be more easily blown due to the smaller channel.

[0043] The present disclosure also provides a method 20 for forming the semiconductor device 10 . Figure 3The method 20 shown in the flowchart of FIG. 1 includes operations 21 to 26. Operation 21 includes performing a first ion implantation process 201 to form a first implant region 202 in the substrate 101. Operation 22 includes forming a gate structure 102G of the electronic fuse 102 and a gate structure 103G of the switch transistor 103 above the first implant region 202. Operation 23 includes forming a first spacer S1 on the sidewalls of the gate structure 102G of the electronic fuse 102. Operation 24 includes performing a second ion implantation process 206 adjacent to the first spacer S1 to convert a plurality of first portions 202A of the first implant region 202 into a plurality of second implant regions 207 in the substrate 101, wherein the conductivity type of the second implant regions 207 is different from the conductivity type of the first implant regions 202. Operation 25 includes forming a second spacer S2 on the first spacer S1. Operation 26 includes performing a third ion implantation process 209 adjacent to the second spacer S2 to convert the plurality of first portions 207A of the second implanted region 207 into a plurality of third implanted regions (i.e., the source / drain doped regions D5 described above) in the substrate 101, wherein the conductivity type of the third implanted regions is the same as the conductivity type of the second implanted regions 207. Next, the method 20 of the present disclosure will be described in detail through the following embodiments.

[0044] Operation 21 includes performing a first ion implantation process 201 to form a first implantation region 202 in the substrate 101, such as Figure 4 As shown. Multiple portions of the first injection region 202 (eg, Figure 7 The first portion 202A in the first implantation process 201 will be converted into the second implantation region 207, and the portion of the first implantation region 202 remaining below the gate structure 102G of the electronic fuse 102, below the gate structure 103G of the switch transistor 103, and below the first spacer S1 is the first doped region D1 and the second doped region D2 mentioned above. Since the first doped region D1 and the second doped region D2 are implanted together in the first ion implantation process 201, the implantation region (for example, Figure 2In the embodiment shown, the area shown by the dotted line 108 may be larger than the implantation area into which the first doped region D1 and the second doped region D2 are implanted separately. Therefore, the present disclosure does not require the use of manufacturing tools that implant the first doped region D1 and the second doped region D2 separately to avoid the limitations of the manufacturing tools. For example, the pattern formed by the photolithography tool may have size limitations and cannot be smaller, so that the size of the implantation area formed according to the pattern formed by the photolithography tool may be limited. In addition, since the first doped region D1 and the second doped region D2 are implanted together in the first ion implantation process 201, the conductivity type of the first doped region D1 and the conductivity type of the second doped region D2 are the same. In some embodiments, the first ion implantation process 201 uses a P-type dopant (for example, boron or gallium, etc.). In some embodiments, the first ion implantation process 201 uses an N-type dopant (for example, phosphorus, antimony or arsenic, etc.). In some embodiments, the dopant concentration used in the first ion implantation process 201 is preferably 1x10 11 atoms / cm 3 Up to 1x10 14 atoms / cm 3 , for example, 1x10 11 atoms / cm 3 , 1x10 12 atoms / cm 3 , 1x10 13 atoms / cm 3 or 1x10 14 atoms / cm 3 In some embodiments, as Figure 5 As shown, after forming the first implant region 202 , the insulating layer 104 may be formed on the first implant region 202 by any suitable deposition method, such as a chemical deposition process or a physical deposition process.

[0045] Operation 22 includes forming a gate structure 102G of the electronic fuse 102 and a gate structure 103G of the switch transistor 103 on the first implant region 202, such as Figures 5 and 6As shown. In some embodiments, a material 203 for the gate structure 102G and the gate structure 103G is formed on the first implant region 202 by any suitable deposition method, such as a chemical deposition process or a physical deposition process. Next, a patterned photoresist layer 204 is formed on the material 203 to define the pattern of the gate structure 102G and the gate structure 103G. Specifically, portions of the material 203 exposed by the openings 204O of the patterned photoresist layer 204 can be removed by any suitable etching method, such as a dry etching process or a wet etching process, to form the gate structure 102G and the gate structure 103G. In some embodiments, after the gate structure 102G and the gate structure 103G are formed, the patterned photoresist layer 204 is removed.

[0046] Operation 23 includes forming a first spacer S1 on the sidewalls of the gate structure 102G of the electronic fuse 102, such as Figures 7 and 8 As shown. In some embodiments, forming the first spacer S1 also includes forming the first spacer S1 on the sidewalls of the gate structure 103G of the switching transistor 103. Specifically, the material 205 of the first spacer S1 is conformally formed on the gate structure 102G and the gate structure 103G by any suitable deposition method, for example, by an atomic layer deposition process. Next, a portion of the material 205 is removed by any suitable etching method, for example, by a dry etching process or a wet etching process, so as to retain another portion of the material 205 on the sidewalls of the gate structure 102G and the sidewalls of the gate structure 103G. In some embodiments, the material 205 can be any suitable material, such as silicon nitride. The first spacer S1 will be used to define the formation position of the second implantation region 207, and the portion of the substrate 101 below the first spacer S1 can be used to provide process tolerance for the diffusion of the second implantation region 207.

[0047] Operation 24 includes performing a second ion implantation process 206 adjacent to the first spacer S1 to transform the first portion 202A of the first implantation region 202 into a second implantation region 207 of the substrate 101, as shown in FIG. Figures 7 and 8 As shown, the conductivity type of the second injection region 207 is different from the conductivity type of the first injection region 202. Multiple portions of the second injection region 207 (e.g., Figure 9The first portion 207A of the second implanted region 207 is converted into the third implanted region (i.e., the source / drain doped region D5), while the portion of the second implanted region 207 remaining below the second spacer S2 is the third doped region D3 and the fourth doped region D4 described above. In embodiments where a P-type dopant is implanted into the first implanted region 202, the second ion implantation process 206 uses an N-type dopant (e.g., phosphorus, antimony, or arsenic). In embodiments where an N-type dopant is implanted into the first implanted region 202, the second ion implantation process 206 uses a P-type dopant (e.g., boron or gallium). In some embodiments, the dopant concentration used in the second ion implantation process 206 is preferably 1x10 13 atoms / cm 3 Up to 1x10 15 atoms / cm 3 , for example 1x10 13 atoms / cm 3 , 5x10 13 atoms / cm 3 , 1x10 14 atoms / cm 3 , 5x10 14 atoms / cm 3 or 1x10 15 atoms / cm 3 In some embodiments, the ion implantation energy for the second ion implantation process 206 is preferably 2 KeV to 10 KeV, for example, 2 KeV, 4 KeV, 6 KeV, 8 KeV, or 10 KeV, to obtain a desired depth of the second implantation region 207 (eg, the depth D3' described above).

[0048] Operation 25 includes forming a second spacer S2 on the first spacer S1, such as Figures 9 and 10 As shown. Specifically, the material 208 of the second spacer S2 is conformally formed on the first spacer S1, the gate structure 102G and the gate structure 103G by any suitable deposition method (e.g., an atomic layer deposition process). Next, a portion of the material 208 is removed by any suitable etching method (e.g., a dry etching process or a wet etching process) to retain another portion of the material 208 on the first spacer S1. In some embodiments, the material 208 can be any suitable material, such as silicon nitride. The second spacer S2 will be used to define the formation position of the third implantation region (i.e., the source / drain doped region D5) in the following operation, and the portion of the substrate 101 below the second spacer S2 can be used to provide process tolerance for the diffusion of the third implantation region.

[0049] Operation 26 includes performing a third ion implantation process 209 adjacent to the second spacer S2 to convert the first portion 207A of the second implant region 207 into a third implant region (ie, source / drain doped region D5) in the substrate 101, as shown in FIG. Figure 10 As shown, the conductivity type of the third implanted region is the same as the conductivity type of the second implanted region 207. After performing the third ion implantation process 209, the portions of the first implanted region 202 remaining below the gate structure 102G and the gate structure 103G are the first doped region D1 and the second doped region D2 described above, respectively. The portions of the second implanted region 207 remaining below the second spacer S2 are the third doped region D3 and the fourth doped region D4 described above. The third implanted region is the source / drain doped region D5 described above. In embodiments where a P-type dopant is implanted into the first implanted region 202, an N-type dopant (e.g., phosphorus, antimony, or arsenic) is used in the second ion implantation process 206 and the third ion implantation process 209. In embodiments where an N-type dopant is implanted into the first implanted region 202, a P-type dopant (e.g., boron or gallium) is used in the second ion implantation process 206 and the third ion implantation process 209. In some embodiments, the dopant concentration used in the third ion implantation process 209 is preferably 1x10 14 atoms / cm 3 Up to 1x10 16 atoms / cm 3 , for example 1x10 14 atoms / cm 3 , 5x10 14 atoms / cm 3 , 1x10 15 atoms / cm 3 , 5x10 15 atoms / cm 3 or 1x10 16 atoms / cm 3 In some embodiments, the ion implantation energy for the third ion implantation process 209 is greater than the ion implantation energy for the second ion implantation process 206. In some embodiments, the ion implantation energy for the third ion implantation process 209 is preferably 10KeV to 15KeV, such as 10KeV, 11KeV, 12KeV, 13KeV, 14KeV, or 15KeV, to obtain a desired depth of the third implantation region (e.g., the depth D5' described above). In some embodiments, after performing the third ion implantation process 209, the first electrode 105 is formed on the third implantation region to obtain a desired depth of the third implantation region (e.g., the depth D5' described above). Figure 1 The semiconductor device 10 is shown.

[0050] In some embodiments, when the plurality of cells 100 are formed, the first implant region 202 formed in operation 21 extends between different cells 100, such as Figure 2 In addition, the material 203 of the gate structure 102G and the gate structure 103G formed in operation 22 extends along the first direction X and the second direction Y, and after the material 203 is patterned by the patterned photoresist layer 204, the remaining material 203 is as shown in FIG. Figure 2 , the gate structures 102G of the electronic fuses 102 in different cells 100 are physically connected, and the gate structures 103G of the switch transistors 103 in different cells 100 are physically connected. In addition, a second electrode 106 is formed on the portion of the material 203 remaining with the physically connected gate structure 102G, and a third electrode 107 is formed on the portion of the material 203 remaining with the physically connected gate structure 103G.

[0051] The semiconductor device and its formation method avoid dopant diffusion, which could contaminate the doped regions beneath the electronic fuse and the switching transistor. Furthermore, the size of the semiconductor device can be reduced without dopant contamination of the doped regions beneath the electronic fuse and the switching transistor. Furthermore, the method is easy to implement and is not limited by current manufacturing tools.

[0052] This disclosure describes certain embodiments in considerable detail, but other embodiments are also possible. Therefore, the description of embodiments in this disclosure is not intended to limit the scope and spirit of the appended claims. Modifications and variations of this disclosure may occur to those skilled in the art without departing from the scope and spirit of this disclosure. This disclosure is intended to cover such modifications and variations as long as they fall within the scope and spirit of the appended claims.

[0053]

Explanation of symbols

[0054] 10: Semiconductor devices

[0055] 20: Method

[0056] 21: Operation

[0057] 22: Operation

[0058] 23: Operation

[0059] 24: Operation

[0060] 25: Operation

[0061] 26: Operation

[0062] 100: Unit

[0063] 101: Substrate

[0064] 101A: Active area

[0065] 102: Electronic fuse

[0066] 102G: Gate structure

[0067] 103: Switching transistor

[0068] 103A: Switching transistor

[0069] 103B: Switching transistor

[0070] 103G: Gate structure

[0071] 104: Insulation layer

[0072] 105: First electrode

[0073] 105A: First electrode

[0074] 105B: First electrode

[0075] 106: Second electrode

[0076] 107: Third electrode

[0077] 107A: Third electrode

[0078] 107B: Third electrode

[0079] 108: Dashed line

[0080] 201: First ion implantation process

[0081] 202: First injection area

[0082] 202A: Part 1

[0083] 203: Materials

[0084] 204: Patterned photoresist layer

[0085] 204O: Opening

[0086] 205: Materials

[0087] 206: Second ion implantation process

[0088] 207: Second injection area

[0089] 207A: Part 1

[0090] 208: Materials

[0091] 209: The third ion implantation process

[0092] AA: Line

[0093] D1: first doped region

[0094] D2: Second doped region

[0095] D3: third doping region

[0096] D3': Depth

[0097] D4: fourth doping region

[0098] D5: Source / drain doping region

[0099] D5': Depth

[0100] P1: Part

[0101] P2: Part

[0102] S1: First interstitial

[0103] S2: Second interstitial

[0104] W1: Minimum distance

[0105] W2: width

[0106] W3: Width

[0107] X: First direction

[0108] Y: Second direction

[0109] Z: The third direction.

Claims

1. A semiconductor device, characterized in that: include: substrate; An electronic fuse is on the substrate; as well as A switching transistor is on the substrate and next to the electronic fuse, wherein: A first doped region of the substrate below the electronic fuse has a first conductivity type, a second doped region of the substrate below the switching transistor has a second conductivity type, and the first conductivity type and the second conductivity type are the same; as well as The first doping region of the substrate is disposed between a plurality of third doping regions of the substrate, and a plurality of third conductivity types of the plurality of third doping regions are different from the first conductivity type. 2 . The semiconductor device according to claim 1 , wherein the first doped region and the plurality of third doped regions are disposed between a plurality of source / drain doped regions of the substrate. 3 . The semiconductor device according to claim 2 , wherein depths of the plurality of source / drain doped regions in the substrate are greater than depths of the plurality of third doped regions in the substrate. 4 . The semiconductor device according to claim 2 , wherein dopant concentrations of the source / drain doping regions are greater than dopant concentrations of the third doping regions. 5 . The semiconductor device according to claim 2 , wherein the fourth conductivity type of the plurality of source / drain doped regions is the same as the third conductivity type.

6. The semiconductor device according to claim 2, wherein the second doping region of the substrate is arranged between a plurality of fourth doping regions of the substrate, a plurality of fourth conductivity types of the plurality of fourth doping regions are different from the second conductivity type, and one of the plurality of source / drain doping regions extends continuously from one of the plurality of third doping regions to one of the plurality of fourth doping regions. The semiconductor device according to claim 1 , wherein the first doped region is in direct contact with the plurality of third doped regions. 8 . The semiconductor device of claim 1 , wherein the e-fuse comprises a gate structure, a plurality of first spacers on a plurality of sidewalls of the gate structure, and a plurality of second spacers on the plurality of first spacers. 9 . The semiconductor device of claim 8 , wherein the first doped region is disposed under the gate structure and the plurality of first spacers, and the plurality of third doped regions are disposed under the plurality of second spacers.

10. The semiconductor device according to claim 1, wherein: The first conductivity type is P type, the second conductivity type is P type, and the plurality of third conductivity types are a plurality of N types; or The first conductivity type is N type, the second conductivity type is N type, and the plurality of third conductivity types are a plurality of P types. 11 . The semiconductor device according to claim 1 , wherein a minimum distance between a gate structure of the electronic fuse and a gate structure of the switch transistor is less than 100 nm.

12. A method for forming a semiconductor device, characterized in that: include: performing a first ion implantation process to form a first implantation region in the substrate; forming a gate structure of an electronic fuse and a gate structure of a switching transistor on the first implantation region; forming a plurality of first spacers on a plurality of sidewalls of the gate structure of the electronic fuse; performing a second ion implantation process proximate the plurality of first spacers to convert the plurality of first portions of the first implant regions into a plurality of second implant regions in the substrate, wherein the plurality of conductivity types of the plurality of second implant regions are different from the conductivity type of the first implant regions; forming a plurality of second spacers on the plurality of first spacers; as well as A third ion implantation process is performed proximate the second spacers to convert first portions of the second implant regions into third implant regions in the substrate, wherein the third implant regions have the same conductivity types as the second implant regions.

13. The method of claim 12 , wherein after performing the third ion implantation process, a second portion of the first implantation region remains below the gate structure of the electronic fuse and the plurality of first spacers, a plurality of second portions of the plurality of second implantation regions remain below the plurality of second spacers, and the second portion of the first implantation region and the plurality of second portions of the plurality of second implantation regions are located between the plurality of third implantation regions. 14 . The method according to claim 12 , wherein ion implantation energy used in the third ion implantation process is greater than ion implantation energy used in the second ion implantation process.

15. The method according to claim 12, wherein the dopant concentration used in the second ion implantation process is 1×10 13 atoms / cm 3 Up to 1x10 15 atoms / cm 3 , and the dopant concentration used in the third ion implantation process is 1x10 14 atoms / cm 3 Up to 1x10 16 atoms / cm 3 .

16. The method of claim 12, wherein: Forming the plurality of first spacers further comprises forming the plurality of first spacers on a plurality of sidewalls of the gate structure of the switch transistor; as well as After performing the third ion implantation process, the plurality of second portions of the plurality of second implantation regions remain and are located near the gate structure of the electronic fuse, the plurality of third portions of the plurality of second implantation regions remain and are located near the gate structure of the switching transistor, and one of the plurality of third implantation regions continuously extends from one of the plurality of second portions of the plurality of second implantation regions to one of the plurality of third portions of the plurality of second implantation regions.

17. The method of claim 12, wherein: Using a P-type dopant in the first ion implantation process, and using a plurality of N-type dopants in the second ion implantation process and the third ion implantation process; or An N-type dopant is used in the first ion implantation process, and a plurality of P-type dopants are used in the second and third ion implantation processes.

18. The method according to claim 12, wherein the dopant concentration used in the first ion implantation process is 1×10 11 atoms / cm 3 Up to 1x10 14 atoms / cm 3 .

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