Gate driver circuit

Abstract

A driver circuit for controlling a high power switch. The driver circuit includes a flyback converter and a driver stage. The flyback converter includes a controller configured to: receive a PWM control signal, the PWM control signal being used to control the high power switch; receiving a feedback voltage signal representing a measured voltage of a positive output rail or a negative output rail of the flyback converter; and providing a primary side switch control signal comprising a burst of pulses for operating a primary switch, where the controller is configured to start a burst of pulses in response to an edge of the PWM control signal and stop the burst of pulses in response to the feedback voltage crossing a threshold. The drive stage is connected between the positive output rail and the negative output rail. A drive circuit is configured to provide a high power switch control signal for controlling a state of the high power switch based on the PWM control signal.

Description

Technical Field

[0001] The present disclosure relates to a gate driver circuit, and in particular to an isolated gate driver circuit suitable for driving the gate of a high power switch in an inverter such as found in an electric vehicle. Background Art

[0002] Electronic converters, such as AC to DC, or DC to AC converters, are known in the art. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a driver circuit for controlling a high-power switch, the driver circuit comprising:

[0004] A flyback converter comprising:

[0005] Primary switch;

[0006] a positive output rail configured to provide a positive output voltage;

[0007] a negative output rail configured to provide a negative output voltage; and

[0008] A controller configured to:

[0009] receiving a PWM control signal, wherein the PWM control signal is used to control the high-power switch;

[0010] receiving a feedback voltage signal representing a measured voltage of the positive output rail or the negative output rail; and

[0011] providing a primary side switch control signal, the primary side switch control signal comprising a burst of pulses for operating the primary switch, wherein the controller is configured to start the burst of pulses in response to an edge of the PWM control signal and to stop the burst of pulses in response to a feedback voltage crossing a threshold;

[0012] A driver stage is connected between the positive output rail and the negative output rail, wherein the driver circuit is configured to provide a high power switch control signal for controlling a state of the high power switch based on the PWM control signal.

[0013] Advantageously, using the edge of the PWM control signal to initiate a burst can improve the performance of the gate driver circuit because the primary switch can operate more quickly in response to the edge of the PWM control signal, rather than waiting for the effect of the edge to be reflected in the feedback voltage signal.

[0014] In one or more embodiments, the feedback voltage represents the measured voltage of the positive output rail. The controller can be configured to:

[0015] A burst is started in response to any of the following:

[0016] i) the falling edge of the PWM control signal, or

[0017] ii) the feedback voltage is less than the lower threshold, and

[0018] The burst is stopped in response to the feedback voltage exceeding an upper threshold.

[0019] In one or more embodiments, a flyback converter includes a flyback transformer having a primary winding and a secondary winding. The flyback converter may further include a shunt regulator configured to provide a negative output voltage as a regulated version of a negative voltage at the secondary winding of the flyback transformer.

[0020] In one or more embodiments, the flyback converter further includes an LDO voltage regulator configured to provide a positive output voltage as a regulated version of the positive voltage at the secondary winding of the flyback transformer.

[0021] In one or more embodiments, the controller is additionally configured to:

[0022] receiving a shunt active signal indicating whether the shunt regulator is active; and

[0023] The burst stops in response to any of the following:

[0024] The feedback voltage exceeds the upper threshold; or

[0025] The shunt active signal has a value indicating that the shunt regulator is active.

[0026] In one or more embodiments, the feedback voltage represents the measured voltage of the negative output rail. The controller can be configured to:

[0027] A burst is started in response to any of the following:

[0028] i) The rising edge of the PWM control signal, or

[0029] ii) the feedback voltage drops below a lower threshold; and

[0030] The burst is stopped when the feedback voltage is greater than the upper threshold.

[0031] In one or more embodiments, the controller is configured to:

[0032] receiving a flyback clock signal;

[0033] providing a burst enable signal that is: set to a first value when the controller starts a burst; and set to a second value when the controller stops a burst; and

[0034] The flyback clock signal is selectively provided as a primary side switch control signal for the primary switch based on a value of the burst enable signal.

[0035] In one or more embodiments:

[0036] A flyback converter has a primary side and a secondary side;

[0037] The controller includes a primary side controller on the primary side of the flyback converter;

[0038] The controller includes a secondary side controller on a secondary side of a flyback converter; and

[0039] The driver circuit additionally includes a galvanically isolated communication layer configured to transmit signaling from the secondary side controller to the primary side controller.

[0040] In one or more embodiments, the secondary side controller is configured to:

[0041] asserting a burst enable signal; and

[0042] The determined burst enable signal is sent to the primary side controller via a galvanically isolated communication layer.

[0043] In one or more embodiments, the secondary side controller is configured to:

[0044] The determined burst enable signal is sent to the primary side controller via the galvanically isolated communication layer such that the determined burst enable signal is time-division multiplexed with other data.

[0045] In one or more embodiments, the other data represents measurements associated with the secondary side.

[0046] In one or more embodiments, a flyback converter includes a flyback transformer having a primary winding and a single secondary winding.

[0047] In one or more embodiments, a flyback converter includes:

[0048] positive track capacitors;

[0049] negative rail capacitor; and

[0050] diode.

[0051] The positive rail capacitor and the diode may be connected in series with each other between the first end of the secondary winding of the flyback transformer and the reference terminal; and the negative rail capacitor may be connected in series between the second end of the secondary winding of the flyback transformer and the reference terminal.

[0052] The positive rail capacitor may be connected in series between a first end of the secondary winding of the flyback transformer and a reference end; and the negative rail capacitor and the diode may be connected in series with each other between a second end of the secondary winding of the flyback transformer and the reference end.

[0053] In one or more embodiments, the primary switch is connected in series with the primary winding of the flyback transformer between the voltage source on the primary side and a reference terminal.

[0054] Although the present disclosure allows for various modifications and alternative forms, details thereof have been shown in the drawings by way of example and will be described in detail. However, it should be understood that other embodiments besides the specific embodiments described are also possible. All modifications, equivalents, and alternative embodiments that fall within the spirit and scope of the appended claims are also encompassed.

[0055] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future technology set. The drawings and the following detailed description also illustrate various example embodiments. The various example embodiments can be more fully understood by considering the following detailed description in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0057] Figure 1 An example of a gate driver circuit according to an embodiment of the present disclosure is shown;

[0058] Figure 2 Show Figure 1 Example curves of the flyback clock signal, burst enable signal, and primary side switch control signal;

[0059] Figure 3 Show Figure 1 Curves of various signals in the gate driver circuit;

[0060] Figure 4 Show Figure 1 Another curve of the signal in the gate driver circuit;

[0061] Figure 5a Show that it can be Figure 1 Representation of the three different state machines implemented by the secondary-side controller;

[0062] Figures 5b-5d Show Figure 5a The VCC curves of three different state machines;

[0063] Figure 6 Show Figure 1 The signal curve of the gate driver circuit is similar to Figure 4curve, but this time with adaptive control; and

[0064] Figure 7 Show for example Figure 1 An example embodiment of (at least a portion of) a galvanically isolated communication layer is shown. DETAILED DESCRIPTION

[0065] For example, inverters used in electric vehicles (EVs) can use isolated gate driver ICs (integrated circuits). These gate driver ICs can include isolated flyback converters to power their high-voltage side, rather than using external controllers. Some safety cases can use separate controllers for each inverter branch.

[0066] Figure 1 An example of a gate driver circuit 100 according to an embodiment of the present disclosure is shown. The gate driver circuit 100 is used to drive the gate of a high power switch 103, such as found in an inverter in an electric vehicle. As will be discussed in detail below, the state of the high power switch 103 is controlled based on a pulse width modulation (PWM) signal 104.

[0067] The gate driver circuit 100 includes a flyback converter 101 and a gate driver stage 102. The flyback converter 101 includes a primary switch 110 and a flyback transformer 107 having a primary winding and a secondary winding. The flyback transformer 107 provides galvanic isolation between the primary side of the flyback converter 101 and the secondary side of the flyback converter 101. Figure 1 In the example shown, the primary side of the flyback converter 101 is the relatively low voltage side connected to the microprocessor. The secondary side of the flyback converter 101 is the relatively high voltage side connected to the gate drive stage 102 of the high power switch 103, which represents one power device in the half bridge to drive each of the phases of the inverter system.

[0068] The secondary winding of flyback transformer 107 provides a positive output voltage (VCC) for positive output voltage rail 105, and also provides a negative output voltage (VEE) for negative output voltage rail 106. Flyback converter 101 also includes a positive rail capacitor (CVCC) 119, a negative rail capacitor (CVEE) 120, and a diode 121. Positive rail capacitor (CVCC) 119 and diode 121 are connected in series between a first end of the secondary winding of flyback transformer 107 and a reference terminal (HV_GND). Negative rail capacitor (CVEE) 120 is connected in series between a second end of the secondary winding of flyback transformer 107 and a reference terminal (HV_GND).

[0069] As will be discussed in detail below, Figure 1In the example of FIG, the flyback converter 101 includes an LDO (low dropout) voltage regulator 108 associated with the positive output voltage rail 105. The LDO voltage regulator 108 provides a positive output voltage as a regulated version of the positive voltage (VCC) at the secondary winding of the flyback transformer 107. This regulated version of the positive output voltage is Figure 1 is marked as VCCREG. Figure 1 In the example of FIG. 1 , the flyback converter 101 includes a shunt regulator 109 associated with the negative output voltage rail 106. The shunt regulator 109 is configured to provide a negative output voltage as a regulated version of the negative voltage (VEE) at the secondary winding of the flyback transformer 107. This regulated version of the negative output voltage is Figure 1 Marked as VEEREG.

[0070] The gate driver stage 102 is connected between the positive output rail 105 and the negative output rail 106. It provides a high power switch control signal for controlling the state of the high power switch 103 based on the PWM control signal 104. In this example, the high power switch is a FET having a gate terminal for controlling the conductivity of a conductive channel between the source terminal and the drain terminal of the FET. Therefore, the gate driver stage 102 provides a gate control signal to the high power switch 103. Figure 1 In the example, the gate control signal has a voltage based on the positive output voltage (VCCREG) on the positive output voltage rail 105 or the negative output voltage (VEREG) on the negative output voltage rail 106, depending on whether the high power switch 103 is open or closed.

[0071] The flyback converter 101 further includes a controller. Figure 1 In the embodiment of the present invention, the functionality of the controller to be described herein may be performed by the primary side controller 111 and / or the secondary side controller 112. The primary side controller 111 and the secondary side controller 112 communicate with each other via a galvanically isolated communication layer 113, as shown in FIG. Figure 1 It will be appreciated that the galvanic isolation communication layer 113 may be implemented in any of several known ways, for example, using a transformer, such as Figure 1 As shown; using an optocoupler; or using any other suitable components. We will first describe the secondary side controller 112 as performing most of the functionality of the controller. However, as indicated, some or all of the functionality can be performed by the primary side controller 111.

[0072] The secondary-side controller 112 receives the PWM control signal 104, which, as discussed above, is used to control the high-power switch 103. In this example, the PWM control signal 104 is provided by a microprocessor associated with the primary side of the flyback converter 101. The PWM control signal 104 is transmitted to the secondary-side controller 112 via a galvanically isolated communication layer 113.

[0073] The secondary side controller 112 also receives a feedback voltage signal 114 that represents a measured voltage of the positive output rail 105 or the negative output rail 106. In this example, the feedback voltage signal 114 is the positive output voltage (VCC) at the secondary winding of the flyback transformer 107. In other examples, which will be briefly discussed below, the feedback voltage signal 114 can be a negative output voltage (VEE) at the secondary winding of the flyback transformer 107. In still other examples, the feedback voltage signal 114 can be a shunt-regulated version of the negative voltage (VEE) at the secondary winding of the flyback transformer 107. Figure 1 or a shunt regulated version of the positive voltage (VCC) at the secondary winding of the flyback transformer 107, which is shown as VEEREG; Figure 1 This is because the shunt regulator is a shunt regulator and therefore the input voltage of the regulator is equal to the output voltage of the regulator.

[0074] The primary switch 110 may be controlled according to a burst mode of operation such that its gate is provided with a primary-side switch control signal 116 that includes bursts of pulses to transfer energy from the primary side of the flyback transformer 107 to the secondary side of the flyback transformer 107. Between the bursts of pulses, the state of the primary switch 110 does not change such that no energy is transferred across the flyback transformer 107. Burst modes of operation are known in the art.

[0075] The secondary side controller 112 provides a burst enable signal 115 that is set to a first value when the controller starts a burst and to a different second value when the controller stops a burst. Figure 1 In the example shown, this burst enable signal 115 is transmitted from the secondary-side controller 112 to the primary-side controller 111 across the galvanically isolated communication layer 113. The primary-side controller 111 also receives a flyback clock signal 118, which in this example has a constant frequency and duty cycle. The primary-side controller 111 selectively provides the flyback clock signal 118 as the primary-side switch control signal 116 for the primary switch 110 based on the value of the burst enable signal 115.

[0076] In this example, the primary switch 110 is connected in series with the primary winding of the flyback transformer 107 between the primary side voltage source (VBAT) and the reference terminal (LV_DIE). In this example, the primary side voltage source (VBAT) is a battery. Figure 1 , sense resistor 122 is also connected in series with primary switch 110 so that the sensed current from the primary side of flyback transformer 107 is provided to primary side controller 111. In this manner, primary side controller 111 may also optionally use the sensed primary current when determining primary side switch control signal 116. For example, primary side controller 111 may set the duty cycle of each pulse in a burst based on the sensed primary current.

[0077] Figure 2 Show Figure 1 2. FIG. 2 shows example graphs of the flyback clock signal 218, the burst enable signal 215, and the primary side switch control signal 216. As can be seen, the burst enable signal 215 is applied as a mask to the flyback clock signal 218 to generate the primary side switch control signal 216.

[0078] Return to Figure 1 , as we will now describe in detail, advantageously, Figure 1 The primary side controller 111 and the secondary side controller 112 provide the switching control signal 116 for the primary switch 110 as a burst of pulses so as to:

[0079] • starting a pulse burst in response to an edge of the PWM control signal 104 (which may be a rising or falling edge) and stopping the pulse burst in response to the feedback voltage 114 crossing a threshold; or

[0080] • Starting a burst of pulses in response to the feedback voltage 114 crossing a threshold, and stopping the burst of pulses in response to the feedback voltage 114 crossing a different threshold.

[0081] Using the edge of the PWM control signal 104 to start the burst can improve the performance of the gate driver circuit 100. This is because the primary switch 110 can operate more quickly in response to the edge of the PWM control signal 104, rather than waiting for the effect of the edge to be reflected in the feedback voltage signal 114. That is, the primary side controller 111 (on the low voltage side of the flyback converter 101) can anticipate the load pulse by monitoring the PWM control signal 104 provided by the microprocessor, so that it can anticipate the flyback activation directly in the LV domain (at the primary side controller 111). Figure 1In the example of FIG. 1 , the PWM control signal 104 is provided from the primary side of the flyback converter 101 to the secondary side controller 112, and the secondary side controller 112 then provides the burst enable signal 115 to the primary side controller 111. In an alternative example, the primary side controller 111 may directly process the PWM control signal (e.g., Figure 1 In this manner, the control scheme for flyback converter 101 can take advantage of the fact that the primary loading of the output occurs on the rising and falling PWM edges. Thus, control of primary switch 110 can utilize both feedback from PWM control signal 104 and available PWM information.

[0082] The first of the above points is described below, wherein a pulse burst may be initiated in response to an edge of the PWM control signal 104. Then, the second point is described, wherein a pulse burst may be stopped in response to the feedback voltage signal 114 crossing a threshold or shunt_dig signal 134.

[0083] Figure 3 Show Figure 1 The following signal curves in the gate driver circuit:

[0084] PWM control signal 304;

[0085] A positive voltage (VCC) 323 at the secondary winding of the flyback transformer; and

[0086] • Negative voltage (VEE) 324 at the secondary winding of the flyback transformer.

[0087] Figure 3 The curve of φ(V) shows how the rising edge of the PWM control signal 304 indicates a pulse load on the positive voltage at the secondary winding of the flyback transformer (VCC) 323, which results in the discharge of the positive rail capacitor (CVCC). Figure 3 The curve also shows how the falling edge of the PWM control signal 304 indicates a pulsed load on the negative voltage at the secondary winding of the flyback transformer (VEE) 324, which results in the discharge of the negative rail capacitor (CVEE). Due to the charge required to drive the gate of the large power device according to the PWM signal, the load on the secondary side of the flyback transformer in the HV domain has a predominantly load step behavior. This is particularly true when the power device is used for a rotating electric machine, in one example, a traction inverter with a small DC component (gate driver die quiescent current).

[0088] exist Figure 1In the embodiment of FIG. 1 , as indicated above, the positive output voltage (VCC) of the secondary winding is post-regulated by the LDO voltage regulator 108 to VCCREG to power the boost stage of the gate driver stage 102. The shunt VEE regulator 109 effectively ensures that VEEREG does not go more negative than its regulation point. The falling edge of the PWM control signal 104 causes some charge loss on the negative rail capacitor (CVEE) 120, causing the VEE level to become too positive relative to its regulation point. (This is in the Figure 4 . ) Therefore, in Figure 1 In the example shown in FIG. 1 , the falling edge of the PWM control signal 104 is used to trigger the primary-side burst.

[0089] Figure 4 Show Figure 1 Another curve of the signal in the gate driver circuit. Figure 4 In the simulation, the edge of the PWM control signal is not used to start the burst. In fact, hysteresis control is performed by comparing the feedback voltage with the upper and lower thresholds.

[0090] for Figure 4 , VEE = -5V, VCCREG = 14V, and Cload = 100nF. Where Cload is the capacitance of the load (i.e., the external power device being driven). CVEE can be appropriately selected (e.g., CVEE = 20uF) to meet the 2% ripple performance target after one PWM falling edge.

[0091] Figure 4 The curve in shows:

[0092] VCC 423, together with: a curve 427 showing an upper band of hysteretic control of VCC (VCC_UB); and a curve 428 showing a lower band of hysteretic control of VCC (VCC_LB);

[0093] VEE 424, along with: curve 425 showing a set point for VEE of -5V; and curve 426 showing a 2% ripple performance target;

[0094] PWM control signal 404; and

[0095] • Burst enable signal 415 .

[0096] Although the bill of materials (BOM) is appropriately selected, Figure 4The simulation results show that the ripple in VEE 424 exceeds the 2% performance target 426. This is because the frequency of the burst enable signal 115 is lower than the frequency of the PWM control signal when using standard hysteretic control. This can depend on the value of the positive rail capacitor (CVCC) and the hysteresis selection (vhyst). In this example, the allowed values ​​within the range are: CVCC = 20uF; and vhyst = + / - 600mV.

[0097] We can also observe an error on VEE 424 on the OV side (i.e., VEE 424 is more negative than the set point 425). This performance, related to the amplitude being more negative than the set point, depends on the gain and bandwidth of the error amplifier driving the shunt MOS gate in the shunt regulator 109, and the ratio between the peak current on the secondary winding of the flyback transformer 107 and the selected value of the negative rail capacitor (CVEE).

[0098] Figure 5a Show that it can be Figure 1 Representation of the three different state machines implemented by the secondary-side controller.

[0099] In the detailed description Figure 5a Before, we will return to Figure 1 To introduce Figure 5a The signal shown. Figure 1 The flyback converter 101 includes a hysteretic control block 133 , which includes the secondary-side controller 112 described above.

[0100] The hysteresis control block 133 also includes a feedback voltage divider block. The feedback voltage divider block in this example includes a resistor voltage divider and a comparator (not shown). As will be understood from the following description, the resistor voltage divider can provide a divided voltage version of the feedback signal received by the feedback voltage divider block, and the comparator can provide an output signal indicating whether the feedback signal has crossed a threshold. Depending on whether the threshold is an upper threshold or a lower threshold, a threshold crossing can occur when the feedback voltage becomes less than or greater than the threshold.

[0101] exist Figure 1 , the feedback divider block receives the positive output voltage (VCC) at the secondary winding of the flyback transformer 107 as feedback voltage signal 114. The feedback divider block also receives a regulated version of the negative output voltage (VEEREG). In addition, the feedback divider block receives a 1Vref signal, which is an on-chip reference signal used to define the hysteresis band.

[0102] exist Figure 1 In the example shown in FIG. 1 , the feedback divider block provides the following four output signals to the secondary-side controller 112 :

[0103] VCC_UB, which indicates whether the positive output voltage (VCC) received at the secondary winding of the flyback transformer 107, referenced to ground, is greater than an upper band (UB) threshold. In this example, VCC_UB has a value of 1 when VCC is greater than the UB threshold;

[0104] VCC_LB, which indicates whether the positive output voltage (VCC) received at the secondary winding of the flyback transformer 107, referenced to ground, is less than a lower band (LB) threshold. In this example, VCC_LB has a value of 1 when VCC is less than the LB threshold;

[0105] VCC_VEE_UB, which indicates whether the positive output voltage (VCC) received at the secondary winding of the flyback transformer 107 is greater than an upper band (UB) threshold with reference to the negative voltage (VEE) at the secondary winding of the flyback transformer 107. In this example, VCC_VEE_UB has a value of 1 when VCC - VEE is greater than the UB threshold; and

[0106] VCC_VEE_LB, which indicates whether the positive output voltage (VCC) received at the secondary winding of the flyback transformer 107 is less than a lower band (LB) threshold with reference to the negative voltage (VEE) at the secondary winding of the flyback transformer 107. In this example, VCC_VEE_UB has a value of 1 when VCC - VEE is less than the LB threshold.

[0107] It will be appreciated that the UB thresholds are higher than their corresponding LB thresholds such that hysteresis control is applied.

[0108] The secondary-side controller 112 also receives a shunt_dig signal 134 from the shunt regulator 109. The shunt_dig signal 134 indicates whether the shunt regulator 109 is active and, therefore, may also be referred to as a shunt activity signal. In this example, the shunt_dig signal 134 has a value of 1 when the shunt regulator 109 is active and a value of 0 when the shunt regulator 109 is not active. It should be understood that the shunt regulator 109 is active when the negative voltage (VEE) at the secondary winding of the flyback transformer 107 is too low (i.e., VEE is less than its set point).

[0109] The output signal from the feedback divider block and the shunt_dig signal 134 are given by Figure 5a It will be understood from the following description that in other examples, different feedback voltage signals may be used, so that correspondingly different thresholds may be applied, and thus different output signals may be provided.

[0110] Now return to Figure 5a , Figure 5aThe left portion of represents a state machine 530 that does not use the edge of the PWM control signal to start or stop a pulse burst. In fact, only hysteresis control is applied. In the present disclosure, this may be referred to as not using adaptive control. As shown, when VCC_LB=1 or VCC_VEE_LB=1, a burst is started by setting the burst enable signal to 1. That is, when the positive output voltage rail or the differential voltage (i.e., the voltage between the positive output rail and the negative output voltage rail) becomes too low. For this state machine 530, when VCC_UB=1 or VCC_VEE_UB=1, a burst is stopped by setting the burst enable signal to 0. That is, when the positive output voltage rail or the differential voltage (i.e., the voltage between the positive output rail and the negative output voltage rail) becomes too high.

[0111] Figure 5b Show when applied Figure 5a The leftmost state machine 530 is a curve of VCC with reference to VCC_UB and VCC_LB.

[0112] Return to Figure 5a , Figure 5a The right side portion of represents a state machine 531 that can use the edge of the PWM control signal to start a pulse burst. In the present disclosure, this may be referred to as using adaptive control. As shown, when VCC_LB=1 or "PWM off", a burst is started by setting the burst enable signal to 1. That is, when the voltage on the positive output voltage rail becomes too low or when a falling edge of the PWM control signal occurs. For this state machine 531, when VCC_UB=1, a burst is stopped by setting the burst enable signal to 0. That is, when the voltage on the positive output voltage rail becomes too high. In this way, the state machine 531 can use the PWM control signal instead of using any feedback voltage representing VEE (as used by the leftmost state machine 530 in Figure 5). In this example, VCC can still be regulated by the associated hysteresis band. That is, if VCC drops below VCC_LB before a falling edge in the PWM control signal occurs. Recall that by Figure 1 The post-regulation of VCC performed by the LDO voltage regulator will provide an accurate VCCREG to the gate driver stage.

[0113] In this way, the feedback voltage represents the measured voltage of the positive output rail (VCC); and the controller:

[0114] A burst is started in response to any of the following:

[0115] i) the falling edge of the PWM control signal, or

[0116] ii) The feedback voltage (VCC) is less than the lower threshold (VCC_LB), and

[0117] The burst is stopped in response to the feedback voltage (VCC) exceeding an upper threshold (VCC_UB).

[0118] Figure 5c Show when applied Figure 5a The rightmost state machine 531 refers to the VCC curve of VCC_UB and VCC_LB.

[0119] Return to Figure 5a , Figure 5a The middle portion of the diagram represents a state machine 532, which can use the edge of the PWM control signal to start a pulse burst and can also use the shunt_dig signal to stop the pulse. This is another embodiment of adaptive control. As shown, when VCC_LB = 1 or "PWM off", a burst is started by setting the burst enable signal to 1. That is, when the voltage on the positive output voltage rail becomes too low or when the falling edge of the PWM control signal occurs. For this state machine 532, when VCC_UB = 1 or shunt_dig = 1, a burst is stopped by setting the burst enable signal to 0. That is, when the voltage on the positive output voltage rail becomes too high or when the shunt regulator becomes active, this indicates that the value of VEE is too low. In this way, the state machine 532 can also use the state of the shunt regulator to end a burst.

[0120] Figure 5d Show when applied Figure 5a The intermediate state machine 532 refers to the VCC curve of VCC_UB and VCC_LB. Figure 5c By comparing the curves of , it can be seen that the advantage of the intermediate state machine 532 is that VCC has a time average value in the middle of the hysteresis loop. Figure 5d It can be seen that the ripple in VCC is between VCC_UB and VCC_LB.

[0121] As indicated at various points above, in other examples, the secondary-side controller can use alternative feedback signals. In one such example, the feedback voltage represents the measured voltage of the negative output rail (VEE). The controller (either the primary-side controller or the secondary-side controller, or a combination of both) can then:

[0122] ■ A burst is started in response to any of the following:

[0123] i) The rising edge of the PWM control signal, or

[0124] ii) The feedback voltage (VEE) is greater than the upper threshold (VEE_UB). That is, when the feedback voltage (VEE) is not negative enough; and

[0125] ■ Stop the burst in response to the feedback voltage (VEE) falling below the lower threshold (VEE_LB). That is, when the feedback voltage (VEE) becomes too negative.

[0126] In addition, in this example, Figure 1 The shunt regulator can be connected to VCC instead of VEE (such as Figure 1 In this case, the shunt regulator can provide a shunt_dig signal used by the controller so that it can stop the burst in response to either:

[0127] The feedback voltage (VEE) is greater than the upper threshold; or

[0128] The shunt_dig signal has a value indicating that the shunt regulator is active.

[0129] Figure 6 Show Figure 1 The signal curve of the gate driver circuit is similar to Figure 4 This is a similar curve to the one in Figure 1, but this time with adaptive control. That is, the edges of the PWM control signal are used to start or stop the burst.

[0130] Figure 6 The curve in shows:

[0131] VCC 623, together with: a curve 627 showing an upper band of hysteretic control of VCC (VCC_UB); and a curve 628 showing a lower band of hysteretic control of VCC (VCC_LB);

[0132] VEE 624, along with: a curve showing a set point for VEE of -5V; and a curve 626 showing a 2% ripple performance target;

[0133] PWM control signal 604; and

[0134] ●Burst enable signal 615 .

[0135] Figure 6 shows that adaptive control results in deactivation and ripple resolution after each PWM falling edge (i.e., Figure 4 In contrast, there is a burst of pulses in response to each falling edge in the PWM control signal 604 . Thus, the use of adaptive control causes the VEE 644 to not exceed the 2% allowed error amplitude 626 .

[0136] Figure 7 Show for example Figure 1 An example embodiment of (at least a portion of) a galvanically isolated communication layer 713a is shown. The galvanically isolated communication layer 713a is connected to the secondary side controller ( Figure 7(not shown) receives input signaling 740 and sends a signal to the primary side controller ( Figure 7 ) provides output signaling 741. Figure 7 The lower part of shows example curves of input / output signaling 740 , 741 transmitted by the galvanically isolated communication layer 713 a .

[0137] In this example, the secondary-side controller determines the burst enable signal. In the same manner as discussed above, the burst enable signal is a binary signal having a value of 0 when a burst of pulses should be provided as the primary-side switch control signal. The burst enable signal has a value of 1 when a burst of pulses should not be provided as the primary-side switch control signal. The advantages associated with this choice of polarity are safety-related, but it should be understood that the polarity of the burst enable signal can be reversed.

[0138] The secondary side controller sends the determined burst enable signal to the primary side controller via the galvanic isolation communication layer 713a so that it is time-multiplexed with other data. This other data is in Figure 7 742 in the lower portion of the flyback converter. The other data 742 may represent measurements associated with the secondary side of the flyback converter, such as a measured temperature. In this example, the burst enable signal 743 is time-division multiplexed with the other data 742 by setting the idle state of the input / output signaling 740, 741 through the galvanically isolated communication layer 713a to either: a high value 744 indicating an instruction to the primary-side controller that a burst of pulses should not be provided to the primary switch; or a low value 744 indicating an instruction to the primary-side controller that a burst of pulses should be provided to the primary switch.

[0139] In this way, existing digital isolated communication channels (such as Figure 7 The galvanically isolated communication layer 713a) shown can be used to send data back to the primary / low voltage (LV) side, but now has primary burst commands encoded into it by setting its idle state. When the idle state is low, the LV side will begin burst control of the primary switch. When the idle state is high, the LV side will stop burst control of the primary switch. Advantageously, this example provides feedback from the isolated output voltage to the low voltage side by multiplexing the existing isolated data channel with commands to drive or not drive the LV side primary switch.

[0140] for Figure 7 In the example signals 740 and 741 shown in FIG, periodic narrow pulses are present between "other data" 742. These narrow pulses can be referred to as "heartbeats"; that is, signals that the secondary-side controller 112 sends to the primary-side controller to inform it that the secondary-side controller 112 is "active." This heartbeat signal can also be referred to as "other data" multiplexed with the burst enable signal.

[0141] It will be appreciated that in other examples, the burst enable signal may be communicated from the secondary side to the primary side using a dedicated channel for the burst enable command.

[0142] In another alternative embodiment, as indicated above and as Figure 1 As shown in FIG. 1 with reference numeral 104a, the LV side controller can process the PWM control signal on the LV side to start a burst in response to seeing a PWM edge during an ongoing data transfer. Advantageously, this can avoid the need for reference numeral 104b. Figure 7 Describes the delay associated with time-division multiplexing.

[0143] Return to Figure 1 Advantageously, the flyback transformer 107 comprises a single secondary winding. This is in contrast to a flyback transformer comprising a split secondary winding / coil. This split secondary winding does not allow any changes in the VCC to VEE ratio during operation and is therefore less efficient than a conventional flyback transformer. Figure 1 The flyback converter 101 is flexible. In addition, the use of a split secondary winding would require an additional rectifier diode in the BOM.

[0144] Advantageously, a flyback hysteresis control has been implemented (an example of which is shown in Figure 1 ) can have an internal VEE shunt regulator that allows maximum flexibility in regulated voltage setting and BOM selection. It can also handle a wide range of BOM combinations while still achieving acceptable percentage ripple performance on the VEE REG output voltage. This may be due to Figure 7 The application of adaptive control is illustrated in the middle and rightmost state machines in Figure 1. This can offer significant advantages in terms of PCB BOM, as one or more of the following may not be required: additional BOM components for flyback compensation, split-coil solutions for VEE regulation, or an auxiliary winding for providing feedback. As described, the state machine can exploit advance knowledge of the upcoming load on the flyback output by monitoring the PWM control signal on the LV side and applying burst control to the primary even before the output voltage crosses the hysteresis band.

[0145] Figure 1 The components can be summarized as follows:

[0146] On the low voltage (LV) microprocessor side:

[0147] Primary side of the flyback transformer

[0148] External low-side transistor to drive the primary

[0149] Shunt resistor for sensing primary current

[0150] On the high voltage (HV) inverter side:

[0151] Secondary side of the flyback transformer

[0152] Diodes and capacitors used to split the rails to isolate the output voltage.

[0153] Integrated in the gate driver unit (on the LV side):

[0154] Driver stage for external low-side transistor

[0155] Gate Control Digital Logic

[0156] Current Sense Amplifier

[0157] LV side control logic

[0158] Current communication receiver

[0159] Integrated in the gate driver unit (on the HV side):

[0160] Resistor ladder for sensing VCC to GND and setting hysteresis

[0161] Synchronous Finite State Machine

[0162] Comparators to sense the resistor ladder and create UB and LB signals

[0163] VEEREG shunt regulator for creating split-rail supplies

[0164] Current communication transmitter

[0165] VCCREG LDO (post-regulates the positive rail on the isolated side)

[0166] It should be appreciated that the examples disclosed herein may also be implemented in several different configurations, such as one or more of the following: closing the loop on the negative output (VEE); implementing a shunt on VCC; an LDO on VEE; Figure 1 A variation of the regulator shown; operating on the PWM rising edge instead of the falling edge. As another alternative, other conditions can be used to stop the burst request, such as when the count of flyback bursts reaches a predetermined value.

[0167] Unless a particular order is explicitly stated, the instructions and / or flowchart steps in the above figures may be executed in any order. Furthermore, those skilled in the art will recognize that although one example instruction set / method has been discussed, the materials in this specification may be combined in various ways to produce other examples, and should be understood within the context provided in this detailed description.

[0168] In some example embodiments, the instruction sets / method steps described above are implemented as functions and software instructions embodied as executable instruction sets that are implemented on a computer or a machine programmed and controlled with the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor can refer to a single component or a plurality of components.

[0169] In other examples, the instruction sets / methods described herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer readable or computer usable storage media. Such computer readable or computer usable storage media are considered part of an article (or product). An article or product may refer to any manufactured single component or multiple components. As defined herein, non-transitory machine or computer usable media does not include signals, but such media may be capable of receiving and processing information from signals and / or other transient media.

[0170] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via network, computer, or data-based devices and / or services. These may include the cloud, the Internet, an intranet, a mobile device, a desktop computer, a processor, a lookup table, a microcontroller, a consumer device, infrastructure, or other enabling devices and services. As used herein and in the claims, the following non-exclusive definitions are provided.

[0171] In one example, one or more instructions or steps discussed herein are automated. The terms automation or automatic (and similar variations thereof) mean the use of computers and / or mechanical / electrical devices to control the operation of equipment, systems, and / or processes without the need for human intervention, observation, effort, and / or decision-making.

[0172] It should be understood that any components that are said to be coupled can be coupled or connected directly or indirectly. In the case of indirect coupling, additional components may be positioned between the two components that are said to be coupled.

[0173] In this specification, example embodiments have been presented based on a selected set of details. However, one skilled in the art will appreciate that many other example embodiments can be practiced that include different selected sets of these details. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A driver circuit for controlling a high-power switch, characterized in that: The driver circuit comprises: A flyback converter comprising: Primary switch; a positive output rail configured to provide a positive output voltage; a negative output rail configured to provide a negative output voltage; and A controller configured to: receiving a PWM control signal, wherein the PWM control signal is used to control the high-power switch; receiving a feedback voltage signal representing a measured voltage of the positive output rail or the negative output rail; and providing a primary-side switch control signal comprising a burst of pulses for operating the primary switch, wherein the controller is configured to start the burst of pulses in response to an edge of the PWM control signal and to stop the burst of pulses in response to a feedback voltage crossing a threshold; A driver stage is connected between the positive output rail and the negative output rail, wherein a driver circuit is configured to provide a high power switch control signal for controlling a state of the high power switch based on the PWM control signal.

2. The driver circuit according to claim 1, wherein: The feedback voltage represents a measured voltage of the positive output rail; and The controller is configured to: The burst is initiated in response to either: i) the falling edge of the PWM control signal, or ii) the feedback voltage is less than a lower threshold, and The burst is stopped in response to the feedback voltage exceeding an upper threshold.

3. The driver circuit according to claim 2, wherein: The flyback converter comprises: a flyback transformer having a primary winding and a secondary winding; and A shunt regulator is configured to provide the negative output voltage as a regulated version of a negative voltage at the secondary winding of the flyback transformer.

4. The driver circuit according to claim 3, wherein: The flyback converter further comprises: An LDO voltage regulator is configured to provide the positive output voltage as a regulated version of the positive voltage at the secondary winding of the flyback transformer.

5. The driver circuit according to claim 3 or claim 4, characterized in that: The controller is further configured to: receiving a shunt active signal indicating whether the shunt regulator is active; and The burst is stopped in response to any of the following: The feedback voltage exceeds the upper threshold; or The shunt active signal has a value indicating that the shunt regulator is active.

6. The driver circuit according to claim 1, wherein: The feedback voltage represents a measured voltage of the negative output rail; and The controller is configured to: The burst is initiated in response to either: i) the rising edge of the PWM control signal, or ii) the feedback voltage is greater than an upper threshold; and The burst is stopped in response to the feedback voltage falling below a lower threshold.

7. Driver circuit according to any of the preceding claims, characterized in that The controller is configured to: receiving a flyback clock signal; providing a burst enable signal, the burst enable signal being: set to a first value when the controller starts a burst; and being set to a second value when the controller stops a burst; as well as The flyback clock signal is selectively provided as the primary side switch control signal for the primary switch based on the value of the burst enable signal.

8. The driver circuit according to claim 7, wherein: The flyback converter has a primary side and a secondary side; The controller includes a primary side controller on the primary side of the flyback converter; The controller includes a secondary side controller on the secondary side of the flyback converter; and The driver circuit additionally includes a galvanically isolated communication layer configured to transmit signaling from the secondary side controller to the primary side controller.

9. The driver circuit according to claim 8, wherein: The secondary-side controller is configured to: determining the burst enable signal; and The determined burst enable signal is sent to the primary side controller via the galvanically isolated communication layer.

10. The driver circuit according to claim 9, wherein: The secondary-side controller is configured to: The determined burst enable signal is sent to the primary side controller via the galvanically isolated communication layer such that the determined burst enable signal is time division multiplexed with other data.

Images