Flexible circuit substrate and chip-on-film packaging structure

Abstract

A flexible circuit substrate comprises a flexible base material, a plurality of pins and a plurality of test pad groups. The flexible substrate comprises a chip setting area, a circuit area and a test pad area, and the circuit area is located between the chip setting area and the test pad area. The pins are arranged on the flexible substrate. The test pad groups are arranged in the test pad area and are repeatedly arranged along the first direction. Each test pad group includes a plurality of test pads arranged in a plurality of rows along a second direction. The second direction is perpendicular to the first direction. The test pads of the two opposite outermost test pad groups in the test pad area respectively comprise an alignment test pad, and the area of each alignment test pad is larger than the area of any one of the test pads of the adjacent test pad group. In addition, a chip-on-film package structure is also provided. The flexible circuit substrate and the thin film flip chip packaging structure can provide alignment reference during testing under space limitation.

Description

Technical Field

[0001] The present invention relates to a substrate and a packaging structure, and in particular to a flexible circuit substrate and a chip-on-film packaging structure having the flexible circuit substrate. Background Art

[0002] To facilitate post-package testing, chip-on-film (CFP) packaging structures feature multiple test pads outside the packaging area of ​​the flexible circuit substrate for contact with multiple probes from a test probe card. These test pads correspond to densely distributed pins and are arranged continuously across the width of the FFP. Since the width of the FFP is typically specified, to accommodate numerous test pads within the limited space, these pads are typically arranged in multiple rows perpendicular to the width. These pads, arranged in groups of several rows, are repeated across the width. During testing, the multiple probes of the test probe card must precisely contact these densely distributed test pads. However, these repeated test pad groups lack the ability to identify each other, preventing alignment. Therefore, alignment patterns are typically placed adjacent to these pads to facilitate probe card alignment. As the functional requirements of CFP packaging continue to increase, the number of pins and corresponding test pads has also increased. This has left insufficient space on the FFP substrate for additional alignment patterns, making alignment between the test probe card and the CFP difficult. Summary of the Invention

[0003] The present invention provides a flexible circuit substrate and a chip-on-film packaging structure, which can provide an alignment reference during testing under space limitations.

[0004] According to an embodiment of the present invention, a flexible circuit substrate includes a flexible substrate, a plurality of pins and a plurality of test pad groups. The flexible substrate includes a chip setting area, a circuit area and a test pad area, and the circuit area is located between the chip setting area and the test pad area. The pins are arranged on the flexible substrate and extend from the chip setting area through the circuit area to the test pad area. The test pad groups are arranged in the test pad area and are repeatedly arranged along a first direction. Each test pad group includes a plurality of test pads arranged in multiple rows along a second direction. The second direction is perpendicular to the first direction. The test pads of the two outermost test pad groups in the test pad area respectively include a pair of test pads, and the area of ​​each pair of test pads is larger than the area of ​​any of the test pads of the adjacent test pad groups.

[0005] In the flexible circuit substrate according to an embodiment of the present invention, the length of each alignment test pad in the second direction corresponds to the plurality of test pads in multiple rows of adjacent test pad groups.

[0006] In the flexible circuit substrate according to an embodiment of the present invention, each of the alignment test pads has a hollow pattern.

[0007] In the flexible circuit substrate according to an embodiment of the present invention, the hollow patterns of the alignment test pads of the two outermost test pad groups are mirror-symmetrical with respect to a center line of the test pad groups.

[0008] In the flexible circuit substrate according to an embodiment of the present invention, each of the alignment test pads has a central portion, and the hollow pattern is offset from the central portion.

[0009] In the flexible circuit substrate according to an embodiment of the present invention, an area of ​​the central portion of each alignment test pad is not less than an area of ​​a smallest one of the plurality of test pads in the adjacent test pad group.

[0010] In the flexible circuit substrate according to an embodiment of the present invention, the hollow pattern of each alignment test pad surrounds the central portion.

[0011] In the flexible circuit substrate according to an embodiment of the present invention, the hollow pattern of each alignment test pad includes two blocks, which are respectively located on two opposite sides of the central portion.

[0012] In the flexible circuit substrate according to an embodiment of the present invention, the hollow pattern of each alignment test pad includes a plurality of blocks located at at least two corners of the alignment test pad.

[0013] According to an embodiment of the present invention, a chip-on-film package structure includes the aforementioned flexible circuit substrate, a chip, and an encapsulant. The chip is disposed within the chip mounting area of ​​the flexible circuit substrate and is electrically connected to the pins. The encapsulant is filled at least between the chip and the flexible circuit substrate.

[0014] Based on the above, in the flexible circuit substrate of the thin film chip package structure of the present invention, the test pads of the two outermost test pad groups in multiple test pad groups arranged repeatedly in the same pattern are enlarged in size (i.e., area) to serve as alignment test pads, thereby distinguishing them from the test pads in other test pad groups. Due to the size difference, the testing machine can easily identify and grasp the position of the alignment test pad from the numerous test pads and perform alignment using the alignment test pad. Therefore, the flexible circuit substrate does not need to be provided with an additional alignment pattern, which can save space and increase the flexibility of the test pad layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic top view of a chip-on-film package structure according to an embodiment of the present invention;

[0016] Figure 2 yes Figure 1 A partial enlarged view of the test pad area of ​​the Chip-on-Thin Film package structure;

[0017] Figure 3 is a partial enlarged view of a test pad area of ​​a chip-on-film package structure according to an embodiment of the present invention;

[0018] Figure 4 is a partial enlarged view of a test pad area of ​​a chip-on-film package structure according to an embodiment of the present invention;

[0019] Figure 5 FIG. 1 is a partial enlarged view of a test pad area of ​​a chip-on-film package structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0021] Figure 1 FIG. 1 is a top view of a chip-on-film package structure according to an embodiment of the present invention, where dots are filled in to schematically illustrate the arrangement range of the pins 220 of the flexible circuit substrate 200 . Figure 2 yes Figure 1 A partial enlarged view of the test pad area of ​​the film chip package structure. It should be noted that Figure 1 The Chip-on-Film Package structure is shown in the reel-to-reel tape transfer operation stage, and only one Chip-on-Film Package structure is shown schematically. Please also refer to Figure 1 and Figure 2 The chip-on-film package structure 100 includes a flexible circuit substrate 200, a chip 110, and an encapsulant 120. The flexible circuit substrate 200 includes a flexible substrate 210, a plurality of pins 220, and a plurality of test pad groups 230. The flexible substrate 210 includes a chip placement area 212, a circuit area 214, and a test pad area 216. The circuit area 214 is located between the chip placement area 212 and the test pad area 216. The chip 110 is disposed within the chip placement area 212 of the flexible circuit substrate 200 and is electrically connected to the pins 220. The encapsulant 120 is at least filled between the chip 110 and the flexible circuit substrate 200. In addition, the chip-on-film package structure 100 also includes a solder mask 130. The solder mask 130 is located in the circuit area 214 and partially covers the pins 220 to protect the pins 220. The chip placement area 212 is defined by an opening in the solder mask 130.

[0022] These pins 220 are disposed on the flexible substrate 210 and extend from the chip placement area 212 through the circuit area 214 to the test pad area 216. These test pad groups 230 are disposed in the test pad area 216 and are repeatedly arranged along the first direction X. Each test pad group 230 includes a plurality of test pads 231 arranged in multiple rows along the second direction Y. The second direction Y is perpendicular to the first direction X. The film chip package structure 100 is tested through these test pads 231 to confirm whether the film chip package structure 100 is operating normally. Please refer to Figure 2 The flexible circuit substrate 200 of this embodiment schematically illustrates that the test pads 231 of each test pad group 230 are arranged in seven rows (R1-R7). However, the present invention is not limited to the test pad layout pattern of the test pad groups. Specifically, the test pad groups 230 of this embodiment have a test pad layout pattern of seven rows of test pads 231 extending in the same direction (left or right). These test pad groups 230 are repeatedly arranged along the first direction X using the same test pad layout pattern. Furthermore, in this embodiment, the test pad groups 230 may be arranged in mirror symmetry with respect to the centerline L of the test pad groups 230. That is, with respect to the centerline L, the test pads 231 in the left test pad group 230 extend leftward, while the test pads 231 in the right test pad group 230 extend rightward. However, the present invention is not limited to this.

[0023] like Figure 2 As shown, the two outermost test pad groups 230a and 230b in the test pad area 216 (ie, Figure 1 The test pads 231 of the leftmost test pad group 230a and the rightmost test pad group 230b in the test pad area 216 above the PCB include alignment test pads 231a and 231b, respectively. The alignment test pads 231a and 231b have an area greater than that of any of the test pads 231 in the adjacent test pad group 230. In this embodiment, the two alignment test pads 231a and 231b have the same structure, but are not limited thereto.

[0024] The length D of the alignment test pads 231a and 231b in the second direction Y corresponds to the test pads 231 in multiple rows of adjacent test pad groups 230. In this embodiment, the length D of the alignment test pads 231a and 231b corresponds to, for example, the test pads 231 in rows R5, R6, and R7 of the adjacent test pad groups 230, but is not limited thereto. The length D of the alignment test pads 231a and 231b may be greater than or equal to 0.3 mm, and the width W of the alignment test pads 231a and 231b may be greater than or equal to 0.3 mm. Specifically, in this embodiment, the length D of the alignment test pads 231a and 231b is 0.37 mm, and the width W is 0.3 mm, but is not limited thereto. In an embodiment not shown, the length D of the alignment test pads 231a and 231b may be 0.5 mm, and the width W may be 0.5 mm.

[0025] In this embodiment, the alignment test pads 231a and 231b of the two outermost test pad groups 230a and 230b are enlarged in size (i.e., area) to distinguish them from the test pads 231 of the other test pad groups 230. When a test machine (e.g., a probe card) is used to test the chip-on-film package structure 100, the size difference between the alignment test pads 231a and 231b allows the test machine to easily identify and grasp the alignment test pads 231a and 231b from among the numerous test pads 231. The alignment test pads 231a and 231b are then used for alignment, ensuring that the test machine's multiple probes accurately contact the test pads 231 and the alignment test pads 231a and 231b. Thus, the chip-on-film package structure 100 (flexible circuit substrate 200) can be directly aligned with the test machine through the alignment test pads 231a, 231b of the outermost test pad groups 230a, 230b, without the need to set up additional alignment patterns, thereby saving space and increasing the flexibility of the test pad layout of the chip-on-film package structure 100 (flexible circuit substrate 200).

[0026] Figure 3 This is a partial enlarged view of the test pad area of ​​the thin film chip package structure according to an embodiment of the present invention. Figure 2 and Figure 3The chip-on-film package structure 100a (flexible circuit substrate 200a) of this embodiment is similar to the aforementioned embodiment, with the difference being that the two alignment test pads 231c and 231d of this embodiment each have a hollow pattern 233a. The alignment test pads 231c and 231d each have a central portion 235, and the hollow pattern 233a is offset from the central portion 235. In addition, the area of ​​the central portion 235 of the alignment test pads 231c and 231d is not less than the area of ​​the smallest of the test pads 231 in the adjacent test pad group 230. For example, the area of ​​the central portion 235 of the alignment test pads 231c and 231d of this embodiment is larger than the area of ​​the smallest test pad 231', but is not limited thereto. By displacing the hollow pattern 233a away from the central portion 235 and ensuring that the central portion 235 has a sufficient contact area, the probes of the test machine can be prevented from accidentally contacting the hollow pattern 233a, ensuring that the probes actually contact the alignment test pads 231c and 231d, thereby maintaining test accuracy.

[0027] The shape of the hollow pattern 233a is, for example, a rectangle, but is not limited thereto. The hollow patterns 233a of the two aligned test pads 231c and 231d have the same shape, but are not limited thereto. In an embodiment not shown, the shape of the hollow pattern 233a can be circular, triangular, polygonal, T-shaped, inverted T-shaped, etc., and the shapes of the two hollow patterns 233a can be different, and the present invention is not limited thereto. The hollow patterns 233a of the aligned test pads 231c and 231d of the two outermost test pad groups 230c and 230d are mirror-symmetrical with respect to the center line L of the test pad groups 230, but are not limited thereto. In an embodiment not shown, the hollow pattern 233a can be set at any position offset from the central portion 235.

[0028] The hollow pattern 233a is formed, for example, by shielding part of the hollow pattern 233a when forming the alignment test pads 231c and 231d, so as to form the hollow pattern 233a at the same time when forming the alignment test pads 231c and 231d, but is not limited to this. The surface 211 of the flexible substrate 210 can be exposed from the hollow pattern 233a. The hollow pattern 233a can increase the recognition of the alignment test pads 231c and 231d. The test machine can identify the alignment test pads 231c and 231d by means of the hollow pattern 233a, and can also perform alignment by the position of the hollow pattern 233a. The thin film flip chip packaging structure 100a (flexible circuit substrate 200a) of this embodiment has the same effect as the aforementioned embodiment, and will not be repeated here.

[0029] Figure 4 This is a partial enlarged view of the test pad area of ​​the thin film chip package structure according to an embodiment of the present invention. Figure 3 and Figure 4The chip-on-film package structure 100b (flexible circuit substrate 200b) of this embodiment is similar to the previous embodiment. The difference between the two is that the alignment test pads 231e and 231f of this embodiment have a hollow pattern 233b surrounding the central portion 235. The shape of the hollow pattern 233b can be, for example, a square ring. The chip-on-film package structure 100b (flexible circuit substrate 200b) of this embodiment has the same functions as the previous embodiment and will not be further described here.

[0030] Figure 5 This is a partial enlarged view of the test pad area of ​​the thin film chip package structure according to an embodiment of the present invention. Figure 4 and Figure 5 The film-on-chip packaging structure 100c of this embodiment is similar to the aforementioned embodiment, and the difference between the two is that the shapes of the hollow patterns 233c and 233d of the two alignment test pads 231g and 231h of this embodiment may be inconsistent. The hollow pattern 233c of the alignment test pad 231g may include two blocks, respectively located on opposite sides of the central part 235. The shape of the two blocks of the hollow pattern 233c may be rectangular. The hollow pattern 233d of the alignment test pad 231h may include multiple blocks, located at at least two corners of the alignment test pad 231h. In this embodiment, it is schematically shown that the hollow pattern 233d includes four blocks, respectively located at the four corners of the alignment test pad 231h, and the shape of the four blocks is square, but it is not limited to this. The film-on-chip packaging structure 100c (flexible circuit substrate 200c) of this embodiment has the same function as the aforementioned embodiment, and will not be repeated here.

[0031] In summary, in the flexible circuit substrate of the thin film chip package structure of the present invention, the test pads of the two outermost test pad groups in a plurality of test pad groups repeatedly arranged in the same pattern are enlarged in size (i.e., area) to serve as alignment test pads, thereby distinguishing them from the test pads in other test pad groups. Due to the size difference, the testing machine can easily identify and grasp the position of the alignment test pad from the numerous test pads and perform alignment using the alignment test pads. Therefore, the flexible circuit substrate does not need to be provided with additional alignment patterns, which can save space and increase the flexibility of the test pad layout.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flexible circuit substrate, characterized in that: include: A flexible substrate comprising a chip setting area, a circuit area, and a test pad area, wherein the circuit area is located between the chip setting area and the test pad area; A plurality of pins are disposed on the flexible substrate and extend from the chip placement area through the circuit area to the test pad area; as well as a plurality of test pad groups disposed in the test pad area and repeatedly arranged along a first direction, each of the test pad groups including a plurality of test pads arranged in a plurality of rows along a second direction, wherein the second direction is perpendicular to the first direction; The test pads of the two outermost test pad groups in the test pad area respectively include an alignment test pad, and an area of ​​each alignment test pad is larger than an area of ​​any of the test pads of the adjacent test pad group.

2. The flexible circuit substrate according to claim 1, wherein: The length of each alignment test pad in the second direction corresponds to the plurality of test pads in multiple rows of adjacent test pad groups.

3. The flexible circuit substrate according to claim 1, wherein: Each alignment test pad has a hollow pattern.

4. The flexible circuit substrate according to claim 3, wherein: The plurality of hollow patterns of the plurality of alignment test pads of the two outermost test pad groups are mirror-symmetrical with respect to a center line of the plurality of test pad groups.

5. The flexible circuit substrate according to claim 3, wherein: Each alignment test pad has a central portion, and the hollow pattern deviates from the central portion.

6. The flexible circuit substrate according to claim 5, wherein: An area of ​​the central portion of each alignment test pad is not smaller than an area of ​​a smallest one of the plurality of test pads in the adjacent test pad group.

7. The flexible circuit substrate according to claim 5, wherein: The hollow pattern of each alignment test pad surrounds the central portion.

8. The flexible circuit substrate according to claim 5, wherein: The hollow pattern of each alignment test pad includes two blocks, which are respectively located on two opposite sides of the central portion.

9. The flexible circuit substrate according to claim 5, wherein: The hollow pattern of each alignment test pad includes a plurality of blocks located at at least two corners of the alignment test pad.

10. A chip-on-film packaging structure, characterized in that: include: The flexible circuit substrate according to any one of claims 1 to 9; a chip, disposed in the chip placement area of ​​the flexible circuit substrate and electrically connected to the plurality of pins; as well as The packaging colloid is at least filled between the chip and the flexible circuit substrate.

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