MOS transistor and manufacturing method thereof

Abstract

This method for manufacturing a MOS transistor is provided with: a step for etching the surface of a SiC substrate by means of hydrogen gas in a state in which the SiC substrate is heated to a temperature of 1200 DEG C or higher; a step for forming an amorphous silicon layer on the surface of the SiC substrate after the etching using hydrogen gas has been performed; a step for forming a gate insulating film comprising silicon oxide on the surface of the amorphous silicon layer by chemical vapor deposition; and a step for performing a nitrogen termination process on the SiC substrate after the gate insulating film has been formed.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a MOS transistor and a method for manufacturing the same. Background Art

[0002] In the method for manufacturing a MOS (metal oxide semiconductor) transistor disclosed in Patent Document 1, a substrate composed of SiC (i.e., silicon carbide) is etched using hydrogen (i.e., H2) in a silicon-excess atmosphere. This cleans the surface of the SiC substrate while forming a thin film of silicon crystals (i.e., Si) on the surface of the SiC substrate. Next, a silicon oxide film (i.e., SiO2) is formed as a gate insulating film on the surface of the silicon thin film formed on the surface of the SiC substrate. At this time, the oxidation of the silicon thin film can suppress the oxidation of the surface of the SiC substrate. Thus, by suppressing the oxidation of the surface of the SiC substrate, the interface energy level density at the interface between the silicon oxide film and the SiC substrate can be reduced. By reducing the interface energy level density at the interface between the silicon oxide film and the SiC substrate, the path mobility is increased and the path resistance is reduced. Therefore, the on-state resistance of the MOS transistor can be reduced. After the silicon oxide film is formed, a nitrogen termination treatment is performed. The nitrogen termination treatment can further reduce the interface energy level density at the interface between the silicon oxide film and the SiC substrate.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-192397 Summary of the Invention

[0006] This specification proposes a technique for manufacturing a MOS transistor having low on-resistance by a method different from that of Patent Document 1.

[0007] The method for manufacturing a MOS transistor disclosed in this specification includes: a step of etching the surface of a SiC substrate using hydrogen gas while the SiC substrate is heated to a temperature of 1200°C or higher; a step of forming an amorphous silicon layer on the surface of the SiC substrate after the etching using hydrogen gas; a step of forming a gate insulating film composed of silicon oxide on the surface of the amorphous silicon layer by chemical vapor deposition; and a step of performing a nitrogen termination treatment on the SiC substrate after the gate insulating film is formed.

[0008] In this manufacturing method, the surface of the SiC substrate is cleaned by etching with hydrogen. Then, an amorphous silicon layer is formed on the surface of the SiC substrate. Next, a gate insulating film composed of silicon oxide is formed on the surface of the amorphous silicon layer by chemical vapor deposition (hereinafter sometimes referred to as CVD). When the gate insulating film is formed, the amorphous silicon layer is oxidized to become silicon oxide. Thus, the oxidation of the surface of the SiC substrate can be suppressed. Then, by nitrogen termination treatment, the SiC crystal is terminated by nitrogen at the interface between the gate insulating film and the SiC substrate. According to this manufacturing method, since the oxidation of the SiC substrate can be suppressed when the gate insulating film is formed, the interface energy level density at the interface between the gate insulating film and the SiC substrate can be reduced. Therefore, according to this manufacturing method, the path resistance can be reduced, and a MOS transistor with low on-state resistance can be manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a cross-sectional view of a MOS transistor.

[0010] Figure 2 It is an explanatory diagram of the manufacturing method of an Example.

[0011] Figure 3 It is an explanatory diagram of the manufacturing method of an Example.

[0012] Figure 4 This is the electron diffraction image of the amorphous layer.

[0013] Figure 5 This is a photograph of the shoulder of the gate structure formed by the manufacturing method of the embodiment (high-temperature hydrogen etching for 15 minutes).

[0014] Figure 6 This is a photograph of the shoulder of the gate structure formed by the manufacturing method of the embodiment (high-temperature hydrogen etching for 30 minutes).

[0015] Figure 7 This is a photograph of the shoulder of the gate structure formed by the manufacturing method of the comparative example.

[0016] Figure 8 yes Figures 5-7 Evaluation results of the withstand voltage of the gate insulating film. DETAILED DESCRIPTION

[0017] In one example of the manufacturing method disclosed in this specification (hereinafter referred to as the manufacturing method of a specific example), a channel may be provided on the main surface of the SiC substrate. In the step of etching the surface of the SiC substrate, the side surfaces of the channel may be etched using hydrogen gas. In the step of forming the amorphous silicon layer, the amorphous silicon layer may be formed on the side surfaces of the channel. In the step of forming the gate insulating film, the gate insulating film may be formed on the surface of the amorphous silicon layer covering the side surfaces of the channel.

[0018] According to the manufacturing method of the above-mentioned specific example, as described below, a trench-gate MOS transistor with low on-state resistance can be suitably manufactured. In the hydrogen etching process of Patent Document 1 (i.e., the process of hydrogen etching the SiC substrate in a silicon excess atmosphere), a silicon thin film cannot be suitably formed on the side of the channel. Therefore, in the trench-gate MOS transistor, the interface energy level density at the interface between the gate insulating film and the SiC substrate (i.e., the side of the channel) cannot be reduced. That is, in the technology of Patent Document 1, it is difficult to reduce the path resistance in the trench-gate MOS transistor, and it is difficult to manufacture a trench-gate MOS transistor with low on-state resistance. Correspondingly, in the manufacturing method of the above-mentioned specific example, the side of the channel is cleaned by etching with hydrogen. Then, an amorphous silicon layer is formed on the side of the channel. The amorphous silicon layer can be suitably formed on the side of the channel. Next, a gate insulating film composed of silicon oxide is formed on the surface of the amorphous silicon layer by chemical vapor deposition (hereinafter sometimes referred to as CVD). When forming the gate insulating film, the amorphous silicon layer is oxidized to form silicon oxide. This can suppress oxidation of the side surfaces of the channel. Then, a nitrogen termination treatment is performed to terminate the SiC crystals with nitrogen at the interface between the gate insulating film and the SiC substrate. Thus, according to the manufacturing method of this specific example, oxidation of the side surfaces of the channel can be suppressed when forming the gate insulating film, thereby reducing the interface energy level density at the interface between the gate insulating film and the SiC substrate. Therefore, according to this manufacturing method, the path resistance can be reduced, and a trench-gate MOS transistor with low on-state resistance can be manufactured.

[0019] In one example of the manufacturing method disclosed in this specification, during the etching using hydrogen gas, the side surfaces of the channel and the main surface of the SiC substrate may be etched. During the step of forming the amorphous silicon layer, the amorphous silicon layer may be formed on the side surfaces of the channel and the main surface of the SiC substrate. During the step of forming the gate insulating film, the gate insulating film may be formed on the surface of the amorphous silicon layer covering the side surfaces of the channel and the main surface of the SiC substrate.

[0020] In one example of the manufacturing method disclosed in this specification, the amorphous silicon layer may be formed by chemical vapor deposition.

[0021] According to this configuration, an amorphous silicon layer can be suitably formed.

[0022] In one example of the manufacturing method disclosed in this specification, the amorphous silicon layer may be formed in a nitrogen atmosphere by chemical vapor deposition while the SiC substrate is heated to a temperature of 400° C. to 550° C. inclusive.

[0023] According to this configuration, an amorphous silicon layer can be suitably formed.

[0024] In one example of the manufacturing method disclosed in this specification, the amorphous silicon layer may be formed by chemical vapor deposition in a state where the SiC substrate is disposed under a pressure of 0.3 Torr to 1.0 Torr.

[0025] According to this configuration, an amorphous silicon layer can be suitably formed.

[0026] In the manufacturing method of one example disclosed in this specification, the thickness of the amorphous silicon layer on the side surface of the channel may be 6 nm or less.

[0027] If the amorphous silicon layer is too thick, a portion of the amorphous silicon layer may remain in an unoxidized state. In contrast, if the thickness of the amorphous silicon layer is 6 nm or less, the amorphous silicon layer can be prevented from remaining unoxidized.

[0028] In one example of the manufacturing method disclosed in this specification, the main surface of the SiC substrate may be a surface of an epitaxial layer.

[0029] In one example of the manufacturing method disclosed in this specification, in the nitrogen termination treatment, the SiC substrate may be heated to a temperature of 1200° C. or higher in a nitrogen gas or a nitrogen oxide gas.

[0030] In a manufacturing method of one example disclosed in this specification, after forming the gate insulating film, in a cross section along the main surface of the SiC substrate in a direction perpendicular to the channel and in the thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the channel may be connected by an arc having a minimum curvature radius of 53 nm or more.

[0031] According to this configuration, current leakage in the boundary portion between the main surface of the SiC substrate and the side surface of the channel can be suppressed.

[0032] In a manufacturing method of an example disclosed in this specification, after forming the gate insulating film, in a cross section along the main surface of the SiC substrate in a direction orthogonal to the channel and in the thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the channel may be connected by an elliptical arc or a circular arc having a flattening ratio of less than 0.29.

[0033] According to this configuration, current leakage in the boundary portion between the main surface of the SiC substrate and the side surface of the channel can be suppressed.

[0034] A MOS transistor according to an example disclosed in this specification may include a SiC substrate having a channel provided on a primary surface, a gate insulating film covering side surfaces of the channel, and a gate electrode provided within the channel. In a cross section taken along a direction perpendicular to the channel on the primary surface and along the thickness direction of the SiC substrate, the primary surface of the SiC substrate and the side surfaces of the channel may be connected by an arc having a minimum radius of curvature of 53 nm or greater.

[0035] According to this configuration, current leakage in the boundary portion between the main surface of the SiC substrate and the side surface of the channel can be suppressed.

[0036] A MOS transistor according to an example disclosed in this specification may include a SiC substrate having a channel formed on a primary surface, a gate insulating film covering side surfaces of the channel, and a gate electrode disposed within the channel. In a cross section taken along a direction perpendicular to the channel on the primary surface and along the thickness direction of the SiC substrate, the primary surface of the SiC substrate and the side surfaces of the channel may be connected by an elliptical arc or circular arc having an oblateness of 0.29 or less.

[0037] According to this configuration, current leakage in the boundary portion between the main surface of the SiC substrate and the side surface of the channel can be suppressed.

[0038] Figure 1MOS transistor 10 manufactured by the manufacturing method of an embodiment is shown. MOS transistor 10 includes a SiC substrate 12, a gate insulating film 14, a gate electrode 16, an interlayer insulating film 18, a source electrode 20, and a drain electrode 22. SiC substrate 12 has an upper surface 12a and a lower surface 12b as main surfaces. Multiple channels 24 are provided on upper surface 12a of SiC substrate 12. Each channel 24 extends linearly and parallel to each other on upper surface 12a. Gate insulating film 14 covers the inner surface of each channel 24 (i.e., the side surfaces 24a and bottom surfaces 24b of channel 24). Gate electrode 16 is disposed within each channel 24. Gate electrode 16 is insulated from SiC substrate 12 by gate insulating film 14. Interlayer insulating film 18 covers the upper surface of gate electrode 16. Source electrode 20 covers the upper surface 12a of SiC substrate 12 and the upper surface of interlayer insulating film 18. The source electrode 20 is insulated from the gate electrode 16 by the interlayer insulating film 18 . The drain electrode 22 covers the lower surface 12 b of the SiC substrate 12 .

[0039] SiC substrate 12 includes a source region 30, a contact region 32, a body region 34, a drift region 36, and a drain region 38. Source region 30 is an n-type region with a high n-type impurity concentration. Source region 30 contacts source electrode 20 and gate insulating film 14. Contact region 32 is a p-type region with a high p-type impurity concentration. Contact region 32 contacts source electrode 20. Body region 34 is a p-type region with a lower p-type impurity concentration than contact region 32. Body region 34 contacts source region 30 and contact region 32 from below. Body region 34 contacts gate insulating film 14 below source region 30. Drift region 36 is an n-type region with a lower n-type impurity concentration than source region 30. Drift region 36 contacts body region 34 from below. Drift region 36 contacts gate insulating film 14 below body region 34. The drain region 38 is an n-type region having a higher n-type impurity concentration than the drift region 36. The drain region 38 is in contact with the drift region 36 from below. The drain region 38 is in contact with the drain electrode 22.

[0040] When a potential above the threshold is applied to the gate electrode 16, a path is formed along the gate insulating film 14 (i.e., the side surface 24a of the channel 24) in the body region 34. The path connects the source region 30 and the drift region 36. When a potential higher than that of the source electrode 20 is applied to the drain electrode 22 while the path is formed, electrons flow from the source region 30 to the drain region 38 via the path and the drift region 36.

[0041] Next, a method for manufacturing the MOS transistor 10 will be described as an embodiment. The manufacturing method of the embodiment enables the manufacture of a MOS transistor 10 with low on-resistance. Furthermore, the manufacturing method of the embodiment is characterized by a method for forming a trench gate structure. Therefore, the p-type and n-type regions within the SiC substrate 12 are omitted from the figures illustrating the manufacturing method.

[0042] like Figure 2 As shown in (a), a SiC substrate 12 is prepared before the channel is formed. The SiC layer exposed on the upper surface 12a is an epitaxial layer (i.e., a SiC layer formed by epitaxial growth). Figure 2 Although not shown, a source region 30 , a contact region 32 , a body region 34 , a drift region 36 , and a drain region 38 are provided in the SiC substrate 12 .

[0043] First, if Figure 2 As shown in FIG. 5( b ), the upper surface 12 a of the SiC substrate 12 is selectively etched to form a trench 24 on the upper surface 12 a .

[0044] The surface of the SiC substrate 12 contains a high density of carbon defects with C-C bonds. These defects form interface states and trap electrons. If these defects are present at a high density at the interface between the side surfaces 24 a of the channel 24 and the gate insulating film 14, electrons trapped in these interface states, for example, will cause Coulomb scattering. This reduces the path mobility and increases the path resistance. In contrast, as described below, the manufacturing method of the embodiment allows the formation of a gate structure with a low density of interface states on the side surfaces 24 a of the channel 24.

[0045] In such Figure 2 (b) After forming the trench 24, Figure 3 High-temperature hydrogen etching shown in (a). In high-temperature hydrogen etching, the SiC substrate 12 is heated to a temperature of 1200°C or higher (e.g., 1300°C) in hydrogen (H2) gas. The surface of the SiC substrate 12 (i.e., the upper surface 12a and the inner surface of the trench 24) is then etched by hydrogen gas. Here, a very thin layer near the surface of the SiC substrate 12 is etched. As a result, carbon defects can be removed from the surface of the SiC substrate 12. In other words, high-temperature hydrogen etching can reduce the carbon defect density in the surface of the SiC substrate 12.

[0046] Next, implement Figure 3 (b) shows the amorphous silicon layer forming step. Here, a reduced pressure CVD device is used to form a silicon layer on the surface of the SiC substrate 12 in a nitrogen atmosphere. Here, SiH4 gas and N2 gas are used as gases. In addition, here, the film forming temperature can be controlled to a temperature of not less than 400°C and not more than 550°C, and the film forming pressure can be controlled to a pressure of not less than 0.3 Torr and not more than 1.0 Torr. If CVD is performed under low temperature and low pressure conditions in this way, the silicon layer grows at a low speed. As a result, an amorphous silicon layer 42 can be formed with a relatively uniform thickness on the upper surface 12a of the SiC substrate 12 and the inner surface of the channel 24. Figure 4FIG. 4 shows an electron beam diffraction image of the amorphous silicon layer 42 formed on the side surface of the trench 24 by this method. Figure 4 As shown, a broad halo pattern was observed, and it was confirmed that the silicon layer formed on the side surface of the trench 24 was amorphous.

[0047] Furthermore, by performing CVD under such conditions, the surface roughness of the amorphous silicon layer 42 can be reduced. Furthermore, for example, the flow rate of SiH4 gas can be controlled to 250 sccm, and the flow rate of N2 gas can be controlled to 230 sccm. Here, by adjusting the film formation time, the amorphous silicon layer 42 is formed so that the thickness of the amorphous silicon layer 42 on the side surface 24a is 6 nm or less.

[0048] Next, implement Figure 3 (c) Gate insulating film forming step: Here, a silicon oxide layer 44 is formed on the surface of the amorphous silicon layer 42 using a reduced pressure CVD apparatus. That is, the silicon oxide layer 44 is formed above the upper surface 12a and within the channel 24.

[0049] Next, a nitrogen termination treatment is performed. In the nitrogen termination treatment, the SiC substrate 12 is heated to a temperature of 1200°C or higher (e.g., 1250°C) in nitrogen gas (i.e., N2 gas) or nitrogen oxide gas (e.g., NO gas, N2O gas, NO2 gas, etc.). This causes the SiC crystal to be nitrogen terminated.

[0050] In the conventional manufacturing method, the surface of the SiC substrate is sometimes oxidized during the gate insulating film forming process. In addition, in the conventional manufacturing method, the surface of the SiC substrate is sometimes oxidized during the nitrogen termination process. For example, when nitrogen oxide gas is used in the nitrogen termination process, the surface of the SiC substrate is sometimes oxidized by the oxygen atoms in the nitrogen oxide gas. In addition, even when nitrogen gas is used in the nitrogen termination process, the surface of the SiC substrate is sometimes oxidized by a trace amount of oxidizing gas mixed into the container. If the surface of the SiC substrate is oxidized during the gate insulating film forming process and the nitrogen termination process, carbon defects are generated on the surface of the SiC substrate. In contrast, in the present embodiment, Figure 3In the gate insulating film forming process and nitrogen termination treatment process shown in (c), the amorphous silicon layer 42 is oxidized instead of the SiC substrate 12. The silicon oxide layer 42a formed by the oxidation of the amorphous silicon layer 42 is integrated with the silicon oxide layer 44 formed by CVD. Thus, the gate insulating film 14 can be formed. In addition, by replacing the SiC substrate 12 and oxidizing the amorphous silicon layer 42, the oxidation of the surface of the SiC substrate 12 can be suppressed. Therefore, carbon defects are not easily generated in the surface of the SiC substrate 12 (that is, the interface between the SiC substrate 12 and the gate insulating film 14). Therefore, the interface energy level density in the surface of the SiC substrate 12 can be reduced. Based on this effect and the effect of nitrogen-terminating the SiC crystal by the nitrogen termination treatment, the interface energy level density in the interface between the SiC substrate 12 and the gate insulating film 14 can be greatly reduced. In particular, in this embodiment, since the amorphous silicon layer 42 can be formed on the side surface 24 a of the trench 24 , the interface state density can be significantly reduced at the side surface 24 a (ie, the interface between the SiC substrate 12 and the gate insulating film 14 ).

[0051] Then, if Figure 3 As shown in (d), the gate electrode 16 is formed in the trench 24. Furthermore, the interlayer insulating film 18 is formed on the gate electrode 16. Thus, the trench gate structure is completed.

[0052] Then, if Figure 1 As shown in FIG. 1 , the gate insulating film 14 on the upper surface 12a is selectively removed to form a contact hole 20a. Next, the source electrode 20 is formed so as to cover the upper surface 12a of the SiC substrate 12. Then, the drain electrode 22 is formed so as to cover the lower surface 12b of the SiC substrate 12. Through the above steps, the Figure 1 MOS transistor 10 is shown.

[0053] According to the manufacturing method of the embodiment, the carbon defects present in the side 24a of the channel 24 can be removed by high-temperature hydrogen etching. In addition, according to the manufacturing method of the embodiment, since the amorphous silicon layer 42 is oxidized in the gate insulating film formation process and the nitrogen termination treatment process, the oxidation of the SiC substrate 12 can be suppressed, and the generation of carbon defects in the side 24a of the channel 24 can be suppressed. In addition, according to the manufacturing method of the embodiment, the interface energy level density in the interface between the SiC substrate 12 and the gate insulating film 14 can be reduced by nitrogen termination treatment. Therefore, a MOS transistor 10 with a low interface energy level density in the side 24a (i.e., the interface between the main region 34 and the gate insulating film 14) can be manufactured. Therefore, according to this manufacturing method, the path resistance of the MOS transistor 10 can be reduced. In other words, according to this manufacturing method, a MOS transistor 10 with low on-state resistance can be manufactured.

[0054] The characteristics of the MOS transistor 10 manufactured by the manufacturing method of the embodiment (hereinafter referred to as the embodiment prototype) and the MOS transistor manufactured by the conventional manufacturing method (hereinafter referred to as the conventional product) were evaluated, and the results confirmed that: in the embodiment prototype, the path mobility can be improved compared with the conventional product. In addition, in the conventional product, the lower the temperature, the lower the path mobility, but in the embodiment prototype, the lower the temperature, the higher the path mobility. It is believed that this is because: in the embodiment prototype, the interface energy level density is reduced, and the influence of Coulomb scattering at low temperature is reduced. In addition, in the embodiment prototype, the effect of reducing the on-state resistance of the element is found compared with the conventional product. It is believed that this is because: in the embodiment prototype, the path resistance is reduced by increasing the mobility of the path. In addition, in the embodiment prototype, it is found that the same withstand voltage as the conventional product can be obtained.

[0055] Figures 5-7 A cross section along the direction perpendicular to the direction in which the trench 24 extends in the upper surface 12 a and the thickness direction of the SiC substrate 12 is shown. Figure 5 、 6 An enlarged photograph of the boundary portion (hereinafter referred to as the shoulder portion) between the side surface 24a and the upper surface 12a when the gate insulating film 14 is formed by the manufacturing method of the embodiment is shown. Figure 5 The shape of the shoulder portion is shown when high-temperature hydrogen etching is performed for 15 minutes without performing the sacrificial oxide film forming step and the sacrificial oxide film removing step. Figure 5 This corresponds to the MOS transistor 10 manufactured by the manufacturing method of the embodiment (hereinafter referred to as the embodiment prototype). Figure 6 The shape of the shoulder portion is shown when high-temperature hydrogen etching is performed for 30 minutes without performing the sacrificial oxide film forming step and the sacrificial oxide film removing step. Figure 7 An enlarged photograph of the shoulder portion of the gate insulating film 14 when formed by the manufacturing method of the comparative example is shown. Figure 7 The shape of the shoulder portion is shown when a sacrificial oxide film forming step and a sacrificial oxide film removing step are performed and argon etching is performed instead of high-temperature hydrogen etching.

[0056] In the argon etching, the etching rates are greatly different between the upper surface 12a and the side surface 24a, and the etching rate of the upper surface 12a is higher than the etching rate of the side surface 24a. Figure 7 As shown, an inclined portion 100 is formed on the shoulder portion, which gradually shifts downward as it approaches the channel. In addition, in a portion 102 between the inclined portion 100 and the side surface 24a, the surface of the SiC substrate 12 is curved with a small curvature radius. In other words, Figure 7 In FIG. 1 , the radius of curvature of the shoulder is the smallest in portion 102, and its value is 47 nm. In addition, Figure 7The dashed line 200 shown represents the shoulder portion connecting the upper surface 12a and the side surface 24a as an elliptical arc. The flattening ratio of the ellipse forming the elliptical arc 200 is 0.40. Furthermore, the flattening ratio f is expressed as f = 1 - b / a, where the major radius of the ellipse is a and the minor radius is b. During argon etching, the etching rate for the upper surface 12a is higher than the etching rate for the side surface 24a, thus increasing the flattening ratio of the elliptical arc 200.

[0057] On the other hand, in high temperature hydrogen etching, the upper surface 12a and the side surface 24a can be etched more uniformly than in argon etching. Figure 5 、 6 As shown, no portion with a locally small curvature radius is formed in the shoulder portion between the upper surface 12a and the side surface 24a ( Figure 7 Therefore, in the high temperature hydrogen etching, the minimum value of the curvature radius in the shoulder increases. For example, Figure 5 The minimum value of the curvature radius of the middle shoulder is 53nm. Figure 6 The minimum value of the curvature radius of the middle shoulder is 71nm. Figure 5 、 6 The dashed lines 202, 204 of FIG. 1 illustrate the shoulder connecting the upper surface 12a and the side surface 24a as an elliptical arc. Figure 5 The flattening rate of the middle elliptical arc 202 is 0.29. Figure 6 The flattening rate of the middle elliptical arc 204 is 0.25. That is, Figure 5 、 6 In the case of an elliptical arc, the flattening rate is less than Figure 7 That is to say, Figure 5 、 6 In, with Figure 7 In comparison, the elliptical arc is closer to a perfect circle. In high-temperature hydrogen etching, the upper surface 12a and the side surface 24a can be etched more uniformly than in argon etching, so the flatness of the elliptical arcs 202 and 204 can be reduced.

[0058] Figure 8 The evaluation results of the breakdown voltage of the gate insulating film 14 at the position of the shoulder are shown. Figure 8 The horizontal axis represents the voltage applied to the gate insulating film 14, Figure 8 The vertical axis represents the leakage current flowing in the gate insulating film 14 . Figure 8 In the figure, curves G5, G6, and G7 represent Figure 5 、 6 、7 MOS transistor results. Figure 8 As shown in FIG, curves G5 and G6 have a higher withstand voltage than curve G7. Figure 8It can be seen that when the minimum curvature radius of the shoulder is greater than 53nm and the flattening rate of the shoulder's elliptical arc is less than 0.29, the withstand voltage remains stable at a high value. In this way, high-temperature hydrogen etching can form the shoulder in a smoother curved shape, further improving the withstand voltage.

[0059] Furthermore, in the above embodiments, a method for manufacturing a trench-type MOS transistor is described. However, the technology disclosed in this specification can also be used to manufacture a MOS transistor having a planar gate structure. In this case, the technology disclosed in this specification can be used to form a gate insulating film so as to cover the main surface (e.g., the upper surface) of the SiC substrate.

[0060] The specific examples of the present invention have been described in detail above, but these examples are merely illustrative and do not limit the scope of the patent claims. The technology described in the scope of the patent claims includes various modifications and changes to the specific examples illustrated above. In addition, the technical elements described in this specification or the drawings can exert the usefulness of the technology alone or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or the drawings is a technology that achieves multiple purposes at the same time. As long as one of the purposes is achieved, it itself has technical usefulness.

Claims

1. A manufacturing method for a MOS transistor, comprising the following steps: A step of etching the surface of the SiC substrate with hydrogen gas while heating the SiC substrate to a temperature of 1200° C. or higher; After performing the etching using hydrogen gas, forming an amorphous silicon layer on the surface of the SiC substrate; forming a gate insulating film made of silicon oxide on the surface of the amorphous silicon layer by chemical vapor deposition; and After forming the gate insulating film, a step of performing nitrogen termination treatment on the SiC substrate is performed.

2. The manufacturing method according to claim 1, wherein A trench is pre-set on the main surface of the SiC substrate. In the step of etching the surface of the SiC substrate, the side surfaces of the trench are etched by hydrogen gas. In the step of forming the amorphous silicon layer, the amorphous silicon layer is formed on the side surface of the channel. In the step of forming the gate insulating film, the gate insulating film is formed on the surface of the amorphous silicon layer covering the side surface of the channel.

3. The manufacturing method according to claim 2, wherein: In the etching using hydrogen gas, the side surfaces of the trench and the main surface of the SiC substrate are etched. In the step of forming the amorphous silicon layer, the amorphous silicon layer is formed on the side surfaces of the trench and the main surface of the SiC substrate. In the step of forming the gate insulating film, the gate insulating film is formed on the surface of the amorphous silicon layer in a region covering the side surfaces of the channel and the main surface of the SiC substrate.

4. The production method according to any one of claims 1 to 3, wherein The amorphous silicon layer is formed by a chemical vapor deposition method.

5. The manufacturing method according to claim 4, wherein: The amorphous silicon layer is formed in a nitrogen atmosphere by chemical vapor deposition while the SiC substrate is heated to a temperature of 400° C. or higher and 550° C. or lower.

6. The manufacturing method according to claim 4, wherein: The amorphous silicon layer is formed by chemical vapor deposition in a state where the SiC substrate is disposed under a pressure of 0.3 Torr to 1.0 Torr.

7. The production method according to any one of claims 1 to 3, wherein The thickness of the amorphous silicon layer is less than 6 nm.

8. The production method according to any one of claims 1 to 3, wherein The main surface of the SiC substrate is a surface of an epitaxial layer.

9. The production method according to any one of claims 1 to 3, wherein In the nitrogen termination process, the SiC substrate is heated to a temperature of 1200° C. or higher in nitrogen or nitrogen oxide gas.

10. The manufacturing method according to claim 2 or 3, wherein: After forming the gate insulating film, in a cross section along the main surface of the SiC substrate in a direction perpendicular to the channel and along the thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the channel are connected by an arc with a minimum curvature radius of 53 nm or more.

11. The manufacturing method according to claim 2 or 3, wherein: After forming the gate insulating film, in a cross section along the direction orthogonal to the channel in the main surface of the SiC substrate and the thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the channel are connected by an elliptical arc or a circular arc with a flattening ratio of less than 0.

29.

12. A MOS transistor, which is a trench-gate MOS transistor, having: SiC substrate with a trench on its main surface, a gate insulating film covering the side surfaces of the channel, and a gate electrode disposed in the channel; In a cross section along a direction perpendicular to the trench in the main surface and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench are connected by an arc having a minimum curvature radius of 53 nm or more.

13. A MOS transistor, which is a trench-gate MOS transistor, having: SiC substrate with a trench on its main surface, a gate insulating film covering the side surfaces of the channel, and a gate electrode disposed in the channel; In a cross section along a direction perpendicular to the trench in the main surface and a thickness direction of the SiC substrate, the main surface of the SiC substrate and the side surface of the trench are connected by an elliptical arc or a circular arc having an oblateness of 0.29 or less.

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