Power device and manufacturing method thereof

Abstract

The invention discloses a power device and a manufacturing method thereof. The power device comprises a substrate; the epitaxial layer of the first doping type is located on the substrate; a first distance exists between the bottom of the groove and the second surface of the epitaxial layer, and the groove is located in the middle area of the epitaxial layer; a second distance exists between the bottom of the injection region and the second surface of the epitaxial layer, the injection region is located at the two ends of the epitaxial layer in the first direction, and the injection region and the groove are spaced; the well region of the second doping type, the first source region of the first doping type and the second source region of the first doping type are located in the epitaxial layer at intervals between the injection region and the groove, the first source region is located above the well region, and the second source region is located on the two sides of the groove; the second source region extends into the well region from the interface of the first source region and the well region and is spaced from the injection region. The injection region is a protection structure of the grid, so that the breakdown field strength of the bottom of the groove is reduced, and the short-circuit current capability of the device can be improved by the first source region and the second source region.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power device and a manufacturing method thereof. Background Art

[0002] Semiconductor technology has played a decisive role in the development of the power electronics industry, among which power semiconductor devices have always been considered the key components of power electronics equipment.

[0003] Silicon carbide (SiC), a next-generation semiconductor material, boasts outstanding properties such as a wide bandgap, high breakdown electric field, high saturated electron drift velocity, and high thermal conductivity. It is widely used in high-temperature, high-voltage, high-current, and high-frequency applications. Compared to silicon (Si)-based power devices, SiC power devices can operate at high temperatures, exhibit lower switching losses, and exhibit lower leakage current.

[0004] Silicon carbide MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device structures are broadly classified into two types: planar and trench. Planar devices are affected by the resistivity of the epitaxial layer, making it difficult to minimize forward resistance. Consequently, a relatively low forward resistance device must be achieved by increasing the chip area. Trench devices, on the other hand, can effectively reduce forward resistance and offer greater current handling capabilities. However, due to the structural characteristics of trench SiC MOSFETs, high electric field strength is likely to occur at the bottom of the trench, leading to significant instability during operation. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a power device and a manufacturing method thereof to improve the reliability of the power device.

[0006] According to one aspect of the present application, a power device is provided, comprising at least one cell, each of the cells comprising:

[0007] a substrate, the first direction being parallel to the substrate, and the second direction being perpendicular to the substrate;

[0008] An epitaxial layer of a first doping type, located on the first surface of the substrate;

[0009] A trench, extending from the first surface of the epitaxial layer to the second surface of the epitaxial layer along a second direction, with a first distance between the bottom of the trench and the second surface of the epitaxial layer, and the trench being located in a middle region of the epitaxial layer along the first direction;

[0010] an implantation region of a second doping type, the implantation region extending from the first surface of the epitaxial layer to the second surface of the epitaxial layer along a second direction, the implantation region being spaced a second distance from the second surface of the epitaxial layer, the implantation region being located at both ends of the epitaxial layer along the first direction, and the implantation region being spaced apart from the trench;

[0011] A well region of a second doping type is located in the epitaxial layer in the interval between the implantation region and the trench;

[0012] a first source region of a first doping type, located in the epitaxial layer between the implantation region and the trench, the first source region being located above the well region;

[0013] A second source region of the first doping type is located in the well region in the gap between the injection region and the trench and is located on both sides of the trench. The second source region extends from the junction of the first source region and the well region to the well region, and there is a gap between the second source region and the injection region.

[0014] Optionally, the power device further includes:

[0015] a gate dielectric layer, the gate dielectric layer being located on the sidewalls and bottom of the trench;

[0016] a gate conductor, the gate conductor being located in the trench and separated from the epitaxial layer outside the trench by the gate dielectric layer;

[0017] a shielding region of the second doping type, located at the bottom of the trench and extending toward the second surface of the epitaxial layer, wherein a third distance exists between the bottom of the shielding region and the second surface of the epitaxial layer;

[0018] The second spacing is smaller than the first spacing, and the second spacing is smaller than the third spacing.

[0019] Optionally, the second doping type injection region includes a first injection region and a second injection region, the first injection region is located at the bottom of the injection region, the second injection region is located above the first injection region, and the second injection region extends to a portion of the epitaxial layer under the well region.

[0020] Optionally, the doping concentration of the first source region is greater than the doping concentration of the second source region.

[0021] Optionally, a depth between the bottom of the first source region and the first surface of the epitaxial layer is 0 μm to 0.2 μm.

[0022] Optionally, a depth between the bottom of the second source region and the first surface of the epitaxial layer is 0.1 μm to 0.5 μm.

[0023] Optionally, the doping concentration of the first source region is 1E14 cm -3 ~2E15 cm -3 .

[0024] Optionally, the doping concentration of the second source region is 1E12 cm -3 ~3E13 cm -3 .

[0025] Optionally, the doping concentration of the first implantation region is lower than the doping concentration of the second implantation region.

[0026] Optionally, a depth between the bottom of the first implantation region and the first surface of the epitaxial layer is 2 μm to 3 μm.

[0027] Optionally, the width of the first injection region is 0.5 μm to 1 μm.

[0028] Optionally, the width of the first injection region is the same as the width of the second injection region.

[0029] Optionally, a distance between two side edges of two adjacent implantation regions close to the trench is 1.5 μm to 3 μm.

[0030] Optionally, a depth between the bottom of the trench and the first surface of the epitaxial layer is 0.8 μm to 1.2 μm.

[0031] Optionally, the width of the groove is 0.5 μm to 1.0 μm.

[0032] Optionally, a depth between the bottom of the well region and the first surface of the epitaxial layer is 0.3 μm to 0.8 μm.

[0033] Optionally, it also includes:

[0034] an interlayer dielectric layer, covering surfaces of the gate conductor and the gate dielectric layer, and a portion of a surface of the first source region;

[0035] a source electrode, located on the interlayer dielectric layer and in contact with and electrically connected to the first source region and the injection region;

[0036] a drain electrode, located on the second surface of the substrate and electrically connected to the substrate, the first surface and the second surface of the substrate being opposite to each other; and

[0037] The gate electrode is located on the interlayer dielectric layer and penetrates the interlayer dielectric layer to be electrically connected to the gate conductor.

[0038] Optionally, the power device is a silicon carbide MOSFET device.

[0039] According to another aspect of the present application, a method for manufacturing a power device is provided. The power device includes at least one cell. The method for manufacturing each cell includes:

[0040] Providing a substrate, wherein the first direction is parallel to the substrate and the second direction is perpendicular to the substrate;

[0041] forming an epitaxial layer of a first doping type on a first surface of the substrate;

[0042] forming a trench, wherein the trench extends from the first surface of the epitaxial layer to the second surface of the epitaxial layer along a second direction, a first distance exists between the bottom of the trench and the second surface of the epitaxial layer, and the trench is located in a middle region of the epitaxial layer along the first direction;

[0043] forming an implantation region of a second doping type, wherein the implantation region extends from the first surface of the epitaxial layer to the second surface of the epitaxial layer along a second direction, the implantation region is spaced a second distance from the second surface of the epitaxial layer, the implantation region is located at both ends of the epitaxial layer along the first direction, and the implantation region is spaced from the trench;

[0044] forming a well region of a second doping type in the epitaxial layer in the interval between the implantation region and the trench;

[0045] forming a first source region of a first doping type in the epitaxial layer in the interval between the implantation region and the trench, wherein the first source region is located above the well region;

[0046] A second source region of the first doping type is formed in the epitaxial layer in the gap between the injection region and the trench, the second source region is located on both sides of the trench, the second source region extends from the junction surface of the first source region and the well region to the well region, and there is a gap between the second source region and the injection region.

[0047] Optionally, it also includes:

[0048] forming a gate dielectric layer on the sidewalls and bottom of the trench;

[0049] forming a gate conductor in the trench, wherein the gate conductor is separated from the epitaxial layer outside the trench by the gate dielectric layer;

[0050] forming a shielding region of the second doping type at the bottom of the trench and extending toward the second surface of the epitaxial layer, wherein a third distance exists between the bottom of the shielding region and the second surface of the epitaxial layer;

[0051] The second spacing is smaller than the first spacing, and the second spacing is smaller than the third spacing.

[0052] Optionally, forming the implantation region of the second doping type includes:

[0053] forming a first implantation region at the bottom;

[0054] A second implantation region is formed, where the second implantation region is located on an upper portion of the first implantation region and extends to a portion of the epitaxial layer below the well region.

[0055] Optionally, the doping concentration of the first source region is greater than the doping concentration of the second source region.

[0056] Optionally, a depth between the bottom of the first source region and the first surface of the epitaxial layer is 0 μm to 0.2 μm.

[0057] Optionally, a depth between the bottom of the second source region and the first surface of the epitaxial layer is 0.1 μm to 0.5 μm.

[0058] Optionally, the doping concentration of the first source region is 1E14 cm -3 ~2E15 cm -3 .

[0059] Optionally, the doping concentration of the second source region is 1E12 cm -3 ~3E13 cm -3 .

[0060] Optionally, the doping concentration of the first implantation region is lower than the doping concentration of the second implantation region.

[0061] Optionally, a depth between the bottom of the first implantation region and the first surface of the epitaxial layer is 2 μm to 3 μm.

[0062] Optionally, the width of the first injection region is 0.5 μm to 1 μm.

[0063] Optionally, the width of the first injection region is the same as the width of the second injection region.

[0064] Optionally, a distance between two side edges of two adjacent implantation regions close to the trench is 1.5 μm to 3 μm.

[0065] Optionally, a depth between the bottom of the trench and the first surface of the epitaxial layer is 0.8 μm to 1.2 μm.

[0066] Optionally, the width of the groove is 0.5 μm to 1.0 μm.

[0067] Optionally, a depth between the bottom of the well region and the first surface of the epitaxial layer is 0.3 μm to 0.8 μm.

[0068] Optionally, it also includes:

[0069] forming an interlayer dielectric layer covering surfaces of the gate conductor and the gate dielectric layer and a portion of the surface of the first source region;

[0070] forming a source electrode on the interlayer dielectric layer, wherein the source electrode contacts and is electrically connected to the first source region and the injection region;

[0071] forming a drain electrode located on the second surface of the substrate, the drain electrode being electrically connected to the substrate, the first surface and the second surface of the substrate being opposite to each other; and

[0072] A gate electrode is formed on the interlayer dielectric layer, and the gate electrode penetrates the interlayer dielectric layer and is electrically connected to the gate conductor.

[0073] Optionally, the power device is manufactured using a silicon carbide MOSFET device.

[0074] The power device and its manufacturing method provided herein form an implanted region of the second doping type within the epitaxial layer, with a depth greater than the trench depth, to form a protective structure at the trench bottom, reducing the electric field strength at the trench bottom. Furthermore, in the active region, the present invention comprises a composite source region of the first doping type, formed from a first source region and a second source region, with different junction depths and doping concentrations, to improve the short-circuit current capability of the device.

[0075] Furthermore, the second doping type injection region in the power device provided by the present application includes a first injection region and a second injection region. When the power device is in the reverse high voltage cutoff state, the depletion layer of the P-type composite injection region expands, and the depletion layer of the P-type shielding region at the bottom of the trench forms a protective structure at the bottom of the trench, reducing the electric field strength at the bottom of the trench. The power device provided by the present application not only reduces process complexity and difficulty, but also reduces the breakdown field strength of the electric field at the bottom of the trench in the device when in the reverse high voltage cutoff operating state. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0077] Figure 1 A schematic structural diagram of a cell of a power device according to an embodiment of the present application is shown;

[0078] Figures 2a to 2h Schematic cross-sectional views of a power device at various stages according to an embodiment of the present application are shown. DETAILED DESCRIPTION

[0079] Various embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings. In the various figures, identical elements are denoted by identical or similar reference numerals. For clarity, parts in the figures are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps may be depicted in a single figure.

[0080] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meanings as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this disclosure are only for the purpose of describing specific embodiments and are not intended to limit this disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the relevant listed items.

[0081] The specific implementation methods of the present disclosure are further described in detail below with reference to the accompanying drawings and examples.

[0082] Figure 1 A schematic structural diagram of a cell of a power device according to an embodiment of the present application is shown.

[0083] The power device includes at least one cellular structure.

[0084] like Figure 1 As shown, the area between the two dotted lines is a cell in the power device.

[0085] Each cell includes a substrate 100 , an epitaxial layer 200 , a trench 201 , an implantation region 240 , a well region 280 , a first source region 290 , and a second source region 240 .

[0086] The first direction is parallel to the substrate 100, and the second direction is perpendicular to the substrate 100. The substrate 100 includes a first surface and a second surface opposite to each other.

[0087] The epitaxial layer 200 of the first doping type is located on the first surface of the substrate 100 .

[0088] The trench 201 extends from the first surface of the epitaxial layer 200 to the second surface of the epitaxial layer 200 along the second direction, and a first distance exists between the bottom of the trench 201 and the second surface of the epitaxial layer 200. The trench 201 is located in the middle area of ​​the epitaxial layer 200 along the first direction.

[0089] The second doping type implantation region 230 extends along a second direction from the first surface of the epitaxial layer 200 to the second surface of the epitaxial layer 200, and a second distance exists between the implantation region 230 and the second surface of the epitaxial layer 200. The second doping type implantation region 230 is located at both ends of the epitaxial layer 200 along the first direction, and the implantation region 230 is spaced apart from the trench 201. The second distance is smaller than the first distance.

[0090] A well region 280 of the second doping type is located in the epitaxial layer 200 between the implantation region 230 and the trench 201 .

[0091] The first source region 290 of the first doping type is located in the epitaxial layer 200 between the implantation region 230 and the trench 201 . The first source region 290 is located above the well region 280 .

[0092] The second source region 240 of the first doping type is located in the well region 280 between the injection region 230 and the trench 201 and is located on both sides of the trench 201. The second source region 240 extends from the junction of the first source region 290 and the well region 280 to the well region 280. There is a gap between the second source region 240 and the injection region 230.

[0093] Furthermore, each cell further includes a gate dielectric layer 260 , a gate conductor 270 , and a shielding region 250 .

[0094] The gate dielectric layer 260 is located on the sidewalls and bottom of the trench 201 .

[0095] The gate conductor 270 is located in the trench 201 and is separated from the epitaxial layer 200 outside the trench 201 by the gate dielectric layer 260 .

[0096] The shielding region 250 of the second doping type is located at the bottom of the trench 201 and extends toward the second surface of the epitaxial layer 200 . A third distance exists between the bottom of the shielding region 250 and the second surface of the epitaxial layer 200 .

[0097] Furthermore, the second interval is smaller than the third interval.

[0098] Furthermore, the implantation region 230 includes a first implantation region 210 of the second doping type and a second implantation region 220. The first implantation region 210 is located at the bottom of the implantation region 230, and the second implantation region 220 is located above the first implantation region 210. The second implantation region 220 extends to the portion of the epitaxial layer 200 below the well region 280.

[0099] Exemplarily, the substrate 100 is, for example, of a first doping type. The first doping type is one of an N-doping type and a P-doping type, and the second doping type is the other of the N-doping type and the P-doping type. In this embodiment, the first doping type is, for example, an N-doping type, and the second doping type is, for example, a P-doping type.

[0100] Furthermore, a depth L6 between the bottom of the first source region 290 and the first surface of the epitaxial layer 200 is 0 μm-0.2 μm.

[0101] Furthermore, a depth L8 between the bottom of the second source region 240 and the first surface of the epitaxial layer 200 is 0.1 μm-0.5 μm.

[0102] Furthermore, the doping concentration of the first source region 290 is different from the doping concentration of the second source region 240 . Furthermore, the doping concentration of the first source region 290 is greater than the doping concentration of the second source region 240 .

[0103] Furthermore, the doping concentration of the first source region 290 is 1E14 cm -3 ~2E15 cm -3 .

[0104] Furthermore, the doping concentration of the second source region 240 is 1E12 cm -3 ~3E13 cm -3 .

[0105] In the present application, a composite source region of the first doping type with different junction depths and doping concentrations is formed in the active region by the first source region and the second source region, so as to improve the short-circuit current capability of the device.

[0106] Furthermore, the doping concentration of the first implantation region 210 is different from the doping concentration of the second implantation region 220 . For example, the doping concentration of the first implantation region 210 is less than the doping concentration of the second implantation region 220 .

[0107] Furthermore, the depth between the bottom of the first implantation region 210 and the first surface of the epitaxial layer 200 is 2 μm to 3 μm, and the width of the first implantation region 210 is 0.5 μm to 1 μm.

[0108] Furthermore, the width of the first injection region 210 is the same as the width of the second injection region 220 .

[0109] Furthermore, a depth L2 between the bottom of the second doping type implantation region 230 and the first surface of the epitaxial layer 200 is 2 μm-3 μm, and a width W2 of the second doping type implantation region 230 is 0.5 μm-1 μm.

[0110] Furthermore, a depth L1 between the bottom of the trench 201 and the first surface of the epitaxial layer 200 is 0.8 μm to 1.2 μm, and a width W1 of the trench 201 is 0.5 μm to 1.0 μm.

[0111] Furthermore, a distance d1 between two side edges of two adjacent implantation regions 230 close to the trench 201 is 1.5 μm to 3 μm.

[0112] Furthermore, a depth L7 between the bottom of the well region 280 and the first surface of the epitaxial layer 200 is 0.3 μm to 0.8 μm.

[0113] Furthermore, the power device further includes an interlayer dielectric layer 300, which covers the surfaces of the gate conductor 270 and the gate dielectric layer 260, and a portion of the surface of the first source region 290. In this embodiment, the interlayer dielectric layer 300 is, for example, a borophosphosilicate glass layer (BPSG) oxide film. In other embodiments, the interlayer dielectric layer 300 is, for example, a borophosphosilicate glass layer (BPSG) and a silicon nitride layer (SIN x ) composite structure.

[0114] The power device further includes a source electrode 410 and a drain electrode 420. The source electrode 410 is located on the interlayer dielectric layer 300 and is in contact with and electrically connected to the first source region 290 and the second injection region 220 in the injection region 230. The drain electrode 420 is located on the second surface of the substrate 100 and is electrically connected to the substrate 100. Figure 1 Although not shown in the figure, it should be understood that the power device further includes a gate electrode, which is located on the interlayer dielectric layer 300 and penetrates the interlayer dielectric layer 300 to be electrically connected to the gate conductor 270.

[0115] The power device in this embodiment is, for example, a silicon carbide MOSFET device.

[0116] Figures 2a to 2h Schematic cross-sectional views of a power device at various stages according to an embodiment of the present application are shown.

[0117] like Figure 2a As shown, an epitaxial layer 200 is formed on a substrate 100 , and a first implantation region 210 is formed in the epitaxial layer 200 by extending downward along a first surface of the epitaxial layer 200 .

[0118] For example, a silicon carbide epitaxial layer 200 of a first doping type (e.g., N-type) is grown on a substrate 100 of a first doping type (e.g., N+ type). The substrate 100 is, for example, an N+-doped SiC substrate having a (0001) crystal plane and an angle of 4±0.5° toward the <11-20> crystal orientation. The doping concentration of the substrate 100 is, for example, 6E18 / cm 3 ~1.5E19 / cm 3 The doping concentration of the epitaxial layer 200 is, for example, 8E15 / cm 3 ~2E16 / cm 3 The thickness of the epitaxial layer 200 is, for example, 8 μm to 12 μm. The epitaxial layer 200 includes a second surface facing the substrate 100 and a first surface opposite to the second surface.

[0119] Furthermore, for example, a 2-3 μm thick oxide layer (not shown) is formed on the first surface of the epitaxial layer 200 using low-pressure chemical vapor deposition. Then, through photolithography and etching processes, windows are formed in the oxide layer. The designed width of the windows is 0.5-1 μm, and the center-to-center distance between the windows is 1.5-3 μm. This forms first implantation regions 210 located in the epitaxial layer 200 and extending downward from the first surface of the epitaxial layer 200. The depth L2 between the bottom of the first implantation region 210 and the first surface of the epitaxial layer 200 is 2-3 μm, and the width W2 of the first implantation region 210 is 0.5-1 μm. The distance d1 between two adjacent first implantation regions 210 near the two sides of the trench 201 is 1.5-3 μm. Furthermore, the distance d1 between two adjacent implantation regions 230 near the two sides of the trench 201 is 1.5-3 μm. The depth between the bottom of the implantation region 230 and the first surface of the epitaxial layer 200 is 2 μm-3 μm.

[0120] Furthermore, the first implantation region 210 is, for example, a dielectric layer implanted with a second doping type (e.g., P-type) by high-energy implantation. For example, the first implantation region 210 is formed at an implantation temperature of approximately 500°C, an implantation angle of approximately tilt0°, an implantation energy of 1MeV to 3MeV, and an implantation dose of 2E13 / cm 3 ~8E13 / cm 3 In an alternative embodiment, for example, a <11-20> crystal direction tunnel implant of the SIC process can be used, implanted at room temperature, with an implant angle of about 4°, an implant energy of 600KeV~900KeV, and an implant dose of 2E13 / cm 3 ~8E13 / cm 3 .

[0121] like Figure 2b As shown, an implantation region 230 of the second doping type including a first implantation region 210 of the second doping type and a second implantation region 220 of the second doping type is formed.

[0122] Furthermore, the first implantation region 210 is located on both sides of the trench 201 and at the bottom of the implantation region 230. The second implantation region 220 is located above the first implantation region 210. The second implantation region 220 extends to a portion of the epitaxial layer 200 below the well region 280. Furthermore, the width of the first implantation region 210 is consistent with the width of the second implantation region 220.

[0123] Furthermore, the doping concentration of the first implantation region 210 is different from the doping concentration of the second implantation region 220 . For example, the doping concentration of the first implantation region 210 is less than the doping concentration of the second implantation region 220 .

[0124] For example, multiple high-temperature Al ion box implants of the second doping type (e.g., P-type) are continued in the implant window of the oxide layer formed in the above step, and then different implant angles, implant energies, and doses are adjusted to form P-type implant regions 230 of different structures and depths. Specifically, the multiple implants include: aluminum implants with an implant angle of about tilt 0°, an implant energy of 50KeV to 450KeV, and an implant dose of 5E13cm 3 ~2E15 / cm 3 , to form a second implantation region located above the first implantation region 210 .

[0125] like Figure 2c As shown, a well region 280 of the second doping type and a first source region 290 of the first doping type located above the well region 280 are formed in the epitaxial layer.

[0126] For example, the oxide layer on the first surface of the silicon carbide epitaxial layer 200 in the above step is first removed. Then, through the process of oxide layer deposition, photolithography, and etching, an oxide layer is formed on the first surface of the epitaxial layer 200, and an active area window is formed. Then, for example, by high-temperature aluminum ion implantation, a second doping type well region 280 is formed in the active area with a depth L7 of 0.3μm to 0.8μm between the bottom and the first surface of the epitaxial layer 200, the implantation angle is about tilt 0°, the implantation energy is 200KeV to 450KeV, and the implantation dose is 1E13 / cm 3 ~2E14 / cm 3 In an alternative embodiment, the formation of the well region 280 by high temperature aluminum ion implantation can also be divided into two steps of box implantation, that is, the first step is to implant the aluminum ion with an energy of 300KeV to 450KeV and an implantation dose of 1E13 / cm 3 ~2E14 / cm 3 The first injection is performed, and the injection energy is 200KeV~300KeV, and the injection dose is 1E13 / cm 3 ~2E14 / cm 3 The second implantation is performed to form a well region 280 with a relatively uniform implant concentration. Then, at the location of the oxide layer window, the temperature is about 500°C, the implantation angle is about 0°, the implantation energy is 30KeV~100KeV, and the implantation dose is 1E14 / cm 3 ~2E15 / cm 3 Nitrogen ions are implanted to form a first source region 290 of the first doping type located above the well region 280 in the active region and having a depth L6 of 0 μm to 0.2 μm between the bottom and the first surface of the epitaxial layer 200. Furthermore, the doping concentration of the first source region 290 is 1E14 cm -3 ~2E15 cm -3 .

[0127] like Figure 2d As shown, a second source region 240 of the first doping type is formed extending from the interface between the first source region 290 and the well region 280 to the well region 280 to form a composite source region consisting of the first source region 290 and the second source region 240 .

[0128] Furthermore, there is a gap between the second source region 240 and the implantation region 230 .

[0129] Furthermore, a depth L8 between the bottom of the second source region 240 and the first surface of the epitaxial layer 200 is 0.1 μm-0.5 μm.

[0130] Furthermore, the doping concentration of the first source region 290 is different from the doping concentration of the second source region 240 . Furthermore, the doping concentration of the first source region 290 is greater than the doping concentration of the second source region 240 .

[0131] Furthermore, the doping concentration of the second source region 240 is 1E12 cm -3 ~3E13 cm -3 .

[0132] Exemplarily, at the location where the trench 201 is subsequently formed in the epitaxial layer 200, a window is again formed by oxide layer deposition and photolithography and etching processes, and first doping type ion implantation is performed to form a second source region 240 of the first doping type extending from the interface between the first source region 290 and the well region 280 to the well region 280 and spaced apart from the implantation region 230. The second source region 240 is located between two adjacent implantation regions 230 of the second doping type and is separated from the first implantation region 210 and the second implantation region 220. The depth L8 between the bottom of the second source region 240 and the first surface of the epitaxial layer 200 is 0.1 μm to 0.5 μm. The doping concentration of the first source region 290 is different from the doping concentration of the second source region 240. Furthermore, the doping concentration of the first source region 290 is greater than the doping concentration of the second source region 240. Specifically, the implantation energy is 100 KeV to 250 KeV, and the implantation dose is 1E12 / cm 3 ~3E13 / cm 3 .

[0133] That is, in the active region, the first source region 290 and the second source region 240 form a composite source region of the first doping type with different junction depths and different doping concentrations, so as to improve the short-circuit current capability of the device.

[0134] like Figure 2e As shown, a trench 201 is formed downwardly along the first surface of the epitaxial layer 200 and is located in the center of the epitaxial layer 200 . The trench 201 is located between two adjacent implantation regions 230 .

[0135] Furthermore, the trench 201 penetrates the first source region 290 and the second source region 240. Furthermore, the trench 201 also penetrates the well region 280 to reach the epitaxial layer 200.

[0136] Furthermore, the depth of the trench 201 is less than the depth of the implantation region 230. For example, the depth L1 between the bottom of the trench 201 and the first surface of the epitaxial layer 200 is 0.8 μm to 1.2 μm. The width W1 of the trench 201 is 0.5 μm to 1.0 μm.

[0137] For example, a conventional semiconductor oxide deposition method, such as low-pressure chemical vapor deposition, is used to form an oxide layer 500 with a thickness of 2 μm to 3 μm on the first surface of the epitaxial layer 200. Subsequently, using the oxide layer 500 as a mask and employing semiconductor photolithography and etching techniques, a pattern is selected on the surface of the silicon carbide epitaxial layer 200 perpendicular to the (0001) crystal plane. Silicon carbide trenches are etched in the <11-20> crystal orientation using SF6 and O2 as etching gases to form trenches 201 with a width W1 of 0.5 μm to 1.0 μm and a depth L1 of 0.8 μm to 1.2 μm.

[0138] like Figure 2f As shown, a shielding region 250 of the second doping type is formed in the epitaxial layer 200 , and the shielding region 250 extends downward along the bottom of the trench 201 .

[0139] For example, the oxide layer 500 is retained, and a low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) method is continued to be used to deposit an oxide layer with a thickness of 300 to 500 angstroms on the surface of the semiconductor structure. Low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) is then continued to be used to deposit 1000 to 1500 angstroms of silicon nitride on the 300 to 500 angstroms oxide layer. Anisotropic vertical etching is then performed, such as by dry reactive ion etching, to etch away the silicon nitride at the bottom of the trench 201 while retaining the silicon nitride on the inner sidewalls of the trench 201. High-temperature implantation of Al ions of the second doping type is then performed, with an implantation energy of 25 keV to 45 keV and an implantation dose of 5E13 / cm 3 ~3E14 / cm 3 , to form a shielding region 250 of the second doping type below the trench 201 .

[0140] Furthermore, along the first direction, the width of the shielding region 250 is, for example, smaller than the width of the trench 201 .

[0141] Furthermore, the method further includes removing all oxide layers and silicon nitride layers on the surface of the silicon carbide epitaxial layer 200 using a wet etching process for semiconductor integrated circuits, and then applying a carbon film to the silicon carbide epitaxial layer 200 to protect all exposed surfaces of the silicon carbide epitaxial layer 200. The carbon film protection can be performed using a photoresist, sputtered carbon film, or chemical vapor deposition carbon film deposition method. The semiconductor structure is then subjected to a high-temperature annealing in an argon environment to activate all impurity implantation structures in the semiconductor structure to form the active region of the trench-gate MOSFET device. The annealing temperature is, for example, 1650° C. to 1750° C., and the annealing time is, for example, 10 minutes to 60 minutes.

[0142] like Figure 2g As shown, a gate dielectric layer 260 and a gate conductor 270 are formed in the trench 201 , and the gate conductor 270 is separated from the epitaxial layer 200 by the gate dielectric layer 260 .

[0143] For example, in Figure 2f A field oxide layer with a thickness of 2000 to 5000 angstroms is grown on the semiconductor structure to protect the first surface of the epitaxial layer 200, excluding the trench 201 region. The oxide layer within the trench 210 is then removed by photolithography and etching. Subsequently, a sacrificial oxide layer with a thickness of approximately 200 angstroms is formed in the trench 201 by thermal oxidation, for example, at a temperature of approximately 1100°C. The sacrificial oxide layer is then etched away again by wet etching. A gate oxide layer and gate dielectric layer 260 with a thickness of 400 to 600 angstroms is then grown in the trench 201. In-situ doped polysilicon is then deposited and etched away using photolithography and etching techniques to form a gate conductor 270.

[0144] like Figure 2h As shown, an interlayer dielectric layer 300, a source electrode 410, a drain electrode 420, and a gate electrode are formed. The interlayer dielectric layer 300 covers the surfaces of the gate conductor 270 and the gate dielectric layer 260, as well as a portion of the surface of the first source region 290. The source electrode 410 is located on the interlayer dielectric layer 300 and contacts and is electrically connected to the first source region 290 and the second implantation region 220 in the implantation region 230. The drain electrode 420 is located on the second surface of the substrate 100 and is electrically connected to the substrate 100. A gate electrode (not shown) is located on the interlayer dielectric layer 300 and penetrates the interlayer dielectric layer 300 to be electrically connected to the gate conductor 270.

[0145] For example, in Figure 2g A boro-phospho-silicate-glass (BPSG) oxide film is deposited on the semiconductor structure to form an interlayer dielectric layer 300 on the surfaces of the gate conductor 270 and the gate dielectric layer 260 and a portion of the surface of the first source region 290 .

[0146] Then, lead holes are formed using photolithography and etching methods used in semiconductor integrated circuit processes, and a gate electrode (not shown) and a source electrode 410 are formed on the interlayer dielectric layer 300. A thinning process and a backside metallization process are performed on the surface of the substrate 100 away from the epitaxial layer 200 to form the drain electrode 420. The source electrode 410 is located on the interlayer dielectric layer 300 and is electrically connected to the first source region 290 and the second implanted region 220 in the implanted region 230. The drain electrode 420 is located on the second surface of the substrate 100 away from the epitaxial layer 200 and is electrically connected to the substrate 100. A gate electrode (not shown) is located on the interlayer dielectric layer 300 and penetrates the interlayer dielectric layer 300 to be electrically connected to the gate conductor 270.

[0147] The power device provided by the present application forms an injection region of the second doping type in the epitaxial layer with a depth greater than the trench depth. Furthermore, the first injection region in the injection region of the second doping type is located on both sides of the trench, and the second injection region is located on the upper part of the first injection region. When the power device is in the reverse high voltage cut-off state, the depletion layer of the P-type composite injection region expands, and the depletion layer of the P-type shielding region at the bottom of the trench forms a protective structure at the bottom of the trench, reducing the electric field strength at the bottom of the trench. The power device provided by the present application not only reduces the process complexity and process difficulty, but also can reduce the breakdown field strength of the electric field at the bottom of the trench in the device when in the reverse high voltage cut-off working state. At the same time, the present application forms a composite source region of the first doping type with different junction depths and different doping concentrations in the active region by the first source region and the second source region to improve the short-circuit current capability of the device.

[0148] That is, the power device provided in this application can achieve very high reliability and parameter performance, and reduce process complexity and difficulty, and can achieve mass production.

[0149] While the embodiments of the present application are described above, these embodiments do not exhaustively describe all details and do not limit the present application to specific embodiments. Clearly, many modifications and variations are possible based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to better utilize the present application and its modifications and uses. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A power device, characterized in that: comprising at least one cell, each of the cells comprising: a substrate, the first direction being parallel to the substrate, and the second direction being perpendicular to the substrate; An epitaxial layer of a first doping type, located on the first surface of the substrate; A trench, extending from the first surface of the epitaxial layer to the second surface of the epitaxial layer along a second direction, with a first distance between a bottom of the trench and the second surface of the epitaxial layer, and the trench being located in a middle region of the epitaxial layer along the first direction; an implantation region of a second doping type, the implantation region extending from the first surface of the epitaxial layer to the second surface of the epitaxial layer along a second direction, the implantation region being spaced a second distance from the second surface of the epitaxial layer, the implantation region being located at both ends of the epitaxial layer along the first direction, and the implantation region being spaced apart from the trench; A well region of a second doping type is located in the epitaxial layer in the interval between the implantation region and the trench; a first source region of a first doping type, located in the epitaxial layer between the implantation region and the trench, the first source region being located above the well region; A second source region of the first doping type is located in the well region in the gap between the injection region and the trench and is located on both sides of the trench. The second source region extends from the junction of the first source region and the well region to the well region, and there is a gap between the second source region and the injection region.

2. The power device according to claim 1, wherein: The power device further includes: a gate dielectric layer, the gate dielectric layer being located on the sidewalls and bottom of the trench; a gate conductor, the gate conductor being located in the trench and separated from the epitaxial layer outside the trench by the gate dielectric layer; A shielding region of the second doping type is located at the bottom of the trench and extends toward the second surface of the epitaxial layer, and a third distance exists between the bottom of the shielding region and the second surface of the epitaxial layer. The second spacing is smaller than the first spacing, and the second spacing is smaller than the third spacing.

3. The power device according to claim 1, wherein: The second doping type injection region includes a first injection region and a second injection region, the first injection region is located at the bottom of the injection region, the second injection region is located above the first injection region, and the second injection region extends to a portion of the epitaxial layer under the well region.

4. The power device according to claim 1, wherein: The doping concentration of the first source region is greater than the doping concentration of the second source region.

5. The power device according to claim 1, wherein: The depth between the bottom of the first source region and the first surface of the epitaxial layer is 0 μm to 0.2 μm.

6. The power device according to claim 1, wherein: The depth between the bottom of the second source region and the first surface of the epitaxial layer is 0.1 μm to 0.5 μm.

7. The power device according to claim 1, wherein: The doping concentration of the first source region is 1E14 cm -3 ~2E15 cm -3 .

8. The power device according to claim 1, wherein: The doping concentration of the second source region is 1E12 cm -3 ~3E13 cm -3 .

9. The power device according to claim 3, characterized in that The doping concentration of the first implantation region is lower than the doping concentration of the second implantation region.

10. The power device according to claim 3, characterized in that: The depth between the bottom of the first implantation region and the first surface of the epitaxial layer is 2 μm to 3 μm.

11. The power device according to claim 3, characterized in that: The width of the first injection region is 0.5 μm to 1 μm.

12. The power device according to claim 3, wherein: The width of the first injection region is the same as the width of the second injection region.

13. The power device according to claim 1, wherein: The distance between two side edges of the two adjacent implantation regions close to the trench is 1.5 μm to 3 μm.

14. The power device according to claim 1, wherein: The depth between the bottom of the trench and the first surface of the epitaxial layer is 0.8 μm to 1.2 μm.

15. The power device according to claim 1, characterized in that The width of the groove is 0.5 μm to 1.0 μm.

16. The power device according to claim 1, characterized in that The depth between the bottom of the well region and the first surface of the epitaxial layer is 0.3 μm to 0.8 μm.

17. The power device according to claim 2, characterized in that: Also includes: an interlayer dielectric layer, covering surfaces of the gate conductor and the gate dielectric layer, and a portion of a surface of the first source region; a source electrode, located on the interlayer dielectric layer and in contact with and electrically connected to the first source region and the injection region; a drain electrode, located on the second surface of the substrate and electrically connected to the substrate, wherein the first surface and the second surface of the substrate are opposite to each other; as well as The gate electrode is located on the interlayer dielectric layer and penetrates the interlayer dielectric layer to be electrically connected to the gate conductor.

18. The power device according to any one of claims 1 to 17, characterized in that: The power device is a silicon carbide MOSFET device.

19. A method for manufacturing a power device, characterized in that: The power device includes at least one cell, and the manufacturing method of each cell includes: Providing a substrate, wherein the first direction is parallel to the substrate and the second direction is perpendicular to the substrate; forming an epitaxial layer of a first doping type on a first surface of the substrate; forming a trench, wherein the trench extends from the first surface of the epitaxial layer to the second surface of the epitaxial layer along a second direction, a first distance exists between the bottom of the trench and the second surface of the epitaxial layer, and the trench is located in a middle region of the epitaxial layer along the first direction; forming an implantation region of a second doping type, wherein the implantation region extends from the first surface of the epitaxial layer to the second surface of the epitaxial layer along a second direction, the implantation region is spaced a second distance from the second surface of the epitaxial layer, the implantation region is located at both ends of the epitaxial layer along the first direction, and the implantation region is spaced from the trench; forming a well region of a second doping type in the epitaxial layer in the interval between the implantation region and the trench; forming a first source region of a first doping type in the epitaxial layer in the interval between the implantation region and the trench, wherein the first source region is located above the well region; A second source region of the first doping type is formed in the epitaxial layer in the gap between the injection region and the trench, the second source region is located on both sides of the trench, the second source region extends from the junction surface of the first source region and the well region to the well region, and there is a gap between the second source region and the injection region.

20. The method for manufacturing a power device according to claim 19, wherein: Also includes: forming a gate dielectric layer on the sidewalls and bottom of the trench; forming a gate conductor in the trench, wherein the gate conductor is separated from the epitaxial layer outside the trench by the gate dielectric layer; forming a shielding region of the second doping type at the bottom of the trench and extending toward the second surface of the epitaxial layer, wherein a third distance exists between the bottom of the shielding region and the second surface of the epitaxial layer; The second spacing is smaller than the first spacing, and the second spacing is smaller than the third spacing.

21. The method for manufacturing a power device according to claim 19, wherein: Forming an implantation region of a second doping type includes: forming a first implantation region at the bottom; A second implantation region is formed, where the second implantation region is located on an upper portion of the first implantation region and extends to a portion of the epitaxial layer below the well region.

22. The method for manufacturing a power device according to claim 19, wherein: The doping concentration of the first source region is greater than the doping concentration of the second source region.

23. The method for manufacturing a power device according to claim 19, wherein: The depth between the bottom of the first source region and the first surface of the epitaxial layer is 0 μm to 0.2 μm.

24. The method for manufacturing a power device according to claim 19, wherein: The depth between the bottom of the second source region and the first surface of the epitaxial layer is 0.1 μm to 0.5 μm.

25. The method for manufacturing a power device according to claim 19, wherein: The doping concentration of the first source region is 1E14 cm -3 ~2E15 cm -3 .

26. The method for manufacturing a power device according to claim 19, wherein: The doping concentration of the second source region is 1E12 cm -3 ~3E13 cm -3 .

27. The method for manufacturing a power device according to claim 21, wherein: The doping concentration of the first implantation region is lower than the doping concentration of the second implantation region.

28. The method for manufacturing a power device according to claim 21, wherein: The depth between the bottom of the first implantation region and the first surface of the epitaxial layer is 2 μm to 3 μm.

29. The method for manufacturing a power device according to claim 21, wherein: The width of the first injection region is 0.5 μm to 1 μm.

30. The method for manufacturing a power device according to claim 21, wherein: The width of the first injection region is the same as the width of the second injection region.

31. The method for manufacturing a power device according to claim 19, wherein: The distance between two side edges of the two adjacent implantation regions close to the trench is 1.5 μm to 3 μm.

32. The method for manufacturing a power device according to claim 19, wherein: The depth between the bottom of the trench and the first surface of the epitaxial layer is 0.8 μm to 1.2 μm.

33. The method for manufacturing a power device according to claim 19, wherein: The width of the groove is 0.5 μm to 1.0 μm.

34. The method for manufacturing a power device according to claim 19, wherein: The depth between the bottom of the well region and the first surface of the epitaxial layer is 0.3 μm to 0.8 μm.

35. The method for manufacturing a power device according to claim 20, wherein: Also includes: forming an interlayer dielectric layer covering surfaces of the gate conductor and the gate dielectric layer and a portion of the surface of the first source region; forming a source electrode on the interlayer dielectric layer, wherein the source electrode contacts and is electrically connected to the first source region and the injection region; forming a drain electrode located on the second surface of the substrate, the drain electrode being electrically connected to the substrate, and the first surface and the second surface of the substrate being opposite to each other; as well as A gate electrode is formed on the interlayer dielectric layer, and the gate electrode penetrates the interlayer dielectric layer and is electrically connected to the gate conductor.

36. The method for manufacturing a power device according to any one of claims 19 to 35, wherein: The power device is manufactured using a silicon carbide MOSFET device.

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