Optimized thin film deposition and ion implantation for mitigating stress and deformation in substrates

Abstract

The disclosed systems and techniques relate to correcting out-of-plane deformation (OPD) of a substrate (e.g., a wafer) by: identifying a profile of the OPD of the substrate using optical inspection data; and performing a polynomial decomposition of the contour to determine polynomial coefficients characterizing an element deformation shape of the substrate. The technique further includes identifying a characteristic of a stress compensation layer (SCL) for the substrate based on the polynomial coefficient; and causing the SCL to be deposited on the substrate. The technique further includes performing a statistical simulation to identify settings of non-uniform stress mitigation illumination for the SCL by sampling from one or more statistical distributions associated with previously performed stress mitigation illumination; and performing the non-uniform stress mitigation irradiation of the SCL using the identified setting.

Description

Technical Field

[0001] This disclosure relates to semiconductor fabrication, including the fabrication of wafers. Background Art

[0002] Modern semiconductor components (such as processing circuits, memory components, photodetectors, solar cells, light-emitting semiconductor components and the like) are typically manufactured on silicon wafers (or other suitable substrates). The wafer may undergo many processing operations, such as physical vapor deposition, chemical vapor deposition, etching, photomasking, polishing and / or various other operations. In order to continuously reduce the cost of semiconductor components, multilayer stacks of bare crystals, insulating films, patterned and / or doped semiconductor films and / or other features are typically deposited on a single wafer to produce high aspect ratio components, such as those used in three-dimensional flash memory components and other applications. The processes of depositing, patterning, etching, polishing, etc. of the multilayer structure stack typically result in significant stress being applied to the underlying wafer. Such stress can cause both out-of-plane and in-plane distortions of the features supported by the wafer. These distortions can cause misalignment of the deposited features and can significantly reduce the quality of the manufactured component. Summary of the Invention

[0003] In one embodiment, disclosed is a method for correcting out-of-plane deformation of a substrate, the method comprising: identifying a profile of the out-of-plane deformation of the substrate using optical inspection data. The method further comprises: performing a polynomial decomposition on the identified profile to determine a plurality of polynomial coefficients, each of the plurality of polynomial coefficients characterizing a corresponding one of a plurality of elemental deformed shapes of the substrate. The method further comprises: identifying one or more properties of a stress-compensating layer (SCL) for the substrate based on at least a subset of the plurality of polynomial coefficients. The method further comprises: depositing the SCL on the substrate; and performing a plurality of statistical simulations to identify settings for non-uniform stress mitigation irradiation of the SCL, wherein performing the plurality of statistical simulations comprises: sampling from one or more statistical distributions associated with previously performed stress mitigation irradiations. The method further comprises: performing the non-uniform stress mitigation irradiation of the SCL using the identified settings, wherein the non-uniform stress mitigation irradiation is performed using a first setting for at least a first region of the SCL and a second setting for a second region of the SCL.

[0004] In another embodiment, disclosed is a system comprising a memory and a processing device communicatively coupled to the memory. The processing device is configured to identify a profile of an out-of-plane deformation of a substrate using optical inspection data. The processing device is further configured to perform a polynomial decomposition on the identified profile to determine a plurality of polynomial coefficients, each of the plurality of polynomial coefficients characterizing a corresponding one of a plurality of elemental deformed shapes of the substrate. The processing device is further configured to identify one or more properties of a stress-compensating layer (SCL) for the substrate based on at least a subset of the plurality of polynomial coefficients. The processing device is further configured to deposit the SCL on the substrate. The processing device is further configured to perform a plurality of statistical simulations to identify settings for non-uniform stress mitigation irradiation of the SCL, wherein performing the plurality of statistical simulations includes sampling from one or more statistical distributions associated with previously performed stress mitigation irradiations. The processing device is further configured to perform the non-uniform stress mitigation irradiation of the SCL using the identified settings, wherein the non-uniform stress mitigation irradiation is performed using a first setting for at least a first region of the SCL and a second setting for a second region of the SCL.

[0005] In another embodiment, disclosed is a semiconductor manufacturing system comprising one or more processing chambers for processing a substrate and a computing device. The computing device is configured to: identify a profile of an out-of-plane deformation of the substrate using optical inspection data; and perform a polynomial decomposition on the identified profile to determine a plurality of polynomial coefficients, each of the plurality of polynomial coefficients characterizing a corresponding one of a plurality of elemental deformed shapes of the substrate. The computing device is further configured to: identify one or more properties of a stress-compensating layer (SCL) for the substrate based on at least a subset of the plurality of polynomial coefficients; and deposit the SCL on the substrate. The computing device is further configured to: perform a plurality of statistical simulations to identify settings for a non-uniform stress-relief irradiation of the SCL, wherein performing the plurality of statistical simulations includes sampling from one or more statistical distributions associated with previously performed stress-relief irradiations. The computing device is further configured to: perform the non-uniform stress-relief irradiation of the SCL using the identified settings, wherein the non-uniform stress-relief irradiation is performed using a first setting for at least a first region of the SCL and a second setting for a second region of the SCL.

[0006] In yet another embodiment, disclosed is a non-transitory computer-readable memory having instructions stored thereon that, when executed by a processing device, cause the processing device to perform operations comprising: identifying a profile of an out-of-plane deformation of a substrate using optical inspection data. The operations further include performing a polynomial decomposition on the identified profile to determine a plurality of polynomial coefficients, each of the plurality of polynomial coefficients characterizing a corresponding one of a plurality of elemental deformed shapes of the substrate. The operations further include identifying one or more properties of a stress-compensating layer (SCL) for the substrate based on at least a subset of the plurality of polynomial coefficients. The operations further include depositing the SCL on the substrate. The operations further include performing a plurality of statistical simulations to identify settings for a non-uniform stress mitigation irradiation of the SCL, wherein performing the plurality of statistical simulations includes sampling from one or more statistical distributions associated with previously performed stress mitigation irradiations. The operations further include performing the non-uniform stress mitigation irradiation of the SCL using the identified settings, wherein the non-uniform stress mitigation irradiation is performed using a first setting for at least a first region of the SCL and a second setting for a second region of the SCL. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure can be more fully understood from the following detailed description and accompanying drawings of various embodiments of the present disclosure.

[0008] Figure 1A-1E A process for stress correction of a backside deposited film using additional ion implantation is schematically illustrated in accordance with at least one embodiment.

[0009] Figure 2 An example Zernike polynomial decomposition of an actual deformation of a wafer (upper left) in arbitrary units is shown to decompose it into parabolic bow deformation (upper right), saddle deformation (lower left), and residual deformation (lower right), in accordance with at least one embodiment.

[0010] Figure 3 An example wafer is shown for use in accordance with at least one embodiment. Figure 1A-1E Disclosed process for stress and deformation relief.

[0011] Figure 4 An example profile of a Gaussian ion beam that may be used for stress and deformation mitigation in a wafer is shown in accordance with at least one embodiment.

[0012] Figure 5 An example silicon wafer having a silicon nitride film deposited thereon and having saddle-point deformation is shown, in accordance with at least one embodiment.

[0013] Figure 6 is a flow chart illustrating an example process for mitigating wafer stress and deformation in accordance with at least one embodiment.

[0014] Figure 7 is a flow chart illustrating an example process for ion implantation performed to mitigate wafer deformation and stress in accordance with at least one embodiment.

[0015] Figure 8A The dependence of the number of vacancies created by ions of an implanted species in a silicon nitride film as a function of depth (distance traveled by the ions in angstroms) is shown, in accordance with at least one embodiment.

[0016] Figure 8B The estimated response of a 200 nm silicon nitride film to various doses of implanted species ions is shown, in accordance with at least one embodiment.

[0017] Figure 9 The dependence of the number of vacancies created by different types of ions as a function of depth is shown, in accordance with at least one embodiment.

[0018] Figure 10 The response of a 200 nm silicon nitride film as a function of ion dose for various ion types is shown, in accordance with at least one embodiment.

[0019] Figure 11 The ion distribution as a function of depth for different types of atomic implantation is shown.

[0020] Figure 12A The distribution of implanted ions at various incident angles is shown in accordance with at least one embodiment.

[0021] Figure 12B The number of created vacancies as a function of depth (with the distance traveled by the ions expressed in angstroms) is shown for ions incident at various angles, in accordance with at least one embodiment.

[0022] Figure 12C The response of an example silicon nitride film as a function of ion dose for various types of ions is shown, in accordance with at least one embodiment.

[0023] Figure 13A An ion implantation system capable of performing ion implantation into a stress-compensating layer in accordance with at least one embodiment is schematically illustrated.

[0024] Figure 13B According to at least one embodiment, Figure 13A The ion implantation system delivers ions to the wafer at any incident angle.

[0025] Figure 14A block diagram of an example computer system capable of supporting operations of the present disclosure in accordance with at least one embodiment is depicted. DETAILED DESCRIPTION

[0026] The prior art includes a variety of approaches to addressing substrate or wafer deformation. For example, a deformed (warped) substrate (such as a silicon wafer) with various films and features deposited on one side (referred to herein as the front, top, or primary side) can be coated with a film that applies compressive or tensile stress to the wafer on the other side (referred to herein as the backside or bottom side). This backside-deposited deformation-correcting film (also referred to herein as a stress-compensating layer) typically applies a uniform (or global) stress across the entire wafer and is unable to compensate for localized stress modulation and / or anisotropic stress. Additional correction can be achieved by implanting ions into the stress-compensating layer (e.g., bombarding the stress-compensating layer with an ion beam) to adjust the stress in the stress-compensating layer, thereby further mitigating deformation of the underlying wafer.

[0027] As used herein, "wafer" refers to any substrate, or surface of a material formed on a substrate, on which thin film processing is performed during the manufacturing process. For example, depending on the application, wafer surfaces on which processing may be performed include materials such as silicon, silicon oxide, silicon nitride, strained silicon, silicon-on-insulator structures, carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material (e.g., metals, metal nitrides, metal alloys, and other conductive materials). In some cases, a wafer may comprise a plastic substrate. Wafers include, but are not limited to, semiconductor wafers. Wafers may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to performing thin film processing directly on the surface of the wafer itself, any of the disclosed thin film processing steps may also be performed on underlying layers formed on the wafer, as disclosed in more detail below, and the term "wafer surface" is intended to include such underlying layers as the context dictates. Thus, for example, if a thin film / layer or portion of a thin film / layer has already been deposited onto the wafer surface, the exposed surface of the newly deposited thin film / layer becomes the wafer surface. In some embodiments, the thickness of the wafer is in the range of 0.25 mm to 1.5 mm, or in the range of 0.5 mm to 1.25 mm, or in the range of 0.75 mm to 1.0 mm, or thicker. In some embodiments, the diameter of the wafer is about 10 cm, 20 cm, 30 cm or more.

[0028] Stress compensation layers deposited by ion implantation are used to correct uniform and isotropic stress (σ xx ≈σ yy ) can be quite efficient. On the other hand, the stress (σ) that varies with position x, y on the wafer can be mitigated. jk(x, y)), anisotropic stress (σ xx ≠σ yy ) or both is a more challenging problem. Certain patterns may result in compressive stress along one direction (e.g. σ xx >0), and tensile stress (σ yy <0), for example Figure 5 Such features may occur, for example, in material stacks with directional patterning (e.g., the patterning of word lines in flash memory devices). Correcting the subsequent anisotropic and / or non-uniform stresses and the resulting wafer deformation remains a difficult task.

[0029] Aspects and embodiments of the present disclosure address these and other challenges of modern semiconductor manufacturing technology by providing systems and techniques that can mitigate non-uniform and / or anisotropic stresses and deformations of wafers. In one embodiment, the vertical profile z=h(r, φ) of the wafer deformation can be measured using optical metrology techniques. For example, optical interferometry can be used to obtain an interference pattern of the profile h(r, φ). The wafer profile h(r, φ) can then be represented by a plurality of parameters that qualitatively and quantitatively characterize the geometry of the wafer deformation. In some embodiments, the wafer profile can be represented using a set of Zernike (or a similar set of) polynomials,

[0030]

[0031] where r is the radial coordinate and φ is the polar coordinate in the (average) plane of the wafer. The successive coefficients A1, A2, A3, A4, ... represent the weighting of certain geometrical features of the wafer (element deformations) described by the corresponding Zernike polynomials Z1(r, φ), Z2(r, φ), Z3(r, φ), Z4(r, φ), ... . The first three coefficients are less important, since they describe a uniform movement of the wafer (coefficient A1, associated with the polynomial Z1(r, φ) = 1), a deformation-free x-tilt equivalent to a rotation about the y-axis (coefficient A2, associated with the polynomial Z2(r, φ) = 2r Cosφ), and a deformation-free x-tilt equivalent to a rotation about the x-axis (coefficient A3, associated with the polynomial Z3(r, φ) = 2rsinφ), which can be eliminated by realigning the coordinate axes. The fourth coefficient A4 is associated with The fifth coefficient A5 and the sixth coefficient A6 are related to and The polynomials are associated and characterize saddle-type deformations. The A5 coefficient characterizes the saddle shape that bends downward (A5>0) or upward (A5<0) along the diagonal y=x and bends upward (A5>0) or downward (A5<0) along the diagonal y=-x. The A6 coefficient characterizes the saddle shape that bends upward (A6>0) or downward (A6<0) along the x-axis and bends downward (A6>0) or upward (A6<0) along the y-axis. Higher coefficients A7, A8, etc. characterize that the wafer deformation h(r, curvature) changes increasingly faster along the radial direction, along the azimuthal direction, or both, and together represent the residual deformation Figure 2 An example Zernike polynomial decomposition 200 of an actual deformation h(r, φ) of a wafer (upper left) in arbitrary units is shown to decompose the deformation into a parabolic bow deformation A4Z4(r, φ) (upper right), a saddle deformation A5Z5(r, φ)+A6Z6(r, φ) (lower left), and a residual deformation h res (r, φ) (lower right).

[0032] In some embodiments, the thickness d of the deformation compensation film may be selected based on the value of the parabola bow coefficient A4. Figure 1A-1E A process for stress correction of a backside deposited film using additional ion implantation is schematically illustrated in accordance with at least one embodiment. Figure 1A The wafer 102 is depicted with deformations, which may include parabolic bow deformation (with negative coefficient A4 < 0) and other deformations, such as saddle deformation and residual deformation (both are shown in Figure 1 for simplicity and ease of review). Figure 1A-1D (not shown in the figures). Wafer 102 has a front side 104 and a back side 106. Any number of features (e.g., deposited and / or etched patterns), bare die, photomasks, and / or any other structures may be deposited on or etched in front side 104. In some embodiments, back side 106 may be free of deposited / etched features / structures. In some embodiments, back side 106 may also have one or more deposited / etched features / structures. Figure 1B The schematic diagram shows the deposition of a stress-compensating layer on the backside of wafer 102. In some embodiments, stress-compensating layer 108 can include one or more thin films of different materials. The thickness of individual films can be in the range of 10 to 200 nanometers, or in the range of 20 to 180 nanometers, or in the range of 30 to 160 nanometers, or in the range of 40 to 140 nanometers, or greater. The total thickness of the stress-compensating layer can be up to several micrometers or even thicker. In some embodiments, stress-compensating layer 108 is deposited at a temperature in the range of 100°C to 500°C or higher.

[0033] The material (type) of the stress compensating layer 108 may be selected based on the sign of the coefficient A4. For example, for negative bow, A4 < 0, and the stress compensating layer 108 may be selected to have a tensile stress (e.g., Figure 1A-1E For a silicon wafer, this film can be a silicon nitride (Si3N4) film. Conversely, for a positive bow, A4>0, and the stress compensation layer 108 can be selected to have a tensile stress ( Figure 1A-1E (not shown). The stress-compensating layer 108 can be deposited using any suitable deposition technique, including physical vapor deposition (e.g., sputtering), chemical vapor deposition (e.g., plasma-assisted deposition), epitaxy, lift-off, and / or the like. Deposition can be performed at room temperature or at a temperature different from room temperature (e.g., elevated temperature). In some embodiments, the thickness d of the stress-compensating layer 108 can be selected to overcorrect deformation to a certain extent, e.g., Figure 1C As shown, the negative parabolic bow becomes a positive parabolic bow. Thickness-dependent parabolic bow correction A corr (d) Change the wafer deformation from h(r, φ) to h corr (r, φ).

[0034] h corr (r, φ) = h(r, φ) + A corr (d)·Z4(r,φ)

[0035] The overcorrection is selected in conjunction with the implant species, energy, and dose to ensure maximum benefit from stress compensation. The overcorrection allows the combined structure of the wafer 102 and the stress compensating layer 108 to be susceptible to further control of stress (and thus to wafer deformation). corr (further control of r, φ). Figure 1D As shown, an ion beam implanter 110 can generate an ion beam 112 that strikes the stress-compensating layer 108 and deposits ions therein. The ion beam 112 can carry silicon ions, phosphorus ions, argon ions, neon ions, xenon ions, krypton ions, and / or the like. In some embodiments, the energy and type of ions in the ion beam 112 can be selected to confine the implanted ions to the volume of the stress-compensating layer 108 and prevent the ions from reaching the wafer 102. Ions retained in the stress-compensating layer 108 can generate substitutional defects therein. Furthermore, the ions can also leave traces of vacancy defects along their propagation paths in the stress-compensating layer 108. The substitutional defects and / or vacancies modify (e.g., reduce) the stress in the stress-compensating layer 108 and can reduce the degree of stress overcorrection caused by thin film deposition. This results in a flattening of the combination of the wafer 102 and the stress-compensating layer 108.

[0036] While the stress mitigating beam used to modify stress in the stress-compensating layer 108 is referred to as an ion beam (e.g., ion beam 112) for purposes of detail, throughout this disclosure, the stress mitigating beam may include other species (e.g., electrons), electromagnetic waves (e.g., ultraviolet light, visible light, infrared light, etc.), and / or suitable combinations thereof. The stress mitigating beam impacts the stress-compensating layer 108 and modifies the bonding network of the stress-compensating layer 108. For example, a low-energy stress mitigating beam may interact with surface atoms of the stress-compensating layer 108, for example, removing some of the surface atoms, thereby effectively etching the surface region of the stress-compensating layer 108. The effectiveness of this etching can be controlled by selecting the ion species / radicals / ambient gas. In another example, a high-energy stress mitigating beam may deposit ions within the stress-compensating layer 108. The ions and / or photons may disrupt bonds in the bonding network (or lattice) of the stress-compensating layer 108, thereby forming vacancies therein, which may further induce annealing due to localized heating, UV curing, and / or other effects.

[0037] In some embodiments, simulations (performed in more detail below) can be used to estimate the deformation h based on the correction. corr The local value of (r, φ) determines the number of ions deposited per small area of ​​the wafer ΔA = ΔxΔy ΔN i The corrected deformation may include saddle deformation, residual deformation, and a parabolic bow-shaped deformation portion A that has been overcorrected by the deposition of the stress compensation layer 108. corr (d) + A4. The desired local density of ions ΔN can be delivered by controlling the scanning speed v of the ion beam 112. i / ΔxΔy. In some embodiments, the profile of the ion beam 112 can be approximated by a Gaussian function, for example, ion flux j(ρ)=j0exp(-x 2 / a 2 -y 2 / b 2 ), where x and y are Cartesian coordinates, j0 is the maximum ion flux at the beam center, and a and b are the characteristic spread of the beam along the x and y axes, respectively. Correspondingly, a point at a distance y relative to the beam center path receives an ion dose comprising the following number of ions:

[0038]

[0039] Correspondingly, by reducing the scanning speed v, the number of ions received by various regions of the stress compensation layer 108 can be increased, and vice versa. In addition, the ion beam 112 can be scanned multiple times with different offsets y, so that various points of the stress compensation layer 108 are scanned with different coefficients. For example, after n passes through the ion beam implanter 110 (each at a different distance y from the center of the ion beam 112), the coefficients can be averaged to a target dose. k At the corresponding speed v k For area ΔxΔy), the total ion dose received by this area will be

[0040]

[0041] like Figure 1E As shown, the implanted layer 114 formed as part of the stress compensating layer 108 significantly reduces deformation of the wafer 102, particularly the saddle and residual portions thereof.

[0042] Figure 3 An example wafer is shown for use in accordance with at least one embodiment. Figure 1A-1E The disclosed process reduces stress and deformation by 300. Figure 3 As shown, a 30 cm silicon wafer 102 having a maximum negative strain of -75.0 μm is first overcorrected to a maximum strain of +83.5 μm using a silicon nitride tensile stress compensating layer 108. The stress in the stress compensating layer 108 is then reduced by forming an implanted layer 114 using an ion beam, resulting in a final maximum strain of +15.4 μm. Figure 4 An example profile of a Gaussian ion beam 112 that may be used for stress and deformation mitigation in a wafer is shown in accordance with at least one embodiment.

[0043] Figure 1- Figure 3 The techniques shown for strain and deformation mitigation can also be applied to wafers with complex deformations, where the stress tensor components σ xx and σ yy have different signs, resulting in a saddle-shaped deformation of the wafer. Figure 5 An example wafer 500 (e.g., a silicon wafer with a silicon nitride film deposited thereon) having saddle point deformation is shown in accordance with at least one embodiment. As seen in the cross-sectional xz view 502, the stress component σ in the wafer (top layer) xx may be lower than the stress component σ in the thin film (bottom layer) deposited on the back side of the wafer xx In contrast, as shown in the cross-sectional yz view 504, the stress component σ in the wafer yy may be higher than the stress component σ in the film yy In some embodiments, the stress state in the wafer can be represented by a position-dependent stress tensor that can be approximated as:

[0044]

[0045] This structure of the stress tensor is usually a good approximation because the wafer is generally in pure bending and is independent of the shear stresses represented by the off-diagonal terms in the stress tensor. Correcting for the saddle shape requires special care in the dose map calculation and optimization to ensure that no additional residual terms are introduced into the wafer.

[0046] Figure 6 6 is a flow chart illustrating an example process 600 for mitigating wafer stress and deformation according to at least one embodiment. Process 600 can be performed using a semiconductor manufacturing system that includes one or more processing chambers, such as a deposition chamber, a plasma chamber, an etch chamber, a polishing chamber, a thin film removal chamber, a beam irradiation chamber, an optical inspection chamber, and / or the like. The processing chambers can be coupled to one or more transfer chambers, which can be equipped with robots to transfer wafers, such as to move wafers into and out of the processing chambers. The transfer chambers can further be coupled to a load lock chamber (front-end interface), which can be coupled to one or more front-opening unified pod (FUP) carriers that hold bare wafers, processed wafers, partially processed wafers, and / or the like. The operations performed by the semiconductor manufacturing system, including any, some, or all of the operations of process 600, can be performed in response to instructions issued by a suitable computing device having processing logic and memory for storing instructions.

[0047] At block 610, process 600 includes measuring a shape of a wafer, such as a displacement of a surface (e.g., a top surface) of the wafer as a function of some in-plane coordinates (e.g., polar coordinates z=h(r, φ), Cartesian coordinates z=h(x, y), or any other suitable coordinates). At block 620, process 600 includes decomposing the determined shape by a set of suitable polynomials (e.g., Zernike polynomials) and obtaining a set of polynomial expansion coefficients, {A j =(A1, A2, A3)A4, A5, A6, A7, ..., where each coefficient in the set of coefficients characterizes the degree of presence of a particular element geometry in the wafer deformation. At decision block 625, process 600 includes deciding the type of deformation compensating film to be used with the wafer. In some embodiments, the decision can be made based on a coefficient (e.g., coefficient A4) that determines the degree of parabolic deformation. If the wafer bows downward (toward the back side of the wafer), process 600 can select a compressive film for backside deposition and stress relief in the wafer at block 630. If the wafer bows upward (toward the top side of the wafer), process 600 can select a tensile film for backside deposition and stress relief at block 632.

[0048] At block 640, process 600 may continue by determining the type of material of the deformation compensation film to be deposited and the thickness d of the film. Figure 6 As shown by the dashed arrow in FIG, in some embodiments, the determination at block 640 may be based on the j} can be made by using multiple expansion coefficients of the parabola (not just the parabola bow coefficient A4) or the entire profile h(r, φ). In a specific non-limiting example, the thickness d can be determined as follows. First, a target parabola deformation sufficient to overcompensate for the measured wafer deformation can be determined. For example, for h(r, φ) < 0, the following conditions can be met:

[0049] In other words, the target parabola can be deformed is chosen to be large enough to compensate for parabola deformation (A4), saddle deformation (A5 and A6), and residual deformation (A7 and higher coefficients). In some embodiments, the target parabola can be deformed is selected to have at least one excess amplitude A relative to the minimum value required to overcompensate for wafer deformation E ,For example

[0050]

[0051] Excess Amplitude E The choice can be made empirically and may depend on the specific material used for the deformation compensating film.

[0052] Once the target parabola deformation is determined You can use table functions Or define the function in other ways The thickness d of the film is selected based on the calibration data of It can be a nonlinear function. In some embodiments, the function Can be a linear function The proportionality factor α is determined based on mathematical modeling of elastic equations, empirical calibration, or any combination thereof. At block 650, a deformation compensating film of a selected thickness d is deposited on the back side of the wafer. At block 660, a dose is calculated for the ion implantation. In some embodiments, the ion dose is calculated based on the expansion coefficients A5, A6 (to compensate for saddle deformation) and A7, A8, ... (to compensate for residual deformation). In some embodiments, the ion dose is calculated after a new measurement of the deformation of the wafer is made, which is made at block 650 (not shown). Figure 6 After that, and after redetermining the expansion coefficient {A j The calculated ion dose is then applied to the deposited thin film at block 670 .

[0053] Figure 7 is a flow chart illustrating an example process 700 for ion implantation performed to mitigate wafer deformation and stress in accordance with at least one embodiment. Process 700 may be performed as part of blocks 660-670 of process 600. At block 710, process 700 may include identifying saddle deformation and residual deformation of the wafer after a stress-compensating layer has been deposited on the wafer. In some embodiments, saddle deformation (e.g., Zernike coefficients A5, A6) and residual deformation (e.g., Zernike coefficients A7, A8, ...) may be estimated using profilometry performed before film deposition based on the assumption that, while parabolic bow deformation is strongly affected by film deposition, saddle deformation and residual deformation may remain substantially unaffected by film placement. In some embodiments, for improved accuracy, saddle deformation and residual deformation are determined based on profilometry performed after film deposition.

[0054] At block 720, process 700 may include performing a Monte Carlo simulation on the wafer and the deposited thin film. The Monte Carlo simulation may be performed on a thin film made of the actual material (or material compound) used for deposition and having a specific thickness d. An initial Monte Carlo simulation may be performed for specific baseline (preset) conditions for ion implantation (e.g., default settings for an ion implantation apparatus). The baseline conditions may include a preset ion type, a preset ion energy, a preset ion dose to be applied to the thin film (e.g., a default scan speed and a default scan pattern), and the like. The Monte Carlo simulation may use measurement data (calibration data) 722 collected for ion implantations actually performed for various ion energies, ion types, types and materials of deposited thin films, ion incidence angles on the thin film, and / or the like.

[0055] The measurement data 722 may include a characterization of the number of vacancies created by ions of different types and energies. Figure 8A Figure 2 shows the dependence of the number of vacancies created by ions of an implanted species in a silicon nitride film as a function of depth (distance traveled by the ions in angstroms), in accordance with at least one embodiment. The different curves correspond to phosphorus ions of different energies, such as 30 keV (low energy, solid line), 65 keV (medium energy, dotted line), and 100 keV (high energy, dashed line). It should be understood that this example is non-limiting and that many different energies (e.g., 10-500 keV or higher) of different species of ions (e.g., silicon, arsenic, gallium, argon, boron, carbon, and the like) can be used. As the ion energy increases, the number of vacancies created shifts toward greater depths. Figure 8BFigure 2 shows the estimated response of a 200 nm silicon nitride film to various doses of implanted species ions according to at least one embodiment. In one non-limiting example, the estimated response (ratio of bow change to initial bow) characterizes the effect of approximately 10 kilovolts of phosphorus ion implantation at different energies, such as 30 keV (low energy, solid line), 65 keV (mid energy, dotted line), and 100 keV (high energy, dashed line). 14 ions / cm 2 to about 10 16 ions / cm 2 The stress (e.g., tensile stress) induced in the film by various ion doses is shown in Figure 1. At low ion doses, the response is linear (where the slope increases with increasing ion energy), and as the ion dose increases, the response tends to saturate.

[0056] like Figure 8A As shown, a significant portion of the medium and high energy ions may pass through the 100 nm film and remain in the wafer as substitutional impurities. This may adversely affect the electrical (or mechanical) properties of the wafer. This can be prevented by changing the type of ions. In some embodiments, ion implantation can be performed using ions of the same type as the wafer material (e.g., silicon ions).

[0057] Figure 9 Figure 2 shows the dependence of the number of vacancies created by different types of ions as a function of depth, according to at least one embodiment. The different curves correspond to different species of ions, with AMUs ranging from 10 (low mass), 30 (medium mass), and 100 (high mass); all ions have the same energy. It should be understood that these examples are non-limiting, and that many other species of ions (e.g., hydrogen, silicon, arsenic, gallium, argon, boron, carbon, krypton, and the like) with different energies (e.g., 10-500 keV or higher) can be used.

[0058] Figure 10 The response of a 200 nm silicon nitride film as a function of ion dose for various ion types is shown, in accordance with at least one embodiment.

[0059] Figure 11 Figure 2 shows the ion distribution as a function of depth for different types of atomic implantation. The ion distribution is measured in atoms implanted per cubic centimeter.

[0060] The measurement data 722 may further include a characterization of the number of vacancies created by ions incident at different angles. Figure 12A The distribution of implanted ions at various angles of incidence is shown in accordance with at least one embodiment. The different curves correspond to phosphorus ions incident at angles of 0 degrees (normal incidence), 30 degrees, 45 degrees, and 60 degrees. Figure 12BThe number of created vacancies as a function of depth (distance traveled by the ions in angstroms) is shown as a function of ion incidence at various angles according to at least one embodiment. The different curves correspond to phosphorus ions incident at angles of 0, 30, 45, and 60 degrees. Figure 12A and Figure 12B As shown, increasing the incident angle decreases the depth of ion implantation and increases the number of deposited ions and vacancies created in the shallow region near the wafer surface. Figure 12C The response of a 200 nm silicon nitride film as a function of ion dose for various ion types is shown, in accordance with at least one embodiment.

[0061] Continue to refer Figure 7 The Monte Carlo simulation performed at block 720 may use the aforementioned measurement data 722 as well as any additional data. In some embodiments, the measurement data 722 may be statistically pre-processed. For example, various measurement data (such as the data shown in FIG8-FIG12 and the like) may be collected for a variety of film materials, ion types, incident angles, and / or other parameters. The statistically processed measurement data may be stored (e.g., in the memory of a processing device performing the Monte Carlo simulation) in the form of probability distributions of various quantities, including but not limited to:

[0062] Density distribution of ion implantation with depth for different ion types, ion energies, and incident angles;

[0063] The distribution of the number of vacancies generated at different depths (per unit ion travel length) for different ion types, ion energies, and incident angles;

[0064] The stress distribution created by the implanted ions for different ion implantation densities and / or the number of generated vacancies.

[0065] Performing a Monte Carlo simulation may include sampling from a stored distribution and identifying a given deformation compensation film of thickness d that will achieve the target stress relief with a preset ion implantation setting (e.g., as described above in conjunction with Figure 6The process 700 may include several verification operations designed to determine whether the target stress can be achieved without adversely affecting the properties of the wafer. For example, at block 725, the process 700 may include verifying whether the penetration depth of the selected (e.g., preset) ion type is sufficient. For example, the penetration depth may be at least a certain fraction of the thickness of the stress compensating layer, such as 20%, 30%, 50%, 80% or more of the thickness. In some embodiments, the penetration depth may be as high as 100% of the thickness. If the energy is insufficient, the process 700 may include checking at block 730 whether the ion beam implanter 110 is capable of outputting ions at a higher energy. If a higher energy is available, the process 700 may continue to increase the ion energy (block 740) and repeat the Monte Carlo simulation for the increased energy. If the maximum energy of the ion beam implanter 110 has been reached, the process 700 may continue by replacing the ions with ions of a different type (block 750) (eg, replacing silicon ions with boron, carbon, fluorine, etc. ions) and repeating the Monte Carlo simulation for the new type of ions.

[0066] At block 755, process 700 may include verifying whether the expected number of vacancies formed is sufficient. To verify sufficiency, process 700 may evaluate the stress relief caused by the formed vacancies. In one embodiment, process 700 may start with a certain stress value (e.g., -3.0 GPa or some other suitable value (a negative sign indicates compressive stress)) in the stress-compensating layer and use ion implantation to relieve this stress toward a neutral point (0.0 GPa) at various locations in the stress-compensating layer.

[0067] If the number of vacancies is insufficient, process 700 may include increasing the ion dose (at block 760) and repeating the Monte Carlo simulation for the increased dose.

[0068] At block 765, process 700 may include verifying that vacancies will be placed within a target depth, such as the thickness d of the film or a certain fraction of the film, such as 0.8d, 0.7d, 0.5d, or some other value empirically set to prevent ions from penetrating into the wafer and affecting wafer properties. If vacancies are formed at a depth exceeding the target depth, process 700 may include increasing the ion incidence angle (tilt of the ion beam implanter 110) and dose (at block 770) to keep the vacancies (and substitutional impurities) in a shallower region of the film.

[0069] Blocks 725-765 may be repeated multiple times until the Monte Carlo simulation predicts that the desired stress relief is achieved, such as a reduction in tensile stress in the deformation compensation film such that saddle deformation and residual deformation of the wafer are eliminated or at least reduced to acceptable tolerances. The final ion implantation settings determined based on the Monte Carlo simulation (at block 780) may then be used for ion implantation (at block 790).

[0070] To compensate for saddle and residual deformations, Monte Carlo simulations can be performed separately for different regions of the wafer to ensure that the position-dependent local stress σ xx (x, y) and σ yy (x,y) are lightened to the same or approximately the same uniform baseline value σ base Correspondingly, different regions of the deformation compensation film may receive different ion doses. In some cases, different regions of the deformation compensation film may receive ions with different incident directions.

[0071] Figure 13A An ion implantation system 1300 is schematically illustrated, capable of performing ion implantation into a stress-compensating layer, in accordance with at least one embodiment. The ion implantation system 1300 may be or include the ion beam implanter 110 of FIG. While for purposes of illustration, the stress mitigating beam used to modify stress in the stress-compensating layer 108 is referred to as an ion beam (e.g., ion beam 112), in some embodiments, the stress mitigating beam may include particles of other species (e.g., electrons), electromagnetic waves (e.g., ultraviolet light, visible light, infrared light, etc.), and / or suitable combinations thereof. The ion implantation system 1300 may include an ion source 1302 for generating an ion beam 1304. The ion source 1302 may include a chamber (e.g., a plasma chamber) for generating ions. The ion source 1302 may be powered by a power supply 1306 and may include an extraction electrode assembly (not shown). The ion implantation system 1300 may include a mass spectrometer 1308 and a collimating and focusing column 1310. The collimating and focusing column 1310 may direct the ion beam 112 toward the wafer 102. The wafer 102 can be supported by a support table 1312. In some embodiments, the support table 1312 and wafer 102 can remain stationary while components of the ion implantation system 1300 are repositioned relative to the wafer 102 while the ion beam 112 is scanned across the wafer 102. In some embodiments, the ion implantation system 1300 can remain stationary while the support table 1312 repositions the wafer 102. The ion beam 112 can be scanned in multiple directions, such as along the x-axis and along the y-axis according to any suitable predetermined pattern, such as back and forth along the x-axis, in a spiral pattern, etc. In various embodiments, the ion beam 112 can be scanned at a frequency of a few hertz, tens of hertz, hundreds of hertz, a few kilohertz, or higher.

[0072] The operation of the ion implantation system 1300 may be controlled by a controller 1314, which may include any suitable computing device, microcontroller, or any other processing device having a processor (e.g., a central processing unit (CPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and / or the like) and a memory element (e.g., a random access memory (RAM), a read-only memory (ROM), flash memory, and / or the like), or any combination thereof. The controller 1314 may control the operation of the power supply 1306, the support stage 1312, and / or various other components and modules of the ion implantation system 1300. The controller 1314 may include an ion beam simulation module 1316 that is capable of performing the operations described above in conjunction with Figure 7 -Simulation as described in Figure 12. In some embodiments, for example, Figure 13B As shown, support stage 1312 can apply a tilt to wafer 102 (e.g., in one or two spatial directions) to change the angle of incidence of ion beam 112 relative to wafer 102. In some embodiments, controller 1314 can tilt ion implantation system 1300 relative to wafer 102 rather than tilting wafer 102.

[0073] Figure 14 Described according to at least one embodiment, can support the block diagram of the example computer system 1400 of the operation of the present disclosure.In various illustrative examples, example computer system 1400 can be or include the controller 1314 of Figure 13.Example computer system 1400 can be connected with other computer systems in LAN, internal network, external network and / or the Internet.Computer system 1400 can operate as a server in a client-server network environment.Computer system 1400 can be a personal computer (PC), set-top box (STB), server, network router, switch or bridge, or any device that can execute a set of instructions (executed sequentially or otherwise) that specify the actions to be taken by the device.Further, although only a single example computer system is described, the term "computer" should also be considered to include the collection of any computers that execute a set (or multiple sets) of instructions to perform any one or more methods discussed herein, either individually or collectively.

[0074] The example computer system 1400 may include a processing device 1402 (also referred to as a processor or CPU), a main memory 1404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous dynamic random access memory (SDRAM), etc.), a static memory 1406 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory (e.g., a data storage device 1418), which may communicate with each other via a bus 1430.

[0075] Processing device 1402 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. Processing device 1402 includes processing logic 1426. Processing device 1402 can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 1402 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. In accordance with one or more aspects of the present disclosure, processing device 1402 can be configured to execute instructions for implementing the example process 600 for mitigating wafer stress and deformation and / or the example process 700 for performing ion implantation to mitigate wafer stress and deformation.

[0076] The example computer system 1400 may further include a network interface device 1408, which may be communicatively coupled to a network 1420. The example computer system 1400 may further include a video display 1410 (e.g., a liquid crystal display (LCD), a touch screen, or a cathode ray tube (CRT)), an alphanumeric input device 1412 (e.g., a keyboard), a cursor control device 1414 (e.g., a mouse), and an acoustic signal generating device 1416 (e.g., a speaker).

[0077] The data storage device 1418 may include a computer-readable storage medium (or more specifically, a non-transitory computer-readable storage medium) 1424 on which is stored one or more sets of executable instructions 1422. The executable instructions 1422 may include executable instructions for implementing the example process 600 for mitigating wafer stress and deformation and / or the example process 700 for performing ion implantation to mitigate wafer stress and deformation, in accordance with one or more aspects of the present disclosure.

[0078] The executable instructions 1422 may also reside, completely or at least partially, within the main memory 1404 and / or within the processing device 1402 during execution of such instructions by the example computer system 1400. The main memory 1404 and the processing device 1402 also constitute computer-readable storage media. The executable instructions 1422 may further be transmitted or received over a network via the network interface device 1408.

[0079] Although Figure 14While computer-readable storage medium 1424 is shown as a single medium, the term "computer-readable storage medium" should also be considered to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of operating instructions. The term "computer-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine, causing the machine to perform any one or more of the methods described herein. Thus, the term "computer-readable storage medium" should be considered to include (but not be limited to) solid-state memory and optical and magnetic media.

[0080] Some portions of the foregoing detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein, and generally, considered to be a self-consistent sequence of steps leading to a desired result. These steps are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It proves convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0081] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, it will be understood from the following discussion that discussions throughout the description utilizing terms such as "identify," "determine," "store," "adjust," "result in," "return," "compare," "create," "stop," "load," "copy," "throwing," "replace," "execute," or similar terms refer to actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the computer system's caches and memory into other data similarly represented as physical quantities within the computer system's memory or caches or other such information storage, transmission, or display devices.

[0082] Examples of the present disclosure also relate to an apparatus for performing the methods described herein. This apparatus may be specially constructed for the desired purpose, or it may be a general-purpose computer system selectively programmed by a computer program stored in the computer system. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic disk storage media, optical storage media, flash memory elements, other types of machine-accessible storage media, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0083] The methods and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may prove convenient to construct a more specialized device to perform the required method steps. The structures required for various such systems will appear in the following description. Furthermore, the scope of this disclosure is not limited to any particular programming language. It will be understood that various programming languages ​​may be used to implement the teachings of this disclosure.

[0084] It is to be understood that the above description is intended to be illustrative and not restrictive. Many other examples of implementations will be apparent to those skilled in the art upon reading and understanding the above description. Although this disclosure describes specific examples, it will be appreciated that the systems and methods of the present disclosure are not limited to the examples described herein, but may be practiced with modification within the scope of the appended claims. Accordingly, the specification and drawings should be viewed in an illustrative and not a restrictive sense. The scope of the present disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A method for correcting out-of-plane deformation of a substrate, the method comprising: identifying a profile of the out-of-plane deformation of the substrate using optical inspection data; performing a polynomial decomposition on the identified profile to determine a plurality of polynomial coefficients, each of the plurality of polynomial coefficients characterizing a corresponding one of a plurality of elemental deformed shapes of the substrate; identifying one or more characteristics of a stress compensating layer (SCL) for the substrate based on at least a subset of the plurality of polynomial coefficients; depositing the SCL on the substrate; performing a plurality of statistical simulations to identify settings for non-uniform stress mitigation irradiation of the SCL, wherein performing the plurality of statistical simulations comprises: sampling from one or more statistical distributions associated with previously performed stress mitigation irradiations; as well as The non-uniform stress mitigation irradiation of the SCL is performed using the identified settings, wherein the non-uniform stress mitigation irradiation is performed using a first setting for at least a first region of the SCL and a second setting for a second region of the SCL. 2 . The method of claim 1 , wherein the plurality of elemental deformation shapes of the substrate include a parabolic deformation of the substrate and a saddle-shaped deformation of the substrate.

3. The method of claim 2, wherein the polynomial decomposition of the identified contour comprises decomposing the identified contour by Zernike polynomials.

4. The method of claim 1 , wherein the one or more characteristics of the SCL include one or more of the following: the material of the SCL; or The thickness of the SCL.

5. The method of claim 1 , wherein the identified settings include one or more of: a particle type of a stress mitigation beam used for the non-uniform stress mitigation irradiation of the SCL; the energy of the particles of the stress mitigation beam; or An angle of incidence of the particles of the stress mitigation beam on the SCL.

6. The method of claim 1, wherein the SCL causes the substrate to overcorrect the out-of-plane deformation of the substrate, and wherein the non-uniform stress-relief irradiation relieves the overcorrected out-of-plane deformation of the substrate.

7. The method of claim 1 , wherein the non-uniform stress-relief irradiation of the SCL comprises ion implantation, and wherein the one or more statistical distributions comprise at least one of: a depth profile of said ion implantation of one or more types of ions and / or one or more energies of said ions; or The distribution of the number of created vacancies for one or more types of ions and / or one or more energies of said ions.

8. The method of claim 7, wherein one or more of the depth distribution or the distribution of the number of created vacancies depends on an angle of incidence of the ions on the SCL.

9. A system comprising: Memory; as well as a processing device, the processing device being communicatively coupled to the memory, the processing device being configured to: identifying a profile of out-of-plane deformation of the substrate using optical inspection data; performing a polynomial decomposition on the identified profile to determine a plurality of polynomial coefficients, each of the plurality of polynomial coefficients characterizing a corresponding one of a plurality of elemental deformed shapes of the substrate; identifying one or more characteristics of a stress compensating layer (SCL) for the substrate based on at least a subset of the plurality of polynomial coefficients; depositing the SCL on the substrate; performing a plurality of statistical simulations to identify settings for non-uniform stress mitigation irradiation of the SCL, wherein performing the plurality of statistical simulations comprises: sampling from one or more statistical distributions associated with previously performed stress mitigation irradiations; as well as The non-uniform stress mitigation irradiation of the SCL is performed using the identified settings, wherein the non-uniform stress mitigation irradiation is performed using a first setting for at least a first region of the SCL and a second setting for a second region of the SCL.

10. The system of claim 9, wherein the plurality of elemental deformed shapes of the substrate include a parabolic deformation of the substrate and a saddle-shaped deformation of the substrate.

11. The system of claim 9, wherein the polynomial decomposition of the identified contour comprises decomposing the identified contour by Zernike polynomials.

12. The system of claim 9, wherein the one or more characteristics of the SCL include one or more of the following: the material of the SCL; or The thickness of the SCL.

13. The system of claim 9, wherein the identified settings include one or more of: a particle type of a stress mitigation beam used for the non-uniform stress mitigation irradiation of the SCL; the energy of the particles of the stress mitigation beam; or An angle of incidence of the particles of the stress mitigation beam on the SCL.

14. The system of claim 9, wherein the SCL causes the substrate to overcorrect the out-of-plane deformation of the substrate, and wherein the non-uniform stress-relief irradiation relieves the overcorrected out-of-plane deformation of the substrate.

15. The system of claim 9, wherein the non-uniform stress mitigating irradiation of the SCL comprises ion implantation, and wherein the one or more statistical distributions comprise at least one of: a depth profile of said ion implantation of one or more types of ions and / or one or more energies of said ions; or The distribution of the number of created vacancies for one or more types of ions and / or one or more energies of said ions.

16. The system of claim 15, wherein one or more of the depth distribution or the distribution of the number of created vacancies depends on an angle of incidence of the ions on the SCL.

17. A semiconductor manufacturing system, comprising: one or more processing chambers for processing a substrate; as well as A computing device configured to: identifying a profile of out-of-plane deformation of the substrate using optical inspection data; performing a polynomial decomposition on the identified profile to determine a plurality of polynomial coefficients, each of the plurality of polynomial coefficients characterizing a corresponding one of a plurality of elemental deformed shapes of the substrate; identifying one or more characteristics of a stress compensating layer (SCL) for the substrate based on at least a subset of the plurality of polynomial coefficients; depositing the SCL on the substrate; performing a plurality of statistical simulations to identify settings for non-uniform stress mitigation irradiation of the SCL, wherein performing the plurality of statistical simulations comprises: sampling from one or more statistical distributions associated with previously performed stress mitigation irradiations; as well as The non-uniform stress mitigation irradiation of the SCL is performed using the identified settings, wherein the non-uniform stress mitigation irradiation is performed using a first setting for at least a first region of the SCL and a second setting for a second region of the SCL.

18. The semiconductor manufacturing system of claim 17, wherein the one or more characteristics of the SCL include one or more of the following: the material of the SCL; or The thickness of the SCL.

19. The semiconductor manufacturing system of claim 17, wherein the identified settings include one or more of the following: a particle type of a stress mitigation beam used for the non-uniform stress mitigation irradiation of the SCL; the energy of the particles of the stress mitigation beam; or An angle of incidence of the particles of the stress mitigation beam on the SCL.

20. The semiconductor manufacturing system of claim 17, wherein the non-uniform stress mitigating irradiation of the SCL comprises ion implantation, and wherein the one or more statistical distributions comprise at least one of: a depth profile of said ion implantation of one or more types of ions and / or one or more energies of said ions; or The distribution of the number of created vacancies for one or more types of ions and / or one or more energies of said ions.

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