Memory device, operating method of memory device, and memory module including memory device

Abstract

The invention provides a memory device, an operating method of the memory device, and a memory module including the memory device. The memory device includes a command decoder to receive a write command signal in synchronization with a clock signal, and to generate a write equalization pulse signal in response to the write command signal and in synchronization with the clock signal in a write equalization operation; a first write circuit for receiving a first data strobe signal at a first position on the data strobe signal path, first sampling a write equalization pulse signal in synchronization with the first data strobe signal in a write equalization operation, and outputting a first write equalization signal; and a second write circuit for receiving a second data strobe signal at a second position on the data strobe signal path, performing second sampling on the write equalization pulse signal in synchronization with the second data strobe signal in a write equalization operation, and outputting a second write equalization signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an electronic device, and more particularly, to a memory device that performs a write leveling operation with improved reliability, an operating method of the memory device, and a memory module including the memory device. Background Art

[0002] Memory devices are used to store data in computing devices such as computers, smartphones, and tablets. As the industries associated with these computing devices grow, the performance requirements for memory devices are also increasing. A key performance requirement for memory devices is communication speed. As overall performance expectations for memory devices increase, the demand for higher communication speeds is also growing.

[0003] To meet the demand for increased communication speeds in storage devices, the frequency of signals used to communicate with a host device may be increased. However, operating at higher communication frequencies may impair the storage device's ability to accurately receive signals at the correct timing, thereby potentially reducing communication reliability. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory device designed to improve reliability by achieving more accurate timing when receiving communication signals, a method of operating the memory device, and a memory module including the memory device.

[0005] According to an embodiment of the present disclosure, a memory device is provided, comprising: a memory cell array comprising a plurality of memory cells; a command decoder configured to receive a write command signal from a host device in synchronization with a clock signal received from the host device, and to generate a write equalization pulse signal in response to the write command signal and in synchronization with the clock signal in a write equalization operation; a data strobe signal path configured to transmit a data strobe signal received from the host device; a first write circuit configured to receive a first data strobe signal at a first position on the data strobe signal path, and to generate a write equalization pulse signal in synchronization with the clock signal in a write equalization operation; In a write equalization operation, the memory device performs a first sampling of the write equalization pulse signal in synchronization with the first data selection signal, and outputs a first write equalization signal based on the first sampling; and a second write circuit, the second write circuit being configured to receive a second data selection signal at a second position on the data selection signal path, perform a second sampling of the write equalization pulse signal in synchronization with the second data selection signal in the write equalization operation, and output a second write equalization signal based on the second sampling, wherein, in the write equalization operation, the memory device is configured to generate a feedback signal to be sent to the host device based on the first write equalization signal and the second write equalization signal.

[0006] According to an embodiment of the present disclosure, a method for operating a memory device is provided, the method comprising: performing a first write-leveling operation at the memory device to align timing between a clock signal and a data strobe signal received from a host device; and performing a second write-leveling operation at the memory device to align timing between an internal clock signal path through which the clock signal is transmitted and an internal data strobe signal path through which the data strobe signal is transmitted, wherein the second write-leveling operation is performed based on internal data strobe signals obtained at two or more locations on the internal data strobe signal path.

[0007] According to an embodiment of the present disclosure, a memory module is provided, which includes a plurality of memory devices, each memory device being configured to receive a data signal and a data select signal from a host device; and a register clock driver, the register clock driver being configured to receive a clock signal from the host device and provide the clock signal to the plurality of memory devices, wherein each of the plurality of memory devices is configured to: perform a first write equalization operation to align the timing of the clock signal provided from the register clock driver and the timing of the data select signal provided from the host device; and perform a second write equalization operation to align the timing between an internal clock signal path through which the clock signal is transmitted and an internal data select signal path through which the data select signal is transmitted, and wherein the second write equalization operation is performed based on the internal data select signal obtained at two or more positions on the internal data select signal path. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0009] Figure 1 A computing device according to an embodiment of the present disclosure is shown.

[0010] Figure 2 A storage module according to an embodiment of the present disclosure is shown.

[0011] Figure 3 An example of a method in which a computing device performs a write-leveling operation according to an embodiment of the present disclosure is shown.

[0012] Figure 4 A memory device according to an embodiment of the present disclosure is shown.

[0013] Figure 5 A first write circuit according to an embodiment of the present disclosure is shown.

[0014] Figure 6 Shown Figure 5 An example of a method for a memory device to perform a location-selective internal write-leveling operation.

[0015] Figure 7 A memory device according to an embodiment of the present disclosure is shown.

[0016] Figure 8 Shown Figure 7 An example of a method for a memory device to perform a location-selective internal write-leveling operation.

[0017] Figure 9A memory device according to an embodiment of the present disclosure is shown.

[0018] Figure 10 Shown Figure 9 An example of a method for a memory device to perform a location-selective internal write-leveling operation.

[0019] Figure 11 A memory device according to an embodiment of the present disclosure is shown.

[0020] Figure 12 Shown Figure 11 An example of a method for a memory device to perform a location-selective internal write-leveling operation.

[0021] Figure 13 An example of an operating method of a host device and a memory device is shown. DETAILED DESCRIPTION

[0022] The following sections will describe the embodiments of the present disclosure in detail and clearly so that those skilled in the art can easily implement the present disclosure.

[0023] Figure 1 FIG. 1 shows a computing device 10 according to an embodiment of the present disclosure. Figure 1 , the computing device 10 may include a host device 100 , a first storage device 210 , and a second storage device 220 .

[0024] The host device 100 may include a central processing unit (CPU) or an application processor (AP). The host device 100 may also include a hardware accelerator, such as a graphics processing unit (GPU) or a neural processing unit (NPU). The host device 100 may run an operating system and various applications. The host device 100 may include various devices, such as a modem for communicating with an external device, a storage device for storing data in a non-volatile manner, and a user interface for communicating with a user.

[0025] The host device 100 may include a memory controller 110. The memory controller 110 may control the first memory device 210 and the second memory device 220, and may access the first memory device 210 and the second memory device 220. The memory controller 110 may be implemented in hardware as a circuit.

[0026] The memory controller 110 may include a write leveling module 111. The write leveling module 111 may be implemented in hardware as a circuit. The write leveling module 111 may perform write leveling for each of the first memory device 210 and the second memory device 220. The write leveling operation may include adjusting the timing at which each of the first memory device 210 and the second memory device 220 latches (or captures) a data signal from the memory controller 110, and the timing at which the write operation is performed, during a write operation performed by the memory controller 110 on each of the first memory device 210 and the second memory device 220.

[0027] Each of the first and second storage devices 210 and 220 may include an external write leveling module EM and a location selection internal write leveling module LIM. Each of the external write leveling module EM and the location selection internal write leveling module LIM may be implemented in hardware as a circuit.

[0028] The external write leveling module EM may perform external write leveling under the control of the write leveling module 111 of the memory controller 110 . This operation aims to align any timing differences caused by external factors affecting the first and second memory devices 210 and 220 .

[0029] The location-selective internal write-leveling module LIM can address timing differences caused by internal factors within the first storage device 210 and the second storage device 220. The location-selective internal write-leveling module LIM supports internal write-leveling operations based on signals obtained from two or more locations along an internal signal path. By performing internal write-leveling operations based on these signals, operational reliability can be improved, thereby providing more accurate timing for data acquisition in each of the first storage device 210 and the second storage device 220.

[0030] The write leveling module 111 of the memory controller 110 may perform an external write leveling operation and a location-selective internal write leveling operation on each of the first memory device 210 and the second memory device 220. For example, these operations may be performed sequentially or simultaneously. The write leveling operation may include the external write leveling operation and the location-selective internal write leveling operation.

[0031] In an embodiment, the first storage device 210 or the second storage device 220 may be connected to the host device 100 together with another storage device that does not support the location-selective internal write-leveling operation (hereinafter referred to as a "non-supporting storage device"). The write-leveling module 111 may perform an external write-leveling operation on the first storage device 210 or the second storage device 220 and the non-supporting storage device in the same manner.

[0032] The write-leveling module 111 can perform a location-selective internal write-leveling operation on the first storage device 210 or the second storage device 220. For non-supporting storage devices that do not support this function, the write-leveling module 111 can instead perform a standard internal write-leveling operation, such as an operation based on a signal obtained from a single location. As another example, the write-leveling module 111 can perform a standard write-leveling operation on the non-supporting storage device while simultaneously performing a standard internal write-leveling operation on the first storage device 210 or the second storage device 220.

[0033] Figure 2 FIG. 3 shows a storage module 300 according to an embodiment of the present disclosure. Figure 1 and Figure 2 , the memory module 300 may include a memory device MEM, a register clock driver RCD (implemented as a circuit in hardware), and a power management device PMIC.

[0034] Each memory device MEM can communicate a data signal DQ and a data strobe signal DQS with an external device. Each memory device MEM can latch (or capture) the data signal DQ by using the data strobe signal DQS. An example in which the memory devices MEM are arranged in a matrix of two rows and nine columns is shown, but the number and arrangement of the memory devices MEM are not limited to this configuration.

[0035] Each memory device MEM may include an external write leveling module EM and a location-selective internal write leveling module LIM. The host device 100 may perform the external write leveling operation and the location-selective internal write leveling operation on each memory device MEM.

[0036] The register clock driver RCD may receive a command and address CA and a clock signal CK from an external device. The register clock driver RCD may jointly provide the command and address CA and the clock signal CK to the memory device MEM.

[0037] Each memory device MEM may latch (or capture) a command and an address CA by using a clock signal CK. Each memory device MEM may select a timing for performing an operation requested by the command and the address CA based on the clock signal CK.

[0038] The power management device PMIC may receive an input voltage from an external device. The power management device PMIC may convert the input voltage into an output voltage. The power management device PMIC may provide the output voltage to the memory device MEM. The power management device PMIC may provide the output voltage to the register clock driver RCD, or may provide another output voltage converted from the input voltage to the register clock driver RCD.

[0039] In an embodiment, the storage module 300 may correspond to the reference Figure 1 Alternatively, each memory device MEM of the memory module 300 may correspond to one of the first memory device 210 and the second memory device 220 described with reference to FIG. Figure 1 One of the first storage device 210 and the second storage device 220 is described.

[0040] The host device 100 may simultaneously or sequentially perform an external write leveling operation and a location-selective internal write leveling operation on the memory device MEM.

[0041] like Figure 1 and Figure 2 As shown, the data signal DQ and the data strobe signal DQS may be directly transmitted from the host device 100 to the memory device MEM. The clock signal CK and the command and address CA are transmitted from the host device 100 to the memory device MEM through the register clock driver RCD.

[0042] The paths through which commands and addresses CA and clock signal CK are transmitted on the memory module 300 may vary in length. This variation in path length may cause inconsistent timing of clock signal CK and commands and addresses CA reaching the memory device MEM.

[0043] The external write leveling operation can align (or correct) timing differences caused by external factors affecting the memory device MEM. For example, by performing the external write leveling operation, the host device 100 can adjust the timing for transmitting the data signal DQ and the data strobe signal DQS so that the data signal DQ, the data strobe signal DQS, the clock signal CK, and the command and address CA arrive at each memory device MEM simultaneously and synchronously.

[0044] In an embodiment, the memory module 300 may communicate with an external device using a dual in-line memory module (DIMM), a registered DIMM (RDIMM), or a load reduced DIMM (LRDIMM) configuration.

[0045] Figure 3 An example of a method in which the computing device 10 performs a write-leveling operation according to an embodiment of the present disclosure is shown. Figure 1 、 Figure 2 and Figure 3 , in operation S110 , operation S120 , and operation S130 , the computing device 10 may perform an external write-leveling operation.

[0046] In operation S110, the host device 100 may request the memory device MEM to enter an external write-leveling operation. For example, the memory controller 110 of the host device 100 may enter the external write-leveling operation by programming the second mode register of the memory device MEM. For example, the memory controller 110 may enter the external write-leveling operation by programming "1" (=MR2:OP[1]) in the second mode register MR2 of the memory device MEM.

[0047] In operation S120, the host device 100 and the memory device MEM may perform an external write leveling operation. The host device 100 may send a command and address CA indicating a write operation, a clock signal CK, and a data strobe signal DQS to the memory device MEM. In an embodiment, the host device 100 may send a write preamble as the data strobe signal DQS along with a signal toggled by a fraction of the burst length. For example, the host device 100 may send a signal including the write preamble and a single toggled signal as the data strobe signal DQS.

[0048] The memory device MEM may detect whether a high level of the clock signal CK is latched (or captured) by a rising edge (or falling edge) of the data strobe signal DQS.

[0049] For example, the memory device MEM may generate a write equalization pulse signal based on the command and address CA and the clock signal CK. The memory device MEM may output the level of the write equalization pulse signal latched (or captured) by the rising edge (or falling edge) of the data strobe signal DQS as the data signal DQ (e.g., as a feedback signal).

[0050] Until a high level of the write equalization pulse signal is detected from the memory device MEM, the memory controller 110 may repeat the following operations while scanning the data strobe signal DQS: sending a command and address CA, the data strobe signal DQS, and the clock signal CK to the memory device MEM, and receiving a feedback signal from the memory device MEMS. When a high level of the write equalization pulse signal is detected from the memory device MEM, the memory controller 110 may add an offset (e.g., 1 / 4 of the period of the data strobe signal DQS) to the detected high level timing from the memory device MEM (or subtract the offset (e.g., 1 / 4 of the period of the data strobe signal DQS) from the detected high level timing from the memory device MEM), and then determine the timing of the corresponding data strobe signal DQS for each memory device MEM.

[0051] In operation S130 , the host device 100 may request the memory device MEM to exit the external write leveling operation. For example, the memory controller 110 may exit the external write leveling operation by programming “0” (=MR2:OP[1]) in the second mode register MR2 of the memory device MEM.

[0052] In operations S140 , S150 , and S160 , the computing device 10 may perform a location-selective internal write-leveling operation.

[0053] In operation S140, the host device 100 may request the memory device MEM to enter a position-selected internal write-leveling operation. For example, the memory controller 110 of the host device 100 may enter the internal write-leveling operation by programming the second mode register MR2 of the memory device MEM. For example, the memory controller 110 may enter the internal write-leveling operation by programming "1" (=MR2:OP[7]) in the second mode register MR2 of the memory device MEM.

[0054] In operation S150, the host device 100 and the memory device MEM may perform an internal write-leveling operation based on the internal data strobe signal iDQS. For example, the host device 100 and the memory device MEM may perform a position-selective internal write-leveling operation.

[0055] The host device 100 can set the delay amount of the write equalization pulse signal in the memory device MEM by programming the third mode register MR3 of the memory device MEM. For example, the host device 100 can set the write equalization pulse signal delay by programming the write leveling inner cycle alignment (WICA) setting of the third mode register MR3 of the memory device MEM.

[0056] The host device 100 may transmit a command and address CA indicating a write operation, a clock signal CK, and a data strobe signal DQS to the memory device MEM. In an embodiment, the host device 100 may transmit a write preamble as the data strobe signal DQS along with a signal toggled by a fraction of the burst length. For example, the host device 100 may transmit a signal including the write preamble and a single toggle as the data strobe signal DQS.

[0057] The memory device MEM may internally use the received data strobe signal DQS as the internal data strobe signal iDQS. The memory device MEM may detect whether the high level of the clock signal CK is latched (or captured) by the rising edge (or falling edge) of the internal data strobe signal iDQS at two or more locations along the internal data strobe signal path through which the internal data strobe signal iDQS is transmitted.

[0058] For example, the memory device MEM may generate a write equalization pulse signal based on the command and address CA and the clock signal CK. The memory device MEM may output the level of the write equalization pulse signal latched (or captured) by the rising edge (or falling edge) of the internal data strobe signal iDQS as the data signal DQ (e.g., as a feedback signal).

[0059] Until a high level of the write equalization pulse signal is detected from the memory device MEM, the memory controller 110 may repeat the following operations while scanning the delay amount of the write equalization pulse signal stored in the third mode register MR3 of the memory device MEM: transmitting a command and address CA, a data strobe signal DQS, and a clock signal CK to the memory device MEM, and receiving a feedback signal from the memory device MEM. When a high level of the write equalization pulse signal is detected from all the memory devices MEM, the memory controller 110 may program a delay amount obtained by adding an offset (e.g., 1 / 4 of the period of the data strobe signal DQS) to the detected high level timing (or subtracting the offset (e.g., 1 / 4 of the period of the data strobe signal DQS) from the detected high level timing) in the third mode register MR3 of each memory device MEM as a WICA setting.

[0060] In operation S160 , the host device 100 may request the memory device MEM to exit the internal write leveling operation. For example, the memory controller 110 may exit the internal write leveling operation by programming “0” (=MR2:OP[7]) in the second mode register MR2 of the memory device MEM.

[0061] Figure 4 FIG shows a memory device 400 according to an embodiment of the present disclosure. In an embodiment, the memory device 400 may correspond to Figure 1 one of the first storage device 210 and the second storage device 220, or Figure 2 One of the memory devices MEM of the memory module 300 .

[0062] Reference Figure 1 and Figure 4 , the memory device 400 may include a command and address pad CAP, a clock signal pad CKP, a data strobe signal pad DQSP, and a data signal pad DQP. The command and address pad CAP may receive a command and address CA from the host device 100. The clock signal pad CKP may receive a clock signal CK from the host device 100. The data strobe signal pad DQSP may receive a data strobe signal DQS from the host device 100 or may transmit the data strobe signal DQS to the host device 100. The data signal pad DQP may receive a data signal DQ from the host device 100 or may transmit the data signal DQ to the host device 100.

[0063] The memory device 400 may further include a command and address buffer CAB, a clock buffer CKB, a command and address sampler CAS, and a command decoder CMDD, each of which is implemented in hardware as a circuit. The command and address buffer CAB may buffer commands and addresses CA received via the command and address pads CAP. The clock buffer CKB may buffer the clock signal CK received via the clock signal pads CKP. The command and address sampler CAS may sample commands and addresses CA output from the command and address buffer CAB in synchronization with the clock signal CK output from the clock buffer CKB.

[0064] The command decoder CMDD may receive the command and address CA sampled by the command and address sampler CAS and may output various command signals (eg, pulse signals) for controlling the operation of the memory device 400 based on the sampled command and address CA.

[0065] In particular, when the sampled command and address CA indicates a write operation, the command decoder CMDD may output a first write command WR_CMD1, a second write command WR_CMD2, and a third write command WR_CMD3. The first write command WR_CMD1, the second write command WR_CMD2, and the third write command WR_CMD3 may be signals converted at different times, for example, having different column write delays (CWLs).

[0066] In an external write-leveling operation or a position-selective internal write-leveling operation, when the sampled command and address CA indicate a write operation, the command decoder CMDD may output a write-leveling pulse signal WL_PUL. The write-leveling pulse signal WL_PUL may be a pulse signal that transitions at a default timing and reaches a high level (e.g., at CWL0, CWL1, and CWL2).

[0067] The memory device 400 may also include a data strobe signal generator DQSG, a read data strobe buffer DQSBR, and a write data strobe buffer DQSBW, each of which is implemented as a hardware circuit. After receiving a command and address CA indicating a read operation, the data strobe signal generator DQSG may generate a data strobe signal DQS based on a clock signal CK output from a clock buffer CKB at a specified timing. The read data strobe buffer DQSBR may then buffer the data strobe signal DQS output from the data strobe signal generator DQSG and output the data strobe signal DQS to the host device 100 via a data strobe signal pad DQSP.

[0068] For example, in a write operation or a write-leveling operation, the write data strobe buffer DQSBW may receive a data strobe signal DQS from the host device 100 via the data strobe signal pad DQSP. The write data strobe buffer DQSBW may buffer the data strobe signal DQS and may transmit an internal data strobe signal iDQS to an internal data strobe signal path. For example, the internal data strobe signal path may include a first path PT1, a second path PT2 following the first path PT1, and a third path PT3 following the second path PT2. In an embodiment, the internal data strobe signal path may include one or more buffers configured to buffer the internal data strobe signal iDQS.

[0069] The memory device 400 may also include a write data buffer DQBW (implemented in hardware as a circuit), a first write circuit WC1, a second write circuit WC2, a third write circuit WC3, a storage body BK (implemented in hardware as a circuit), a read circuit RC and a read data buffer DQBR (implemented in hardware as a circuit).

[0070] The write data buffer DQBW may receive the data signal DQ through the data signal pad DQP from the host device 100. The write data buffer DQBW may transmit the data signal DQ to the first write circuit WC1.

[0071] The first write circuit WC1 can receive a first write command WR_CMD1 and a write equalization pulse signal WL_PUL from the command decoder CMDD. For example, during a write operation, the first write circuit WC1 can receive the first write command WR_CMD1 from the command decoder CMDD. During a write equalization operation, the first write circuit WC1 can receive the write equalization pulse signal WL_PUL from the command decoder CMDD.

[0072] The first write circuit WC1 can receive the first internal data strobe signal iDQS1 obtained at the location where the internal data strobe signal iDQS passes through the first path PT1. In other words, the first write circuit WC1 can receive the first internal data strobe signal iDQS1 generated at the point where the internal data strobe signal iDQS passes through the first path PT1. The first write circuit WC1 can sample the data signal DQ transmitted from the write data buffer DQBW in synchronization with the first internal data strobe signal iDQS1 in response to the first write command WR_CMD1 or the write equalization pulse signal WL_PUL. For example, the first write circuit WC1 can latch (or capture) the data signal DQ output from the write data buffer DQBW at the rising edge (or falling edge) of the first internal data strobe signal iDQS1 in response to the rising edge (or falling edge) of the first write command WR_CMD1 or the write equalization pulse signal WL_PUL.

[0073] During a write operation, the first write circuit WC1 can support a write operation for writing a data signal DQ to a memory bank BK. For example, the first write circuit WC1 can perform various operations to support the write operation, including removing or suppressing noise on the data signal DQ, realigning the timing of the data signal DQ, decoding the data signal DQ, initializing (or preparing) a path for transmitting the data signal DQ, or serializing the data signal DQ. The first write circuit WC1 can output the processed data signal DQ to the second write circuit WC2.

[0074] In the external write leveling operation, the first write circuit WC1 may sample the write leveling pulse signal WL_PUL and output the result as a first write leveling output signal WLO1 synchronized with the first internal data strobe signal iDQS1 .

[0075] In the position-selective internal write-leveling operation, the first write circuit WC1 may sample the write-leveling pulse signal WL_PUL in synchronization with the first internal data strobe signal iDQS1 and output the result as the first write-leveling output signal WLO1 .

[0076] The second write circuit WC2 can receive the second internal data strobe signal iDQS2 obtained at a position on the second path PT2 after the internal data strobe signal iDQS passes through the first path PT1. In other words, the second write circuit WC2 can receive the second internal data strobe signal iDQS2 obtained at a point where the internal data strobe signal iDQS passes through the second path PT2 following the first path PT1. The second write circuit WC2 can sample the data signal DQ transmitted from the first write circuit WC1 in synchronization with the second internal data strobe signal iDQS2 in response to the second write command WR_CMD2 or the write equalization pulse signal WL_PUL. For example, in response to the rising edge (or falling edge) of the second write command WR_CMD2 or the write equalization pulse signal WL_PUL, the second write circuit WC2 can latch (or capture) the data signal DQ output from the first write circuit WC1 at the rising edge (or falling edge) of the second internal data strobe signal iDQS2.

[0077] During a write operation, the second write circuit WC2 can support a write operation for writing a data signal DQ to the memory bank BK. For example, the second write circuit WC2 can perform various operations to support the write operation, including removing or suppressing noise on the data signal DQ, realigning the timing of the data signal DQ, decoding the data signal DQ, initializing (or preparing) a path for transmitting the data signal DQ, or serializing the data signal DQ. The second write circuit WC2 can output the processed data signal DQ to the third write circuit WC3.

[0078] In the position-selective internal write-leveling operation, the second write circuit WC2 samples the write-leveling pulse signal WL_PUL and outputs the result as a second write-leveling output signal WLO2 synchronized with the second internal data strobe signal iDQS2.

[0079] The third write circuit WC3 can receive a third internal data strobe signal iDQS3 obtained at a location where the internal data strobe signal iDQS crosses a third path PT3 that follows the first path PT1 and the second path PT2. In other words, the third write circuit WC3 can receive the third internal data strobe signal iDQS3 obtained at a point where the internal data strobe signal iDQS crosses the third path PT3 that follows the first path PT1 and the second path PT2. The third write circuit WC3 can sample the data signal DQ transmitted from the second write circuit WC2 in synchronization with the third internal data strobe signal iDQS3 in response to a third write command WR_CMD3 or a write equalization pulse signal WL_PUL. For example, in response to a rising edge (or falling edge) of the third write command WR_CMD3 or the write equalization pulse signal WL_PUL, the third write circuit WC3 can latch (or capture) the data signal DQ output from the second write circuit WC2 at a rising edge (or falling edge) of the third internal data strobe signal iDQS3.

[0080] During a write operation, the third write circuit WC3 can support the write operation for writing the data signal DQ to the memory bank BK. For example, the third write circuit WC3 can perform various operations to support the write operation, including removing or suppressing noise on the data signal DQ, realigning the timing of the data signal DQ, decoding the data signal DQ, initializing (or preparing) a path for transmitting the data signal DQ, or serializing the data signal DQ. The third write circuit WC3 can then output the processed data signal DQ to the memory bank BK.

[0081] In the position-selective internal write-leveling operation, the third write circuit WC3 may sample the write-leveling pulse signal WL_PUL and output the result as a third write-leveling output signal WLO3 synchronized with the third internal data strobe signal iDQS3 .

[0082] The memory bank BK may be used to store data and may include a memory cell array MCA, a row decoder RDEC, a write driver DRV, a sense amplifier ISA, and a column decoder CDEC.

[0083] The memory cell array MCA may include a plurality of memory cells arranged in rows and columns. A row decoder RDEC may be connected to the rows of memory cells and may select a row of memory cells. A write driver DRV may be connected to the columns of memory cells and may write data to the memory cells in the row selected by the row decoder RDEC. A sense amplifier ISA may be connected to the columns of memory cells and may read data from the memory cells in the row selected by the row decoder RDEC.

[0084] The column decoder CDEC may be connected to columns of memory cells and may select a column of memory cells. The column decoder CDEC may provide a data signal DQ transmitted from the third write circuit WC3 to the write driver DRV of the selected column. The column decoder CDEC may output data stored in the sense amplifier ISA of the selected column.

[0085] In an embodiment, the memory bank BK may operate in response to a command transmitted from the command decoder CMDD. For example, the memory bank BK may operate in response to at least one of the first write command WR_CMD1, the second write command WR_CMD2, the third write command WR_CMD3, or a command signal having a timing different from that of the first write command WR_CMD1, the second write command WR_CMD2, and the third write command WR_CMD3.

[0086] In an embodiment, Figure 4 , one memory bank BK is shown, but the memory device 400 may include two or more memory banks. The memory device 400 may include two or more memory bank groups, and each memory bank group may include two or more memory banks. The memory bank group and the memory bank may be identified by the memory bank group address and the memory bank address of the command and address CA, respectively.

[0087] In an embodiment, at least one of the first write circuit WC1, the second write circuit WC2, and the third write circuit WC3 may be included in the memory bank BK. At least one of the first write circuit WC1, the second write circuit WC2, and the third write circuit WC3 may be implemented using at least one of a row decoder RDEC, a write driver DRV, a sense amplifier ISA, and a column decoder CDEC, or a portion of at least one of them.

[0088] In a read operation, the read circuit RC may receive the data signal DQ output from the column decoder CDEC and perform various operations to support the read operation, such as parallelizing the data signal DQ or pre-emphasizing the data signal DQ.

[0089] During an external write-leveling operation, the read circuit RC can receive a first write-leveling output signal WLO1 from the first write circuit WC1. The read circuit RC can transmit the first write-leveling output signal WLO1 to the read data buffer DQBR. In other words, during an external write-leveling operation, the memory device 400 can generate a write-leveling pulse signal WL_PUL using the command decoder CMDD and sample the write-leveling pulse signal WL_PUL in synchronization with the first internal data strobe signal iDQS1 using the first write circuit WC1. The memory device 400 can output the first write-leveling output signal WLO1, which is the sampling result, to the host device 100 via the data signal pad DQP.

[0090] In other words, during the external write-leveling operation, the host device 100 and the memory device 400 can align (or synchronize) the timing at which the write-leveling pulse signal WL_PUL and the first internal data strobe signal iDQS1 arrive at the first write circuit WC1. During the external write-leveling operation, since the write-leveling pulse signal WL_PUL is synchronized with the clock signal CK, the host device 100 and the memory device 400 align the clock signal CK and the first internal data strobe signal iDQS1 in the first write circuit WC1. When the external write-leveling operation is completed, the host device 100 can align the clock signal CK and the data strobe signal DQS by adding an offset to (or subtracting an offset from) the aligned timing to output the data strobe signal DQS to the memory device 400.

[0091] In the position selection internal write leveling operation, the read circuit RC may output one of the first write leveling output signal WLO1 , the second write leveling output signal WLO2 , and the third write leveling output signal WLO3 to the read data buffer DQBR.

[0092] The memory device 400 may further include control logic CL (implemented in hardware as a circuit). The control logic CL may control the operation of the memory device 400. The control logic CL may include a mode register set MRS and a test mode register set TMRS. The mode register set MRS may include multiple registers for setting the operating mode of the memory device 400. For example, the mode register set MRS may include the second mode register MR2 and the third mode register MR3 described above. The test mode register set TMRS may include multiple test mode registers for setting multiple pieces of information to perform tests.

[0093] In an embodiment, the first internal data strobe signal iDQS1 passes through the first path PT1 from the write data strobe buffer DQSBW. The first internal data strobe signal iDQS1 may have a delay corresponding to the time taken to pass through the first path PT1 compared to the data strobe signal DQS.

[0094] The second internal data strobe signal iDQS2 passes through the first path PT1 and the second path PT2 from the write data strobe buffer DQSBW. Compared to the first internal data strobe signal iDQS1, the second internal data strobe signal iDQS2 may have a delay corresponding to the time taken to pass through the second path PT2.

[0095] The third internal data strobe signal iDQS3 passes through the first path PT1, the second path PT2, and the third path PT3 from the write data strobe buffer DQSBW. Compared with the first internal data strobe signal iDQS1, the third internal data strobe signal iDQS3 may have a delay corresponding to the time taken to pass through both the second path PT2 and the third path PT3. In addition, compared with the second internal data strobe signal iDQS2, the third internal data strobe signal iDQS3 may have a delay corresponding to the time taken to pass through the third path PT3.

[0096] As the frequency of the data strobe signal DQS increases and its period decreases, delay differences among the first internal data strobe signal iDQS1, the second internal data strobe signal iDQS2, and the third internal data strobe signal iDQS3 may affect the reliability of the memory device 400. Specifically, process, voltage, and temperature (PVT) variations affecting the memory device 400 may amplify the reliability impact associated with these delay differences.

[0097] According to embodiments of the present disclosure, the host device 100 and the memory device 400 can perform location-selective internal write-leveling operations based on internal data strobe signals obtained at different locations. The host device 100 and the memory device 400 can select locations where the first, second, and third write circuits WC1, WC2, and WC3 can appropriately sample the data signal DQ as final write-leveling locations. Consequently, the timing at which the memory device 400 samples the data signal DQ becomes more accurate, and the reliability of the memory device 400 is improved.

[0098] Figure 5 FIG. 1 shows a first writing circuit WC1 according to an embodiment of the present disclosure. Figure 4 and Figure 5 , the first write circuit WC1 may include a multiplexer MUX, a write circuit sampler WCS, an AND gate AG and a core circuit CC.

[0099] The multiplexer MUX may receive a first write command WR_CMD1 and a write equalization pulse signal WL_PUL. The multiplexer MUX may output one of the first write command WR_CMD1 and the write equalization pulse signal WL_PUL in response to a write equalization enable signal WL_EN. For example, when the write equalization enable signal WL_EN is active, the multiplexer MUX may output the write equalization pulse signal WL_PUL. When the write equalization enable signal WL_EN is in an inactive state, the multiplexer MUX may output the first write command WR_CMD1. For example, the write equalization enable signal WL_EN may be received from the control logic CL and activated during both an external write equalization operation and a position selection internal write equalization operation.

[0100] The write circuit sampler WCS may sample the output of the multiplexer MUX in synchronization with the first internal data strobe signal iDQS1 , and the sampling result from the write circuit sampler WCS is then transmitted to the core circuit CC and the AND gate AG.

[0101] AND gate AG can receive the output signal of write circuit sampler WCS and write equalization enable signal WL_EN. When the output signal of write circuit sampler WCS and write equalization enable signal WL_EN are both at a high level, AND gate AG can output a first write equalization output signal WLO1 at a high level. When at least one of the output signal of write circuit sampler WCS and write equalization enable signal WL_EN is at a low level, AND gate AG can output a first write equalization output signal WLO1 at a low level.

[0102] In other words, when the write-leveling enable signal WL_EN is at a high level indicating that a write-leveling operation is being performed, the AND gate AG can output the output signal of the write circuit sampler WCS as the first write-leveling output signal WLO1. The output signal of the write circuit sampler WCS is the result of sampling the write-leveling pulse signal WL_PUL in synchronization with the first internal data strobe signal iDQS1.

[0103] The core circuit CC can receive the output signal of the write circuit sampler WCS and can receive the data signal DQ from the write data buffer DQBW. When the output of the write circuit sampler WCS is at a high level, the core circuit CC can perform a specific operation on the data signal DQ. In other words, during a write operation, when a high-level first write command WR_CMD1 is received synchronously with the first internal data strobe signal iDQS1, the core circuit CC can process the data signal DQ by performing a specific operation on the data signal DQ. The core circuit CC can then output the processed data signal DQ to the second write circuit WC2.

[0104] The configuration of the second write circuit WC2 is similar to that of the first write circuit WC1, but there are some differences: the second write circuit WC2 receives a second write command WR_CMD2 instead of the first write command WR_CMD1, it receives an internal write equalization signal (e.g., IWL_EN) activated in a position-selective internal write equalization operation instead of the write equalization enable signal WL_EN, it receives a second internal data strobe signal iDQS2 instead of the first internal data strobe signal iDQS1, it outputs a second write equalization output signal WLO2 instead of the first write equalization output signal WLO1, it receives a data signal DQ from the first write circuit WC1 instead of the write data buffer DQBW, and the processed data signal DQ is output to the third write circuit WC3. Therefore, to avoid redundancy, additional description will be omitted.

[0105] In addition, the configuration of the third write circuit WC3 is similar to that of the first write circuit WC1, but there are some differences: the third write circuit WC3 receives a third write command WR_CMD3 instead of the first write command WR_CMD1, it receives an internal write equalization signal (e.g., IWL_EN) activated in a position selection internal write equalization operation instead of the write equalization enable signal WL_EN, it receives a third internal data strobe signal iDQS3 instead of the first internal data strobe signal iDQS1, it outputs a third write equalization output signal WLO3 instead of the first write equalization output signal WLO1, it receives a data signal DQ from the second write circuit WC2 instead of the write data buffer DQBW, and the processed data signal DQ is output to the memory bank BK. Therefore, additional description will be omitted to avoid redundancy.

[0106] Figure 6 Shown Figure 4 An example of a method of performing a location-selective internal write-leveling operation in a memory device 400. Figure 1 、 Figure 4 and Figure 6 In operation S210, the host device 100 may select a position of the internal data strobe signal iDQS in the memory device 400. For example, the host device 100 may select one of the first internal data strobe signal iDQS1, the second internal data strobe signal iDQS2, and the third internal data strobe signal iDQS3 by programming a specific test mode register of the test mode register set TMRS of the control logic CL of the memory device 400.

[0107] In operation S220, the host device 100 may select a delay amount of the write equalization pulse signal WL_PUL. For example, the host device 100 may select a delay amount of the write equalization pulse signal WL_PUL corresponding to the selected internal data strobe signal iDQS by programming the delay amount in the third mode register MR3 of the mode register set MRS of the control logic CL of the memory device 400.

[0108] In operation S230, the host device 100 may transmit a command indicating write WR and an address CA and a data strobe signal DQS to the memory device 400. The host device 100 may transmit the data strobe signal DQS including a write preamble and at least one toggle to the memory device 400.

[0109] The command decoder CMDD of the memory device 400 may output a write equalization pulse signal WL_PUL in response to the command indicating write WR and the address CA. The write equalization pulse signal WL_PUL may have a delay amount corresponding to information programmed in the third mode register MR3.

[0110] In operation S240, the memory device 400 may send feedback to the host device 100. In an embodiment, the first write circuit WC1, the second write circuit WC2, and the third write circuit WC3 may respectively send a first write equalization output signal WLO1, a second write equalization output signal WLO2, and a third write equalization output signal WLO3 to the read circuit RC. The read circuit RC may provide the host device 100 with a write equalization output signal corresponding to the selected internal data strobe signal iDQS among the first write equalization output signal WLO1, the second write equalization output signal WLO2, and the third write equalization output signal WLO3 as the data signal DQ via the data signal pad DQP.

[0111] As another example, the write circuit corresponding to the selected internal data strobe signal iDQS among the first write circuit WC1, the second write circuit WC2, and the third write circuit WC3 can output a corresponding write equalization output signal to the read circuit RC. The read circuit RC can provide the received write equalization output signal as the data signal DQ to the host device 100 through the data signal pad DQP.

[0112] In operation S250, the host device 100 may determine whether the write equalization pulse signal WL_PUL is detected. For example, when the feedback provided from the memory device 400 is a high-level (or low-level) signal, the host device 100 may determine that the write equalization pulse signal WL_PUL is detected. When the feedback provided from the memory device 400 is a low-level (or high-level) signal, the host device 100 may determine that the write equalization pulse signal WL_PUL is not detected.

[0113] When the write equalization pulse signal WL_PUL is not detected, the host device 100 may select the delay amount of the write equalization pulse signal WL_PUL again. In other words, operation S220 is performed again. Thereafter, the host device 100 and the memory device 400 may perform operations S230, S240, and S250 again. In other words, until the write equalization pulse signal WL_PUL is detected, the host device 100 and the memory device 400 may scan the delay amount of the write equalization pulse signal WL_PUL.

[0114] When the write equalization pulse signal WL_PUL is detected, the host device 100 may store a delay amount of the write equalization pulse signal WL_PUL corresponding to the selected internal data strobe signal iDQS. The delay amount indicates a specific time point at which the write equalization pulse signal WL_PUL is detected. Then, operation S260 is performed.

[0115] In operation S260, the host device 100 may determine whether the selected position is the last position. This involves evaluating all targets of the position selection internal write leveling operation, in other words, the first internal data strobe signal iDQS1, the second internal data strobe signal iDQS2, and the third internal data strobe signal iDQS3, and the host device 100 may determine whether the delay amount of the write leveling pulse signal WL_PUL is detected for each.

[0116] When the selected position is not the last position, the host device 100 may select the next internal data strobe signal iDQS. In other words, operation S210 is performed again. Thereafter, the host device 100 and the memory device 400 may perform operations S220, S230, S240, S250, and S260. In other words, until the delay amount of the write equalization pulse signal WL_PUL is detected for each internal data strobe signal, the host device 100 and the memory device 400 may sequentially select internal data strobe signals and detect the delay amount of the corresponding write equalization pulse signal WL_PUL.

[0117] When the selected position is the last position, in operation S270, the host device 100 may select a final internal data strobe signal (iDQS) position. For example, based on the corresponding delay amounts of the internal data strobe signal and the write equalization pulse signal, the host device 100 may select a delay amount of the write equalization pulse signal WL_PUL that enables appropriate sampling of the data signal DQ in the first write circuit WC1, the second write circuit WC2, and the third write circuit WC3. The host device 100 may select the internal data strobe signal (iDQS) position corresponding to the selected delay amount of the write equalization pulse signal WL_PUL as the final internal data strobe signal (iDQS) position.

[0118] In operation S280, the host device 100 may program the final internal data strobe signal (iDQS) position and the corresponding delay amount in the memory device 400. For example, the host device 100 may program information of the final internal data strobe signal (iDQS) position in a specific test mode register of the test mode register group TMRS of the control logic CL of the memory device 400. For example, the host device 100 programs information of the second internal data strobe signal iDQS2 in the test mode register.

[0119] The host device 100 may program the delay amount of the write leveling pulse signal WL_PUL corresponding to the second internal data strobe signal iDQS2 in the third mode register MR3 of the mode register set MRS of the control logic CL of the memory device 400. Thereafter, the position selection internal write leveling operation may be exited.

[0120] In an embodiment, in a write operation, the first, second, and third write commands WR_CMD1, WR_CMD2, and WR_CMD3 may be activated in synchronization with a clock signal CK having a specific time difference (e.g., a CWL difference). The first, second, and third write commands WR_CMD1, WR_CMD2, and WR_CMD3 may be delayed relative to the clock signal CK by a delay amount programmed in the third mode register MR3 and then activated.

[0121] Figure 7 Schematic diagram of a memory device 500 according to an embodiment of the present disclosure. Figure 1 and Figure 7The memory device 500 may include a command and address pad CAP, a command and address buffer CAB, a clock signal pad CKP, a clock buffer CKB, a data strobe signal pad DQSP, a write data strobe buffer DQSBW, a read data strobe buffer DQSBR, a data signal pad DQP, a write data buffer DQBW, a read data buffer DQBR, a command and address sampler CAS, a command decoder CMDD, a data strobe signal generator DQSG, a first write circuit WC1, a second write circuit WC2, a third write circuit WC3, a first path PT1, a second path PT2, and a third path PT3 through which an internal data strobe signal iDQS is transmitted, a memory bank BK, a read circuit RC, and control logic CL. The memory bank BK may include a memory cell array MCA, a row decoder RDEC, a write driver DRV, a sense amplifier ISA, and a column decoder CDEC.

[0122] The components of the memory device 500 are similar to those of the reference 1 and reference 2 devices except for the read circuit RC and the control logic CL. Figure 4 and Figure 6 The components of the described memory device 400 are the same, and the operation of the memory device 500 is similar to that of the memory device 400. Therefore, to avoid redundancy, additional description will be omitted.

[0123] The control logic CL may include a mode register set MRS, a test mode register set TMRS, and a logic circuit LC. The configuration and operation of the mode register set MRS and the test mode register set TMRS are similar to those of the reference register set MRS, except that the test mode register set TMRS is not used to select the internal data strobe signal position. Figure 4 and Figure 6 The configuration and operation of the described mode register set MRS and the test mode register set TMRS are similar. Therefore, in order to avoid redundancy, additional description will be omitted.

[0124] The logic circuit LC may receive the first write equalization output signal WLO1 from the first write circuit WC1 , the second write equalization output signal WLO2 from the second write circuit WC2 , and the third write equalization output signal WLO3 from the third write circuit WC3 .

[0125] The logic circuit LC may perform a logic operation on the first write equalization output signal WLO1, the second write equalization output signal WLO2, and the third write equalization output signal WLO3. For example, the logic circuit LC may perform an OR operation or an AND operation on the first write equalization output signal WLO1, the second write equalization output signal WLO2, and the third write equalization output signal WLO3.

[0126] The number and type of logical operations that the logic circuit LC can perform are not limited. For example, the logic circuit LC can be configured to gradually perform two or more of various logical operations including OR, AND, exclusive OR, exclusive AND, NOR, NAND, exclusive NOR, and exclusive NAND operations in one or more stages.

[0127] The logic circuit LC may output a result of a logic operation performed on the first write equalization output signal WLO1 , the second write equalization output signal WLO2 , and the third write equalization output signal WLO3 as a write equalization output signal WLO.

[0128] In an external write-leveling operation, the read circuit RC can receive the first write-leveling output signal WLO1 from the first write circuit WC1. In a position-selective internal write-leveling operation, the read circuit RC can receive the write-leveling output signal WLO from the logic circuit LC of the control logic CL. The read circuit RC can provide the first write-leveling output signal WLO1 or the write-leveling output signal WLO as feedback to the host device 100 via the data signal pad DQP.

[0129] Figure 8 Shown Figure 7 An example of a method of performing a location-selective internal write-leveling operation in a memory device 500. Figure 1 、 Figure 7 and Figure 8 In operation S310, the host device 100 may select a delay amount of the write equalization pulse signal WL_PUL. For example, the host device 100 may select a delay amount of the write equalization pulse signal WL_PUL corresponding to the selected internal data strobe signal iDQS by programming the delay amount in the third mode register MR3 of the mode register set MRS of the control logic CL of the memory device 500.

[0130] In operation S320, the host device 100 may transmit a command indicating a write WR and an address CA and a data strobe signal DQS to the memory device 500. The host device 100 may transmit the data strobe signal DQS including a write preamble and at least one toggle to the memory device 500.

[0131] The command decoder CMDD of the memory device 500 may output a write equalization pulse signal WL_PUL in response to the command indicating write WR and the address CA. The write equalization pulse signal WL_PUL may have a delay amount corresponding to information programmed in the third mode register MR3.

[0132] In operation S330, the memory device 500 may calculate a write equalization output signal WLO. For example, the logic circuit LC of the control logic CL of the memory device 500 may calculate the write equalization output signal WLO by performing a logic operation on the first write equalization output signal WLO1, the second write equalization output signal WLO2, and the third write equalization output signal WLO3.

[0133] In operation S340, the memory device 500 may send feedback to the host device 100. In an embodiment, the logic circuit LC of the control logic CL of the memory device 500 may send a write equalization output signal WLO to the read circuit RC. The read circuit RC may provide the write equalization output signal WLO as the data signal DQ to the host device 100 through the data signal pad DQP.

[0134] In operation S350, the host device 100 may determine whether the write equalization pulse signal WL_PUL is detected. For example, when the feedback provided from the memory device 500 is a high-level (or low-level) signal, the host device 100 may determine that the write equalization pulse signal WL_PUL is detected. When the feedback provided from the memory device 500 is a low-level (or high-level) signal, the host device 100 may determine that the write equalization pulse signal WL_PUL is not detected.

[0135] When the write equalization pulse signal WL_PUL is not detected, the host device 100 may reselect the delay amount of the write equalization pulse signal WL_PUL. In other words, operation S310 may be performed again. Thereafter, the host device 100 and the memory device 500 may perform operations S320, S330, and S340 again. In other words, until the write equalization pulse signal WL_PUL is detected, the host device 100 and the memory device 500 may scan the delay amount of the write equalization pulse signal WL_PUL.

[0136] When the write-leveling pulse signal WL_PUL is detected, the host device 100 may program the delay amount in the memory device 500. For example, the host device 100 may program the delay amount of the detected write-leveling pulse signal WL_PUL in the third mode register MR3 of the mode register set MRS of the control logic CL of the memory device 500. Thereafter, the position selection internal write-leveling operation may be exited.

[0137] In an embodiment, in a write operation, a first write command WR_CMD1, a second write command WR_CMD2, and a third write command WR_CMD3 may be activated synchronously with a clock signal CK having a specific time difference (e.g., a CWL difference). The first write command WR_CMD1, the second write command WR_CMD2, and the third write command WR_CMD3 may be delayed relative to the clock signal CK by a delay amount programmed in the third mode register MR3. Once this delay is applied, these commands (WR_CMD1, WR_CMD2, and WR_CMD3) may be activated.

[0138] As described above, the host device 100 and the memory device 500 can skip testing multiple internal data strobe signal positions. Instead, they can select the delay amounts for the first write command WR_CMD1, the second write command WR_CMD2, and the third write command WR_CMD3 based on the results obtained by performing a logical operation on the multiple internal data strobe signal positions through the logic circuit LC. Therefore, the time for the position selection internal write leveling operation can be shortened.

[0139] Figure 9 Schematic diagram of a memory device 600 according to an embodiment of the present disclosure. Figure 1 and Figure 9 The memory device 600 may include a command and address pad CAP, a command and address buffer CAB, a clock signal pad CKP, a clock buffer CKB, a data strobe signal pad DQSP, a write data strobe buffer DQSBW, a read data strobe buffer DQSBR, a data signal pad DQP, a write data buffer DQBW, a read data buffer DQBR, a command and address sampler CAS, a command decoder CMDD, a data strobe signal generator DQSG, a first write circuit WC1, a second write circuit WC2, a third write circuit WC3, a first path PT1, a second path PT2, and a third path PT3 through which an internal data strobe signal iDQS is transmitted, a memory bank BK, a read circuit RC, and control logic CL. The memory bank BK may include a memory cell array MCA, a row decoder RDEC, a write driver DRV, a sense amplifier ISA, and a column decoder CDEC.

[0140] The components of the memory device 600 are similar to those of the reference 100 except for the read circuit RC and the control logic CL. Figure 4 and Figure 6 The components of the described memory device 400 are similar, and the operation of the memory device 600 is similar to the operation of the memory device 400. Therefore, to avoid redundancy, additional description will be omitted.

[0141] The control logic CL may include a mode register set MRS, a test mode register set TMRS, and a logic circuit LC. The configuration and operation of the mode register set MRS and the test mode register set TMRS are similar to those of the reference circuit LC1, except that the test mode register set TMRS is not used to select the internal data strobe signal position and the test mode register set TMRS is used to select one of the first logic circuit LC1 and the second logic circuit LC2. Figure 4 and Figure 6 The configuration and operation of the mode register set MRS and the test mode register set TMRS are described above. Therefore, in order to avoid redundancy, additional description will be omitted.

[0142] The logic circuit LC may receive the first write equalization output signal WLO1 from the first write circuit WC1 , the second write equalization output signal WLO2 from the second write circuit WC2 , and the third write equalization output signal WLO3 from the third write circuit WC3 .

[0143] The logic circuit LC can perform a logic operation on the first, second, and third write equalization output signals WLO1, WLO2, and WLO3. The logic circuit LC may include a first logic circuit LC1 and a second logic circuit LC2. For example, the first logic circuit LC1 may perform one of an OR operation and an AND operation on the first, second, and third write equalization output signals WLO1, WLO2, and WLO3. The second logic circuit LC2 may perform the other of an OR operation and an AND operation on the first, second, and third write equalization output signals WLO1, WLO2, and WLO3.

[0144] In an embodiment, the number and type of logic operations performed by the first logic circuit LC1 and the second logic circuit LC2 are not limited. For example, the first logic circuit LC1 and the second logic circuit LC2 can be configured to gradually perform two or more of various logic operations including OR, AND, exclusive OR, exclusive AND, NOR, NAND, exclusive NOR, and exclusive NAND operations in one or more stages.

[0145] A logic circuit selected from the first logic circuit LC1 and the second logic circuit LC2 can output the result of a logical operation on the first write equalization output signal WLO1, the second write equalization output signal WLO2, and the third write equalization output signal WLO3 as the write equalization output signal WLO. For example, one of the first logic circuit LC1 and the second logic circuit LC2 can be selected using a test mode register set TMRS.

[0146] In an external write-leveling operation, the read circuit RC can receive the first write-leveling output signal WLO1 from the first write circuit WC1. In a position-selective internal write-leveling operation, the read circuit RC can receive the write-leveling output signal WLO from the logic circuit LC of the control logic CL. The read circuit RC can provide the first write-leveling output signal WLO1 or the write-leveling output signal WLO as feedback to the host device 100 via the data signal pad DQP.

[0147] Figure 10 Shown Figure 9 An example of a method of performing a location-selective internal write-leveling operation in a memory device 600. Figure 1 、 Figure 9 and Figure 10 In operation S410, the host device 100 may select logic in the memory device 600. For example, the host device 100 may select one of the first logic circuit LC1 and the second logic circuit LC2 by programming a specific test mode register of the test mode register set TMRS of the control logic CL of the memory device 600.

[0148] In operation S420, the host device 100 may select a delay amount of the write equalization pulse signal WL_PUL. For example, the host device 100 may select a delay amount of the write equalization pulse signal WL_PUL corresponding to the selected internal data strobe signal iDQS by programming the delay amount in the third mode register MR3 of the mode register set MRS of the control logic CL of the memory device 600.

[0149] In operation S430, the host device 100 may transmit a command indicating write WR and an address CA and a data strobe signal DQS to the memory device 600. The host device 100 may transmit the data strobe signal DQS including a write preamble and at least one toggle to the memory device 600.

[0150] The command decoder CMDD of the memory device 600 may output a write equalization pulse signal WL_PUL in response to the command indicating write WR and the address CA. The write equalization pulse signal WL_PUL may have a delay amount corresponding to information programmed in the third mode register MR3.

[0151] In operation S440, the memory device 600 may calculate a write equalization output signal WLO. For example, a logic circuit selected from the first logic circuit LC1 and the second logic circuit LC2 of the logic circuit LC of the control logic CL of the memory device 600 may calculate the write equalization output signal WLO by performing a logic operation on the first write equalization output signal WLO1, the second write equalization output signal WLO2, and the third write equalization output signal WLO3.

[0152] In operation S450, the memory device 600 may send feedback to the host device 100. In an embodiment, a logic circuit selected from the first logic circuit LC1 and the second logic circuit LC2 of the logic circuit LC of the control logic CL of the memory device 600 may send a write equalization output signal WLO to the read circuit RC. The read circuit RC may provide the write equalization output signal WLO as the data signal DQ to the host device 100 through the data signal pad DQP.

[0153] In operation S460, the host device 100 may determine whether the write equalization pulse signal WL_PUL is detected. For example, when the feedback provided from the memory device 600 is a high-level (or low-level) signal, the host device 100 may determine that the write equalization pulse signal WL_PUL is detected. When the feedback provided from the memory device 600 is a low-level (or high-level) signal, the host device 100 may determine that the write equalization pulse signal WL_PUL is not detected.

[0154] When the write equalization pulse signal WL_PUL is not detected, the host device 100 may select the delay amount of the write equalization pulse signal WL_PUL again. In other words, operation S420 may be performed again. Thereafter, the host device 100 and the memory device 600 may perform operations S430, S440, S450, and S460 again. In other words, before detecting the write equalization pulse signal WL_PUL, the host device 100 and the memory device 600 may scan the delay amount of the write equalization pulse signal WL_PUL.

[0155] When the write equalization pulse signal WL_PUL is detected, the host device 100 may record the delay associated with the write equalization pulse signal WL_PUL for the selected logic circuit. The recorded delay corresponds to the specific time point at which the write equalization pulse signal WL_PUL was detected. Then, operation S470 is performed.

[0156] In operation S470 , the host device 100 may determine whether the selected logic circuit is the last logic circuit. For example, the host device 100 may determine whether a delay amount of the write equalization pulse signal WL_PUL of each of the first and second logic circuits LC1 and LC2 is detected.

[0157] When the selected logic circuit is not the last logic circuit, the host device 100 may select the next logic circuit. In other words, operation S410 may be performed again. Thereafter, the host device 100 and the memory device 600 may perform operations S420, S430, S440, S450, S460, and S470. In other words, until the delay amount of the write equalization pulse signal WL_PUL is detected for each of the first logic circuit LC1 and the second logic circuit LC2, the host device 100 and the memory device 600 may sequentially select the first logic circuit LC1 and the second logic circuit LC2 to detect the corresponding delay amount of the write equalization pulse signal WL_PUL for each of the first logic circuit LC1 and the second logic circuit LC2.

[0158] If the selected logic circuit is the final logic circuit, the host device 100 may select the final logic circuit in operation S480. For example, based on the delay amounts of the first and second logic circuits LC1 and LC2 and their corresponding write equalization pulse signals, the host device 100 may select a delay amount of the write equalization pulse signal WL_PUL that enables appropriate sampling of the data signal DQ in the first, second, and third write circuits WC1, WC2, and WC3. The host device 100 may select the internal data strobe signal (iDQS) position corresponding to the selected delay amount of the write equalization pulse signal WL_PUL as the final internal data strobe signal (iDeQS) position.

[0159] In operation S490, the host device 100 may program the final logic circuit and the corresponding delay amount in the memory device 600. For example, the host device 100 may program information of the final logic circuit in a specific test mode register of the test mode register set TMRS of the control logic CL of the memory device 600.

[0160] The host device 100 may program the delay amount of the write leveling pulse signal WL_PUL corresponding to the final logic circuit in the third mode register MR3 of the mode register set MRS of the control logic CL of the memory device 600. Thereafter, the position selection internal write leveling operation may be exited.

[0161] In an embodiment, in a write operation, a first write command WR_CMD1, a second write command WR_CMD2, and a third write command WR_CMD3 may be activated synchronously with a clock signal CK having a given time difference (e.g., a CWL difference). The first write command WR_CMD1, the second write command WR_CMD2, and the third write command WR_CMD3 may be delayed relative to the clock signal CK by a delay amount programmed in the third mode register MR3. After this delay, these commands (WR_CMD1, WR_CMD2, and WR_CMD3) may be activated.

[0162] Figure 11 Schematic diagram of a memory device 700 according to an embodiment of the present disclosure. Figure 1 and Figure 11 The memory device 700 may include a command and address pad CAP, a command and address buffer CAB, a clock signal pad CKP, a clock buffer CKB, a data strobe signal pad DQSP, a write data strobe buffer DQSBW, a read data strobe buffer DQSBR, a data signal pad DQP, a write data buffer DQBW, a read data buffer DQBR, a command and address sampler CAS, a command decoder CMDD, a data strobe signal generator DQSG, a first write circuit WC1, a second write circuit WC2, a third write circuit WC3, a first path PT1, a second path PT2, and a third path PT3 through which an internal data strobe signal iDQS is transmitted, a memory bank BK, a read circuit RC, and control logic CL. The memory bank BK may include a memory cell array MCA, a row decoder RDEC, a write driver DRV, a sense amplifier ISA, and a column decoder CDEC.

[0163] The components of the memory device 700 are similar to those of the reference 100 except for the read circuit RC and the control logic CL. Figure 4 and Figure 6 The components of the described memory device 400 are similar, and the operation of the memory device 700 is similar to the operation of the memory device 400. Therefore, to avoid redundancy, additional description will be omitted.

[0164] The control logic CL may include a mode register set MRS, a test mode register set TMRS, and a logic circuit LC. The configuration and operation of the mode register set MRS and the test mode register set TMRS are similar to those of the reference register set MRS, except that the test mode register set TMRS is not used to select the internal data strobe signal position. Figure 4 and Figure 6 The configuration and operation of the described mode register set MRS and the test mode register set TMRS are similar. Therefore, in order to avoid redundancy, additional description will be omitted.

[0165] The logic circuit LC may receive the first write equalization output signal WLO1 from the first write circuit WC1 , the second write equalization output signal WLO2 from the second write circuit WC2 , and the third write equalization output signal WLO3 from the third write circuit WC3 .

[0166] The logic circuit LC can perform a logic operation on the first, second, and third write equalization output signals WLO1, WLO2, and WLO3. The logic circuit LC may include a first logic circuit LC1 and a second logic circuit LC2. For example, the first logic circuit LC1 may perform one of an OR operation and an AND operation on the first, second, and third write equalization output signals WLO1, WLO2, and WLO3. The second logic circuit LC2 may perform the other of an OR operation and an AND operation on the first, second, and third write equalization output signals WLO1, WLO2, and WLO3.

[0167] In an embodiment, the number and type of logic operations performed by the first logic circuit LC1 and the second logic circuit LC2 are not limited. For example, the first logic circuit LC1 and the second logic circuit LC2 can be configured to gradually perform two or more of various logic operations including OR, AND, exclusive OR, exclusive AND, NOR, NAND, exclusive NOR, and exclusive NAND operations in one or more stages.

[0168] The control logic CL may further include selection logic SL. The first logic circuit LC1 and the second logic circuit LC2 may provide the selection logic SL with the results of a logical operation performed on the first write equalization output signal WLO1, the second write equalization output signal WLO2, and the third write equalization output signal WLO3. The selection logic SL may output one of the results of the logical operation performed on the first write equalization output signal WLO1, the second write equalization output signal WLO2, and the third write equalization output signal WLO3 as the write equalization output signal WLO.

[0169] For example, the selection logic SL can generate the write-leveling output signal WLO based on a first timing when the output of the first logic circuit LC1 is set to a high level and a second timing when the output of the second logic circuit LC2 is set to a high level. If the time difference between the first timing and the second timing is less than a threshold, the selection logic SL can output one of the outputs of the first logic circuit LC1 and the second logic circuit LC2 (e.g., an AND output) as the write-leveling output signal WLO. If the time difference between the first timing and the second timing is greater than or equal to the threshold, the selection logic SL can output a signal obtained by delaying one of the outputs of the first logic circuit LC1 and the second logic circuit LC2 (e.g., an OR output) by a specified offset, and output it as the write-leveling output signal WLO.

[0170] In an external write-leveling operation, the read circuit RC can receive the first write-leveling output signal WLO1 from the first write circuit WC1. In a position-selective internal write-leveling operation, the read circuit RC can receive the write-leveling output signal WLO from the logic circuit LC of the control logic CL. The read circuit RC can provide the first write-leveling output signal WLO1 or the write-leveling output signal WLO as feedback to the host device 100 via the data signal pad DQP.

[0171] Figure 12 Shown Figure 11 An example of a method of performing a location-selective internal write-leveling operation in a memory device 700. Figure 1 、 Figure 11 and Figure 12 In operation S510, the host device 100 may select a delay amount of the write equalization pulse signal WL_PUL. For example, the host device 100 may select a delay amount of the write equalization pulse signal WL_PUL corresponding to the selected internal data strobe signal iDQS by programming the delay amount in the third mode register MR3 of the mode register set MRS of the control logic CL of the memory device 700.

[0172] In operation S520, the host device 100 may transmit a command indicating a write WR and an address CA and a data strobe signal DQS to the memory device 700. The host device 100 may transmit the data strobe signal DQS including a write preamble and at least one toggle to the memory device 700.

[0173] The command decoder CMDD of the memory device 700 may output a write equalization pulse signal WL_PUL in response to the command indicating write WR and the address CA. The write equalization pulse signal WL_PUL may have a delay amount corresponding to information programmed in the third mode register MR3.

[0174] In operation S530, the memory device 700 may calculate a write equalization output signal WLO. For example, each of the first logic circuit LC1 and the second logic circuit LC2 of the logic circuit LC of the control logic CL of the memory device 700 may perform a logic operation on the first write equalization output signal WLO1, the second write equalization output signal WLO2, and the third write equalization output signal WLO3.

[0175] In operation S540 , the memory device 700 may determine whether all outputs are detected. For example, the selection logic SL of the control logic CL of the memory device 700 may determine whether both the output of the first logic circuit LC1 and the output of the second logic circuit LC2 are at a high level.

[0176] When all outputs are not detected, in other words, when at least one of the output of the first logic circuit LC1 and the output of the second logic circuit LC2 is not at a high level, the selection logic SL may determine whether a critical time has elapsed in operation S550. For example, after at least one of the output of the first logic circuit LC1 and the output of the second logic circuit LC2 is set to a high level, the selection logic SL may determine whether the critical time has elapsed.

[0177] When at least one of the output of the first logic circuit LC1 and the output of the second logic circuit LC2 is not at a high level ("No" in operation S540), and when the critical time has not elapsed from the point in time when the output of the first logic circuit LCD1 or the output of the second logic circuit LC2 is set to a high level ("No" in operation S550), the memory device 700 may provide non-detection feedback to the host device 100. For example, the selection logic SL may provide a low-level write-equalization output signal WLO to the read circuit RC, and the read circuit RC may provide a low-level write-equalization output signal WLO to the host device 100. In response to the non-detection feedback, in operation S510, the host device 100 may again select a delay amount for the write-equalization pulse signal WL_PUL. Thereafter, the host device 100 and the memory device 700 may again perform operations S520, S530, S540, and S550. In other words, until the write equalization pulse signal WL_PUL is detected, the host apparatus 100 and the memory device 700 may scan the delay amount of the write equalization pulse signal WL_PUL.

[0178] When both the output of the first logic circuit LC1 and the output of the second logic circuit LC2 are at a high level ("Yes" in operation S540), the memory device 700 may provide detection feedback to the host device 100. Alternatively, when at least one of the output of the first logic circuit LC1 and the output of the second logic circuit LC2 is not at a high level ("No" in operation S540), and when a critical time has passed since at least one of the output of the first logic circuit LC1 or the output of the second logic circuit LC2 was set to a high level ("Yes" in operation S550), the memory device 700 may provide detection feedback to the host device 100. For example, the selection logic SL may provide a high-level write-equalization output signal WLO to the read circuit RC, and the read circuit RC may provide a high-level write-equalization output signal WLO to the host device 100.

[0179] In operation S580, the host device 100 may program the delay amount in the memory device 700. For example, the host device 100 may program the delay amount in the write leveling pulse signal WL_PUL in the third mode register MR3 of the mode register set MRS of the control logic CL of the memory device 700. Thereafter, the position selection internal write leveling operation may be exited.

[0180] In an embodiment, in a write operation, the first, second, and third write commands WR_CMD1, WR_CMD2, and WR_CMD3 may be activated in synchronization with a clock signal CK having a given time difference (e.g., a CWL difference). The first, second, and third write commands WR_CMD1, WR_CMD2, and WR_CMD3 may be delayed relative to the clock signal CK by a delay amount programmed in the third mode register MR3 and then activated.

[0181] Figure 13 An example of an operating method of the host device 100 and the storage device 210 or 220 is shown. Figure 1 and Figure 13 In operation S610, the host device 100 may request device information from the storage device 210 or 220. For example, during the initialization of the storage device 210 or 220, the host device 100 may request device information from the storage device 210 or 220. For example, the device information may be information associated with a location-selective internal write-leveling operation.

[0182] In operation S620, the memory device 210 or 220 may report device information to the host apparatus 100. For example, the device information may include information about whether the memory device 210 or 220 supports a location-selective internal write-leveling operation, information about a reference Figure 4 and Figure 6The optional location information, reference Figure 7 and Figure 8 Information on the type of operation of the logic circuit LC, with reference to Figure 9 and Figure 10 Information on the number or type of logic circuits, and information on reference Figure 11 and Figure 12 The number and type of logic circuits and information on the algorithm for selecting the logic SL.

[0183] In operation S630, the host device 100 may determine whether to perform a location-selective internal write-leveling operation L1. If it is determined that the location-selective internal write-leveling operation L1 is not required, the host device 100 may perform an internal write-leveling operation together with the storage device 210 or 220 in operation S640. If it is determined that the location-selective internal write-leveling operation L1 is required, the host device 100 may perform the location-selective internal write-leveling operation L1 together with the storage device 210 or 220 in operation S650.

[0184] According to an embodiment of the present disclosure, internal data strobe signals are obtained from two or more locations and a write-leveling operation is performed based on these signals. This method improves the reliability of a memory device by ensuring that communication signals are obtained with more precise timing. Furthermore, the method provides an improved operating process for the memory device and includes a memory module incorporating the memory device.

[0185] While the present disclosure has been described with reference to specific embodiments, it will be appreciated by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A storage device, comprising: a memory cell array, the memory cell array comprising a plurality of memory cells; a command decoder configured to receive a write command signal from a host device in synchronization with a clock signal received from the host device, and to generate a write leveling pulse signal in response to the write command signal and in synchronization with the clock signal in a write leveling operation; a data strobe signal path configured to transmit a data strobe signal received from the host device; a first write circuit configured to receive a first data strobe signal at a first position on the data strobe signal path, perform a first sampling of the write equalization pulse signal in synchronization with the first data strobe signal in the write equalization operation, and output a first write equalization signal based on the first sampling; as well as a second write circuit configured to receive a second data strobe signal at a second position on the data strobe signal path, perform a second sampling of the write equalization pulse signal in synchronization with the second data strobe signal in the write equalization operation, and output a second write equalization signal based on the second sampling; The memory device is configured to: in the write-leveling operation, generate a feedback signal to be sent to the host device based on the first write-leveling signal and the second write-leveling signal.

2. The memory device according to claim 1, wherein The memory device is further configured to select the first write-leveling signal or the second write-leveling signal to be output to the host device as the feedback signal.

3. The memory device according to claim 2, wherein: The memory device is further configured to select the first write-equalization signal or the second write-equalization signal based on a request of the host device.

4. The memory device according to claim 3, further comprising: Test mode register set, The memory device is further configured to select the first write equalization signal or the second write equalization signal based on information programmed in the test mode register group.

5. The memory device according to claim 1, wherein The command decoder is further configured to: in a write operation, generate a first write command signal and a second write command signal in response to the write command signal, and The first write circuit and the second write circuit are further configured to: receive the first write command signal and the second write command signal, respectively, during the write operation. The memory device according to claim 5 , wherein: The first write circuit is further configured to: in the write operation, sample the first write command signal in synchronization with the first data strobe signal, and The second write circuit is further configured to: sample the second write command signal synchronously with the second data strobe signal during the write operation.

7. The memory device according to claim 5, wherein: The command decoder is further configured to output the first write command signal and the second write command signal having a time difference corresponding to an offset time.

8. The memory device according to claim 1, wherein A switching timing of the first data strobe signal is different from a switching timing of the second data strobe signal.

9. The memory device according to claim 1, further comprising: A logic circuit is configured to receive the first write equalization signal and the second write equalization signal, and perform a logic operation on the first write equalization signal and the second write equalization signal, wherein a result of the logic operation is the feedback signal.

10. The memory device according to claim 9, wherein The logic circuit is further configured to perform an OR operation or an AND operation.

11. The memory device according to claim 1 , further comprising: a first logic circuit configured to receive the first write equalization signal and the second write equalization signal and perform a first logic operation on the first write equalization signal and the second write equalization signal; as well as A second logic circuit is configured to receive the first write equalization signal and the second write equalization signal and perform a second logic operation on the first write equalization signal and the second write equalization signal.

12. The memory device according to claim 11, wherein The first output of the first logic circuit or the second output of the second logic circuit is the feedback signal.

13. The memory device according to claim 12, wherein: The memory device is further configured to select the first output or the second output based on a request of the host device.

14. The memory device according to claim 11, wherein The memory device is further configured to provide information on the number of logic circuits used to generate the feedback signal to the host device.

15. The memory device according to claim 11, further comprising: a third logic circuit configured to receive the first output of the first logic circuit and the second output of the second logic circuit, and select a delay amount of the write equalization pulse signal based on the first output and the second output.

16. The memory device according to claim 15, wherein The command decoder is further configured to: in a write operation, generate the first write command signal and the second write command signal in response to the write command signal, and The first write circuit is further configured to receive the first write command signal in the write operation, and the second write circuit is further configured to receive the second write command signal in the write operation, and The timing of the first write command signal and the timing of the second write command signal are synchronized with a delay amount of the write equalization pulse signal.

17. The memory device according to claim 16, wherein: The write equalization pulse signal is the first write command signal or the second write command signal.

18. The memory device according to claim 1, wherein The memory device is further configured to provide information to the host device regarding the number of locations on the data strobe signal path at which the data strobe signal is received.

19. A method for operating a memory device, the method comprising: performing a first write-leveling operation at the memory device to align timing between a clock signal and a data strobe signal received from a host device; as well as performing a second write leveling operation at the memory device to align timing between an internal clock signal path through which the clock signal is transmitted and an internal data strobe signal path through which the data strobe signal is transmitted, The second write-leveling operation is performed based on internal data strobe signals obtained at two or more locations on the internal data strobe signal path.

20. A storage module, comprising: a plurality of memory devices, each of the memory devices being configured to receive a data signal and a data strobe signal from a host device; as well as a register clock driver configured to receive a clock signal from the host device and provide the clock signal to the plurality of memory devices, Wherein, each of the plurality of storage devices is configured as: performing a first write-leveling operation to align timing of the clock signal supplied from the register clock driver and timing of the data strobe signal supplied from the host device; and performing a second write leveling operation to align timing between an internal clock signal path through which the clock signal is transmitted and an internal data strobe signal path through which the data strobe signal is transmitted, and The second write-leveling operation is performed based on internal data strobe signals obtained at two or more locations on the internal data strobe signal path.

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