Method and system for scanning wafer atlas in semiconductor

Abstract

The invention relates to a wafer atlas scanning method and system in a semiconductor, and the method comprises the following steps: reading an AOI atlas of all layers before a current layer of a wafer after combination, the AOI atlas being marked with information of all Die, and the information comprising a defect mark fail; determining the position in the current layer based on the Die of the defect mark fail in the AOI map; all Dies of the current layer of the wafer are scanned, information marking is carried out on all the Dies in the current layer, then an AOI atlas of the current layer is output, and the positions of the Dies with the defect marks fail are not scanned in the current layer scanning of the wafer; and merging the AOI map of the current layer into the AOI map. By adopting the scanning method provided by the invention, the position of the Die of the defect mark fail is skipped during scanning of the current layer, so that the total number of defects can be reduced, the scanning time is reduced, the re-judgment workload is reduced, and the scanning method is particularly suitable for projects with relatively low yield in the research and development stage.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor detection, and in particular to a method and system for scanning semiconductor wafer patterns. Background Art

[0002] In the semiconductor industry, a "die" typically refers to a single integrated circuit (IC) chip cut from a wafer. Wafers, the foundation of semiconductor manufacturing, are typically round pieces of silicon with multiple identical chip designs. After manufacturing, the wafer is diced into individual dies, each of which is a complete chip.

[0003] In semiconductor manufacturing, die defects need to be detected and classified. AOI (Automated Optical Inspection) image scanning is usually used to detect the appearance defects and quality issues of the chip (die). AOI is used to capture images of each layer of the die. A layer-by-layer scanning method can be adopted, starting from the top layer of the die and scanning each layer downward in sequence.

[0004] The captured image is compared and analyzed with a pre-set standard image to identify abnormal areas in the image, such as irregular edges, surface scratches, foreign matter, and color anomalies. Once an anomaly is detected, the system classifies and marks the defect according to pre-set rules. In the generated AOI map, defective dies are marked as fail, and non-defective dies are marked as pass.

[0005] Regarding the above-mentioned related technologies, the inventors found that in the current AOI atlas scanning, all the dies in the current layer are scanned first and then the atlas is output. Then all the dies in the next layer are scanned and then the atlas is output. Finally, the atlas of the current layer and the atlas of the next layer are merged.

[0006] Among them, during the scanning process of the next layer, the Die that has been marked as fail in the current layer will still be scanned in the scanning process of the next layer, and due to its surface defects and other problems, a large number of defect images will be generated in the scanning process of the next layer, which prolongs the scanning time. Therefore, there is room for improvement. Summary of the Invention

[0007] In order to reduce scanning time, the present application provides a method and system for scanning semiconductor wafer maps.

[0008] The present application provides a semiconductor wafer atlas scanning method using the following technical solutions: A semiconductor wafer scanning method comprises the following steps: Read the combined AOI map of all layers before the current layer of the wafer, where the AOI map is marked with information about all dies, including the defect mark "fail"; Determine the location of the defect in the current layer based on the Die of the defect mark fail in the AOI map; Scan all dies in the current layer of the wafer, mark all dies in the current layer with information, and output the AOI map of the current layer. In the scanning of the current layer of the wafer, the locations of the dies marked as "fail" are not scanned; Merge the current layer AOI map into the AOI map.

[0009] Preferably, the information further includes defect classification, and the defect classification is configured as a high-risk defect class and a low-risk defect class. The high-risk defect class is marked as a defect mark fail, and the low-risk defect class is not marked as a defect mark fail.

[0010] Preferably, in the wafer current layer scanning, in the position where the die with the defect mark fail is not scanned, the information of the die at the position in the current layer is marked with the defect mark fail.

[0011] The semiconductor wafer scanning system provided in this application adopts the following technical solutions: A semiconductor wafer atlas scanning system, comprising: A reading module is used to read the combined AOI map of all layers before the current layer of the wafer, wherein the AOI map is marked with information of all dies, including the defect mark "fail"; The determination module is used to determine the location of the Die in the current layer based on the defect mark "fail" in the AOI map; The marking module is used to scan all dies in the current layer of the wafer, mark all dies in the current layer with information, and then output the AOI map of the current layer. In the scanning of the current layer of the wafer, the location of the die marked as defective is not scanned; The merging module is used to merge the current layer AOI map into the AOI map.

[0012] Preferably, the information further includes defect classification, and the defect classification is configured as a high-risk defect class and a low-risk defect class. The high-risk defect class is marked as a defect mark fail, and the low-risk defect class is not marked as a defect mark fail.

[0013] Preferably, in the wafer current layer scanning, in the position where the die with the defect mark fail is not scanned, the information of the die at the position in the current layer is marked with the defect mark fail.

[0014] In summary, this application includes at least one of the following beneficial technical effects: In the existing AOI pattern scanning technology, all dies in the current layer are scanned first and then the pattern is output. Then all dies in the next layer are scanned and then the pattern is output. Dies marked as fail in the current layer will still be scanned during the scanning process of the next layer. Due to surface defects and other problems, a large number of defect images will be generated during the scanning process of the next layer, which prolongs the scanning time and increases the workload of personnel re-judgment. At the same time, if the total number of defects exceeds a certain number (5,000 images for mass production), it is necessary to debug the program parameters and relax the card control conditions for re-scanning. By adopting the scanning method of the present application, the location of the Die with the defect mark fail is skipped when scanning the current layer, which can reduce the total number of defects, thereby reducing the scanning time and the workload of re-judgment, making it particularly suitable for projects with low yield in the R&D stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of a wafer atlas scanning method in the prior art.

[0016] Figure 2 It is a flow chart of the wafer map scanning method of this embodiment.

[0017] Figure 3 Schematic diagram of the wafer mapping scanning method of this embodiment. DETAILED DESCRIPTION

[0018] The following is combined with Figure 1-3 This application is described in further detail.

[0019] Based on the wafer map scanning method of the existing technology, such as Figure 1 As shown, the AOI atlas scans each layer of the wafer. For example, all the dies on the first layer are scanned first. The system will mark and classify the defects according to the preset rules and generate an atlas. After human review, the final atlas of the first layer is output.

[0020] Then scan all the dies on the second layer. The system will mark and classify the defects according to the preset rules and generate a map. After human review, the final second-layer map is output, and the first-layer map and the second-layer map are merged.

[0021] All Dies in each subsequent layer are generated using the above steps and merged.

[0022] Therefore, for the Die marked as fail due to defects in the current layer, it will still be scanned during the scanning process of the next layer. Due to surface defects and other problems, a large number of defect images will be generated during the scanning process of the next layer, which will extend the scanning time and increase the workload of personnel re-judgment. At the same time, if the total number of defects exceeds a certain number (5,000 images are required for mass production), it will be necessary to debug the program parameters and relax the card control conditions for re-scanning.

[0023] Based on the defects of the above-mentioned prior art, the technical solution of the present invention provides a solution. By skipping the location of the Die with the defect mark fail when scanning the current layer, the total number of defects can be reduced, thereby reducing the scanning time and the workload of re-judgment, which is particularly suitable for projects with low yield in the research and development stage.

[0024] Example 1 In combination with the above-mentioned inventive ideas of the technical solution of the present invention, the present invention provides a semiconductor wafer atlas scanning method, referring to Figure 2 As shown, the following steps are included: Step S100 , reading the combined AOI map of all layers before the current layer of the wafer, wherein the AOI map is marked with information of all dies, including a defect mark “fail”.

[0025] According to the technical solution defined in step S100, specifically, before scanning the current wafer layer, it is necessary to read the AOI maps of all layers before the current layer. The AOI maps of all layers before the current layer are merged AOI maps. The AOI map is marked with information about all dies, that is, each die in the AOI map is marked with corresponding information, including the defect mark "fail", the defect classification, and the good product mark "pass".

[0026] The defect classification of dies includes but is not limited to uneven edges, scratches on the surface, foreign matter, abnormal color, etc. It is worth noting that not all defective dies will be marked with the defect mark fail. In this embodiment, the defect classification is configured into high-risk defect classes and low-risk defect classes. The high-risk defect class is marked with the defect mark fail, the low-risk defect class is not marked with the defect mark fail, and the low-risk defect class is marked as a good product mark pass.

[0027] The following example illustrates that if surface scratches or foreign matter are classified as high-risk defects, the die will be marked with a "fail" defect. If irregular edges or abnormal colors are classified as low-risk defects, the die will not be marked with a "fail" defect but will be marked as a "pass" good product.

[0028] Step S200: Determine the location of the Die in the current layer based on the defect mark "fail" in the AOI map.

[0029] According to the technical solution defined in step S200, specifically, after reading the information of all dies in the AOI map, the position of the die with the defect mark fail in the AOI map can be determined. Since the position of each die in the current layer of the wafer is the same as the position of each die in the previous layer, the position of the die with the defect mark fail in the current layer can be determined. The position refers to the virtual position mapped in the current layer.

[0030] Step S300: Scan all dies in the current layer of the wafer, mark all dies in the current layer with information, and then output the AOI map of the current layer. In the scanning of the current layer of the wafer, the location of the die marked with defect fail is not scanned.

[0031] According to the technical solution defined in step S300, specifically, the AOI atlas scans all dies of the current layer of the wafer and collects images of the current layer of the wafer. The collected images are compared and analyzed with pre-set standard images to identify abnormal areas in the image. The comparison and analysis method can use grayscale comparison.

[0032] After identifying all dies in the current layer, they are marked with information. Abnormal dies are marked as defects and fail, and the corresponding defect classification is performed. Dies without abnormalities are marked as good products and pass.

[0033] The position of the die with the defect mark fail is not scanned in the current layer scanning of the wafer, that is, as determined in the above step S200, the position of the die with the good mark pass is only scanned in the current layer scanning of the wafer.

[0034] It is worth noting that the location of the die with the defect mark "fail" is not scanned in the current wafer layer scan, and the die information at that location in the current layer is marked with the defect mark "fail". That is, the location of the die with the defect mark "fail" is not scanned in the current wafer layer scan, and the die at that location is directly marked with the defect mark "fail" in the current layer.

[0035] Step S400: Merge the current layer AOI map into the AOI map.

[0036] According to the technical solution defined in step S400, specifically, the AOI map of the current layer is merged into the AOI map, which becomes the AOI map after all layers are merged in step S100. In subsequent wafer layer scans, this AOI map is used as a reference to read the locations of the die with the defect mark "fail" in the AOI map and skip the locations of the die with the defect mark "fail" in the scan of that layer, thereby achieving the invention's purpose of reducing the total number of defects, shortening scanning time, and reducing the workload of re-inspection.

[0037] Reference Figure 3 As shown, the following description starts with the AOI map scanning of the first layer of the wafer and proceeds to the AOI map scanning layer by layer.

[0038] In the AOI map scanning of the first layer of the wafer, the AOI map scanning scans all the dies on the first layer of the wafer, collects the image of the first layer of the wafer, identifies all the dies in the first layer, marks the information, and then outputs the AOI map of the first layer. Abnormal dies are marked as defects and fail, and the corresponding defects are classified. Dies without abnormalities are marked as good products and pass.

[0039] Before scanning the second layer of the wafer, the AOI map of the first layer is read first (that is, the AOI map of all layers before the current layer of the wafer is read after being merged), and the position of the defect mark "fail" in the AOI map of the first layer is determined based on the Die in the second layer.

[0040] The second layer of the wafer is scanned, and the locations of the dies marked with the defect mark "fail" in the second layer are not scanned. Only the dies marked with the pass mark in the first layer are scanned. All dies in the second layer are marked with information and the AOI map of the second layer is output. Among them, the dies not scanned in the second layer are directly marked with the defect mark "fail".

[0041] Merge the AOI map of the second layer into the AOI map of the first layer.

[0042] Before scanning the third layer of the wafer, read the merged AOI map of all layers before the third layer, and follow the above steps in sequence. By using the AOI map scanning method of this application, the location of the die with the defect mark fail is skipped during scanning, which can reduce the total number of defects, thereby reducing the scanning time and the workload of re-judgment, making it particularly suitable for projects with low yield in the research and development stage.

[0043] Example 2 The semiconductor wafer scanning system provided in this application adopts the following technical solutions: A semiconductor wafer atlas scanning system, comprising: The reading module is used to read the AOI map of all layers before the current layer of the wafer after being merged, wherein the AOI map is marked with information of all dies, and the information includes the defect mark fail and defect classification.

[0044] The determination module is used to determine the location of the Die in the current layer based on the defect mark fail in the AOI map.

[0045] The marking module is used to scan all dies in the current layer of the wafer, mark all dies in the current layer with information, and then output the AOI map of the current layer. Among them, the location of the die with the defect mark "fail" is not scanned in the scanning of the current layer of the wafer.

[0046] The merging module is used to merge the current layer AOI map into the AOI map.

[0047] Before scanning the current wafer layer, the AOI maps of all previous layers must be read. The AOI maps of all previous layers are merged AOI maps. This AOI map contains information about all dies. That is, each die in the AOI map is marked with corresponding information, including the defect mark "fail", the defect classification, and the good product mark "pass".

[0048] The defect classification of dies includes but is not limited to uneven edges, scratches on the surface, foreign matter, abnormal color, etc. It is worth noting that not all defective dies will be marked with the defect mark fail. In this embodiment, the defect classification is configured into high-risk defect classes and low-risk defect classes. The high-risk defect class is marked with the defect mark fail, the low-risk defect class is not marked with the defect mark fail, and the low-risk defect class is marked as a good product mark pass.

[0049] The following example illustrates that if surface scratches or foreign matter are classified as high-risk defects, the die will be marked with a "fail" defect. If irregular edges or abnormal colors are classified as low-risk defects, the die will not be marked with a "fail" defect but will be marked as a "pass" good product.

[0050] AOI atlas scanning scans all dies in the current layer of the wafer and collects images of the current layer of the wafer. The collected images are compared and analyzed with pre-set standard images to identify abnormal areas in the image. The comparison and analysis method can use grayscale comparison.

[0051] After identifying all dies in the current layer, they are marked with information. Abnormal dies are marked as defects and fail, and the corresponding defect classification is performed. Dies without abnormalities are marked as good products and pass.

[0052] Among them, the position of the die with the defect mark "fail" is not scanned in the current layer scanning of the wafer, and the position of the die with the good mark "pass" is only scanned in the current layer scanning of the wafer.

[0053] It is worth noting that the location of the die with the defect mark "fail" is not scanned in the current wafer layer scan, and the die information at that location in the current layer is marked with the defect mark "fail". That is, the location of the die with the defect mark "fail" is not scanned in the current wafer layer scan, and the die at that location is directly marked with the defect mark "fail" in the current layer.

[0054] For the various illustrative logic blocks and steps in this embodiment, those skilled in the art can implement them through electronic hardware, computer software, or a combination of the two. To clearly demonstrate the interchangeability of hardware and software, the various illustrative components, units, and steps mentioned above have generally described their functions. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art can use various methods to implement the described functions for various specific applications, but such implementation should not be understood as exceeding the scope of protection of the embodiments of the present invention.

[0055] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor wafer atlas scanning method, characterized in that: The steps include: Read the combined AOI map of all layers before the current layer of the wafer, where the AOI map is marked with information about all dies, including the defect mark "fail"; Determine the location of the defect in the current layer based on the Die of the defect mark fail in the AOI map; Scan all dies in the current layer of the wafer, mark all dies in the current layer with information, and output the AOI map of the current layer. In the scanning of the current layer of the wafer, the locations of the dies marked as "fail" are not scanned; Merge the current layer AOI map into the AOI map.

2. The semiconductor wafer scanning method according to claim 1, wherein: The information further includes defect classification, which is configured as a high-risk defect class and a low-risk defect class. The high-risk defect class is marked as a defect mark fail, and the low-risk defect class is not marked as a defect mark fail.

3. The semiconductor wafer scanning method according to claim 1, wherein: In the wafer current layer scanning, in the position where the die with the defect mark fail is not scanned, the information of the die at the position in the current layer is marked with the defect mark fail.

4. A semiconductor wafer scanning system, characterized in that: include: A reading module is used to read the combined AOI map of all layers before the current layer of the wafer, wherein the AOI map is marked with information of all dies, including the defect mark "fail"; The determination module is used to determine the location of the Die in the current layer based on the defect mark "fail" in the AOI map; The marking module is used to scan all dies in the current layer of the wafer, mark all dies in the current layer with information, and then output the AOI map of the current layer. In the scanning of the current layer of the wafer, the location of the die marked as defective is not scanned; The merging module is used to merge the current layer AOI map into the AOI map.

5. The semiconductor wafer mapping scanning system according to claim 4, characterized in that: The information further includes defect classification, which is configured as a high-risk defect class and a low-risk defect class. The high-risk defect class is marked as a defect mark fail, and the low-risk defect class is not marked as a defect mark fail.

6. The semiconductor wafer mapping scanning system according to claim 4, characterized in that: In the wafer current layer scanning, in the position where the die with the defect mark fail is not scanned, the information of the die at the position in the current layer is marked with the defect mark fail.

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