Adaptive comparator calibration

Abstract

Flash memory analog-to-digital converters and other types of integrated circuits having multiple comparators may employ calibration methods and firmware to efficiently compensate for various offset voltages of the multiple comparators. An illustrative integrated circuit includes: a plurality of comparators, each comparator configured to provide a comparator output signal indicative of whether an input signal exceeds more than an offset voltage than a reference voltage, the plurality of comparators including a current comparator and a previous comparator; and a controller configured to perform a search to sequentially select a calibration setting for each of the comparators, the controller determining an initial search window for a current comparator based on a calibration setting selected for a previous comparator.

Description

Background Art

[0001] Digital communication occurs between a transmitting device and a receiving device through an intermediate communication medium or "channel" (e.g., a fiber optic cable, insulated copper wire, or a wireless connection). Each transmitting device typically transmits symbols at a fixed symbol rate, while each receiving device detects (possibly corrupted) sequences of symbols and attempts to reconstruct the transmitted data. A "symbol" is a state or significant condition of a channel that lasts for a fixed period of time, which is called a "symbol interval." For example, a symbol can be a voltage or current level, an optical power level, a phase value, or a specific frequency or wavelength. The change from one channel state to another is called a symbol transition. Each symbol can represent (i.e., encode) one or more binary bits of data. Alternatively, data can be represented by symbol transitions, or by a sequence of two or more symbols.

[0002] Many digital communication links use only one bit per symbol; a binary "0" is represented by one symbol (e.g., a voltage or current signal within a first range), and a binary "1" is represented by another symbol (e.g., a voltage or current signal within a second range), but higher-order signal constellations are known and frequently used. In four-level pulse amplitude modulation ("PAM4"), each symbol interval can carry any of four symbols, typically labeled -3, -1, +1, and +3. Each symbol can therefore represent two binary bits.

[0003] Channel imperfections create dispersion, which can cause each symbol to interfere with its neighbors—a result known as intersymbol interference (ISI). ISI can make it difficult for a receiving device to determine which symbols were transmitted in each interval, especially when such ISI is combined with additive noise. Receivers can accordingly employ sophisticated equalization techniques to minimize symbol error rates. It is often advantageous to digitize the received signal and perform most of the equalization in the digital domain. At high symbol rates, designers may prefer flash analog-to-digital converters, which provide fast and accurate conversions.

[0004] Flash ADCs use a linear voltage ladder and a comparator at each "step" of the ladder. The comparators operate in parallel to compare the input voltage to each reference voltage. These ladders are usually made up of a series of resistors, but they can also be capacitor dividers, or a set of programmable voltage sources can provide custom reference voltages. Flash converters are very fast, but they require many comparators relative to other ADC implementations. Flash converters require 2 n -1 comparator to perform n-bit conversion. (This 2 nThe output of each comparator can be fed into a digital encoder which converts the comparator output into an n-bit binary representation.

[0005] The Institute of Electrical and Electronics Engineers (IEEE) has published IEEE Standard 802.3ba-2010, a standard for Ethernet communications at rates up to 100 Gb / s. The standard specifies multiple channels, each with a symbol signal rate of up to 25 Gb / s. Since the fundamental limitation of transistor switching in 65nm silicon integrated circuit manufacturing processes is below 40 GHz, the new IEEE standard does place high demands on the implementation of analog-to-digital converters. For additional details, see co-owned U.S. Patent No. 8,427,353, "A High-Speed ​​Flash Analog to Digital Converter," which is incorporated herein by reference. Additional channels may necessitate additional flash ADCs, and each flash ADC may need to be parallelized at higher symbol rates to allow interleaved operation, even further increasing the number of comparators.

[0006] Making the situation even more challenging, the selected receiver design must cope with potential changes in its component performance due to process variations, supply voltage variations, and temperature variations (collectively referred to as "PVT variations"), as well as drift due to component aging. The comparator may manifest such changes as changes in voltage offset, adversely affecting the symbol error rate and overall system performance. Periodic calibration of the comparator, if performed accurately, can compensate for such voltage offset changes, but the receiver cannot operate while calibration is being performed. Therefore, it is desirable to minimize calibration time to maximize receiver throughput while also maintaining the accuracy of the calibration process. Summary of the Invention

[0007] Accordingly, disclosed herein are flash analog-to-digital converters and other types of integrated circuits for calibrating multiple comparators, as well as methods and firmware for such integrated circuits to perform calibration of their multiple comparators. An illustrative integrated circuit includes: a plurality of comparators, each comparator configured to provide a comparator output signal indicating whether an input signal exceeds a reference voltage by more than an offset voltage, the plurality of comparators including a current comparator and a previous comparator; and a controller configured to perform a search to sequentially select a calibration setting for each of the comparators, the controller determining an initial search window for the current comparator based on the calibration setting selected for the previous comparator.

[0008] An illustrative calibration method for use in such an integrated circuit includes: determining an initial search window for a current comparator based on a calibration setting selected for a previous comparator, the search window having a left side (corresponding to a more negative difference in calibration voltages (Vcalp-Vcaln)), a right side (corresponding to a more positive difference in calibration voltages (Vcalp-Vcaln)), and a middle point, the middle point corresponding to the calibration setting selected for the previous comparator; finding a comparator output signal of the current comparator for calibration settings at the left and right sides of the initial search window; determining a refined search window for the current comparator based at least in part on the comparator output signal of the current comparator at the calibration settings at the left and right sides; sequentially trying each calibration setting in the refined search window until a transition in the comparator output signal of the current comparator is detected; and selecting the calibration setting corresponding to the transition.

[0009] An illustrative non-transitory information storage medium, such as a non-volatile memory, may be coupled to the controller to provide firmware that configures the controller to implement the calibration method described above.

[0010] Each of the aforementioned embodiments may be implemented individually or in combination, and may be implemented in any suitable combination with any one or more of the following features: 1. A previous comparator immediately precedes a current comparator only if the previous comparator is the first comparator or the calibration setting difference between the two immediately previous comparators is less than a predetermined threshold. 2. An initial search window has a left side, a middle point, and a right side, with the middle point corresponding to the calibration setting selected for the previous comparator. 3. The controller is configured to find the comparator output signal of the current comparator using the calibration settings at the left and right sides of the initial search window. 4. If the comparator output signal of the current comparator is equal for the calibration settings at the left and right sides, the controller is further configured to find the comparator output signal of the current comparator using the calibration settings at the minimum and maximum settings. 5. If the comparator output signal of the current comparator is different for the calibration settings at the minimum and left sides, the controller determines a refined search window between the minimum and left sides; and if the comparator output signal of the current comparator is different for the calibration settings at the maximum and right sides, the controller determines a refined search window between the right and maximum settings. 6. The controller is configured to: find the comparator output signal for the current comparator at the midpoint. 7. If the comparator output signal of the current comparator differs for the calibration settings at the left and the midpoint, the controller determines a refined search window between the left and the midpoint; and if the comparator output signal of the current comparator differs for the calibration settings at the midpoint and the right, the controller determines a refined search window between the midpoint and the right. 8. The controller is configured to sequentially try each calibration setting in the refined search window until a transition in the comparator output signal of the current comparator is detected. 9. The controller is configured to select the calibration setting that causes the transition. 10. The input signal for the current comparator is a differential signal, and a reference voltage for the current comparator is provided as a differential signal. The controller is configured to couple the differential signal leads of the input signal during the search for the calibration setting for the current comparator, and the controller is configured to adjust the reference voltage for the current comparator based on the selected calibration setting to compensate for the offset voltage. 11. The controller is configured to couple the input signal and the reference voltage leads of the current comparator during the search for the calibration setting for the current comparator. 12. The integrated circuit further includes an adjustable voltage source for each of the plurality of comparators to convert a selected calibration setting into a calibration voltage that compensates for an offset voltage of the comparator. 13. The integrated circuit includes a flash analog-to-digital converter having a plurality of comparators coupled to receive a shared input signal to be digitized. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An illustrative computer network is shown.

[0012] Figure 2 is a block diagram of an illustrative point-to-point communication link.

[0013] Figure 3 is a block diagram of an illustrative integrated circuit receiver device.

[0014] Figure 4 is a block diagram of an illustrative flash analog-to-digital converter (ADC).

[0015] Figure 5 is a schematic diagram of an illustrative comparator.

[0016] Figure 6 is a schematic diagram of an illustrative comparator during calibration.

[0017] Figure 7 is an illustrative calibration sheet.

[0018] Figure 8 is an illustrative table of calibration settings for several comparators.

[0019] Figure 9 is a flow chart of an illustrative calibration method. DETAILED DESCRIPTION

[0020] Note that the specific embodiments set forth in the drawings and the following description do not limit the present disclosure, but rather provide a basis for one of ordinary skill in the art to identify alternatives, equivalents, and modifications that are within the scope of the claims.

[0021] The disclosed integrated circuits, analog-to-digital converters, and comparator calibration methods are best understood in light of the environment in which they are expected to operate. Accordingly, Figure 1 An illustrative computer network 100 is shown that includes a mobile device 102 and computer systems 104A-C coupled to a routing network 106. Routing network 106 may be or may include, for example, part of the Internet, a wide area network, a local area network, a wireless network, and / or a telephone network. Figure 1 In the example, routing network 106 includes a network of equipment items 108, such as switches, routers, hubs, bridges, and the like. Equipment items 108 are connected to each other and to computer systems 104A-C via point-to-point communication links 110 that transmit data between the various network components. Today, an increasing number of communication links are being developed, with an emphasis on speed. IEEE Standard 802.3ba-2010 supports Ethernet frame transmission at speeds of 40 and 100 gigabits per second, with single channel signaling rates up to 25 Gb / s.

[0022] Figure 2 Show Figure 1Representative point-to-point communication link 110. Figure 2 In the embodiment of FIG. 1 , the point-to-point communication link 110 includes a “node A” 202 at one end and a “node B” 204 ​​at the opposite end. Node A may be, for example, Figure 1 Node B may be, for example, one of the equipment items 108 of computer network 100, or one of computer systems 104A-C. Node B may be, for example, a different one of the equipment items 108, or a different one of computer systems 104A-C.

[0023] Transceiver 220 is coupled to node A, and transceiver 222 is coupled to node B. Communication channels 208 and 214 extend between transceivers 220 and 222. Channels 208 and 214 may include transmission media such as, for example, fiber optic cable, twisted pair cable, coaxial cable, and (in the case of wireless transmission) air. Bidirectional communication between node A and node B may be provided using separate channels 208 and 214, or in some embodiments, may be provided using a single channel that transmits signals in opposite directions without interference.

[0024] Transmitter 206 of transceiver 220 obtains data from node A and transmits the data to transceiver 222 via a signal on channel 208. The signal can be, for example, a voltage, current, optical power level, wavelength, frequency, or phase value. Receiver 210 of transceiver 222 receives the signal via channel 208, uses the signal to reconstruct the transmitted data, and provides the data to node B. Similarly, transmitter 212 of transceiver 222 obtains data from node B and transmits the data to transceiver 220 via a signal on channel 214. Receiver 216 of transceiver 220 receives the signal via channel 214, uses the signal to reconstruct the transmitted data, and provides the data to node A.

[0025] As bandwidth requirements for communication links continue to increase, many system engineers are turning to fiber-optic communication channels. While optical fiber must support the necessary communication bandwidth, the primary challenge lies in designing transmitters and receivers (transceivers) capable of supporting these data rates. Existing systems use optical transmitters to convert electrical signals into optical signals for transmission over optical fiber, and optical receivers to receive the optical signals and convert them into electrical data signals.

[0026] Figure 3An illustrative receiver 210 for receiving a fiber optic signal is shown. Receiver 210 includes a photodetector 302, a filter 304, an analog-to-digital converter 306, and a demodulator 308. Photodetector 302 converts the optical signal into a corresponding electrical signal for processing by filter 304, analog-to-digital converter 306, and demodulator 308. While many suitable photodetectors exist and can be used, most existing systems employ one or more photodiodes or phototransistors, which change their conductivity when photons enter a sensitive region of the device. Filter 304 receives the electrical signal from photodetector 302 and limits it to a frequency band of interest to prevent aliasing during the digitization process. Because filter 304 is analog, it is typically kept simple, but this is not required. If desired, filter 304 can be designed to at least partially compensate for channel characteristics, including the spectral response of the transmitter and photodetector. Alternatively, filter 304 can be designed to alter the spectrum of the received signal to a desired shape, such as that of a partial response (PR) channel. Analog-to-digital converter 306 digitizes the filtered signal to provide a stream of digitized signal samples to demodulator 308. Demodulator 308 converts the digitized signal samples into a digital data stream conveyed via the optical signal.

[0027] The transceiver 222 further includes a controller 310 that configures and coordinates the operation of the receiver 210 and the transmitter 212. Typically, the controller 310 is programmable and operates according to firmware instructions stored in the non-volatile memory 312, so that the operation of the controller 310 (and, thereby, the operation of the transceiver 222) can be easily modified via firmware updates. The firmware can implement a boot-up routine when power is applied to the transceiver to initialize various operating parameters of the receiver 210 and the transmitter 212. The boot-up routine can include, for example, a calibration process for the analog-to-digital converter 306 as described below. The firmware can also be stored by other non-transitory information storage media that do not need to be directly connected to the controller.

[0028] The analog-to-digital converter 306 may be a flash memory analog-to-digital converter such as Figure 4 A flash analog-to-digital converter is shown in Figure 1. This type of converter uses multiple comparators operating in parallel to compare the input voltage to a set of reference voltages. A digital encoder can be used to convert the comparator outputs into a binary representation of the voltage.

[0029] exist Figure 4 , a gain controlled amplifier 402 applies an adjustable gain to a differential received signal 403, thereby generating a differential input signal IP, IN for each of a plurality of comparators 406. The adjustable gain of the gain controlled amplifier 402 is adjusted as needed to maintain the input signal range within desired limits.

[0030] Each of the plurality of comparators 406 compares the differential input signals IP and IN with a corresponding reference voltage Vref, which may be provided as a differential voltage as shown herein, to generate a comparator output signal indicating whether the input signal exceeds the corresponding reference voltage. (As discussed further below, each comparator may have an inherent offset voltage that affects the comparison result.) The reference voltages may be evenly or strategically spaced across the expected input signal range so that the comparator output signals collectively indicate the closest digital representation of the input signal voltage. The comparator outputs may be differential (i.e., complementary) digital signals for faster sampling.

[0031] Sampling gates 408 couple the comparator output signals to a set of latches 409 for sampling the comparator output signals according to a sampling clock. The sampling gates can be implemented as NMOS (n-channel metal oxide semiconductor) transistors. The parasitic input capacitance of the latches 409 can cooperate with the sampling gates to provide a sample and hold function.

[0032] Each latch 409 shown includes one or more latch drivers 410, 411 that set or reset an associated bistable circuit 414 when their respective access switches 412, 413 are closed. The access switches 412, 413 can be operated in an interleaved manner so that, for example, even-numbered access gates are closed during even-numbered samples and odd-numbered access gates are closed during odd-numbered samples. Such interleaving provides additional settling time for the bistable circuits 414. A higher degree of interleaving (e.g., four-phase interleaving) can be employed so that each bistable circuit 414 captures every four samples of the comparator output, thereby allowing each bistable circuit more settling time. The bistable circuit shown consists of a pair of inverters 415, 417 connected end-to-end that can hold the binary comparator output until a digital encoder or other subsequent circuitry can combine, process, or otherwise operate on the set of comparator outputs.

[0033] More details on this analog-to-digital converter implementation can be found in incorporated U.S. Patent No. 8,427,353, "A High-Speed ​​Flash Analog to Digital Converter." However, it should be noted that this implementation is illustrative and serves to provide a context for the disclosed comparator calibration method. Other contexts are possible, and the disclosed calibration method is applicable to any integrated circuit having multiple comparators, and is particularly desirable for circuits having many such comparators.

[0034] Figure 5An illustrative comparator 406 is shown coupled to a digital-to-analog converter 502 to receive differential reference voltages on leads, labeled Vrefp and Vrefn. Voltage Vrefp is the analog voltage corresponding to digital input refp, while voltage Vrefn is the analog voltage corresponding to digital input refn. Comparator 406 includes a sign element 504 that indicates, under ideal conditions, whether ((IP-IN)-(VREFP-VREFN)) is greater than or less than 0. If greater than 0, output signals OP are high and ON are low. If less than 0, OP is low and ON is high. In practice, PVT variations and component drift introduce an offset voltage Voff 506, causing sign element 504 to indicate whether ((IP-IN)-(Vrefp-Vrefn)) is greater than or less than Voff, or equivalently, whether ((IP-IN)-(Vrefp-Vrefn+Voff)) is greater than 0.

[0035] The controller 310 performs a calibration process to determine the offset voltage and provide compensation that enables the comparator to perform closer to its ideal performance. Figure 6 As shown, an input shorting switch 508 can be provided for each comparator 406, enabling the controller 310 to short the input IP and IN pins during the calibration process. The controller 310 can then apply the calibration values ​​calp and caln to the digital-to-analog converter 502, testing different values ​​of Vcalp and Vcaln until a transition point is detected in the output of the sign element 504. At this transition point, Voff = -(Vcalp - Vcaln).

[0036] The non-volatile memory 312 may contain a table of indexed calibration settings, each having predetermined values ​​of calp and caln corresponding to evenly or strategically spaced values ​​of (Vcalp - Vcaln). Figure 7 , which shows a table of calibration indices, where lower indices correspond to lower calp values ​​and higher caln values. As the calibration index increases, the caln value gradually decreases and the calp value gradually increases, causing the calibration voltage difference (Vcalp-Vcaln) to gradually increase. When discussing the search window below, smaller calibration index values ​​correspond to smaller (more negative) calibration voltage differences and can be displayed on the left, while larger calibration index values ​​correspond to larger (more positive) calibration voltage differences and can be displayed on the right.

[0037] The non-volatile memory 312 may also contain a table of similar indexed reference voltage settings that specifies the Vrefp and Vrefn settings for the desired reference voltages for the various comparators. In an alternative implementation, the comparator's reference voltage is supplied on the IN pin, the input signal is supplied as a single-ended signal via the IP pin, and the remaining pins are reserved for calibration voltages Vcalp, Vcaln. In either case, the results of the calibration process may be stored in a memory such as Figure 8 The selected calibration settings are shown in the table.

[0038] Figure 8 Each row in the table corresponds to a different comparator in the plurality of comparators 406. In this example, the integrated circuit includes two flash analog-to-digital converters, each with comparators for 46 different reference voltages, which are represented here by indexed reference voltage settings. The selected calibration setting is represented by the calibration index stored in the last column.

[0039] In one contemplated integrated circuit receiver, the integrated circuit includes 192 comparators and includes an indexed calibration settings table having 72 rows. Even though it takes no more than 100 microseconds for the controller to test a given calibration setting for a given comparator, an exhaustive search for the best calibration setting requires well over 1 second. Since calibration may need to be repeated periodically for optimal system performance, this delay represents an undesirable loss of channel capacity. In an effort to reduce the time required for the calibration process, the inventors have noticed that the selected calibration settings tend to be closer to the middle of their range than to the edges of their range, making it less desirable to start the search at the edge of the calibration range. In addition, there is some degree of correlation among the selected calibration settings for a given device. Reference is made herein to FIG. Figure 9 The disclosed calibration process exploits these observations to significantly reduce the average time required for the calibration process.

[0040] The process begins in block 902 where the controller selects an initial comparator, sets the initial calibration index to zero, and sets the search direction to “increase.” The output signal of the selected comparator is measured using calp and caln set according to the current calibration index.

[0041] In block 904, the controller updates the current calibration index. Since the search direction is "increase," the calibration index is incremented. If the search direction is "decrease," the calibration index would be decremented. The controller measures the comparator output signal using calp and caln set according to the updated calibration index.

[0042] In block 906, the controller determines whether the comparator output signal has transitioned compared to the output for the previous calibration index. If not, the controller returns to block 904. Otherwise, in block 906, the controller updates the calibration index by, for example, saving the current calibration index in a table of selected calibration settings (e.g., Figure 8 ) to select the current calibration index. The controller then selects the next comparator.

[0043] In block 908, the controller determines whether calibration settings have been selected for all comparators. If so, the calibration process is complete. If not, in block 912, the comparator determines whether the currently selected comparator is one of the first two comparators, resulting in no more than one calibration setting being selected. If the currently selected comparator is not one of the first two comparators, and if the difference between the last two calibration indices (or alternatively, if the difference between the last two digital values ​​calp or the last two digital values ​​caln) exceeds a threshold value T, this potentially indicates that the most recently selected calibration setting is an outlier. Threshold T can be determined empirically, but values ​​assumed for the indices correspond to approximately 50% or 60% of the range. For the calp or caln values, the maximum difference can be compared to threshold T, where T is 60% to 80% of the maximum value. If the last selected calibration index is not detected as a potential outlier, in block 914, the controller uses the last selected calibration index as a reference, for example, by setting the reference comparator number to the previous comparator number. Otherwise, in block 916 , the controller uses the second to last selected calibration index as a reference, for example, by setting the reference comparator number to be 2 less than the current comparator number.

[0044] In box 918, the controller determines an initial search window for finding the optimal calibration setting for the current comparator. The initial search window has a left side (L), a right side (R) and a middle point, such as, for example, a center (C). The middle point can be set to be equal to the index of the selected calibration setting for the reference comparator. The controller can add and subtract a predetermined half width to the middle point to find the left and right sides of the initial search window. The half width can be a value determined empirically, for example, approximately 25% of the index range. If the calculated left or right side is outside the index range, it can be adjusted to be equal to the nearest edge of the index range.

[0045] In block 920, the controller measures the output signal of the current comparator using the calibration settings at the left side of the search window, the right side of the search window, and the midpoint. In block 922, the controller determines whether the output signals for all three points (or at least for the left and right sides) are equal. If not, the comparator output signal transitions within the initial search window, either to the left of the midpoint or to the right of the midpoint. Accordingly, in block 924, the controller determines a precise search window between the midpoint and either side of the initial search window that has a comparator output signal different from the midpoint. This can be accomplished, for example, by setting the calibration index equal to the midpoint and selecting the appropriate search direction (i.e., increasing or decreasing).

[0046] If the controller determines in block 922 that the comparator output signals are all equal, then no transition in the comparator output signals occurs within the initial search window. Accordingly, in block 926, the controller measures the output signal of the current comparator using calibration settings set at its maximum and minimum values. Within the search window, one of the maximum and minimum values ​​should be unequal to the output signal state. In block 928, the controller determines a refined search window between the side of the search window closest to the unequal comparator output signal and the extreme value index that produced the unequal value. From either block 924 or block 928, the controller returns to block 904 to search for a transition within the refined search window.

[0047] Once the above disclosure is fully understood, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. The order of the operations described in the flow charts may be changed, with certain operations being reordered, pipelined, and / or performed in parallel. Where applicable, the claims are intended to be interpreted as encompassing all such alternatives, equivalents, and modifications.

Claims

1. An integrated circuit, comprising: a plurality of comparators, each comparator configured to provide a comparator output signal indicating whether an input signal exceeds a reference voltage by more than an offset voltage, the plurality of comparators comprising a current comparator and a previous comparator; as well as A controller is configured to perform a search to select a calibration setting for each of the comparators in turn, the controller determining an initial search window for the current comparator based on the calibration setting selected for the previous comparator.

2. The integrated circuit according to claim 1, wherein: The previous comparator immediately precedes the current comparator only if the previous comparator is the first comparator or the calibration setting difference between two immediately previous comparators is less than a predetermined threshold.

3. The integrated circuit according to claim 1, wherein: The initial search window has a left side, a middle point, and a right side, and wherein the middle point corresponds to a calibration setting selected for the previous comparator.

4. The integrated circuit according to claim 3, wherein: The controller is configured to find the comparator output signal of the current comparator using calibration settings at the left side and the right side of the initial search window.

5. The integrated circuit according to claim 4, in, If the comparator output signal of the current comparator is equal for the calibration setting at the left side and the calibration setting at the right side, the controller is further configured to find the comparator output signal of the current comparator using the calibration settings at the minimum setting and the maximum setting, wherein if the comparator output signal of the current comparator is different for the calibration settings at the minimum setting and at the left side, the controller determines a refined search window between the minimum setting and the left side, and Wherein, if the comparator output signal of the current comparator is different for the calibration settings at the maximum setting and at the right side, the controller determines a refined search window between the right side and the maximum setting.

6. The integrated circuit according to claim 4, in, The controller is configured to find the comparator output signal of the current comparator at an intermediate point, wherein if the comparator output signal of the current comparator is different for the calibration settings at the left side and at the middle point, the controller determines a fine search window between the left side and the middle point, and Wherein, if the comparator output signal of the current comparator is different for the calibration settings at the middle point and at the right side, the controller determines a precise search window between the middle point and the right side.

7. The integrated circuit according to claim 6, wherein: The controller is configured to sequentially try each calibration setting in the fine search window until a transition in the comparator output signal of the current comparator is detected, and wherein the controller is configured to select the calibration setting that causes the transition.

8. The integrated circuit according to claim 1, in, said input signal for said current comparator is a differential signal, wherein the reference voltage for the current comparator is provided as a differential signal, wherein the controller is configured to couple the differential signal leads of the input signal during the search for the calibration setting of the current comparator, and The controller is configured to adjust the reference voltage for the current comparator based on the selected calibration setting to compensate for the offset voltage.

9. The integrated circuit according to claim 1, wherein: The controller is configured to couple the input signal of the current comparator and the leads of the reference voltage during a search for a calibration setting for the current comparator, and wherein the integrated circuit further includes an adjustable voltage source for each of the plurality of comparators to convert a selected calibration setting into a calibration voltage that compensates for an offset voltage of the comparator.

10. The integrated circuit of claim 1 including a flash analog-to-digital converter having the plurality of comparators coupled to receive a shared input signal to be digitized.

11. A calibration method for use in an integrated circuit, the integrated circuit having a plurality of comparators, each comparator configured to provide a comparator output signal indicating whether an input signal exceeds a reference voltage by more than an offset voltage, the plurality of comparators comprising a current comparator and a previous comparator, the method comprising: determining an initial search window for the current comparator based on the calibration setting selected for the previous comparator, the search window having a left side, a right side, and a middle point, the middle point corresponding to the calibration setting selected for the previous comparator; finding a comparator output signal of the current comparator using calibration settings at the left side and the right side of the initial search window; determining a fine search window for the current comparator based at least in part on a comparator output signal of the current comparator under calibration settings at the left side and the right side; sequentially trying each calibration setting in the fine search window until a transition in the comparator output signal of the current comparator is detected; and A calibration setup corresponding to the transition is selected.

12. The calibration method according to claim 11, wherein: The previous comparator immediately precedes the current comparator only if the previous comparator is the first comparator or the calibration setting difference between two immediately previous comparators is less than a predetermined threshold.

13. The calibration method according to claim 11, wherein: Determining the precise search window includes: If the comparator output signal of the current comparator for the calibration setting at the left side and the comparator output signal of the current comparator for the calibration setting at the right side are equal: finding a comparator output signal of the current comparator using calibration settings at a minimum setting and a maximum setting; If the comparator output signal of the current comparator is different for the calibration settings at the minimum setting and at the left side, determining that the refine search window is between the minimum setting and the left side; and If the comparator output signal of the current comparator is different for the calibration settings at the right side and at the maximum setting, the fine search window is determined to be between the right side and the maximum setting.

14. The calibration method according to claim 11, wherein: Determining the precise search window includes: At the intermediate point, finding the comparator output signal of the current comparator; If the comparator output signal of the current comparator is different for the calibration settings at the left side and at the middle point, determining that the refined search window is between the left side and the middle point; and If the comparator output signal of the current comparator is different for the calibration settings at the middle point and at the right side, the fine search window is determined to be between the middle point and the right side.

15. The calibration method according to claim 11, wherein: The sequential attempts are performed while differential signal leads for the input signals are coupled together, and wherein the selecting includes adjusting the reference voltage based on a selected calibration setting to compensate for the offset voltage.

16. The calibration method according to claim 11, wherein: The sequential attempts are performed while signal leads for the input signal and the reference voltage are coupled together, and wherein the selecting includes converting the selected calibration setting to a calibration voltage that compensates for the offset voltage using an adjustable source.

17. A non-transitory information storage medium, the non-transitory information storage medium being coupled to a controller and configured to provide firmware, the firmware configuring the controller to implement a calibration method for a plurality of comparators, the plurality of comparators comprising a previous comparator and a current comparator, each comparator in the plurality of comparators being configured to provide a comparator output signal, the comparator output signal indicating whether an input signal exceeds a reference voltage by more than an offset voltage, the calibration method comprising: determining an initial search window for the current comparator based on the calibration setting selected for the previous comparator, the search window having a left side, a right side, and a middle point, the middle point corresponding to the calibration setting selected for the previous comparator; finding a comparator output signal of the current comparator using calibration settings at the left side and the right side of the initial search window; determining a fine search window for the current comparator based at least in part on a comparator output signal of the current comparator under calibration settings at the left side and the right side; sequentially trying each calibration setting in the fine search window until a transition in the comparator output signal of the current comparator is detected; and A calibration setup corresponding to the transition is selected.

18. The non-transitory information storage medium according to claim 17, wherein: The previous comparator immediately precedes the current comparator only if the previous comparator is the first comparator or the calibration setting difference between two immediately previous comparators is less than a predetermined threshold.

19. The non-transitory information storage medium according to claim 17, wherein: Determining the precise search window includes: If the comparator output signal of the current comparator for the calibration setting at the left side and the comparator output signal of the current comparator for the calibration setting at the right side are equal: finding a comparator output signal of the current comparator using calibration settings at a minimum setting and a maximum setting; If the comparator output signal of the current comparator is different for the calibration settings at the minimum setting and at the left side, determining that the refine search window is between the minimum setting and the left side; and If the comparator output signal of the current comparator is different for the calibration settings at the right side and at the maximum setting, the fine search window is determined to be between the right side and the maximum setting.

20. The non-transitory information storage medium according to claim 17, wherein: Determining the precise search window includes: At the intermediate point, finding the comparator output signal of the current comparator; If the comparator output signal of the current comparator is different for the calibration settings at the left side and at the middle point, determining that the refined search window is between the left side and the middle point; and If the comparator output signal of the current comparator is different for the calibration settings at the middle point and at the right side, the fine search window is determined to be between the middle point and the right side.

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