Circuit board and manufacturing method thereof

Abstract

The invention provides a circuit board and a manufacturing method thereof. The circuit board may include: an insulating layer having a via hole penetrating in one direction; a pad disposed on the insulating layer to cover the via hole; and a circuit wiring disposed on the insulating layer. The pad may include a first plurality of metal layers, the circuit wiring may include a second plurality of metal layers, and a number of the first plurality of metal layers of the pad may be greater than a number of the second plurality of metal layers of the circuit wiring.

Description

Technical Field

[0001] The present disclosure relates to a circuit board and a method for manufacturing the same. Background Art

[0002] As electronic devices in the IT field (including mobile phones) become lighter, thinner, shorter and smaller, circuit integration density is increasing and the number of integrated circuits for input / output is increasing, so the width of circuit patterns applied to printed circuit boards for packages is also becoming increasingly miniaturized.

[0003] Reducing line width and space is a core technology for wiring fine circuits. However, due to reasons related to processes such as forming circuit patterns through plating and etching, miniaturization of circuits has been difficult to achieve. Summary of the Invention

[0004] The present disclosure attempts to provide a circuit board and a method of manufacturing the same that can reduce circuit design restrictions and form fine circuit patterns.

[0005] However, the problems to be solved by the embodiments of the present disclosure are not limited to the above-mentioned problems, and can be variously extended within the scope of the technical concept included in the present disclosure.

[0006] A circuit board according to an embodiment may include: an insulating layer having a via hole extending therethrough in one direction; a pad disposed on the insulating layer to cover the via hole; and a circuit wiring disposed on the insulating layer. The pad may include a first plurality of metal layers, and the circuit wiring may include a second plurality of metal layers, wherein the number of the first plurality of metal layers of the pad may be greater than the number of the second plurality of metal layers of the circuit wiring.

[0007] The pad may include a greater number of plating layers than the circuit wiring.

[0008] The pad and the circuit wiring may each include at least one electroless plating layer, and a thickness of the electroless plating layer of the circuit wiring may be greater than a thickness of the electroless plating layer of the pad.

[0009] The pad may include a first pad seed layer pattern, an extension portion of the through-via, a second pad seed layer pattern, and a pad plating layer pattern sequentially stacked on the insulating layer, and the circuit wiring may include a first circuit seed layer pattern, a second circuit seed layer pattern, and a circuit plating layer pattern sequentially stacked on the insulating layer. The extension portion of the through-via may extend from both ends of the through-via portion in a direction perpendicular to the one direction, and the through-via portion extends in the one direction to cover the inner wall of the via hole.

[0010] The extension may be an electroplating pattern, and the first pad seed layer pattern, the second pad seed layer pattern, the first circuit seed layer pattern, and the second circuit seed layer pattern may be electroless plating layer patterns.

[0011] The thickness of the circuit plating layer pattern may be greater than the thickness of the pad plating layer pattern.

[0012] The second pad seed layer pattern may cover at least a portion of a sidewall of the extension.

[0013] The pad plating layer pattern may cover at least a portion of a sidewall of the extension portion.

[0014] The penetration portion may include a hollow portion penetrating in the one direction in the penetration portion.

[0015] The circuit board according to the embodiment may further include a plug provided in the hollow portion and protruding to the outside of the surface of the insulating layer.

[0016] The extension portion may surround a portion of the plug protruding to the outside of the surface of the insulating layer.

[0017] According to an embodiment, a method for manufacturing a circuit board may include: forming a via hole passing through a first insulating layer; forming a first seed layer on a surface of the first insulating layer on which the via hole is formed; forming a first mask pattern on the first seed layer to expose the via hole and an area of ​​the first seed layer around the via hole; forming a through via hole on the area of ​​the first seed layer exposed by the first mask pattern, the through via hole having a hollow portion; forming a pre-plug filling the hollow portion of the through via hole; planarizing the pre-plug, the first mask pattern and the through via hole; removing the first mask pattern remaining after the planarization; forming a second seed layer on the first seed layer, an extension of the through via hole extending on the first insulating layer, and a plug formed by planarizing the pre-plug; forming a second mask pattern, the second mask pattern exposing an area of ​​the second seed layer on the plug and on at least a portion of the extension of the through via hole and another area of ​​the second seed layer spaced apart from the area of ​​the second seed layer; and forming a plating layer pattern on the area of ​​the second seed layer exposed by the second mask pattern.

[0018] The method of manufacturing a printed circuit board may further include removing the second seed layer and portions of the first seed layer exposed by the plating layer pattern after removing the second mask pattern.

[0019] The method of manufacturing a printed circuit board may further include forming a second insulating layer on the first insulating layer to bury the electroplating layer pattern.

[0020] The forming of the plating layer pattern may include forming the pad plating layer pattern to have a step with the extension portion by plating in a region opened using the second mask pattern.

[0021] The forming of the pad plating layer pattern may include forming the pad plating layer pattern to cover a portion of the second seed layer extending on the first seed layer at one end.

[0022] The forming of the plug may include forming the plug to include a non-conductive material.

[0023] The method for manufacturing a printed circuit board may further include forming a copper foil (Cu foil) layer on the first insulating layer, wherein the forming of the first seed layer may include forming the first seed layer on the Cu foil layer.

[0024] The pad may be formed by sequentially stacking the copper foil layer, the first seed layer, the extension of the through via, the second seed layer, and the plating layer pattern on the first insulating layer.

[0025] A circuit wiring may be formed by sequentially stacking the copper foil layer, the first seed layer, the second seed layer, and the plating layer pattern on the first insulating layer.

[0026] The forming of the first seed layer may include forming the first seed layer by electroless plating.

[0027] The forming of the second seed layer may include forming the second seed layer by electroless plating.

[0028] According to an embodiment, a circuit board may include: an insulating layer having a via hole extending therethrough in one direction; a pad disposed on the insulating layer to cover the via hole and including a pad seed layer pattern and a pad electroplating layer pattern disposed on the pad seed layer pattern; and a circuit wiring disposed on the insulating layer and including a circuit seed layer pattern and a circuit electroplating layer pattern disposed on the circuit seed layer pattern. The thickness of the circuit electroplating layer pattern disposed on the circuit seed layer pattern may be greater than the thickness of the pad electroplating layer pattern disposed on the pad seed layer pattern to overlap the via hole.

[0029] According to the circuit board and the method for manufacturing the circuit board of the embodiment, circuit design restrictions due to the metal thickness of the circuit layer can be reduced, and circuit patterns can be miniaturized. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1is a cross-sectional view schematically showing a circuit board according to an embodiment.

[0031] Figure 2 yes Figure 1 Magnified view of area A.

[0032] Figures 3 to 12 is a cross-sectional view schematically illustrating a method of manufacturing a circuit board according to an embodiment.

[0033] Figure 13 is a cross-sectional view schematically showing a circuit board according to another embodiment.

[0034] Figure 14 yes Figure 13 Magnified view of area B.

[0035] Figure 15 It shows Figure 13 A cross-sectional view showing a method for manufacturing a circuit board. DETAILED DESCRIPTION

[0036] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily implement the present disclosure. In order to clearly describe the present disclosure, parts not related to the description are omitted in the accompanying drawings, and the same or similar reference numerals are assigned to the same or similar elements throughout the specification. In addition, in the accompanying drawings, some elements are exaggerated, omitted, or shown schematically, and the size of each element does not fully reflect the actual size.

[0037] The drawings are provided only to facilitate the understanding of the embodiments disclosed in this specification, and the drawings should not be interpreted as limiting the technical concepts disclosed in this specification. It should be understood that the present disclosure includes all modifications, equivalents, and alternatives without departing from the scope and concept of the present disclosure.

[0038] Terms including ordinal numbers such as "first," "second," etc. are only used to describe various elements and should not be interpreted as limiting these elements. These terms are only used to distinguish one element from other elements.

[0039] Furthermore, it will be understood that when an element, such as a layer, film, region, or substrate, is referred to as being "on" another element, the element may be directly on the other element, or other elements may be present between them. In contrast, when an element is referred to as being "directly on" another element, there are no other elements present between them. Furthermore, in the specification, the words "on..." or "above..." indicate positioning above or below a target portion, and do not necessarily mean positioning on the upper side of the target portion based on the direction of gravity.

[0040] It will be further understood that the terms "include / comprising" or "having" used throughout the specification specify the presence of stated features, numbers, steps, operations, elements, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, parts, or combinations thereof. Therefore, unless explicitly described to the contrary, the word "comprise" and its variations will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0041] Furthermore, throughout the specification, the expression “in a plan view” means that a target portion is viewed from above, and the expression “in a cross-sectional view” means that a cross section taken by vertically cutting the target portion is viewed from the side.

[0042] Throughout the specification, the expression "connected" may not only mean that two or more elements are directly connected, but also that two or more elements are indirectly connected, physically connected, and electrically connected through other elements, or that two or more elements are integrated but referred to by different names according to position or function.

[0043] In the following, reference will be made to Figure 1 and Figure 2 A circuit board 10A according to the embodiment is described.

[0044] Figure 1 is a cross-sectional view schematically showing a circuit board according to an embodiment. Figure 2 yes Figure 1 Magnified view of area A.

[0045] Reference Figure 1 and Figure 2 The circuit board 10A according to the embodiment may include a first insulating layer 100 provided as a core layer. The first circuit layer 120 may be provided on both surfaces of the first insulating layer 100 and may include a first pad 120P and a first circuit wiring 120C.

[0046] The second insulating layer 200 may be disposed on the first insulating layer 100 to cover the first circuit layer 120. The second circuit layer 220 including the second pad 220P and the second circuit wiring 220C may be disposed on the second insulating layer 200. The second pad 220P may be connected to the first pad 120P through the stacked via 210 penetrating the second insulating layer 200.

[0047] A passivation layer 300 may be disposed on the second insulating layer 200. The passivation layer 300 may protect internal components from external physical and chemical damage. The passivation layer 300 may cover the surface of the second insulating layer 200 and expose at least a portion of the second pad 220P. For example, the passivation layer 300 may be a solder resist layer formed using a photosensitive resin.

[0048] The first insulating layer 100 and the second insulating layer 200 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material formed by impregnating an inorganic filler (such as silica) and / or a reinforcing material (such as glass fiber) into a thermosetting resin or a thermoplastic resin. The insulating material may be a photosensitive material or a non-photosensitive material. For example, solder resist (SR), Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), resin coated copper (RCC), or copper clad laminate (CCL) etc. may be used as the insulating material, but are not limited thereto. The insulating material may include a polymer material. For example, a semi-cured sheet may be used, but is not limited thereto. In addition, the first insulating layer 100 may be formed on Figure 1 and Figure 2 A plurality of thin layers may be stacked to form the first insulating layer 100.

[0049] Each of the first circuit layer 120 and the second circuit layer 220 can transmit signals within the circuit board 10A. Metal materials can be used for each of the first circuit layer 120 and the second circuit layer 220. Metal materials can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the first circuit layer 120 and the second circuit layer 220 can perform various functions depending on its design, such as serving as a ground pattern, a power pattern, a signal pattern, etc. Each of these patterns can have a linear shape, a flat shape, or a pad shape. The outermost circuit layer among the multiple circuit layers can serve as a pad for connection to another board or component.

[0050] The first insulating layer 100 may have a via hole 104 extending in a first direction through the first insulating layer 100. The first direction may be a stacking direction. The through-via 110 may have a hollow portion extending to fill the through-via 104, the hollow portion extending in the first direction through the through-via 110. The plug 112 may fill the hollow portion and protrude to the outside of the surface of the first insulating layer 100. The through-via 110 may include a through portion 110a extending in the first direction to cover the inner wall of the through-via 104. In addition, the through-via 110 may include an extension portion 110b extending from both ends of the through portion 110a in a direction perpendicular to the first direction and surrounding a portion of the plug 112 protruding to the outside of the surface of the first insulating layer 100. The first pads 120P on both surfaces of the first insulating layer 100 may be connected to each other through the through-via 110.

[0051] A metal material may be used as the material of each of the through via 110 and the stacked via 210. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Depending on the circuit design, each of the through via 110 and the stacked via 210 may include a signal via, a ground via, a power via, or the like.

[0052] The plug 112 may include a plugging ink having insulating properties and may fill the empty space in the via hole 104 to prevent the through-via 110 from being oxidized.

[0053] In the following, reference will be made to Figure 1 and Figure 2 The first pad 120P and the first circuit wiring 120C of the circuit board 10A according to the embodiment are described in detail.

[0054] Reference Figure 1 and Figure 2 , the first pad 120P and the first circuit wiring 120C may be disposed on the first insulating layer 100 and have different layer structures.

[0055] The first pad 120P may include a first pad copper foil layer pattern 102P and a first pad seed layer pattern 106P, the first pad copper foil layer pattern 102P and the first pad seed layer pattern 106P being interposed between the extension 110b of the through-via 110 and the first insulating layer 100 and sequentially stacked on the first insulating layer 100 along a first direction. In addition, the first pad 120P may include a second pad seed layer pattern 114P and a first pad electroplating layer pattern 118P sequentially stacked on the extension 110b. The second pad seed layer pattern 114P may cover the upper surface of the extension 110b. In some cases, the second pad seed layer pattern 114P may cover the upper surface of the extension 110b and may cover at least a portion of the side surface of the extension 110b. As described later, the first pad seed layer pattern 106P and the second pad seed layer pattern 114P may be metal layers formed by electroless plating, such as Cu layers. In addition, the extension portion 110b and the first pad plating layer pattern 118P may be a metal layer, for example, a Cu layer, formed on the first pad seed layer pattern 106P and the second pad seed layer pattern 114P, respectively, by electroplating.

[0056] On the other hand, the first circuit wiring 120C may include a first circuit copper foil layer pattern 102C, a first circuit seed layer pattern 106C, a second circuit seed layer pattern 114C, and a first circuit electroplating layer pattern 118C sequentially stacked on the first insulating layer 100. The first circuit seed layer pattern 106C and the second circuit seed layer pattern 114C may be metal layers formed by electroless plating, such as Cu layers. In addition, the first circuit electroplating layer pattern 118C may be a metal layer formed on the second circuit seed layer pattern 114C by electroplating, such as Cu layers.

[0057] The first pad 120P may include two electroplating layers (the extension 110b and the first pad electroplating layer pattern 118P) and an electroless plating layer (the second pad seed layer pattern 114P) interposed between the two electroplating layers. On the other hand, the first circuit wiring 120C may include two electroless plating layers (the first circuit seed layer pattern 106C and the second circuit seed layer pattern 114C) stacked sequentially and an electroplating layer (the first circuit plating layer pattern 118C).

[0058] The two sequentially stacked electroless plating layers (the first circuit seed layer pattern 106C and the second circuit seed layer pattern 114C) may be considered as a single layer. In this case, the electroless plating layer of the first circuit wiring 120C may have a greater thickness than the electroless plating layer of the first pad 120P.

[0059] The first pad 120P and the first circuit wiring 120C may have substantially the same thickness, but as described later, the first pad plating layer pattern 118P and the first circuit plating layer pattern 118C formed by the same process may have different thicknesses. In other words, the thickness of the first circuit plating layer pattern 118C may be greater than the thickness of the first pad plating layer pattern 118P.

[0060] As described above, according to the embodiments of the circuit board, circuit design restrictions due to the metal thickness of the circuit layer are reduced, and a miniaturized circuit pattern can be achieved.

[0061] In the following, reference will be made to Figures 3 to 12 A method of manufacturing the circuit board 10A according to the embodiment is described.

[0062] Figures 3 to 12 is a cross-sectional view illustrating a method of manufacturing a circuit board according to an embodiment.

[0063] Reference Figure 3A first insulating layer 100 having copper foil layers 102 formed on both surfaces thereof may be prepared. The copper foil layer 102 may be formed by stacking and pressing copper foil on both surfaces of the first insulating layer 100. Via holes 104 may be formed to penetrate the first insulating layer 100 and the copper foil layer 102. The plurality of via holes 104 may be formed by laser processing, mechanical drilling, or the like.

[0064] Reference Figure 4 A first seed layer 106 may be formed on the surface of the first insulating layer 100 where the via hole 104 is formed. The first seed layer 106 may be formed on the copper foil layer 102 and on the inner wall of the via hole 104. The first seed layer 106 may be formed using a copper (Cu) layer by electroless plating. A first mask pattern 108P may be formed on the first seed layer 106 to expose the via hole 104 and the first seed layer 106 surrounding the via hole 104. The first mask pattern 108P may expose areas on the first seed layer 106 located along the edge of the via hole 104. The first mask pattern 108P may be patterned by exposing and developing a photosensitive dry film.

[0065] Reference Figure 5 , a through-via 110 may be formed on the first seed layer 106 exposed by the first mask pattern 108P. The through-via 110 may include a through portion 110a on the inner wall of the via hole 104 and an extension portion 110b connected to the through portion 110a and extending to the upper and lower surfaces of the first insulating layer 100. The through-via 110 may be formed by electroplating the exposed first seed layer 106 using the first mask pattern 108P as a plating mask, and the through-via 110 may be formed using copper (Cu).

[0066] Reference Figure 6 The pre-plug 112P may be formed to fill the interior of the via hole 104 in which the through-via 110 is formed and to extend on the extension 110b. The pre-plug 112P may be formed by printing insulating ink.

[0067] Reference Figure 7 , the portion of the pre-plug 112P formed on the extension 110b of the through-via 110, the extension 110b of the through-via 110, and the first mask pattern 108P may be polished to planarize their surfaces. In this process, the portion of the pre-plug 112P extending on the extension 110b may be removed to form the plug 112. In addition, the thickness of the extension 110b and the first mask pattern 108P may be reduced, and the surfaces of the plug 112, the extension 110b, and the first mask pattern 108P may be arranged on substantially the same plane. The through portion 110a of the through-via 110 may surround the plug 112. The plug 112 may be formed to include a non-conductive material.

[0068] Reference Figure 8 After stripping and removing the remaining first mask pattern 108P, a second seed layer 114 may be formed on the first seed layer 106, the extension 110b of the through via 110, and the plug 112. The second seed layer 114 may be formed using copper (Cu) by electroless plating.

[0069] Reference Figure 9 , a second mask pattern 116P may be formed on the second seed layer 114. The second mask pattern 116P may continuously expose the second seed layer 114 on the plug 112 and the second seed layer 114 on at least a portion of the extension 110b. In addition, the second mask pattern 116P may expose areas of the second seed layer 114 where pads and circuit wiring will be formed. The second mask pattern 116P may be patterned by exposing and developing a photosensitive dry film.

[0070] Reference Figure 9 and Figure 10 , a first pad plating layer pattern 118P and a first circuit plating layer pattern 118C can be formed on the exposed second seed layer 114 by using the second mask pattern 116P as a plating mask. The first pad plating layer pattern 118P and the first circuit plating layer pattern 118C can be formed using copper (Cu). Then, the second mask pattern 116P can be stripped and removed.

[0071] In addition, when Figure 9 When the second mask pattern 116P is formed to be partially or completely spaced apart from the second seed layer 114 formed on the sidewall of the extension portion 110b, the first pad plating layer pattern 118P may be formed to partially or completely cover the second seed layer 114 formed on the sidewall of the extension portion 110b (see Figure 13 ).

[0072] Reference Figure 11 After removing the second mask pattern 116P, the exposed portion of the second seed layer 114 and the portions of the first seed layer 106 and the copper foil layer 102 below the exposed portion of the second seed layer 114 may be removed to form a first pad 120P and a first circuit wiring 120C.

[0073] As a result, the first pad 120P may include a first pad copper foil layer pattern 102P, a first pad seed layer pattern 106P, an extension 110b of the through-via 110, a second pad seed layer pattern 114P, and a first pad electroplating layer pattern 118P sequentially stacked on the first insulating layer 100. The first circuit wiring 120C may include a first circuit copper foil layer pattern 102C, a first circuit seed layer pattern 106C, a second circuit seed layer pattern 114C, and a first circuit electroplating layer pattern 118C sequentially stacked on the first insulating layer 100. The first pad 120P may include two electroplating layers (the extension 110b and the first pad electroplating layer pattern 118P), while the first circuit wiring 120C may include one electroplating layer (the first circuit electroplating layer pattern 118C). Furthermore, the first pad 120P may be formed so that the electroplating layer is interposed between two electroless plating layers, while the first circuit wiring 120C may be formed so that the two electroless plating layers are in direct and complete contact with each other.

[0074] In addition, the exposed portion of the second seed layer 114 and the portions of the first seed layer 106 and the copper foil layer 102 below the exposed portion of the second seed layer 114 can be removed by wet etching using a chemical solution, and depending on the extent or method of etching, the second seed layer 114 on the sidewall of the extension 110b can be partially or completely removed. For example, when the chemical solution is sprayed in a direction perpendicular to the stacking direction, the second seed layer 114 on the sidewall of the extension 110b can partially remain.

[0075] Reference Figure 12 , a second insulating layer 200 may be formed on the first insulating layer 100 to bury the first pad 120P and the first circuit wiring 120C. Then, a second pad 220P and a second circuit wiring 220C may be formed on the second insulating layer 200. In addition, a stacked via 210 may be formed to penetrate the second insulating layer 200 and connect the first pad 120P and the second pad 220P to each other. The second pad 220P, the second circuit wiring 220C, and the stacked via 210 may be formed by a wiring formation process (e.g., a subtractive process, an additive process (AP), a semi-additive process (SAP), or a modified semi-additive process (MSAP)).

[0076] Reference Figure 1 A passivation layer 300 exposing a portion of the second pad 220P may be formed on the second insulating layer 200 on which the second pad 220P and the second circuit wiring 220C are formed. The passivation layer 300 may be a solder resist layer formed by exposing and developing a photosensitive resin.

[0077] According to the method for manufacturing a circuit board of an embodiment, the through via is formed after a mask pattern is formed on the copper foil layer and the seed layer stacked on the insulating layer, so that the through via can be formed finer and more delicate, compared with etching after plating the entire upper surface of the insulating layer.

[0078] In addition, according to the method for manufacturing a circuit board of the embodiment, by forming circuit wiring using the MSAP method, it is possible to reduce circuit design restrictions due to the metal thickness of the circuit wiring and miniaturize the circuit without affecting the formation of through vias and plugs.

[0079] Hereinafter, a circuit board 10B and a method of manufacturing the same according to another embodiment will be described.

[0080] Figure 13 is a cross-sectional view schematically showing a circuit board according to another embodiment. Figure 14 yes Figure 13 Magnified view of area B. Figure 15 It shows Figure 13 A cross-sectional view showing a method for manufacturing a circuit board.

[0081] Reference Figure 13 and Figure 14 , a circuit board 10B according to another embodiment is similar to the circuit board 10B according to the reference Figures 1 to 12 The circuit board 10A of the embodiment is described. Detailed description of the same elements may be omitted.

[0082] Different from Figure 1 and Figure 2 The circuit board 10A of the embodiment shown is Figure 13 and Figure 14 According to another embodiment, a circuit board 10B may include an extension portion 110b and a first pad plating layer pattern 118P having a step arranged at one end. The first pad plating layer pattern 118P may include a portion that does not overlap with the extension portion 110b in the stacking direction. The first pad plating layer pattern 118P may be configured to expose a portion of the second pad seed layer pattern 114P from the first pad plating layer pattern 118P at one end and cover another portion of the second pad seed layer pattern 114P at the other end.

[0083] Reference Figure 15 The manufacturing method of the circuit board 10B according to another embodiment is similar to that according to the reference Figures 3 to 12 The method for manufacturing the circuit board 10A of the embodiment is described. Detailed descriptions of the same elements may be omitted.

[0084] According to Figure 3 and Figure 12 The manufacturing method of the circuit board 10A of the embodiment shown in FIG is different. Figure 13 and Figure 15 In a method for manufacturing a circuit board 10B according to another embodiment, the center of the extension portion 110b and the center of the opening area of ​​the second mask pattern 116P may not coincide with each other, and a portion of the second mask pattern 116P may be formed to overlap the extension portion 110b in the stacking direction. Therefore, the second pad seed layer pattern 114P and the first pad electroplating layer pattern 118P may be formed to have a step with the extension portion 110b by plating in the opening area of ​​the second mask pattern 116P. The second pad seed layer pattern 114P may be formed to extend over the first pad seed layer pattern 106P at one end. The first pad electroplating layer pattern 118P may be formed to cover the second pad seed layer pattern 114P extending over the first pad seed layer pattern 106P at its other end.

[0085] As described above, according to another embodiment of the circuit board and the manufacturing method thereof, the extension portion of the through via and the circuit layer are formed by separate plating processes instead of forming them simultaneously in a single plating process. This can reduce the circuit design limitations caused by the metal thickness of the circuit layer without affecting the formation of the through via and the plug, and can miniaturize the circuit.

[0086] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited thereto, and various modifications can be made within the scope of the claims, detailed description, and drawings, and these modifications naturally also fall within the scope of the present disclosure.

Claims

1. A circuit board, comprising: an insulating layer having a via hole penetrating in one direction; a pad, disposed on the insulating layer to cover the via hole; as well as Circuit wiring is provided on the insulating layer, wherein the pad comprises a first plurality of metal layers, the circuit wiring comprises a second plurality of metal layers, and The number of the first plurality of metal layers of the pad is greater than the number of the second plurality of metal layers of the circuit wiring.

2. The circuit board according to claim 1, wherein: Compared with the circuit wiring, the pad includes a larger number of electroplating layers.

3. The circuit board according to claim 1, wherein: The pad and the circuit wiring each include at least one electroless plating layer, and a thickness of the electroless plating layer of the circuit wiring is greater than a thickness of the electroless plating layer of the pad.

4. The circuit board according to claim 1, wherein: The pad includes a first pad seed layer pattern, an extension portion of the through-via hole, a second pad seed layer pattern, and a pad plating layer pattern sequentially stacked on the insulating layer, and The circuit wiring includes a first circuit seed layer pattern, a second circuit seed layer pattern, and a circuit plating layer pattern sequentially stacked on the insulating layer, The extending portion of the through-via extends from both ends of the through-via portion in a direction perpendicular to the one direction, and the through-via portion extends in the one direction to cover the inner wall of the passage hole.

5. The circuit board according to claim 4, wherein: The extension is a plating pattern, and The first pad seed layer pattern, the second pad seed layer pattern, the first circuit seed layer pattern, and the second circuit seed layer pattern are electroless plating layer patterns.

6. The circuit board according to claim 4, wherein: The thickness of the circuit electroplating layer pattern is greater than the thickness of the pad electroplating layer pattern.

7. The circuit board according to claim 4, wherein: The second pad seed layer pattern covers at least a portion of a sidewall of the extension portion.

8. The circuit board according to claim 4, wherein: The pad plating layer pattern covers at least a portion of a sidewall of the extension portion.

9. The circuit board according to claim 4, wherein: The penetration portion includes a hollow portion that penetrates the penetration portion in the one direction.

10. The circuit board according to claim 9, further comprising: A plug is provided in the hollow portion and protrudes outside the surface of the insulating layer.

11. The circuit board according to claim 10, wherein: The extension portion surrounds a portion of the plug protruding to the outside of the surface of the insulating layer.

12. A method for manufacturing a circuit board, comprising: forming a via hole penetrating the first insulating layer; forming a first seed layer on a surface of the first insulating layer where the via hole is formed; forming a first mask pattern on the first seed layer to expose the via hole and a region of the first seed layer around the via hole; forming a through via hole on the region of the first seed layer exposed by the first mask pattern, wherein the through via hole has a hollow portion; forming a pre-plug filling the hollow portion of the through via; planarizing the pre-plug, the first mask pattern, and the through via; removing the first mask pattern remaining after the planarization; forming a second seed layer on the first seed layer, the extension portion of the through via extending on the first insulating layer, and the plug formed by planarizing the pre-plug; forming a second mask pattern that exposes a region of the second seed layer on the plug and on at least a portion of the extension of the through via and another region of the second seed layer spaced apart from the region of the second seed layer, and An electroplating layer pattern is formed on the region of the second seed layer exposed by the second mask pattern.

13. The manufacturing method according to claim 12, further comprising: After removing the second mask pattern, portions of the second seed layer and the first seed layer exposed by the electroplating layer pattern are removed.

14. The manufacturing method according to claim 12, further comprising: A second insulating layer is formed on the first insulating layer to bury the electroplating layer pattern.

15. The manufacturing method according to claim 12, wherein: The forming of the plating layer pattern includes forming a pad plating layer pattern to have a step with the extension portion by plating in a region opened by the second mask pattern.

16. The manufacturing method according to claim 15, wherein: The forming of the pad plating layer pattern includes forming the pad plating layer pattern to cover a portion of the second seed layer extending on the first seed layer at one end.

17. The manufacturing method according to claim 12, wherein: The forming of the plug includes forming the plug to include a non-conductive material.

18. The manufacturing method according to claim 12, further comprising: forming a copper foil layer on the first insulating layer, The forming of the first seed layer includes forming the first seed layer on the copper foil layer.

19. The manufacturing method according to claim 18, wherein: A pad is formed by sequentially stacking the copper foil layer, the first seed layer, the extension of the through via, the second seed layer, and the plating layer pattern on the first insulating layer.

20. The manufacturing method according to claim 18, wherein: A circuit wiring is formed by sequentially stacking the copper foil layer, the first seed layer, the second seed layer, and the electroplating layer pattern on the first insulating layer.

21. The manufacturing method according to claim 12, wherein: The forming of the first seed layer includes forming the first seed layer by electroless plating.

22. The manufacturing method according to claim 12, wherein: The forming of the second seed layer includes forming the second seed layer by electroless plating.

23. A circuit board comprising: an insulating layer having a via hole penetrating in one direction; a pad disposed on the insulating layer to cover the via hole and comprising a pad seed layer pattern and a pad electroplating layer pattern disposed on the pad seed layer pattern; as well as a circuit wiring, provided on the insulating layer, and comprising a circuit seed layer pattern and a circuit plating layer pattern provided on the circuit seed layer pattern, The thickness of the circuit plating layer pattern disposed on the circuit seed layer pattern is greater than the thickness of the pad plating layer pattern disposed on the pad seed layer pattern to overlap with the via hole.

24. The circuit board of claim 23, wherein: The pad seed layer pattern includes a first pad seed layer pattern and a second pad seed layer pattern, and The pad further includes an extension portion of the through-via, and the extension portion of the through-via is disposed between the first pad seed layer pattern and the second pad seed layer pattern.

25. The circuit board of claim 24, wherein: The extending portion of the through via is spaced apart from the circuit wiring.

26. The circuit board of claim 24, wherein: The second pad seed layer pattern covers at least a portion of a sidewall of the extension portion.

27. The circuit board of claim 24, wherein: The through-via further includes a through portion extending in the one direction to cover an inner wall of the via hole, and a plug provided in a hollow portion in the through portion.

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