Overlay error control method

Abstract

An overlay error control method comprises the following steps: executing a first photoetching process, transferring a first pattern on a first mask to a substrate structure, and forming a plurality of gate grooves and a plurality of identification grooves; forming gate material layers in the plurality of gate grooves and the plurality of identification grooves; planarizing the gate material layer by adopting a first chemical mechanical polishing process, taking the gate material layer in the gate groove as a gate structure, taking the gate material layer in the identification groove as an initial gate identification structure, and enabling the top surface of a part of the initial gate identification structure to have groove defects; performing metal silicide treatment on the gate structure and the initial gate identification structure, forming a compensation layer on the top surface of the initial gate identification structure, taking the initial gate identification structure and the compensation layer as a gate identification structure so as to fill the groove defect, and forming a contact layer on the top surface of the gate structure; and executing the second photoetching process, and carrying out the first alignment operation of the photoetching machine by adopting the gate identification structure, thereby being beneficial to reducing the overlay error.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an overlay error control method. Background Art

[0002] Overlay error is a key parameter in semiconductor manufacturing that measures the alignment accuracy of patterns at different process layers, directly impacting the yield and performance of integrated circuits. To minimize overlay error, the alignment system in the lithography machine aligns the pattern on the mask with the existing pattern on the wafer to ensure accurate overlay between the patterns after exposure.

[0003] The alignment marks used for alignment on the wafer need to be invulnerable to process damage and effectively detected by the alignment optical system, providing maximum signal strength. However, in actual processing, the integrity of the alignment marks is often easily damaged, thus affecting the reduction of overlay error.

[0004] Therefore, the existing overlay error control method needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide an overlay error control method to reduce the overlay error and improve the device yield.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides an overlay error control method, comprising: providing a substrate structure, wherein the substrate structure comprises a substrate and a hard mask layer located on the surface of the substrate, and the substrate structure further comprises a chip area and a cutting road area; performing a first photolithography process to transfer a first pattern on a first mask to the substrate structure, wherein the first pattern comprises a plurality of gate patterns and a plurality of alignment marks, forming a plurality of gate grooves in the chip area, and forming a plurality of mark grooves in the cutting road area, wherein the gate grooves correspond to the gate patterns, and the mark grooves correspond to the alignment marks; forming a gate material layer on the surface of the substrate structure, in the plurality of gate grooves, and in the plurality of mark grooves; adopting a first photolithography process to transfer a first pattern on a first mask to the substrate structure, wherein the first pattern comprises a plurality of gate patterns and a plurality of alignment marks, forming a plurality of gate grooves in the chip area, and forming a plurality of mark grooves in the cutting road area, wherein the gate grooves correspond to the gate patterns, and the mark grooves correspond to the alignment marks; forming a gate material layer on the surface of the substrate structure, in the plurality of gate grooves, and in the plurality of mark grooves; and A chemical mechanical polishing process is used to planarize the gate material layer until the surface of the hard mask layer is exposed, the gate material layer in the gate groove is used as the gate structure, the gate material layer in the identification groove is used as the initial gate identification structure, and the top surface of part of the initial gate identification structure has groove defects; the gate structure and the initial gate identification structure are treated with metal silicide, a compensation layer is formed on the top surface of the initial gate identification structure, the initial gate identification structure and the compensation layer are used as the gate identification structure, so that the groove defects are filled and a contact layer is formed on the top surface of the gate structure; a second photolithography process is performed, and the gate identification structure is used to perform the first alignment operation of the photolithography machine.

[0007] Optionally, after the metal silicide treatment, part of the compensation layer protrudes from the hard mask layer; the method further includes: before the first alignment operation, using a second chemical mechanical polishing process to flatten the protruding compensation layer so that the compensation layer and the hard mask layer are flush.

[0008] Optionally, after the metal silicide treatment, part of the contact layer protrudes from the hard mask layer, and the second chemical mechanical polishing process further performs a planarization treatment on the protruding contact layer to make the contact layer flush with the hard mask layer.

[0009] Optionally, the etching selectivity range of the second chemical mechanical polishing process for the compensation layer and the hard mask layer is greater than 30:1.

[0010] Optionally, the second chemical mechanical polishing process thins the hard mask layer to a thickness ranging from 300Å to 500Å.

[0011] Optionally, performing the first photolithography process also includes: forming a first photoresist material layer on the surface of the substrate structure; using the first mask to expose and develop the first photoresist material layer to transfer the first pattern to the first photoresist material layer to form a patterned first photoresist layer; using the first photoresist layer as a mask to etch the substrate structure; after forming a plurality of gate grooves and a plurality of identification grooves, removing the first photoresist layer.

[0012] Optionally, performing the second photolithography process also includes: forming a second photoresist material layer on the surface of the substrate structure; exposing and developing the second photoresist material layer to form a patterned second photoresist layer, wherein the second photoresist layer exposes a portion of the chip area, and performing the first alignment operation before exposing the second photoresist material layer; after the second photolithography process, it also includes: using the second photoresist layer as a mask to inject dopant ions into the chip area on both sides of the gate structure to form a doped area; after forming the doped area, removing the second photoresist layer.

[0013] Optionally, it also includes: after removing the second photoresist layer, forming a dielectric material layer on the surface of the substrate structure; performing a third photolithography process to form a contact hole in the dielectric material layer, wherein the contact hole exposes a portion of the top surface of the contact layer, and the third photolithography process performs a second alignment operation with the gate identification structure; after performing the third photolithography process, it also includes: forming a conductive plug in the contact hole.

[0014] Optionally, performing the third photolithography process includes: forming a third photoresist material layer on the surface of the dielectric material layer; exposing and developing the third photoresist material layer to form a patterned third photoresist layer, and performing the second alignment operation before exposing the third photoresist material layer; etching the dielectric material layer using the third photoresist layer as a mask to form the contact hole; and removing the third photoresist layer after forming the contact hole.

[0015] Optionally, the material of the compensation layer includes one or more of titanium silicide, cobalt silicide and silicon platinum nickel; and the material of the gate material layer includes polysilicon.

[0016] Optionally, the material of the hard mask layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0017] Optionally, the hard mask layer has a thickness ranging from 1500Å to 5000Å.

[0018] Optionally, the depth of the groove defect ranges from 200Å to 400Å.

[0019] Compared with the existing technology, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0020] In the overlay error control method provided by the technical solution of the present invention, before performing the first alignment operation, metal silicide treatment is used to selectively grow on the surface of the exposed gate structure and the initial gate identification structure, so that the groove defects can be filled. Several gate identification structures are used as alignment marks on the wafer, which improves the stability of the alignment mark morphology, reduces the adverse effects of the groove defects on the alignment signal, and is beneficial to reducing the overlay error, thereby helping to improve the device yield, reduce the rework rate and production costs; in addition, forming a contact layer on the top surface of the gate structure can reduce the contact resistance, increase the speed of the circuit, and overall help to improve product performance.

[0021] Furthermore, a second chemical mechanical polishing process is used to flatten the protruding compensation layer so that the compensation layer and the hard mask layer are flush, which is beneficial to improving the uniformity of several gate identification structures, thereby improving the stability of the alignment signal, reducing the overlay error, and thus improving the device yield and reducing the rework rate and production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 3 It is a schematic diagram of a semiconductor structure of each step of an overlay error control method;

[0023] Figure 41 is a flow chart of an overlay error control method according to an embodiment of the present invention;

[0024] Figures 5 to 12 Schematic diagram of semiconductor structure of each step of the overlay error control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0026] As described in the background art, the existing overlay error control method needs to be further improved. Now, an overlay error control method in a power device process is described and analyzed.

[0027] Figures 1 to 3 The present invention is a schematic diagram of a semiconductor structure showing various steps of an overlay error control method.

[0028] Please refer to Figure 1 , providing a substrate, the substrate comprising a base 100 and an epitaxial layer 101 located on the surface of the base 100; forming a mask layer 102 on the surface of the epitaxial layer 101; using a first photolithography process, transferring the alignment mark on the first mask to the surface of the substrate, and forming a plurality of marking grooves 103 in the epitaxial layer 101.

[0029] Please refer to Figure 2 , forming a gate material layer (not shown in the figure) on the substrate surface and in the plurality of identification grooves 103; using a chemical mechanical polishing (CMP) process to planarize the gate material layer until the surface of the mask layer 102 is exposed, and forming a plurality of gate identification structures 104 in the plurality of identification grooves 103.

[0030] Please refer to Figure 3 A photoresist material layer 106 is formed on the surface of the mask layer 102 and the surfaces of the gate mark structures 104 .

[0031] The above-mentioned overlay error control method is used in the formation process of the trench MOSFET structure, wherein the substrate includes a chip area and a cutting road area, and the alignment mark is usually formed in the cutting road area. Subsequently, a second photolithography process is required to pattern the photoresist material layer 106 to form a source doping region in the chip area. Before the second photolithography process, it is necessary to identify the alignment mark on the wafer to align the photolithography machine. However, the above-mentioned CMP process may cause damage to the alignment mark. Specifically, due to reasons such as the difference in grinding rates of different materials, over-grinding may occur, and groove defects 105 of varying heights may appear on the surface of some gate identification structures 104. The groove defects 105 may cause the alignment mark to have a poor morphology and poor stability, thereby affecting the alignment of the photolithography machine, and ultimately resulting in a large overlay error, affecting the yield of the device.

[0032] In order to overcome the above problems, in another embodiment, various alignment marks are designed on the first mask, and various light sources (red light / green light / far infrared / near infrared) are replaced when aligning the lithography machine to find the best light source and alignment mark for each product.

[0033] However, when trench MOSFET structures are used in power devices, due to the large number of power device products and the differences between each product, the process of finding the optimal light source and alignment mark is complicated and tedious, seriously affecting work efficiency; furthermore, each wafer is affected differently by the CMP process, resulting in overlay error deviations exceeding the control standards, requiring rework and re-evaluation of the alignment signal, which increases costs.

[0034] In order to solve the above problems, the present invention provides a method for controlling overlay errors. Before performing the first alignment operation, metal silicide treatment is used to selectively grow on the surface of the exposed gate structure and the initial gate identification structure, so that the groove defects can be filled. Several gate identification structures are used as alignment marks on the wafer, which improves the stability of the alignment mark morphology, reduces the adverse effects of the groove defects on the alignment signal, and is beneficial to reducing overlay errors, thereby improving device yield, reducing rework rate and production costs; in addition, forming a contact layer on the top surface of the gate structure can reduce contact resistance, increase circuit speed, and overall improve product performance.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figure 4 4 is a flow chart of an overlay error control method according to an embodiment of the present invention.

[0037] Please refer to Figure 4 , the overlay error control method comprises the following steps:

[0038] Step S201, providing a substrate structure, wherein the substrate structure includes a substrate and a hard mask layer located on a surface of the substrate, and the substrate structure also includes a chip area and a dicing area;

[0039] Step S202, performing a first photolithography process to transfer a first pattern on a first mask onto the substrate structure, wherein the first pattern includes a plurality of gate patterns and a plurality of alignment marks, forming a plurality of gate grooves in the chip region, and forming a plurality of mark grooves in the dicing street region, wherein the gate grooves correspond to the gate patterns, and the mark grooves correspond to the alignment marks;

[0040] Step S203, forming a gate material layer on the surface of the substrate structure, in the plurality of gate grooves, and in the plurality of mark grooves;

[0041] Step S204, planarizing the gate material layer using a first chemical mechanical polishing process until the surface of the hard mask layer is exposed, using the gate material layer in the gate groove as a gate structure, and using the gate material layer in the mark groove as an initial gate mark structure, wherein a top surface of a portion of the initial gate mark structure has a groove defect;

[0042] Step S205, performing metal silicide treatment on the gate structure and the initial gate mark structure, forming a compensation layer on the top surface of the initial gate mark structure, using the initial gate mark structure and the compensation layer as a gate mark structure, so that the groove defect is filled, and forming a contact layer on the top surface of the gate structure;

[0043] Step S206 , performing a second photolithography process, and using the gate mark structure to perform a first alignment operation of the photolithography machine.

[0044] The following is a detailed description with reference to the accompanying drawings.

[0045] Figures 5 to 12 Schematic diagram of semiconductor structure of each step of the overlay error control method according to an embodiment of the present invention.

[0046] Please refer to Figure 5 , perform step S201 to provide a substrate structure, the substrate structure includes a substrate 300 and a hard mask layer 301 located on the surface of the substrate 300, and the substrate structure also includes a chip area I and a cutting street area II.

[0047] In this embodiment, the scribe line area II surrounds the chip area I. The chip area I is used to define the positions of functional devices, and the scribe line area II is used to define the positions of alignment marks, overlay marks, test structures, and the like.

[0048] In this embodiment, the substrate 300 includes a base 30a and an epitaxial layer 30b located on a surface of the base.

[0049] In this embodiment, the substrate 300 is made of silicon.

[0050] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0051] The material of the hard mask layer 301 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the hard mask layer 301 is silicon oxide.

[0052] The thickness of the hard mask layer 301 ranges from 1500 Å to 5000 Å. In this embodiment, the thickness of the hard mask layer 301 is 2000 Å.

[0053] In this embodiment, the hard mask layer 301 is a single-layer structure.

[0054] In other embodiments, the hard mask layer may be a multi-layer composite structure, such as silicon oxide / silicon nitride / silicon oxide.

[0055] Please refer to Figure 6 , execute step S202, perform a first photolithography process, transfer a first pattern on a first mask (not shown in the figure) to the substrate structure, the first pattern including a plurality of gate patterns and a plurality of alignment marks, form a plurality of gate grooves 302 in the chip area I, and form a plurality of mark grooves 303 in the cutting lane area II, the gate grooves 302 corresponding to the gate patterns, and the mark grooves 303 corresponding to the alignment marks.

[0056] In this embodiment, the gate groove 302 and the marking groove 303 are located in the epitaxial layer 30 b.

[0057] In this embodiment, performing the first photolithography process also includes: forming a first photoresist material layer (not shown in the figure) on the surface of the substrate structure; using the first mask to expose and develop the first photoresist material layer to transfer the first pattern to the first photoresist material layer to form a patterned first photoresist layer 304; using the first photoresist layer 304 as a mask to etch the substrate structure; after forming a plurality of gate grooves 302 and a plurality of identification grooves 303, removing the first photoresist layer 304.

[0058] Please refer to Figure 7 , execute step S203 to form a gate material layer 305 on the surface of the substrate structure, in the plurality of gate grooves 302 , and in the plurality of identification grooves 303 .

[0059] The gate material layer 305 is made of polysilicon. In this embodiment, the gate material layer 305 is made of polysilicon.

[0060] Please refer to Figure 8 , executing step S204, using a first chemical mechanical polishing process to planarize the gate material layer 305 until the surface of the hard mask layer 301 is exposed, with the gate groove 302 (such as Figure 6 The gate material layer 305 in the identification groove 303 is a gate structure 306, and the gate material layer 305 in the identification groove 303 is an initial gate identification structure 307. The top surface of part of the initial gate identification structure 307 has a groove defect 308.

[0061] Here, the groove defect 308 is caused by different polishing rates between the gate material layer 305 and the hard mask layer 301 during the first chemical mechanical polishing process.

[0062] In this embodiment, the depth of the groove defect 308 ranges from 200 Å to 400 Å.

[0063] Please refer to Figure 9 , execute step S205, perform metal silicide treatment on the gate structure 306 and the initial gate identification structure 307, form a compensation layer 309 on the top surface of the initial gate identification structure 307, and use the initial gate identification structure 307 and the compensation layer 309 as the gate identification structure to make the groove defect 308 (such as Figure 8 As shown in FIG, the gate structure 306 is filled with a contact layer 310, and a contact layer 310 is formed on the top surface of the gate structure 306.

[0064] At this point, before the subsequent first alignment operation, metal silicide treatment is used to selectively grow on the surface of the exposed gate structure 306 and the initial gate identification structure 307, so that the groove defect 308 can be filled. Several gate identification structures are used as alignment marks on the wafer, which improves the stability of the alignment mark morphology, reduces the adverse effects of the groove defect 308 on the alignment signal, and helps to reduce the overlay error, thereby helping to improve the device yield, reduce the rework rate and production cost; in addition, forming a contact layer 310 on the top surface of the gate structure 306 can reduce the contact resistance, increase the speed of the circuit, and overall help to improve product performance.

[0065] The material of the compensation layer 309 includes one or more of titanium silicide, cobalt silicide, and silicon platinum nickel. In this embodiment, the material of the compensation layer 309 is titanium silicide.

[0066] After the metal silicide treatment, a portion of the compensation layer 309 protrudes from the hard mask layer 301 .

[0067] In this embodiment, before the subsequent first alignment operation is performed, a second chemical mechanical polishing process is further used to planarize the protruding compensation layer 309 so that the compensation layer 309 is flush with the hard mask layer 301 .

[0068] The second chemical mechanical polishing process is beneficial to improving the uniformity of a plurality of gate mark structures, thereby improving the stability of the alignment signal, reducing the overlay error, thereby improving the device yield, and reducing the rework rate and production cost.

[0069] In this embodiment, the second chemical mechanical polishing process has an etching selectivity range of greater than 30:1 for the compensation layer 309 and the hard mask layer 301. The purpose of selecting the above etching selectivity is to preferentially etch the protruding compensation layer 309 to improve surface flatness.

[0070] In another embodiment, the second chemical mechanical polishing process may not be performed.

[0071] In this embodiment, after the metal silicide treatment, part of the contact layer 310 protrudes from the hard mask layer 301 , and the second chemical mechanical polishing process further flattens the protruding contact layer 310 to make the contact layer 310 flush with the hard mask layer 301 .

[0072] In this embodiment, the second chemical mechanical polishing process thins the hard mask layer 301 to a thickness ranging from 300 Å to 500 Å.

[0073] Please refer to Figure 10, execute step S206, perform a second photolithography process, and use the gate mark structure to perform a first alignment operation of the photolithography machine.

[0074] In this embodiment, the performing of the second photolithography process also includes: forming a second photoresist material layer (not shown in the figure) on the surface of the substrate structure; exposing and developing the second photoresist material layer to form a patterned second photoresist layer 311, the second photoresist layer 311 exposing a portion of the chip area I, and performing the first alignment operation before exposing the second photoresist material layer.

[0075] In this embodiment, after the second photolithography process, it also includes: using the second photoresist layer 311 as a mask, injecting doping ions into the chip area I on both sides of the gate structure 306 to form a doping area 312; after forming the doping area 312, removing the second photoresist layer 311.

[0076] In this embodiment, a second mask (not shown in the figure) is used to perform the second photolithography process, and the second pattern on the second mask is transferred to the second photoresist material layer. The second pattern includes a main pattern and a second alignment mark. The second photolithography process also causes the second photoresist layer 311 to expose a portion of the cutting path area II, and the doped ions are also implanted into the cutting path area II. The second alignment mark and the gate mark structure are used to perform the first alignment operation.

[0077] In this embodiment, please refer to Figure 11 After removing the second photoresist layer 311, a dielectric material layer 313 is formed on the surface of the substrate structure; a third photolithography process is performed to form a contact hole 314 in the dielectric material layer 313, wherein the contact hole 314 exposes a portion of the top surface of the contact layer 310, and the third photolithography process performs a second alignment operation with the gate identification structure.

[0078] In this embodiment, performing the third photolithography process includes: forming a third photoresist material layer (not shown in the figure) on the surface of the dielectric material layer 313; exposing and developing the third photoresist material layer to form a patterned third photoresist layer 315, and performing the second alignment operation before exposing the third photoresist material layer 315; etching the dielectric material layer 313 using the third photoresist layer 315 as a mask to form the contact hole 314; and removing the third photoresist layer 315 after forming the contact hole 314.

[0079] A third mask (not shown in the figure) is used to perform the third photolithography process, and the third pattern on the third mask is transferred to the third photoresist material layer. The third pattern includes a contact pattern and a third alignment mark. While forming the contact hole 314, an identification hole structure 316 is also formed in the dielectric material layer 313 on the cutting street area II. The identification hole structure 316 corresponds to the third alignment mark, and the contact hole 314 corresponds to the contact pattern. The second alignment operation is performed using the third alignment mark and the gate identification structure.

[0080] In this embodiment, after performing the third photolithography process, please refer to Figure 12 .

[0081] Please refer to Figure 12 , in the contact hole 314 (such as Figure 11 A conductive plug 317 is formed therein.

[0082] In this embodiment, a marking plug 318 is further formed in the marking hole structure 316 .

[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for controlling overlay error, characterized in that: include: Providing a substrate structure, the substrate structure comprising a substrate and a hard mask layer located on a surface of the substrate, the substrate structure further comprising a chip area and a dicing street area; Performing a first photolithography process to transfer a first pattern on a first mask onto the substrate structure, wherein the first pattern includes a plurality of gate patterns and a plurality of alignment marks, forming a plurality of gate grooves in the chip region, and forming a plurality of mark grooves in the dicing street region, wherein the gate grooves correspond to the gate patterns, and the mark grooves correspond to the alignment marks; forming a gate material layer on the surface of the substrate structure, in the plurality of gate grooves, and in the plurality of identification grooves; The gate material layer is planarized using a first chemical mechanical polishing process until the surface of the hard mask layer is exposed, the gate material layer in the gate groove is used as a gate structure, the gate material layer in the identification groove is used as an initial gate identification structure, and a top surface of a portion of the initial gate identification structure has groove defects; Performing metal silicide treatment on the gate structure and the initial gate mark structure, forming a compensation layer on the top surface of the initial gate mark structure, using the initial gate mark structure and the compensation layer as a gate mark structure, so that the groove defect is filled, and forming a contact layer on the top surface of the gate structure; A second photolithography process is performed, and the gate mark structure is used to perform a first alignment operation of the photolithography machine.

2. The overlay error control method according to claim 1, wherein: After the metal silicide treatment, part of the compensation layer protrudes from the hard mask layer; the method further includes: before the first alignment operation, using a second chemical mechanical polishing process to flatten the protruding compensation layer so that the compensation layer and the hard mask layer are flush.

3. The overlay error control method according to claim 2, wherein: After the metal silicide treatment, a portion of the contact layer protrudes from the hard mask layer. The second chemical mechanical polishing process further performs a planarization treatment on the protruding contact layer to make the contact layer flush with the hard mask layer.

4. The overlay error control method according to claim 2, wherein: The second chemical mechanical polishing process has an etching selectivity range of greater than 30:1 for the compensation layer and the hard mask layer.

5. The overlay error control method according to claim 2, wherein: The second chemical mechanical polishing process thins the hard mask layer to a thickness ranging from 300 Å to 500 Å.

6. The overlay error control method according to claim 1, wherein: The execution of the first photolithography process also includes: forming a first photoresist material layer on the surface of the substrate structure; using the first mask to expose and develop the first photoresist material layer to transfer the first pattern to the first photoresist material layer to form a patterned first photoresist layer; using the first photoresist layer as a mask to etch the substrate structure; after forming a plurality of gate grooves and a plurality of identification grooves, removing the first photoresist layer.

7. The overlay error control method according to claim 1, wherein: The performing of the second photolithography process also includes: forming a second photoresist material layer on the surface of the substrate structure; exposing and developing the second photoresist material layer to form a patterned second photoresist layer, wherein the second photoresist layer exposes a portion of the chip area, and performing the first alignment operation before exposing the second photoresist material layer; after the second photolithography process, it also includes: using the second photoresist layer as a mask to inject dopant ions into the chip area on both sides of the gate structure to form a doped area; after forming the doped area, removing the second photoresist layer.

8. The overlay error control method according to claim 7, wherein: Also includes: After removing the second photoresist layer, forming a dielectric material layer on the surface of the substrate structure; performing a third photolithography process to form a contact hole in the dielectric material layer, wherein the contact hole exposes a portion of the top surface of the contact layer, and performing a second alignment operation using the gate mark structure in the third photolithography process; After performing the third photolithography process, the method further includes forming a conductive plug in the contact hole.

9. The overlay error control method according to claim 8, wherein: The performing of the third photolithography process includes: forming a third photoresist material layer on the surface of the dielectric material layer; exposing and developing the third photoresist material layer to form a patterned third photoresist layer, and performing the second alignment operation before exposing the third photoresist material layer; etching the dielectric material layer using the third photoresist layer as a mask to form the contact hole; and removing the third photoresist layer after forming the contact hole.

10. The overlay error control method according to claim 1, wherein: The material of the compensation layer includes one or more of titanium silicide, cobalt silicide and silicon platinum nickel; the material of the gate material layer includes polysilicon.

11. The overlay error control method according to claim 1, wherein: The material of the hard mask layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

12. The overlay error control method according to claim 1, wherein: The hard mask layer has a thickness ranging from 1500 Å to 5000 Å.

13. The overlay error control method according to claim 1, wherein: The depth of the groove defects ranges from 200Å to 400Å.

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