Half-packaging frame capable of inhibiting plastic packaging layering and packaging structure
By introducing a boss and groove design on the frame structure, the contact area is increased, the delamination problem of semiconductor devices caused by mechanical stress and temperature stress during the packaging process is solved, and the stability of the packaging is improved.
Patent Information
- Application Number
- CN202510793665.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-13
- Publication Date
- 2025-09-12
AI Technical Summary
Semiconductor devices are easily affected by mechanical stress and temperature stress during the packaging process, which can lead to package delamination, and then to abnormal electrical parameters and failure.
The design of bosses and grooves is introduced into the frame structure to increase the contact area between the plastic package and the frame structure. The effective value of mechanical stress and temperature stress is reduced through the mortise and tenon structure to improve adhesion.
It effectively reduces the separation between the plastic package and the frame structure, improves the stability of the package, and prevents the occurrence of package delamination.
Smart Images
Figure CN120637356A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semi-encapsulated frame and packaging structure capable of suppressing plastic package delamination. Background Art
[0002] In the field of power electronic device technology, the packaging of semiconductor devices has always been an important part of the semiconductor industry chain. Packaging can protect chips from physical and chemical damage, realize electrical connection between chips and external circuits, help dissipate the heat generated by chips, optimize electrical and thermal performance, and reduce the impact of temperature changes and mechanical stress on chips. However, in actual operation, semiconductor devices are inevitably affected by mechanical stress and temperature stress. For example, the rib cutting process in the packaging process will introduce mechanical stress, and the normal operation of the device will introduce temperature stress due to heat. These stresses will cause the semiconductor device to produce packaging delamination, which will cause the device to have abnormal electrical parameters and then lead to failure. Therefore, how to reduce the packaging delamination problem of semiconductor devices has always been a hot research topic in the field of semiconductor packaging. Summary of the Invention
[0003] In view of the above problems, the present invention provides a semi-encapsulated frame and a packaging structure that improves packaging stability and inhibits plastic packaging delamination.
[0004] The technical solution of the present invention is: A semi-encapsulated frame for suppressing plastic packaging delamination, comprising: The frame body has a chip mounting position on its upper surface, and a plurality of closed first bosses are provided on the side of the chip mounting position; a first groove with a top opening is provided on the first boss; There are multiple frame pins, and some of the frame pins are connected to the frame body.
[0005] Specifically, the frame pin is provided with a plurality of second bosses; The second boss is provided with a second groove with an open top.
[0006] Specifically, the frame pins include: A first pin, fixedly connected to the frame body; There are a plurality of second pins, which are spaced apart from the frame body and are electrically connected to the chip through leads.
[0007] Specifically, the cross section of the first boss is a polygonal structure or a ring structure.
[0008] Specifically, the first groove extends downward from the upper surface of the first boss, and the window width of the first groove is smaller than the distance between the inner and outer side surfaces of the first boss.
[0009] Specifically, the depth of the first groove extending toward the frame body is less than the sum of the heights of the first boss and the frame body.
[0010] Specifically, the frame pins are bent pins or straight pins.
[0011] Specifically, the second groove extends downward from the upper surface of the second boss, and the window width of the second groove is smaller than the distance between the inner and outer side surfaces of the second boss.
[0012] A semi-encapsulated frame packaging structure that suppresses plastic packaging delamination, wherein a chip is provided on the frame body and fixedly connected to the frame body via a solder layer; The chip is electrically connected to the corresponding frame pin through corresponding leads; The first boss, the second boss, the chip and the lead are respectively wrapped in a plastic package; The frame body and a partial area of the frame pins are respectively wrapped in a plastic package.
[0013] Specifically, the chip is located in the first boss.
[0014] The present invention innovatively introduces bosses and grooves on the frame structure to increase the contact area between the plastic package and the frame structure, thereby improving the overall adhesion between the two. At the same time, a groove design is adopted in the boss to provide a larger contact area between the plastic package and the frame structure under the same available area; the mortise and tenon structure formed by multiple bosses, grooves and the plastic package reduces the effective value of the mechanical stress and temperature stress applied to the semiconductor device that will cause separation between the plastic package and the frame structure, thereby solving the problem of semiconductor device packaging stratification from two aspects. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 is a schematic diagram of the front structure of the frame structure in specific embodiment 1, Figure 2 is a schematic cross-sectional view of the frame structure in specific embodiment 1, Figure 3 This is a schematic diagram of the front structure of the package structure after the chip and leads are set in specific embodiment 1. Figure 4 is a schematic cross-sectional view of the packaging structure after the chip and leads are arranged in specific embodiment 1, Figure 5 is a schematic diagram of the front structure of the packaging structure after the plastic sealing layer is provided in the specific embodiment 1, Figure 6 Specific embodiment 1 is a schematic diagram of the cross-sectional structure of the packaging structure after the plastic sealing layer is provided. Figure 7 is a schematic diagram of the front structure of the frame structure in specific embodiment 2, Figure 8is a schematic cross-sectional view of the frame structure in specific embodiment 2, Figure 9 This is a schematic diagram of the front structure of the package structure after the chip and leads are set in specific embodiment 2. Figure 10 is a schematic cross-sectional view of the packaging structure after the chip and leads are arranged in specific embodiment 2, Figure 11 is a schematic diagram of the front structure of the packaging structure after the plastic sealing layer is provided in specific embodiment 2, Figure 12 is a schematic cross-sectional view of the packaging structure after the plastic sealing layer is provided in specific embodiment 2, In the figure, 1 is the frame body, 2 is the frame pin, 3 is the solder layer, 4 is the chip, 5 is the lead, 6 is the plastic layer, 7 is the first boss, 8 is the first groove, 9 is the second boss, and 10 is the second groove. DETAILED DESCRIPTION
[0016] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.
[0017] In the description of the present invention, it should be understood that terms such as "upper," "lower," "left," "right," "vertical," and "horizontal" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are used solely to facilitate and simplify the description of the present invention and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0018] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.
[0019] A semi-encapsulated frame for suppressing plastic packaging delamination, comprising: The frame body 1 has a chip mounting position on its upper surface, and a plurality of closed first bosses 7 are provided on the side of the chip mounting position; a first groove 8 with a top opening is provided on the first boss 7; the number of first bosses 7 can be selected according to specific product requirements, the innermost first boss 7 surrounds the chip mounting position, and the remaining first bosses 7 are enlarged at the same proportion and are sequentially arranged on the outside of the innermost first boss 7.
[0020] The cross section of the first boss 7 is a polygonal structure or an annular structure.
[0021] The first groove 8 extends downward from the upper surface of the first boss 7 , and the window width of the first groove 8 is smaller than the distance between the inner and outer sides of the first boss 7 .
[0022] The first groove 8 extends toward the frame body 1 to a depth that is less than the sum of the heights of the first boss 7 and the frame body 1 .
[0023] There are multiple frame pins 2, and some of the frame pins 2 are connected to the frame body 1; the first pin is fixedly connected to the frame body 1, and the second pin is spaced apart from the frame body and electrically connected to the chip 4 through the lead 5.
[0024] A plurality of second bosses 9 are provided on the frame pin 2 ; a second groove 10 with an opening at the top is provided on the second boss 9 .
[0025] The second groove (10) extends downward from the upper surface of the second boss 9, and the window width of the second groove 10 is smaller than the distance between the inner and outer sides of the second boss 9.
[0026] The depth of the second groove 10 is less than the sum of the heights of the second boss 9 and the frame pin 2 .
[0027] The frame pins 2 can be bent pins or straight pins.
[0028] A semi-encapsulated frame packaging structure for suppressing plastic packaging delamination, wherein a chip 4 is provided on a frame body 1 and fixedly connected thereto via a solder layer 3; the chip 4 is located within a first boss 7.
[0029] The chip 4 is electrically connected to the corresponding frame pin 2 through the corresponding lead 5; The first boss 7, the second boss 9, the chip 4 and the lead 5 are respectively wrapped in the plastic package 6; The frame body 1 and part of the frame pin 2 are respectively wrapped in the plastic package 6, wherein the lower surface of the frame body 1 is located outside the plastic package 6 for electrical connection; part of the frame pin 2 is located outside the plastic package 6 for electrical connection.
[0030] The arrangement and combination of the frame structure and package structure of this case can be the frame structure and package structure of semi-package series such as TO series, DFN series, QFN series, etc. The following is a specific description based on different series: Example 1 In this embodiment, the arrangement and combination of the frame structure and the packaging structure is TO247 packaging, such as Figure 1-6 As shown; TO247 package includes: 1 frame body 1, 3 frame pins 2, 1 solder layer 3, 1 chip 4, 2 leads 5 and plastic layer 6, In the TO247 frame structure, the three frame pins 2 are straight pins whose lower surfaces are higher than the upper surface of the frame body 1; Frame pin 2 includes: A first pin, fixedly connected to the frame body 1; A pair of second pins are provided, each located on the side of the first pin and spaced apart from the frame body 1 , and are electrically connected to the chip 4 through the lead 5 .
[0031] Specifically, the frame pins 2 include one D electrode frame pin, one S electrode frame pin, and one G electrode frame pin, and the D electrode frame pin (the first pin mentioned above) is connected to the frame body 1 .
[0032] Two annular first bosses 7 are provided on the upper surface of the frame body 1, and a first groove 8 is provided on the first boss 7; The distance between the two rectangular first bosses 7 on the upper surface of the frame body 1 is 0.5mm, the distance between the outer side of the outermost first boss 7 and the side of the frame body 1 is 0.5mm; the distance between the inner side of the innermost first boss 7 and the side of the solder layer 3 is 1mm, the distance between the outer side and the inner side of the first boss 7 is 0.9mm, the height of the first boss 7 is 1mm, and the width of the window of the first groove 8 is ( Figure 2 Middle lateral distance) 0.3mm, groove depth ( Figure 2 distance between the middle and the upper part) 1mm.
[0033] Two second bosses 9 are provided on the frame pin 2, and a second groove 10 is provided on the second boss 9; The lower surface of the frame pin 2 is provided with two second bosses 9 structures which are symmetrically distributed with the frame pin 2 as the symmetry axis. The horizontal distance between the second bosses 9 is 0.5mm. The thickness of the inner and outer sides of the second bosses 9 is 0.9mm. The height of the second boss 9 is 1mm. The window width of the second groove 10 is 0.3mm ( Figure 2 The groove depth is 1mm ( Figure 2 distance between the middle and upper parts). Figure 1The front structural diagram of the frame structure consisting of the frame body 1 and the frame pin 2 is shown. Figure 2 The frame structure composed of the frame body 1 and the frame pin 2 is shown. Figure 1 Schematic diagram of the cross-sectional structure of the x1 axis shown.
[0034] A solder layer 3 is provided on the frame body 1, and the inner side surface of the innermost first boss 7 is spaced 1 mm from the side surface of the solder layer 3. A chip 4 is provided on the solder layer 3, and the side surface of the chip 4 is spaced 1 mm from the side surface of the solder layer 3.
[0035] The packaging structure is provided with two leads, the chip 4 is a vertical structure transistor, the upper surface of the chip is provided with a G electrode PAD and an S electrode PAD, the lower surface of the chip is provided with a D electrode PAD, one lead 5 is used to connect the S electrode PAD and the S electrode frame pin 2, and one lead 5 is used to connect the G electrode PAD and the G electrode frame pin 2. Figure 3 The front structure diagram of the package structure after the chip 4 and the lead 5 are set is shown. Figure 4 Shows the package structure after setting chip 4 and lead 5 Figure 3 Schematic diagram of the cross-sectional structure along the x-axis.
[0036] The plastic layer 6 wraps the first boss 7, the second boss 9, the solder layer 3, the chip 4, and the lead 5 respectively; the lower surface of the frame body 1 is located outside the plastic body 6 for electrical connection; part of the frame pin 2 is located outside the plastic body 6 for electrical connection.
[0037] Figure 5 The front structural diagram of the packaging structure after the plastic sealing layer is set is shown. Figure 6 Shows the packaging structure after setting the plastic layer Figure 5 Schematic diagram of the cross-sectional structure of the x1 axis shown.
[0038] Example 2 Reference below Figure 7-12 Describe specific embodiments of the present invention; The packaging structure of this embodiment involves a DFN5060 packaging product, including a frame body 1, 8 frame pins 2, a solder layer 3, a chip 4, 4 leads 5 and a plastic layer 6. The 8 frame pins 2 in the DFN5060 frame structure are straight pins whose lower surfaces are horizontal to the lower surface of the frame body 1, and are 4 D electrode frame pins 2, 3 S electrode frame pins 2, and 1 G electrode frame pin 2. The D electrode frame pin 2 is connected to the frame body 1.
[0039] Frame pin 2 includes: There are four first pins, which are fixedly connected to the frame body 1 and located on one side of the frame body 1; There are four second pins, which are located on the other side of the frame body 1 and spaced apart from the frame body 1 , and are electrically connected to the chip 4 through the leads 5 .
[0040] Specifically, the frame pins 2 include 4 D-electrode frame pins, 3 S-electrode frame pins, and 1 G-electrode frame pin, and the D-electrode frame pin (the first pin mentioned above) is connected to the frame body 1 .
[0041] Two annular first bosses 7 are provided on the upper surface of the frame body 1, and a first groove 8 is provided on the first boss 7; The distance between the two rectangular first bosses 7 on the upper surface of the frame body 1 is 0.5mm, the distance between the outer side of the outermost first boss 7 and the side of the frame body 1 is 0.5mm; the distance between the inner side of the innermost first boss 7 and the side of the solder layer 3 is 1mm, the distance between the outer side and the inner side of the first boss 7 is 0.9mm, the height of the first boss 7 is 1mm, and the width of the window of the first groove 8 is ( Figure 8 Middle lateral distance) 0.3mm, groove depth ( Figure 8 distance between the middle and the upper part) 1mm.
[0042] Two second bosses 9 are provided on the frame pin 2, and a second groove 10 is provided on the second boss 9; The horizontal distance between the second bosses 9 is 0.5mm, the thickness of the inner and outer sides of the second boss 9 is 0.9mm, and the height of the second boss 9 is 1mm; the window width of the second groove 10 is 0.3mm ( Figure 8 The groove depth is 1mm ( Figure 8 distance between the middle and upper parts). Figure 7 The front structural diagram of the frame structure consisting of the frame body 1 and the frame pin 2 is shown. Figure 8 The frame structure composed of the frame body 1 and the frame pin 2 is shown. Figure 1 Schematic diagram of the cross-sectional structure of the x1 axis shown.
[0043] A solder layer 3 is provided on the frame body 1, and the inner side surface of the innermost first boss 7 is spaced 1 mm from the side surface of the solder layer 3. A chip 4 is provided on the solder layer 3, and the side surface of the chip 4 is spaced 1 mm from the side surface of the solder layer 3.
[0044] The packaging structure is provided with 4 leads. The chip 4 is a vertically structured transistor. A G electrode PAD and an S electrode PAD are provided on the upper surface of the chip. A D electrode PAD is provided on the lower surface of the chip. Three leads 5 are used to connect the S electrode PAD and the S electrode frame pin 2. One lead 5 is used to connect the G electrode PAD and the G electrode frame pin 2. Figure 9 The front structure diagram of the package structure after setting the chip and leads is shown. Figure 10 Shows the chip and lead packaging structure along the Figure 9 Schematic diagram of the cross-sectional structure of the x1 axis shown.
[0045] The plastic layer 6 wraps the first boss 7, the second boss 9, the solder layer 3, the chip 4, and the lead 5 respectively; the lower surface of the frame body 1 is located outside the plastic body 6 for electrical connection; part of the frame pin 2 is located outside the plastic body 6 for electrical connection.
[0046] Figure 11 The front structural diagram of the packaging structure after the plastic sealing layer is set is shown. Figure 12 Shows the packaging structure after setting the plastic layer Figure 11 Schematic diagram of the cross-sectional structure of the x1 axis shown.
[0047] The present invention innovatively introduces bosses and grooves on the frame structure to increase the contact area between the plastic package and the frame structure, improving the overall adhesion between the two. At the same time, a groove design is adopted in the bosses to provide a larger contact area between the plastic package and the frame structure under the same available area. The tenon and mortise structure formed by multiple bosses, grooves and the plastic package reduces the effective value of the mechanical stress and temperature stress applied to the semiconductor device that may cause separation between the plastic package and the frame structure, thereby solving the problem of semiconductor device packaging delamination from two aspects.
[0048] High-pressure cooking and temperature cycling, part of the reliability test, were used to characterize the device's tolerance to package delamination. Under the same process conditions, using the TO247 package in the specific embodiment of the present invention, no plastic package delamination occurred in the device after high-pressure cooking and temperature cycling. However, using the TO247 package with a conventional structure, plastic package delamination did occur in the device after high-pressure cooking and temperature cycling.
[0049] Regarding the content disclosed in this case, the following points need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to form new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.
Claims
1. A semi-encapsulated frame for suppressing plastic packaging delamination, characterized in that: include: The frame body (1) has a chip mounting position on its upper surface, and a plurality of closed first bosses (7) are provided on the side of the chip mounting position; the first bosses (7) are provided with a first groove (8) with a top opening; There are a plurality of frame pins (2) connected to the frame body (1).
2. A semi-encapsulated frame for suppressing plastic packaging delamination according to claim 1, characterized in that: A plurality of second bosses (9) are provided on the frame pin (2); A second groove (10) with a top opening is provided on the second boss (9).
3. The semi-encapsulated frame for suppressing plastic packaging delamination according to claim 1, characterized in that: The frame pin (2) comprises: A first pin, fixedly connected to the frame body (1); A plurality of second pins are provided and spaced apart from the frame body (1), and are electrically connected to the chip (4) via leads (5).
4. The semi-encapsulated frame for suppressing plastic packaging delamination according to claim 1, characterized in that: The cross section of the first boss (7) is a polygonal structure or an annular structure.
5. The semi-encapsulated frame for suppressing plastic packaging delamination according to claim 1, characterized in that: The first groove (8) extends downward from the upper surface of the first boss (7), and the window width of the first groove (8) is smaller than the distance between the inner and outer side surfaces of the first boss (7).
6. The semi-encapsulated frame for suppressing plastic packaging delamination according to claim 1, characterized in that: The depth of the first groove (8) extending in the direction of the frame body (1) is less than the sum of the heights of the first boss (7) and the frame body (1).
7. The semi-encapsulated frame for suppressing plastic packaging delamination according to claim 1, characterized in that: The frame pins (2) are bent pins or straight pins.
8. The semi-encapsulated frame for suppressing plastic packaging delamination according to claim 2, characterized in that: The second groove (10) extends downward from the upper surface of the second boss (9), and the window width of the second groove (10) is smaller than the distance between the inner and outer side surfaces of the second boss (9).
9. A semi-encapsulated frame packaging structure for suppressing plastic delamination, comprising the semi-encapsulated frame for suppressing plastic delamination according to claim 1, characterized in that: The frame body (1) is provided with a chip (4) fixedly connected thereto via a solder layer (3); The chip (4) is electrically connected to the corresponding frame pin (2) via a corresponding lead (5); The first boss (7), the second boss (9), the chip (4) and the lead (5) are respectively wrapped in the plastic package (6); Partial areas of the frame body (1) and the frame pins (2) are respectively wrapped in a plastic package (6).
10. The semi-encapsulated frame packaging structure for suppressing plastic packaging delamination according to claim 1, characterized in that: The chip (4) is located in the first boss (7).