High-voltage fast recovery diode with positive temperature characteristic and manufacturing method thereof

Abstract

The invention discloses a high-voltage fast recovery diode with a positive temperature characteristic and a manufacturing method of the high-voltage fast recovery diode. A central region of the device is a P-type doped active region which is used as an anode when the device works in the forward direction; p-type doped field limiting rings are arranged on the two sides of the active region and serve as voltage dividing rings of the device, and the field limiting rings and the active region are doped independently; an N-type doped cut-off ring is arranged on the outermost periphery of the device and provides an electric field cut-off effect; a metal field plate is arranged above each field limiting ring to improve the distribution of a peripheral electric field and improve the stability of the device; except for the position of the contact hole, CVD, silicon nitride and polyimide in the vertical direction of the device are used as passivation layers of the device to isolate the influence of external moisture, charges and the like, so that the reliability of the device is improved; metal is directly deposited above the active region to serve as an anode of the device; and a layer of metal is evaporated on the back of the device after being thinned to serve as a device cathode. A platinum diffusion and electron irradiation process is used as a minority carrier lifetime control technology to adjust the temperature characteristic of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, in particular to a high-voltage fast recovery diode with positive temperature characteristics and a manufacturing method thereof. Background Art

[0002] Fast recovery diodes (FRDs), or fast recovery diodes, are semiconductor devices with unique switching characteristics and extremely short reverse recovery times. Their internal structure utilizes a PIN junction design, formed by adding a thin base region between P-type and N-type silicon materials to create a PIN silicon wafer. This unique structure enables the FRD to rapidly recover from the on-state to the off-state after reverse bias, effectively reducing switching losses and electromagnetic interference in high-frequency applications. FRDs are primarily used in electronic circuits such as switching power supplies, PWM pulse width modulators, and inverters as high-frequency rectifiers, freewheeling diodes, or damping diodes. Their excellent switching performance and reverse recovery characteristics make them an indispensable key component in modern electronic devices. With the increasing demand for smarter and more efficient electronic products, the application of FRDs in power management, power transmission, and power conversion will become increasingly widespread.

[0003] With the continuous development of the new energy industry, fast recovery diodes are increasingly used in module applications that are sealed with IGBTs. In this usage scenario, multiple FRDs are generally connected in parallel. Since the devices generate heat during operation, the performance of the devices changes, which places higher requirements on the temperature coefficient of the FRD. Specifically, if the temperature of one of the devices rises during parallel use, the resistance of the product with a positive temperature coefficient will also increase, and more current will flow through the device with lower resistance, and the heat generated by this device will also increase. Through this dynamic adjustment, the current and heat generated between the various devices can be balanced, thereby preventing a device from thermal runaway or even damage due to excessive current. At the same time, the special usage scenario of the FRD's sealed module also requires it to meet the circuit design requirements of high current and high voltage. In this high-power application scenario, higher requirements are placed on its reliability.

[0004] In summary, it is necessary to design a high-voltage fast recovery diode product with a positive temperature coefficient and high reliability to meet the current growing new energy market. Summary of the Invention

[0005] In view of the problems existing in the prior art, the present invention provides a high-voltage fast recovery diode with positive temperature characteristics and a manufacturing method thereof to solve at least one of the above technical problems.

[0006] In order to achieve the above object, the present invention provides a high-voltage fast recovery diode with positive temperature characteristics, comprising a highly doped silicon substrate, an epitaxial layer grown on the highly doped silicon substrate;

[0007] The central area above the epitaxial layer is a P-type doped active region and serves as the anode when the device is working in the forward direction;

[0008] Field limiting rings, both of which are P-type doped, are symmetrically distributed on both sides of the active area and serve as voltage divider rings of the device and are doped independently of the active area;

[0009] The periphery of the field limiting ring is an N-type doped cutoff ring;

[0010] A metal field plate is placed above each field limiting ring to improve the distribution of the peripheral electric field and enhance device stability.

[0011] A metal is directly deposited on the active area to serve as the anode of the device;

[0012] The bottom of the highly doped silicon substrate is thinned and then a back electrode metal layer is evaporated to serve as the device cathode.

[0013] The present invention balances the relationship between the forward level and breakdown of the device by separately doping and pushing the field limiting ring and the active region.

[0014] Further preferably, the epitaxial layer is covered with an oxide layer except for the contact hole of the active area, the field plate contact hole of the field limiting ring, and the contact hole region of the stop ring.

[0015] More preferably, the width of the field limiting ring is 10-15 μm, the spacing between the field limiting rings increases from the inside to the outside, the spacing between the innermost rings is 20-30 μm, and the increasing spacing is 2-5 μm.

[0016] Further preferably, in order to ensure the withstand voltage of the device, the terminal is provided with seven field limiting rings of equal width with increasing ring spacing, and an N-type cut-off ring is provided at the outermost edge.

[0017] Further preferably, a boron-phosphorus-containing oxide layer is designed above the terminal structure, which completely covers all areas except the active area contact hole, the field plate contact hole at the corner of the terminal ring area, and the N+ contact hole.

[0018] Further preferably, the active area, the ring area, and the N+ cut-off area all have openings for use as electrodes and field plates through metal contacts.

[0019] Further preferably, the surface of the device is designed with a protective layer composed of silicon nitride and polyimide, which fully covers all positions except the contact holes in the source region.

[0020] Further preferably, the implantation dose of the field limiting ring is 3E12-4E14, the implantation energy is 50Kev-100Kev, the thickness of the oxide layer after oxidation diffusion is about 0.5um, and the junction depth is 6-10um;

[0021] Further preferably, the implantation dose of the active region is 5E12-5E13, and the implantation energy is 50Kev-100Kev.

[0022] Further preferably, the distance between the cutoff ring and the outer ring of the field limiting ring is 90-150 μm, the injection energy of the cutoff ring is 40-60 keV, and the injection dose is 5E13-1.5E15.

[0023] A method for preparing a high-voltage fast recovery diode with positive temperature characteristics, characterized by comprising the following steps:

[0024] Step 1: growing an epitaxial layer of the same doping type on a highly doped silicon substrate by CVD or MBE;

[0025] Step 2: growing a SiO2 layer of a certain thickness on the epitaxial wafer by thermal oxidation;

[0026] Step 3: Use photoresist as a mask layer to define the field limit ring and active area through exposure and development processes;

[0027] Step 4: Open the defined field limiting ring and active area doping window by wet etching;

[0028] Step 5: Using a glue ion implantation process, a certain dose of boron ions is implanted into the field limiting ring area;

[0029] Step six, using a glue ion implantation process to implant a certain dose of boron ions into the active area;

[0030] Step 7: Through a high-temperature furnace tube diffusion process, a certain concentration of boron ions is doped into the active area of ​​the epitaxial layer. The high temperature pushes the impurities into a certain depth and activates the impurities, and forms a masking oxide layer on the surface;

[0031] Step eight, using photoresist as a mask layer, and defining the exit cut-off area through exposure and development processes;

[0032] Step nine, doping phosphorus ions into the silicon epitaxial portion of the stop ring region by ion implantation or diffusion;

[0033] Step 10, depositing a boron-phosphorus oxide layer as a dielectric layer by a CVD process, and then performing an annealing process for reflow;

[0034] Step 11: using photoresist as a mask layer and defining the metal contact area through exposure and development processes;

[0035] Step 12: Open the metal contact holes in the active area by wet etching to expose the silicon substrate to ensure contact between the metal and the epitaxial layer;

[0036] Step 13, doping a surface layer of BF2 by ion implantation;

[0037] Step 14: Deposit a platinum metal layer on the front side using a sputtering process. Dope the platinum into the silicon epitaxial layer through heat treatment to form a certain concentration distribution. At the same time, form a PtSi barrier layer on the silicon surface. After the heat treatment, use aqua regia to completely remove the metal.

[0038] Step 15: depositing a metal layer of uniform thickness using a PVD process, and defining the electrode region and field plate region of the device using a photoresist;

[0039] Step 16: etching by a metal wet etching process or a metal dry etching process, and then forming an alloy between the metal and the silicon surface by a heat treatment process;

[0040] Step 17: depositing a silicon nitride layer of a certain thickness on the surface by a PECVD process as a protective layer for the device;

[0041] Step 18, using photoresist as a mask layer, etching the silicon nitride at the source contact hole and on the scribe line;

[0042] Step 19: A polyimide layer of a certain thickness is evenly applied on the front surface, and the imide at the source contact holes and on the scribe lines is removed by exposure and development, and finally high-temperature curing is performed;

[0043] Step 20: irradiating the material with a high-energy electron beam to introduce recombination centers to control carrier lifetime; then performing an annealing process to repair lattice defects introduced during the irradiation process;

[0044] Step 21: thinning the silicon substrate to a certain thickness on the back side of the silicon substrate, and depositing a back electrode metal layer by a physical vapor deposition process.

[0045] Further preferably, in step 1, the highly doped silicon substrate is an N-type substrate, the resistivity of the highly doped silicon substrate is ≤0.004Ω.cm, and the thickness thereof is between 40μm and 700μm;

[0046] The thickness of the epitaxial layer is 90μm~150μm, and the resistivity is 40Ω.cm~80Ω.cm.

[0047] Further preferably, in step 2, the thickness of the SiO2 layer is 1 um to 2 um.

[0048] Further preferably, in step three, the width of the field limiting ring is 10-15 μm; the ring spacing is generally 20-40 μm, and the ring spacing increases outward in an increasing trend.

[0049] Further preferably, in step five, the implantation dose is 3E12-4E14, and the implantation energy is 50Kev-100Kev.

[0050] Further preferably, in step six, the implantation dose is 5E12-4E14, and the implantation energy is 50Kev-100Kev.

[0051] Further preferably, in step seven, the implantation dose is 1.5E14-1.5E15, and the implantation energy is 50Kev-100Kev.

[0052] Further preferably, in step 10, the dielectric layer is USG + BPSG, with a thickness of 0.8um to 1.2um. USG refers to undoped silicate glass, i.e., SiO2 material, and BPSG refers to borophosphosilicate glass.

[0053] Further preferably, in step thirteen, the injection dose is 1E13~1E14.

[0054] Further preferably, in step fourteen, the thickness of the platinum metal layer is 0.02 um.

[0055] Further preferably, in step fifteen, the thickness of the metal layer is 5 um.

[0056] Further preferably, in step 17, the thickness of the silicon nitride is 0.15um to 0.5um;

[0057] Further preferably, in step 19, the thickness of the polyimide layer is 6-9 μm.

[0058] Further preferably, in step 20, a high-energy electron beam with a dose of about 30 to 150 kGY is used to irradiate the material to introduce recombination centers to control the carrier lifetime; and then an annealing process at 355°C to 365°C is performed to repair the lattice defects introduced during the irradiation process.

[0059] Further preferably, in step 21, the silicon substrate is thinned to 190-260 μm, and a 12-15 μm back electrode metal layer is deposited using a physical vapor deposition process.

[0060] Compared with the prior art, the present invention has the following beneficial effects:

[0061] The terminal design of this invention utilizes a process that implants the field-limiting ring and active region separately and pushes the junction simultaneously. By adjusting the active region concentration, the forward voltage drop (VF) and softness factor (S) are maintained while ensuring the terminal structure meets breakdown requirements. To balance the relationship between the device's forward voltage (VF), breakdown (BV), and dynamic loss (Qrr), this product utilizes a process that implants the ring region and source region independently. While maintaining a constant breakdown, the device's recovery characteristics are adjusted by adjusting the source region's implant dose and the intensity of the Pt diffusion.

[0062] The source region supplementary injection process is used to further reduce the contact resistance.

[0063] The use of metal field plates instead of polycrystalline field plates ensures the stability of the chip terminal structure while reducing particle contamination issues caused by polycrystalline deposition. To ensure high device reliability, a unique terminal structure is adopted, abandoning the mainstream floating field plate process in favor of a contact field plate. By opening holes at the corners of the device terminal, the field plate and the ring area are short-circuited. Furthermore, to avoid particle issues caused by traditional polycrystalline field plates during the process, a metal field plate is used to directly replace the polycrystalline field plate.

[0064] By simultaneously utilizing Pt diffusion and irradiation processes to control carrier lifetime, we ensure the device's temperature characteristics while avoiding the device performance degradation associated with pure irradiation. To achieve the product's positive temperature characteristics, this product retains the positive benefits of improved material properties brought about by the irradiation process, while also adding a Pt diffusion process to mitigate the device performance degradation associated with the irradiation process. This solution balances the device's positive temperature characteristics with the relationship between leakage and positive current in irradiated products. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 A cross-sectional view after the specific implementation step 1 of the present invention;

[0066] Figure 2 This is a cross-sectional view after the specific implementation of step 2 of the present invention;

[0067] Figure 3 A cross-sectional view after the specific implementation of step five of the present invention;

[0068] Figure 4 A cross-sectional view after the sixth step of the specific implementation of the present invention;

[0069] Figure 5 A cross-sectional view after the seventh step of the present invention is specifically implemented;

[0070] Figure 6 A cross-sectional view after the ninth step of the present invention is specifically implemented;

[0071] Figure 7A cross-sectional view after the specific implementation step 10 of the present invention;

[0072] Figure 8 This is a cross-sectional view after the specific implementation of step 12 of the present invention;

[0073] Figure 9 This is a cross-sectional view after the specific implementation of step 14 of the present invention;

[0074] Figure 10 A cross-sectional view after the sixteenth step of the specific implementation of the present invention;

[0075] Figure 11 A cross-sectional view of the eighteenth step of the present invention;

[0076] Figure 12 A cross-sectional view of step nineteen of the present invention;

[0077] Figure 13 This is a cross-sectional view of a specific implementation step 21 of the present invention.

[0078] In the figure: SUB is a highly doped silicon substrate, EPI is an epitaxial layer, 1 is a front contact metal electrode, 2 is a polyimide layer, 3 is a silicon nitride layer, 4 is a metal field plate, 5 is an active area, 6 is a field limiting ring, 7 is an oxide layer, 8 is a cut-off ring, 9 is a back electrode metal layer, 10 is a SiO2 layer, and 11 is a dielectric layer. DETAILED DESCRIPTION

[0079] The present invention will be further described below with reference to the accompanying drawings.

[0080] See also Figure 13 Specific embodiment 1: A high-voltage fast recovery diode with positive temperature characteristics includes a highly doped silicon substrate SUB with an epitaxial layer EPI grown on top of the highly doped silicon substrate SUB; the central region above the epitaxial layer EPI is a P-type doped active region 5, which serves as the anode of the device during forward operation; field limiting rings 6, also doped with P-type, are symmetrically distributed on both sides of the active region 5 and serve as voltage divider rings of the device, doped independently of the active region 5; the field limiting rings 6 are surrounded by N-type doped cutoff rings 8; a metal field plate is provided above each field limiting ring 6 to improve the distribution of the peripheral electric field and enhance device stability; a metal is directly deposited above the active region 5 to serve as the anode of the device; the bottom of the highly doped silicon substrate is thinned and then a back electrode metal layer 9 is evaporated to serve as the cathode of the device. The present invention balances the relationship between the forward voltage level and breakdown of the device by doping and pushing the field limiting rings and the active region separately.

[0081] The device's central region is a P-type doped active region, serving as the anode during forward operation. Flanking the active region 5 are P-type doped field-limiting rings 6, independently doped from the active region 5, which act as voltage dividers. At the outermost periphery of the device are N-type doped cutoff rings 8, providing field cutoff. Metal field plates are placed above each field-limiting ring to improve the distribution of the peripheral electric field and enhance device stability. CVD, silicon nitride, and polyimide passivation layers, except for contact holes, are applied vertically to the device to isolate it from external influences such as moisture and charge, enhancing device reliability. Metal is directly deposited above the active region, serving as the anode. A thinned, evaporated metal layer serves as the cathode on the back of the device. A process combining platinum diffusion and electron irradiation is employed as a minority carrier lifetime control technique to adjust the device's temperature characteristics.

[0082] The areas above the epitaxial layer EPI are covered with an oxide layer 7 except for the contact holes of the active area, the field plate contact holes of the field limiting ring, and the contact holes of the stop ring.

[0083] The width of the field-limiting ring is 10~15μm, and the spacing between the field-limiting rings increases from the inside to the outside. The spacing between the innermost rings is 20~30um, and the increasing spacing is 2~5um.

[0084] The field limiting ring has an implantation dose of 3E12~4E14 and an implantation energy of 50Kev~100Kev. After oxidation diffusion, the oxide layer thickness is about 0.5um and the junction depth is 6~10um.

[0085] The implantation dose of the active region is 5E12~5E13, and the implantation energy is 50Kev~100Kev. The thickness of the oxide layer after oxidation is about 0.5um, and the junction depth is 5~8um;

[0086] The distance between the cut-off ring and the outer ring of the field limiting ring is 90-150 μm, the injection energy of the cut-off ring is 40-60 keV, and the injection dose is 5E13-1.5E15.

[0087] See also Figures 1 to 12 A method for preparing a high-voltage fast recovery diode with positive temperature characteristics comprises the following steps:

[0088] Step 1: Grow an epitaxial layer of the same doping type on a highly doped silicon substrate by CVD or MBE. Figure 1 ,

[0089] The highly doped silicon substrate is an N-type substrate, the resistivity of the highly doped silicon substrate is ≤0.004Ω.cm, and the thickness thereof is 40μm~700μm;

[0090] The thickness of the epitaxial layer is 90μm~150μm, and the resistivity is 40Ω.cm~80Ω.cm;

[0091] Step 2: A SiO2 layer of a certain thickness is grown on the epitaxial wafer by thermal oxidation; the thickness of the SiO2 layer is 1um~2um, see Figure 2 ,

[0092] Step 3: Using photoresist as a mask layer, the field-limiting rings and active area are defined through exposure and development processes. The width of the field-limiting rings is 10-15 μm. The ring spacing is generally 20-40 μm, and the ring spacing increases outward in an increasing trend.

[0093] Step 4: Open the defined field limiting ring and active area doping window by wet etching;

[0094] Step 5: Use the glue ion implantation process to implant a certain dose of boron ions into the field limiting ring 6 area; the implantation dose is 3E12~4E14, see Figure 3 ,

[0095] Step 6: Use the glue ion implantation process to implant a certain dose of boron ions into the active area 5; the implantation dose is 5E12~4E14, see Figure 4 ;

[0096] Step 7: Through the high temperature furnace tube diffusion process, a certain concentration of boron ions is doped into the active area of ​​the epitaxial layer. The high temperature pushes the impurities into a certain depth and activates the impurities, and forms a masking oxide layer 7 on the surface; the implantation dose is 1.5E14~1.5E15, see Figure 5 ;

[0097] Step eight, using photoresist as a mask layer, and defining the exit cut-off area through exposure and development processes;

[0098] Step nine, by ion implantation or diffusion process, phosphorus ions are doped into the silicon epitaxial region of the cut-off ring 8; see Figure 6 ;

[0099] Step 10: deposit a layer of oxide layer containing boron and phosphorus as the dielectric layer 11 by CVD process, and then reflow by annealing process. The thickness of the dielectric layer 11 is 0.8um~1.2um. Figure 7 ,

[0100] Step 11: using photoresist as a mask layer and defining the metal contact area through exposure and development processes;

[0101] Step 12: Open the metal contact holes in the active area by wet etching to expose the silicon substrate to ensure contact between the metal and the epitaxial layer. Figure 8 ;

[0102] Step 13: doping a surface layer of BF2 with an ion implantation process, with an implantation energy of 80Kev~100Kev and an implantation dose of 1E13~1E14;

[0103] Step 14: Sputtering process is used to deposit a layer of platinum (Pt) metal layer on the front surface. Platinum is doped into the silicon epitaxial layer through heat treatment to form a certain concentration distribution. At the same time, a layer of PtSi barrier is formed on the silicon surface. After heat treatment, all metal is corroded and removed with aqua regia. The thickness of the platinum metal layer is 0.02 μm. Figure 9 ;

[0104] Step 15: Use PVD process to deposit a metal layer of uniform thickness, and use photoresist to define the electrode area and field plate area of ​​the device; respectively serving as the front contact metal electrode 1 and metal field plate 4. The thickness of the metal layer is 5 μm;

[0105] Step 16: Etching is performed by a metal wet etching process or a metal dry etching process, and then an alloy is formed on the metal and silicon surface by a heat treatment process; see Figure 10 ;

[0106] Step 17: depositing a silicon nitride layer 3 of a certain thickness on the surface by PECVD process as a protective layer of the device; the thickness of the silicon nitride is 0.15um~0.5um;

[0107] Step 18: Use photoresist as a mask layer to etch the silicon nitride at the source contact hole and on the scribe line; Figure 11 ;

[0108] Step 19: A certain thickness of polyimide layer 2 is evenly applied on the front surface. The imide at the source contact hole and the scribe line is removed by exposure and development, and finally high temperature curing is performed. The thickness of the polyimide layer is 6~9um. Figure 12 .

[0109] Step 20: irradiate the material with a high-energy electron beam at a dose of about 30 to 150 kGY to introduce recombination centers to control carrier lifetime; then perform an annealing process at 355°C to 365°C to repair lattice defects introduced during the irradiation process;

[0110] Step 21: On the back side of the silicon substrate, thin the silicon substrate to 190-260 μm, and deposit a 12-15 μm back electrode metal layer 9 by physical vapor deposition process. Figure 13 .

[0111] Figures 1 to 13 It is a cross-sectional view of the device symmetrical along the center.

[0112] The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A high-voltage fast recovery diode with positive temperature characteristics comprises a highly doped silicon substrate with an epitaxial layer grown on the highly doped silicon substrate; The central area above the epitaxial layer is a P-type doped active region and serves as the anode when the device is working in the forward direction; Field limiting rings, both of which are P-type doped, are symmetrically distributed on both sides of the active area and serve as voltage divider rings of the device and are doped independently of the active area; The periphery of the field limiting ring is an N-type doped cutoff ring; A metal field plate is placed above each field limiting ring to improve the distribution of the peripheral electric field and enhance device stability. A metal is directly deposited on the active area to serve as the anode of the device; The bottom of the highly doped silicon substrate is thinned and then a back electrode metal layer is evaporated to serve as the device cathode.

2. The high-voltage fast recovery diode with positive temperature characteristics according to claim 1, characterized in that: The epitaxial layer is covered with an oxide layer except for the contact hole of the active area, the field plate contact hole of the field limiting ring and the contact hole area of ​​the stop ring.

3. The high-voltage fast recovery diode with positive temperature characteristics according to claim 1, characterized in that: The width of the field-limiting ring is 10~15μm, and the spacing between the field-limiting rings increases from the inside to the outside. The spacing between the innermost rings is 20~30um, and the increasing spacing is 2~5um.

4. The high-voltage fast recovery diode with positive temperature characteristics according to claim 1, characterized in that: The implantation dose of the field limiting ring is 3E12~4E14, and the implantation energy is 50Kev~100Kev; The implantation dose of the active region is 5E12-5E13, and the implantation energy is 50Kev-100Kev.

5. The high-voltage fast recovery diode with positive temperature characteristics according to claim 1, characterized in that: The distance between the cut-off ring and the outer ring of the field limiting ring is 90-150 μm, the injection energy of the cut-off ring is 40-60 keV, and the injection dose is 5E13-1.5E15.

6. A method for preparing a high-voltage fast recovery diode with positive temperature characteristics, characterized in that: The steps include: Step 1: growing an epitaxial layer of the same doping type on a highly doped silicon substrate by CVD or MBE; Step 2: growing a SiO2 layer of a certain thickness on the epitaxial wafer by thermal oxidation; Step 3: Use photoresist as a mask layer to define the field limit ring and active area through exposure and development processes; Step 4: Open the defined field limiting ring and active area doping window by wet etching; Step 5: implanting a certain dose of boron ions into the field limiting ring region using a glue ion implantation process; Step six, using a glue ion implantation process to implant a certain dose of boron ions into the active area; Step 7: Through a high-temperature furnace tube diffusion process, a certain concentration of boron ions is doped into the active area of ​​the epitaxial layer. The high temperature pushes the impurities into a certain depth and activates the impurities, and forms a masking oxide layer on the surface; Step eight, using photoresist as a mask layer, and defining the exit cut-off area through exposure and development processes; Step nine, doping phosphorus ions into the silicon epitaxial portion of the stop ring region by ion implantation or diffusion; Step 10, depositing a boron-phosphorus oxide layer as a dielectric layer by a CVD process, and then performing an annealing process for reflow; Step 11: using photoresist as a mask layer and defining the metal contact area through exposure and development processes; Step 12: Open the metal contact holes in the active area by wet etching to expose the silicon substrate to ensure contact between the metal and the epitaxial layer; Step 13, doping a surface layer of BF2 by ion implantation; Step 14: Deposit a platinum metal layer on the front side using a sputtering process. Dope the platinum into the silicon epitaxial layer through heat treatment to form a certain concentration distribution. At the same time, form a PtSi barrier layer on the silicon surface. After the heat treatment, use aqua regia to completely remove the metal. Step 15: depositing a metal layer of uniform thickness using a PVD process, and defining the electrode region and field plate region of the device using a photoresist; Step 16: etching by a metal wet etching process or a metal dry etching process, and then forming an alloy between the metal and the silicon surface by a heat treatment process; Step 17: depositing a silicon nitride layer of a certain thickness on the surface by a PECVD process as a protective layer for the device; Step 18, using photoresist as a mask layer, etching the silicon nitride at the source contact hole and on the scribe line; Step 19: A polyimide layer of a certain thickness is evenly applied on the front surface, and the imide at the source contact holes and on the scribe lines is removed by exposure and development, and finally high-temperature curing is performed; Step 20: irradiating the material with a high-energy electron beam to introduce recombination centers to control carrier lifetime; then performing an annealing process to repair lattice defects introduced during the irradiation process; Step 21: thinning the silicon substrate to a certain thickness on the back side of the silicon substrate, and depositing a back electrode metal layer by a physical vapor deposition process.

7. The method for preparing a high-voltage fast recovery diode with positive temperature characteristics according to claim 6, characterized in that: In step 1, the highly doped silicon substrate is an N-type substrate, the resistivity of the highly doped silicon substrate is ≤0.004Ω.cm, and the thickness thereof is between 40μm and 700μm; The thickness of the epitaxial layer is 90μm~150μm, and the resistivity is 40Ω.cm~80Ω.cm.

8. The method for preparing a high-voltage fast recovery diode with positive temperature characteristics according to claim 6, characterized in that: In step 2, the thickness of the SiO2 layer is 1um~2um.

9. The method for preparing a high-voltage fast recovery diode with positive temperature characteristics according to claim 6, characterized in that: In step 20, a high-energy electron beam with a dose of about 30 to 150 kGY is used to irradiate the material to introduce recombination centers to control the carrier lifetime; then an annealing process at 355°C to 365°C is performed to repair lattice defects introduced during the irradiation process.

10. The method for preparing a high-voltage fast recovery diode with positive temperature characteristics according to claim 6, characterized in that: Step 21: Thin the silicon substrate to 190-260 μm, and deposit a 12-15 μm back electrode metal layer using a physical vapor deposition process.

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